* [Qemu-devel] [PATCH v5-resend 0/2] Basic ATI VGA emulation
@ 2019-03-06 20:05 BALATON Zoltan
2019-03-06 20:05 ` [Qemu-devel] [PATCH v5-resend 2/2] mips_fulong2e: Add on-board graphics chip BALATON Zoltan
2019-03-06 20:05 ` [Qemu-devel] [PATCH v5-resend 1/2] hw/display: Add basic ATI VGA emulation BALATON Zoltan
0 siblings, 2 replies; 14+ messages in thread
From: BALATON Zoltan @ 2019-03-06 20:05 UTC (permalink / raw)
To: qemu-devel
Cc: Gerd Hoffmann, Mark Cave-Ayland, Aleksandar Markovic,
Peter Maydell, philmd
Hello,
This is the latest version of the ati-vga patch, now also including
the mips_fulong2e patch in a series so both can be merged together via
the UI tree as agreed before to avoid needing to sync two maintainers.
That's probably all I can do before the freeze but the rest can be
considered bugfixes (or given that there's nothing to regress from yet
anything can be considered bugfix at this stage) so we may have some
more chance to improve it before the release if it's merged now.
At least Linux console and fulong2e PMON firmware should work but I
wasn't able to completely find out how 2D accel should work so it
still gives some garbled output for guests using it but I won't have
time to figure this out before the freeze. I could take some help in
this from someone knowing this hardware and pixman better than me.
(Pixman not having any documentation does not help.)
Please let me know if there's anything that needs to be fixed for it
to be merged now. I can probably make another version before the
freeze with those changes but not much more at the moment.
Regards,
BALATON Zoltan
BALATON Zoltan (2):
hw/display: Add basic ATI VGA emulation
mips_fulong2e: Add on-board graphics chip
default-configs/pci.mak | 1 +
hw/display/Makefile.objs | 2 +
hw/display/ati.c | 786 +++++++++++++++++++++++++++++++++++++++++++++++
hw/display/ati_2d.c | 167 ++++++++++
hw/display/ati_dbg.c | 259 ++++++++++++++++
hw/display/ati_int.h | 93 ++++++
hw/display/ati_regs.h | 461 +++++++++++++++++++++++++++
hw/display/trace-events | 4 +
hw/mips/mips_fulong2e.c | 6 +
vl.c | 1 +
10 files changed, 1780 insertions(+)
create mode 100644 hw/display/ati.c
create mode 100644 hw/display/ati_2d.c
create mode 100644 hw/display/ati_dbg.c
create mode 100644 hw/display/ati_int.h
create mode 100644 hw/display/ati_regs.h
--
2.13.7
^ permalink raw reply [flat|nested] 14+ messages in thread
* [Qemu-devel] [PATCH v5-resend 2/2] mips_fulong2e: Add on-board graphics chip
2019-03-06 20:05 [Qemu-devel] [PATCH v5-resend 0/2] Basic ATI VGA emulation BALATON Zoltan
@ 2019-03-06 20:05 ` BALATON Zoltan
2019-03-07 0:32 ` Philippe Mathieu-Daudé
2019-03-06 20:05 ` [Qemu-devel] [PATCH v5-resend 1/2] hw/display: Add basic ATI VGA emulation BALATON Zoltan
1 sibling, 1 reply; 14+ messages in thread
From: BALATON Zoltan @ 2019-03-06 20:05 UTC (permalink / raw)
To: qemu-devel; +Cc: Gerd Hoffmann, Mark Cave-Ayland, Aleksandar Markovic, philmd
[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #1: Type: text/plain, Size: 1335 bytes --]
Add (partial) emulation of the on-board GPU of the machine. This
allows the PMON2000 firmware to run and should also work with Linux
console but probably not with X yet.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
hw/mips/mips_fulong2e.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/hw/mips/mips_fulong2e.c b/hw/mips/mips_fulong2e.c
index fbbc543eed..f877693766 100644
--- a/hw/mips/mips_fulong2e.c
+++ b/hw/mips/mips_fulong2e.c
@@ -287,6 +287,7 @@ static void mips_fulong2e_init(MachineState *machine)
I2CBus *smbus;
MIPSCPU *cpu;
CPUMIPSState *env;
+ DeviceState *dev;
/* init CPUs */
cpu = MIPS_CPU(cpu_create(machine->cpu_type));
@@ -347,6 +348,11 @@ static void mips_fulong2e_init(MachineState *machine)
vt82c686b_southbridge_init(pci_bus, FULONG2E_VIA_SLOT, env->irq[5],
&smbus, &isa_bus);
+ /* GPU */
+ dev = DEVICE(pci_create(pci_bus, -1, "ati-vga"));
+ qdev_prop_set_uint16(dev, "x-device-id", 0x5159);
+ qdev_init_nofail(dev);
+
/* Populate SPD eeprom data */
spd_data = spd_data_generate(DDR, ram_size, &err);
if (err) {
--
2.13.7
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [Qemu-devel] [PATCH v5-resend 1/2] hw/display: Add basic ATI VGA emulation
2019-03-06 20:05 [Qemu-devel] [PATCH v5-resend 0/2] Basic ATI VGA emulation BALATON Zoltan
2019-03-06 20:05 ` [Qemu-devel] [PATCH v5-resend 2/2] mips_fulong2e: Add on-board graphics chip BALATON Zoltan
@ 2019-03-06 20:05 ` BALATON Zoltan
1 sibling, 0 replies; 14+ messages in thread
From: BALATON Zoltan @ 2019-03-06 20:05 UTC (permalink / raw)
To: qemu-devel; +Cc: Gerd Hoffmann, Mark Cave-Ayland, Aleksandar Markovic, philmd
At least two machines, the PPC mac99 and MIPS fulong2e, have an ATI
gfx chip by default (Rage 128 Pro and M6/RV100 respectively) and
guests running on these and the PMON2000 firmware of the fulong2e
expect this to be available. Fortunately these are very similar chips
so they can be mostly emulated in the same device model. This patch
adds basic emulation of these ATI VGA chips.
While this is incomplete and currently only enough to run the MIPS
firmware and get framebuffer output with Linux, it allows the fulong2e
board to work more like the real hardware and having it in QEMU in
this state provides a way to experiment with it and allows others to
contribute to improve it. It is compiled for all archs but only the
fulong2e (which currently has no display output at all) is set to use
it by default (in a separate patch).
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Acked-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
v5:
- review suggestions: add const to model aliases, \n to log, %u in trace
- implemented hardware cursor support
v4:
- fix mingw build (from Gerd)
- set dev_id in realize to allow pci_patch_ids to change bios rom
- add model aliases to select device variant by name instead of id
- misc mode switch and 2d fixes (better but still not quite right)
v3:
- add to default-configs/pci.mak instead of mips64el and ppc only
- rename device_id property to x-device-id
- use extract32/deposit32 in *_offs functions
- add ati-vga to vl.c default_list[]
v2:
- Extended debug logs
- Fix mode switching and some registers
- Fixes to 2D functions
default-configs/pci.mak | 1 +
hw/display/Makefile.objs | 2 +
hw/display/ati.c | 786 +++++++++++++++++++++++++++++++++++++++++++++++
hw/display/ati_2d.c | 167 ++++++++++
hw/display/ati_dbg.c | 259 ++++++++++++++++
hw/display/ati_int.h | 93 ++++++
hw/display/ati_regs.h | 461 +++++++++++++++++++++++++++
hw/display/trace-events | 4 +
vl.c | 1 +
9 files changed, 1774 insertions(+)
create mode 100644 hw/display/ati.c
create mode 100644 hw/display/ati_2d.c
create mode 100644 hw/display/ati_dbg.c
create mode 100644 hw/display/ati_int.h
create mode 100644 hw/display/ati_regs.h
diff --git a/default-configs/pci.mak b/default-configs/pci.mak
index 037636fa33..e59e2fa7b6 100644
--- a/default-configs/pci.mak
+++ b/default-configs/pci.mak
@@ -49,3 +49,4 @@ CONFIG_IVSHMEM_DEVICE=$(CONFIG_IVSHMEM)
CONFIG_ROCKER=y
CONFIG_VFIO=$(CONFIG_LINUX)
CONFIG_VFIO_PCI=y
+CONFIG_ATI_VGA=y
diff --git a/hw/display/Makefile.objs b/hw/display/Makefile.objs
index 7c4ae9a0fd..963c23f3c8 100644
--- a/hw/display/Makefile.objs
+++ b/hw/display/Makefile.objs
@@ -53,3 +53,5 @@ virtio-gpu-3d.o-cflags := $(VIRGL_CFLAGS)
virtio-gpu-3d.o-libs += $(VIRGL_LIBS)
obj-$(CONFIG_DPCD) += dpcd.o
obj-$(CONFIG_XLNX_ZYNQMP_ARM) += xlnx_dp.o
+
+obj-$(CONFIG_ATI_VGA) += ati.o ati_2d.o ati_dbg.o
diff --git a/hw/display/ati.c b/hw/display/ati.c
new file mode 100644
index 0000000000..0a03bc3e8a
--- /dev/null
+++ b/hw/display/ati.c
@@ -0,0 +1,786 @@
+/*
+ * QEMU ATI SVGA emulation
+ *
+ * Copyright (c) 2019 BALATON Zoltan
+ *
+ * This work is licensed under the GNU GPL license version 2 or later.
+ */
+
+/*
+ * WARNING:
+ * This is very incomplete and only enough for Linux console and some
+ * unaccelerated X output at the moment.
+ * Currently it's little more than a frame buffer with minimal functions,
+ * other more advanced features of the hardware are yet to be implemented.
+ * We only aim for Rage 128 Pro (and some RV100) and 2D only at first,
+ * No 3D at all yet (maybe after 2D works, but feel free to improve it)
+ */
+
+#include "ati_int.h"
+#include "ati_regs.h"
+#include "vga_regs.h"
+#include "qemu/log.h"
+#include "qemu/error-report.h"
+#include "qapi/error.h"
+#include "hw/hw.h"
+#include "ui/console.h"
+#include "trace.h"
+
+#define ATI_DEBUG_HW_CURSOR 0
+
+static const struct {
+ const char *name;
+ uint16_t dev_id;
+} ati_model_aliases[] = {
+ { "rage128p", PCI_DEVICE_ID_ATI_RAGE128_PF },
+ { "rv100", PCI_DEVICE_ID_ATI_RADEON_QY },
+};
+
+enum { VGA_MODE, EXT_MODE };
+
+static void ati_vga_switch_mode(ATIVGAState *s)
+{
+ DPRINTF("%d -> %d\n",
+ s->mode, !!(s->regs.crtc_gen_cntl & CRTC2_EXT_DISP_EN));
+ if (s->regs.crtc_gen_cntl & CRTC2_EXT_DISP_EN) {
+ /* Extended mode enabled */
+ s->mode = EXT_MODE;
+ if (s->regs.crtc_gen_cntl & CRTC2_EN) {
+ /* CRT controller enabled, use CRTC values */
+ uint32_t offs = s->regs.crtc_offset & 0x07ffffff;
+ int stride = (s->regs.crtc_pitch & 0x7ff) * 8;
+ int bpp = 0;
+ int h, v;
+
+ if (s->regs.crtc_h_total_disp == 0) {
+ s->regs.crtc_h_total_disp = ((640 / 8) - 1) << 16;
+ }
+ if (s->regs.crtc_v_total_disp == 0) {
+ s->regs.crtc_v_total_disp = (480 - 1) << 16;
+ }
+ h = ((s->regs.crtc_h_total_disp >> 16) + 1) * 8;
+ v = (s->regs.crtc_v_total_disp >> 16) + 1;
+ switch (s->regs.crtc_gen_cntl & CRTC_PIX_WIDTH_MASK) {
+ case CRTC_PIX_WIDTH_4BPP:
+ bpp = 4;
+ break;
+ case CRTC_PIX_WIDTH_8BPP:
+ bpp = 8;
+ break;
+ case CRTC_PIX_WIDTH_15BPP:
+ bpp = 15;
+ break;
+ case CRTC_PIX_WIDTH_16BPP:
+ bpp = 16;
+ break;
+ case CRTC_PIX_WIDTH_24BPP:
+ bpp = 24;
+ break;
+ case CRTC_PIX_WIDTH_32BPP:
+ bpp = 32;
+ break;
+ default:
+ qemu_log_mask(LOG_UNIMP, "Unsupported bpp value\n");
+ }
+ assert(bpp != 0);
+ DPRINTF("Switching to %dx%d %d %d @ %x\n", h, v, stride, bpp, offs);
+ vbe_ioport_write_index(&s->vga, 0, VBE_DISPI_INDEX_ENABLE);
+ vbe_ioport_write_data(&s->vga, 0, VBE_DISPI_DISABLED);
+ /* reset VBE regs then set up mode */
+ s->vga.vbe_regs[VBE_DISPI_INDEX_XRES] = h;
+ s->vga.vbe_regs[VBE_DISPI_INDEX_YRES] = v;
+ s->vga.vbe_regs[VBE_DISPI_INDEX_BPP] = bpp;
+ /* enable mode via ioport so it updates vga regs */
+ vbe_ioport_write_index(&s->vga, 0, VBE_DISPI_INDEX_ENABLE);
+ vbe_ioport_write_data(&s->vga, 0, VBE_DISPI_ENABLED |
+ VBE_DISPI_LFB_ENABLED | VBE_DISPI_NOCLEARMEM |
+ (s->regs.dac_cntl & DAC_8BIT_EN ? VBE_DISPI_8BIT_DAC : 0));
+ /* now set offset and stride after enable as that resets these */
+ if (stride) {
+ vbe_ioport_write_index(&s->vga, 0, VBE_DISPI_INDEX_VIRT_WIDTH);
+ vbe_ioport_write_data(&s->vga, 0, stride);
+ if (offs % stride == 0) {
+ vbe_ioport_write_index(&s->vga, 0, VBE_DISPI_INDEX_Y_OFFSET);
+ vbe_ioport_write_data(&s->vga, 0, offs / stride);
+ } else {
+ /* FIXME what to do with this? */
+ error_report("VGA offset is not multiple of pitch, "
+ "expect bad picture");
+ }
+ }
+ }
+ } else {
+ /* VGA mode enabled */
+ s->mode = VGA_MODE;
+ vbe_ioport_write_index(&s->vga, 0, VBE_DISPI_INDEX_ENABLE);
+ vbe_ioport_write_data(&s->vga, 0, VBE_DISPI_DISABLED);
+ }
+}
+
+static void ati_cursor_define(ATIVGAState *s)
+{
+ uint8_t data[1024];
+ uint8_t *src;
+ int i, j, idx = 0;
+
+ if (s->regs.cur_offset & BIT(31)) {
+ return; /* Do not update cursor if locked */
+ }
+ /* FIXME handle cur_hv_offs correctly */
+ src = s->vga.vram_ptr + (s->regs.crtc_offset & 0x07ffffff) +
+ s->regs.cur_offset - (s->regs.cur_hv_offs >> 16) -
+ (s->regs.cur_hv_offs & 0xffff) * 16;
+ for (i = 0; i < 64; i++) {
+ for (j = 0; j < 8; j++, idx++) {
+ data[idx] = src[i * 16 + j];
+ data[512 + idx] = src[i * 16 + j + 8];
+ }
+ }
+ if (!s->cursor) {
+ s->cursor = cursor_alloc(64, 64);
+ }
+ cursor_set_mono(s->cursor, s->regs.cur_color1, s->regs.cur_color0,
+ &data[512], 1, &data[0]);
+ dpy_cursor_define(s->vga.con, s->cursor);
+}
+
+static inline uint64_t ati_reg_read_offs(uint32_t reg, int offs,
+ unsigned int size)
+{
+ if (offs == 0 && size == 4) {
+ return reg;
+ } else {
+ return extract32(reg, offs * BITS_PER_BYTE, size * BITS_PER_BYTE);
+ }
+}
+
+static uint64_t ati_mm_read(void *opaque, hwaddr addr, unsigned int size)
+{
+ ATIVGAState *s = opaque;
+ uint64_t val = 0;
+
+ switch (addr) {
+ case MM_INDEX:
+ val = s->regs.mm_index;
+ break;
+ case MM_DATA ... MM_DATA + 3:
+ /* indexed access to regs or memory */
+ if (s->regs.mm_index & BIT(31)) {
+ if (s->regs.mm_index <= s->vga.vram_size - size) {
+ int i = size - 1;
+ while (i >= 0) {
+ val <<= 8;
+ val |= s->vga.vram_ptr[s->regs.mm_index + i--];
+ }
+ }
+ } else {
+ val = ati_mm_read(s, s->regs.mm_index + addr - MM_DATA, size);
+ }
+ break;
+ case BIOS_0_SCRATCH ... BUS_CNTL - 1:
+ {
+ int i = (addr - BIOS_0_SCRATCH) / 4;
+ if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF && i > 3) {
+ break;
+ }
+ val = ati_reg_read_offs(s->regs.bios_scratch[i],
+ addr - (BIOS_0_SCRATCH + i * 4), size);
+ break;
+ }
+ case CRTC_GEN_CNTL ... CRTC_GEN_CNTL + 3:
+ val = ati_reg_read_offs(s->regs.crtc_gen_cntl,
+ addr - CRTC_GEN_CNTL, size);
+ break;
+ case CRTC_EXT_CNTL ... CRTC_EXT_CNTL + 3:
+ val = ati_reg_read_offs(s->regs.crtc_ext_cntl,
+ addr - CRTC_EXT_CNTL, size);
+ break;
+ case DAC_CNTL:
+ val = s->regs.dac_cntl;
+ break;
+/* case GPIO_MONID: FIXME hook up DDC I2C here */
+ case PALETTE_INDEX:
+ /* FIXME unaligned access */
+ val = vga_ioport_read(&s->vga, VGA_PEL_IR) << 16;
+ val |= vga_ioport_read(&s->vga, VGA_PEL_IW) & 0xff;
+ break;
+ case PALETTE_DATA:
+ val = vga_ioport_read(&s->vga, VGA_PEL_D);
+ break;
+ case CNFG_MEMSIZE:
+ val = s->vga.vram_size;
+ break;
+ case MC_STATUS:
+ val = 5;
+ break;
+ case RBBM_STATUS:
+ case GUI_STAT:
+ val = 64; /* free CMDFIFO entries */
+ break;
+ case CRTC_H_TOTAL_DISP:
+ val = s->regs.crtc_h_total_disp;
+ break;
+ case CRTC_H_SYNC_STRT_WID:
+ val = s->regs.crtc_h_sync_strt_wid;
+ break;
+ case CRTC_V_TOTAL_DISP:
+ val = s->regs.crtc_v_total_disp;
+ break;
+ case CRTC_V_SYNC_STRT_WID:
+ val = s->regs.crtc_v_sync_strt_wid;
+ break;
+ case CRTC_OFFSET:
+ val = s->regs.crtc_offset;
+ break;
+ case CRTC_OFFSET_CNTL:
+ val = s->regs.crtc_offset_cntl;
+ break;
+ case CRTC_PITCH:
+ val = s->regs.crtc_pitch;
+ break;
+ case 0xf00 ... 0xfff:
+ val = pci_default_read_config(&s->dev, addr - 0xf00, size);
+ break;
+ case CUR_OFFSET:
+ val = s->regs.cur_offset;
+ break;
+ case CUR_HORZ_VERT_POSN:
+ val = s->regs.cur_hv_pos;
+ val |= s->regs.cur_offset & BIT(31);
+ break;
+ case CUR_HORZ_VERT_OFF:
+ val = s->regs.cur_hv_offs;
+ val |= s->regs.cur_offset & BIT(31);
+ break;
+ case CUR_CLR0:
+ val = s->regs.cur_color0;
+ break;
+ case CUR_CLR1:
+ val = s->regs.cur_color1;
+ break;
+ case DST_OFFSET:
+ val = s->regs.dst_offset;
+ break;
+ case DST_PITCH:
+ val = s->regs.dst_pitch;
+ if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) {
+ val &= s->regs.dst_tile << 16;
+ }
+ break;
+ case DST_WIDTH:
+ val = s->regs.dst_width;
+ break;
+ case DST_HEIGHT:
+ val = s->regs.dst_height;
+ break;
+ case SRC_X:
+ val = s->regs.src_x;
+ break;
+ case SRC_Y:
+ val = s->regs.src_y;
+ break;
+ case DST_X:
+ val = s->regs.dst_x;
+ break;
+ case DST_Y:
+ val = s->regs.dst_y;
+ break;
+ case DP_GUI_MASTER_CNTL:
+ val = s->regs.dp_gui_master_cntl;
+ break;
+ case SRC_OFFSET:
+ val = s->regs.src_offset;
+ break;
+ case SRC_PITCH:
+ val = s->regs.src_pitch;
+ if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) {
+ val &= s->regs.src_tile << 16;
+ }
+ break;
+ case DP_BRUSH_BKGD_CLR:
+ val = s->regs.dp_brush_bkgd_clr;
+ break;
+ case DP_BRUSH_FRGD_CLR:
+ val = s->regs.dp_brush_frgd_clr;
+ break;
+ case DP_SRC_FRGD_CLR:
+ val = s->regs.dp_src_frgd_clr;
+ break;
+ case DP_SRC_BKGD_CLR:
+ val = s->regs.dp_src_bkgd_clr;
+ break;
+ case DP_CNTL:
+ val = s->regs.dp_cntl;
+ break;
+ case DP_DATATYPE:
+ val = s->regs.dp_datatype;
+ break;
+ case DP_MIX:
+ val = s->regs.dp_mix;
+ break;
+ case DP_WRITE_MASK:
+ val = s->regs.dp_write_mask;
+ break;
+ case DEFAULT_OFFSET:
+ val = s->regs.default_offset;
+ break;
+ case DEFAULT_PITCH:
+ val = s->regs.default_pitch;
+ break;
+ case DEFAULT_SC_BOTTOM_RIGHT:
+ val = s->regs.default_sc_bottom_right;
+ break;
+ default:
+ break;
+ }
+ if (addr < CUR_OFFSET || addr > CUR_CLR1 || ATI_DEBUG_HW_CURSOR) {
+ trace_ati_mm_read(size, addr, ati_reg_name(addr & ~3ULL), val);
+ }
+ return val;
+}
+
+static inline void ati_reg_write_offs(uint32_t *reg, int offs,
+ uint64_t data, unsigned int size)
+{
+ if (offs == 0 && size == 4) {
+ *reg = data;
+ } else {
+ *reg = deposit32(*reg, offs * BITS_PER_BYTE, size * BITS_PER_BYTE,
+ data);
+ }
+}
+
+static void ati_mm_write(void *opaque, hwaddr addr,
+ uint64_t data, unsigned int size)
+{
+ ATIVGAState *s = opaque;
+
+ if (addr < CUR_OFFSET || addr > CUR_CLR1 || ATI_DEBUG_HW_CURSOR) {
+ trace_ati_mm_write(size, addr, ati_reg_name(addr & ~3ULL), data);
+ }
+ switch (addr) {
+ case MM_INDEX:
+ s->regs.mm_index = data;
+ break;
+ case MM_DATA ... MM_DATA + 3:
+ /* indexed access to regs or memory */
+ if (s->regs.mm_index & BIT(31)) {
+ if (s->regs.mm_index <= s->vga.vram_size - size) {
+ int i = 0;
+ while (i < size) {
+ s->vga.vram_ptr[s->regs.mm_index + i] = data & 0xff;
+ data >>= 8;
+ }
+ }
+ } else {
+ ati_mm_write(s, s->regs.mm_index + addr - MM_DATA, data, size);
+ }
+ break;
+ case BIOS_0_SCRATCH ... BUS_CNTL - 1:
+ {
+ int i = (addr - BIOS_0_SCRATCH) / 4;
+ if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF && i > 3) {
+ break;
+ }
+ ati_reg_write_offs(&s->regs.bios_scratch[i],
+ addr - (BIOS_0_SCRATCH + i * 4), data, size);
+ break;
+ }
+ case CRTC_GEN_CNTL ... CRTC_GEN_CNTL + 3:
+ {
+ uint32_t val = s->regs.crtc_gen_cntl;
+ ati_reg_write_offs(&s->regs.crtc_gen_cntl,
+ addr - CRTC_GEN_CNTL, data, size);
+ if ((val & CRTC2_CUR_EN) != (s->regs.crtc_gen_cntl & CRTC2_CUR_EN)) {
+ if (s->regs.crtc_gen_cntl & CRTC2_CUR_EN) {
+ ati_cursor_define(s);
+ }
+ dpy_mouse_set(s->vga.con, s->regs.cur_hv_pos >> 16,
+ s->regs.cur_hv_pos & 0xffff,
+ (s->regs.crtc_gen_cntl & CRTC2_CUR_EN) != 0);
+ }
+ if ((val & (CRTC2_EXT_DISP_EN | CRTC2_EN)) !=
+ (s->regs.crtc_gen_cntl & (CRTC2_EXT_DISP_EN | CRTC2_EN))) {
+ ati_vga_switch_mode(s);
+ }
+ break;
+ }
+ case CRTC_EXT_CNTL ... CRTC_EXT_CNTL + 3:
+ {
+ uint32_t val = s->regs.crtc_ext_cntl;
+ ati_reg_write_offs(&s->regs.crtc_ext_cntl,
+ addr - CRTC_EXT_CNTL, data, size);
+ if (s->regs.crtc_ext_cntl & CRT_CRTC_DISPLAY_DIS) {
+ DPRINTF("Display disabled\n");
+ s->vga.ar_index &= ~BIT(5);
+ } else {
+ DPRINTF("Display enabled\n");
+ s->vga.ar_index |= BIT(5);
+ ati_vga_switch_mode(s);
+ }
+ if ((val & CRT_CRTC_DISPLAY_DIS) !=
+ (s->regs.crtc_ext_cntl & CRT_CRTC_DISPLAY_DIS)) {
+ ati_vga_switch_mode(s);
+ }
+ break;
+ }
+ case DAC_CNTL:
+ s->regs.dac_cntl = data & 0xffffe3ff;
+ s->vga.dac_8bit = !!(data & DAC_8BIT_EN);
+ break;
+/* case GPIO_MONID: FIXME hook up DDC I2C here */
+ case PALETTE_INDEX ... PALETTE_INDEX + 3:
+ if (size == 4) {
+ vga_ioport_write(&s->vga, VGA_PEL_IR, (data >> 16) & 0xff);
+ vga_ioport_write(&s->vga, VGA_PEL_IW, data & 0xff);
+ } else {
+ if (addr == PALETTE_INDEX) {
+ vga_ioport_write(&s->vga, VGA_PEL_IW, data & 0xff);
+ } else {
+ vga_ioport_write(&s->vga, VGA_PEL_IR, data & 0xff);
+ }
+ }
+ break;
+ case PALETTE_DATA ... PALETTE_DATA + 3:
+ data <<= addr - PALETTE_DATA;
+ data = bswap32(data) >> 8;
+ vga_ioport_write(&s->vga, VGA_PEL_D, data & 0xff);
+ data >>= 8;
+ vga_ioport_write(&s->vga, VGA_PEL_D, data & 0xff);
+ data >>= 8;
+ vga_ioport_write(&s->vga, VGA_PEL_D, data & 0xff);
+ break;
+ case CRTC_H_TOTAL_DISP:
+ s->regs.crtc_h_total_disp = data & 0x07ff07ff;
+ break;
+ case CRTC_H_SYNC_STRT_WID:
+ s->regs.crtc_h_sync_strt_wid = data & 0x17bf1fff;
+ break;
+ case CRTC_V_TOTAL_DISP:
+ s->regs.crtc_v_total_disp = data & 0x0fff0fff;
+ break;
+ case CRTC_V_SYNC_STRT_WID:
+ s->regs.crtc_v_sync_strt_wid = data & 0x9f0fff;
+ break;
+ case CRTC_OFFSET:
+ s->regs.crtc_offset = data & 0xc7ffffff;
+ break;
+ case CRTC_OFFSET_CNTL:
+ s->regs.crtc_offset_cntl = data; /* FIXME */
+ break;
+ case CRTC_PITCH:
+ s->regs.crtc_pitch = data & 0x07ff07ff;
+ break;
+ case 0xf00 ... 0xfff:
+ /* read-only copy of PCI config space so ignore writes */
+ break;
+ case CUR_OFFSET:
+ if (s->regs.cur_offset != (data & 0x87fffff0)) {
+ s->regs.cur_offset = data & 0x87fffff0;
+ ati_cursor_define(s);
+ }
+ break;
+ case CUR_HORZ_VERT_POSN:
+ s->regs.cur_hv_pos = data & 0x3fff0fff;
+ if (data & BIT(31)) {
+ s->regs.cur_offset |= data & BIT(31);
+ } else if (s->regs.cur_offset & BIT(31)) {
+ s->regs.cur_offset &= ~BIT(31);
+ ati_cursor_define(s);
+ }
+ if ((s->regs.crtc_gen_cntl & CRTC2_CUR_EN) && !(data & BIT(31))) {
+ dpy_mouse_set(s->vga.con, s->regs.cur_hv_pos >> 16,
+ s->regs.cur_hv_pos & 0xffff, 1);
+ }
+ break;
+ case CUR_HORZ_VERT_OFF:
+ s->regs.cur_hv_offs = data & 0x3f003f;
+ if (data & BIT(31)) {
+ s->regs.cur_offset |= data & BIT(31);
+ } else if (s->regs.cur_offset & BIT(31)) {
+ s->regs.cur_offset &= ~BIT(31);
+ ati_cursor_define(s);
+ }
+ break;
+ case CUR_CLR0:
+ if (s->regs.cur_color0 != (data & 0xffffff)) {
+ s->regs.cur_color0 = data & 0xffffff;
+ ati_cursor_define(s);
+ }
+ break;
+ case CUR_CLR1:
+ /*
+ * Update cursor unconditionally here because some clients set up
+ * other registers before actually writing cursor data to memory at
+ * offset so we would miss cursor change unless always updating here
+ */
+ s->regs.cur_color1 = data & 0xffffff;
+ ati_cursor_define(s);
+ break;
+ case DST_OFFSET:
+ if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) {
+ s->regs.dst_offset = data & 0xfffffff0;
+ } else {
+ s->regs.dst_offset = data & 0xfffffc00;
+ }
+ break;
+ case DST_PITCH:
+ if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) {
+ s->regs.dst_pitch = data & 0x3fff;
+ s->regs.dst_tile = (data >> 16) & 1;
+ } else {
+ s->regs.dst_pitch = data & 0x3ff0;
+ }
+ break;
+ case DST_TILE:
+ if (s->dev_id == PCI_DEVICE_ID_ATI_RADEON_QY) {
+ s->regs.dst_tile = data & 3;
+ }
+ break;
+ case DST_WIDTH:
+ s->regs.dst_width = data & 0x3fff;
+ ati_2d_blt(s);
+ break;
+ case DST_HEIGHT:
+ s->regs.dst_height = data & 0x3fff;
+ break;
+ case SRC_X:
+ s->regs.src_x = data & 0x3fff;
+ break;
+ case SRC_Y:
+ s->regs.src_y = data & 0x3fff;
+ break;
+ case DST_X:
+ s->regs.dst_x = data & 0x3fff;
+ break;
+ case DST_Y:
+ s->regs.dst_y = data & 0x3fff;
+ break;
+ case SRC_PITCH_OFFSET:
+ if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) {
+ s->regs.src_offset = (data & 0x1fffff) << 5;
+ s->regs.src_pitch = (data >> 21) & 0x3ff;
+ s->regs.src_tile = data >> 31;
+ } else {
+ s->regs.src_offset = (data & 0x3fffff) << 11;
+ s->regs.src_pitch = (data & 0x3fc00000) >> 16;
+ s->regs.src_tile = (data >> 30) & 1;
+ }
+ break;
+ case DST_PITCH_OFFSET:
+ if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) {
+ s->regs.dst_offset = (data & 0x1fffff) << 5;
+ s->regs.dst_pitch = (data >> 21) & 0x3ff;
+ s->regs.dst_tile = data >> 31;
+ } else {
+ s->regs.dst_offset = (data & 0x3fffff) << 11;
+ s->regs.dst_pitch = (data & 0x3fc00000) >> 16;
+ s->regs.dst_tile = data >> 30;
+ }
+ break;
+ case SRC_Y_X:
+ s->regs.src_x = data & 0x3fff;
+ s->regs.src_y = (data >> 16) & 0x3fff;
+ break;
+ case DST_Y_X:
+ s->regs.dst_x = data & 0x3fff;
+ s->regs.dst_y = (data >> 16) & 0x3fff;
+ break;
+ case DST_HEIGHT_WIDTH:
+ s->regs.dst_width = data & 0x3fff;
+ s->regs.dst_height = (data >> 16) & 0x3fff;
+ ati_2d_blt(s);
+ break;
+ case DP_GUI_MASTER_CNTL:
+ s->regs.dp_gui_master_cntl = data & 0xf800000f;
+ s->regs.dp_datatype = (data & 0x0f00) >> 8 | (data & 0x30f0) << 4 |
+ (data & 0x4000) << 16;
+ s->regs.dp_mix = (data & GMC_ROP3_MASK) | (data & 0x7000000) >> 16;
+ break;
+ case DST_WIDTH_X:
+ s->regs.dst_x = data & 0x3fff;
+ s->regs.dst_width = (data >> 16) & 0x3fff;
+ ati_2d_blt(s);
+ break;
+ case SRC_X_Y:
+ s->regs.src_y = data & 0x3fff;
+ s->regs.src_x = (data >> 16) & 0x3fff;
+ break;
+ case DST_X_Y:
+ s->regs.dst_y = data & 0x3fff;
+ s->regs.dst_x = (data >> 16) & 0x3fff;
+ break;
+ case DST_WIDTH_HEIGHT:
+ s->regs.dst_height = data & 0x3fff;
+ s->regs.dst_width = (data >> 16) & 0x3fff;
+ ati_2d_blt(s);
+ break;
+ case DST_HEIGHT_Y:
+ s->regs.dst_y = data & 0x3fff;
+ s->regs.dst_height = (data >> 16) & 0x3fff;
+ break;
+ case SRC_OFFSET:
+ if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) {
+ s->regs.src_offset = data & 0xfffffff0;
+ } else {
+ s->regs.src_offset = data & 0xfffffc00;
+ }
+ break;
+ case SRC_PITCH:
+ if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) {
+ s->regs.src_pitch = data & 0x3fff;
+ s->regs.src_tile = (data >> 16) & 1;
+ } else {
+ s->regs.src_pitch = data & 0x3ff0;
+ }
+ break;
+ case DP_BRUSH_BKGD_CLR:
+ s->regs.dp_brush_bkgd_clr = data;
+ break;
+ case DP_BRUSH_FRGD_CLR:
+ s->regs.dp_brush_frgd_clr = data;
+ break;
+ case DP_CNTL:
+ s->regs.dp_cntl = data;
+ break;
+ case DP_DATATYPE:
+ s->regs.dp_datatype = data & 0xe0070f0f;
+ break;
+ case DP_MIX:
+ s->regs.dp_mix = data & 0x00ff0700;
+ break;
+ case DP_WRITE_MASK:
+ s->regs.dp_write_mask = data;
+ break;
+ case DEFAULT_OFFSET:
+ data &= (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF ?
+ 0x03fffc00 : 0xfffffc00);
+ s->regs.default_offset = data;
+ break;
+ case DEFAULT_PITCH:
+ if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) {
+ s->regs.default_pitch = data & 0x103ff;
+ }
+ break;
+ case DEFAULT_SC_BOTTOM_RIGHT:
+ s->regs.default_sc_bottom_right = data & 0x3fff3fff;
+ break;
+ default:
+ break;
+ }
+}
+
+static const MemoryRegionOps ati_mm_ops = {
+ .read = ati_mm_read,
+ .write = ati_mm_write,
+ .endianness = DEVICE_LITTLE_ENDIAN,
+};
+
+static void ati_vga_realize(PCIDevice *dev, Error **errp)
+{
+ ATIVGAState *s = ATI_VGA(dev);
+ VGACommonState *vga = &s->vga;
+
+ if (s->model) {
+ int i;
+ for (i = 0; i < ARRAY_SIZE(ati_model_aliases); i++) {
+ if (!strcmp(s->model, ati_model_aliases[i].name)) {
+ s->dev_id = ati_model_aliases[i].dev_id;
+ break;
+ }
+ }
+ if (i >= ARRAY_SIZE(ati_model_aliases)) {
+ warn_report("Unknown ATI VGA model name, "
+ "using default rage128p");
+ }
+ }
+ if (s->dev_id != PCI_DEVICE_ID_ATI_RAGE128_PF &&
+ s->dev_id != PCI_DEVICE_ID_ATI_RADEON_QY) {
+ error_setg(errp, "Unknown ATI VGA device id, "
+ "only 0x5046 and 0x5159 are supported");
+ return;
+ }
+ pci_set_word(dev->config + PCI_DEVICE_ID, s->dev_id);
+
+ if (s->dev_id == PCI_DEVICE_ID_ATI_RADEON_QY &&
+ s->vga.vram_size_mb < 16) {
+ warn_report("Too small video memory for device id");
+ s->vga.vram_size_mb = 16;
+ }
+
+ /* init vga bits */
+ vga_common_init(vga, OBJECT(s));
+ vga_init(vga, OBJECT(s), pci_address_space(dev),
+ pci_address_space_io(dev), true);
+ vga->con = graphic_console_init(DEVICE(s), 0, s->vga.hw_ops, &s->vga);
+
+ /* mmio register space */
+ memory_region_init_io(&s->mm, OBJECT(s), &ati_mm_ops, s,
+ "ati.mmregs", 0x4000);
+ /* io space is alias to beginning of mmregs */
+ memory_region_init_alias(&s->io, OBJECT(s), "ati.io", &s->mm, 0, 0x100);
+
+ pci_register_bar(dev, 0, PCI_BASE_ADDRESS_MEM_PREFETCH, &vga->vram);
+ pci_register_bar(dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &s->io);
+ pci_register_bar(dev, 2, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->mm);
+}
+
+static void ati_vga_reset(DeviceState *dev)
+{
+ ATIVGAState *s = ATI_VGA(dev);
+
+ /* reset vga */
+ vga_common_reset(&s->vga);
+ s->mode = VGA_MODE;
+}
+
+static void ati_vga_exit(PCIDevice *dev)
+{
+ ATIVGAState *s = ATI_VGA(dev);
+
+ graphic_console_close(s->vga.con);
+}
+
+static Property ati_vga_properties[] = {
+ DEFINE_PROP_UINT32("vgamem_mb", ATIVGAState, vga.vram_size_mb, 16),
+ DEFINE_PROP_STRING("model", ATIVGAState, model),
+ DEFINE_PROP_UINT16("x-device-id", ATIVGAState, dev_id,
+ PCI_DEVICE_ID_ATI_RAGE128_PF),
+ DEFINE_PROP_END_OF_LIST()
+};
+
+static void ati_vga_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+ PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
+
+ dc->reset = ati_vga_reset;
+ dc->props = ati_vga_properties;
+ dc->hotpluggable = false;
+ set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories);
+
+ k->class_id = PCI_CLASS_DISPLAY_VGA;
+ k->vendor_id = PCI_VENDOR_ID_ATI;
+ k->device_id = PCI_DEVICE_ID_ATI_RAGE128_PF;
+ k->romfile = "vgabios-stdvga.bin";
+ k->realize = ati_vga_realize;
+ k->exit = ati_vga_exit;
+}
+
+static const TypeInfo ati_vga_info = {
+ .name = TYPE_ATI_VGA,
+ .parent = TYPE_PCI_DEVICE,
+ .instance_size = sizeof(ATIVGAState),
+ .class_init = ati_vga_class_init,
+ .interfaces = (InterfaceInfo[]) {
+ { INTERFACE_CONVENTIONAL_PCI_DEVICE },
+ { },
+ },
+};
+
+static void ati_vga_register_types(void)
+{
+ type_register_static(&ati_vga_info);
+}
+
+type_init(ati_vga_register_types)
diff --git a/hw/display/ati_2d.c b/hw/display/ati_2d.c
new file mode 100644
index 0000000000..bc98ba6eeb
--- /dev/null
+++ b/hw/display/ati_2d.c
@@ -0,0 +1,167 @@
+/*
+ * QEMU ATI SVGA emulation
+ * 2D engine functions
+ *
+ * Copyright (c) 2019 BALATON Zoltan
+ *
+ * This work is licensed under the GNU GPL license version 2 or later.
+ */
+
+#include "ati_int.h"
+#include "ati_regs.h"
+#include "qemu/log.h"
+#include "ui/pixel_ops.h"
+
+/*
+ * NOTE:
+ * This is 2D _acceleration_ and supposed to be fast. Therefore, don't try to
+ * reinvent the wheel (unlikely to get better with a naive implementation than
+ * existing libraries) and avoid (poorly) reimplementing gfx primitives.
+ * That is unnecessary and would become a performance problem. Instead, try to
+ * map to and reuse existing optimised facilities (e.g. pixman) wherever
+ * possible.
+ */
+
+static int ati_bpp_from_datatype(ATIVGAState *s)
+{
+ switch (s->regs.dp_datatype & 0xf) {
+ case 2:
+ return 8;
+ case 3:
+ case 4:
+ return 16;
+ case 5:
+ return 24;
+ case 6:
+ return 32;
+ default:
+ qemu_log_mask(LOG_UNIMP, "Unknown dst datatype %d\n",
+ s->regs.dp_datatype & 0xf);
+ return 0;
+ }
+}
+
+void ati_2d_blt(ATIVGAState *s)
+{
+ /* FIXME it is probably more complex than this and may need to be */
+ /* rewritten but for now as a start just to get some output: */
+ DisplaySurface *ds = qemu_console_surface(s->vga.con);
+ DPRINTF("%p %u ds: %p %d %d rop: %x\n", s->vga.vram_ptr,
+ s->vga.vbe_start_addr, surface_data(ds), surface_stride(ds),
+ surface_bits_per_pixel(ds),
+ (s->regs.dp_mix & GMC_ROP3_MASK) >> 16);
+ DPRINTF("%d %d, %d %d, (%d,%d) -> (%d,%d) %dx%d\n", s->regs.src_offset,
+ s->regs.dst_offset, s->regs.src_pitch, s->regs.dst_pitch,
+ s->regs.src_x, s->regs.src_y, s->regs.dst_x, s->regs.dst_y,
+ s->regs.dst_width, s->regs.dst_height);
+ switch (s->regs.dp_mix & GMC_ROP3_MASK) {
+ case ROP3_SRCCOPY:
+ {
+ uint8_t *src_bits, *dst_bits, *end;
+ int src_stride, dst_stride, bpp = ati_bpp_from_datatype(s);
+ src_bits = s->vga.vram_ptr + s->regs.src_offset;
+ dst_bits = s->vga.vram_ptr + s->regs.dst_offset;
+ src_stride = s->regs.src_pitch;
+ dst_stride = s->regs.dst_pitch;
+
+ if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) {
+ src_bits += s->regs.crtc_offset & 0x07ffffff;
+ dst_bits += s->regs.crtc_offset & 0x07ffffff;
+ src_stride *= bpp;
+ dst_stride *= bpp;
+ }
+ src_stride /= sizeof(uint32_t);
+ dst_stride /= sizeof(uint32_t);
+
+ DPRINTF("pixman_blt(%p, %p, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d)\n",
+ src_bits, dst_bits, src_stride, dst_stride, bpp, bpp,
+ s->regs.src_x, s->regs.src_y, s->regs.dst_x, s->regs.dst_y,
+ s->regs.dst_width, s->regs.dst_height);
+ end = s->vga.vram_ptr + s->vga.vram_size;
+ if (src_bits >= end || dst_bits >= end ||
+ src_bits + (s->regs.src_y + s->regs.dst_height) * src_stride +
+ s->regs.src_x >= end ||
+ dst_bits + (s->regs.dst_y + s->regs.dst_height) * dst_stride +
+ s->regs.dst_x >= end) {
+ qemu_log_mask(LOG_UNIMP, "blt outside vram not implemented\n");
+ return;
+ }
+ pixman_blt((uint32_t *)src_bits, (uint32_t *)dst_bits,
+ src_stride, dst_stride, bpp, bpp,
+ s->regs.src_x, s->regs.src_y,
+ s->regs.dst_x, s->regs.dst_y,
+ s->regs.dst_width, s->regs.dst_height);
+ if (dst_bits >= s->vga.vram_ptr + s->vga.vbe_start_addr &&
+ dst_bits < s->vga.vram_ptr + s->vga.vbe_start_addr +
+ s->vga.vbe_regs[VBE_DISPI_INDEX_YRES] * s->vga.vbe_line_offset) {
+ memory_region_set_dirty(&s->vga.vram, s->vga.vbe_start_addr +
+ s->regs.dst_offset +
+ s->regs.dst_y * surface_stride(ds),
+ s->regs.dst_height * surface_stride(ds));
+ }
+ s->regs.dst_x += s->regs.dst_width;
+ s->regs.dst_y += s->regs.dst_height;
+ break;
+ }
+ case ROP3_PATCOPY:
+ case ROP3_BLACKNESS:
+ case ROP3_WHITENESS:
+ {
+ uint8_t *dst_bits, *end;
+ int dst_stride, bpp = ati_bpp_from_datatype(s);
+ uint32_t filler = 0;
+ dst_bits = s->vga.vram_ptr + s->regs.dst_offset;
+ dst_stride = s->regs.dst_pitch;
+
+ if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) {
+ dst_bits += s->regs.crtc_offset & 0x07ffffff;
+ dst_stride *= bpp;
+ }
+ dst_stride /= sizeof(uint32_t);
+
+ switch (s->regs.dp_mix & GMC_ROP3_MASK) {
+ case ROP3_PATCOPY:
+ filler = bswap32(s->regs.dp_brush_frgd_clr);
+ break;
+ case ROP3_BLACKNESS:
+ filler = rgb_to_pixel32(s->vga.palette[0], s->vga.palette[1],
+ s->vga.palette[2]) << 8 | 0xff;
+ break;
+ case ROP3_WHITENESS:
+ filler = rgb_to_pixel32(s->vga.palette[3], s->vga.palette[4],
+ s->vga.palette[5]) << 8 | 0xff;
+ break;
+ }
+
+ DPRINTF("pixman_fill(%p, %d, %d, %d, %d, %d, %d, %x)\n",
+ dst_bits, dst_stride, bpp,
+ s->regs.dst_x, s->regs.dst_y,
+ s->regs.dst_width, s->regs.dst_height,
+ filler);
+ end = s->vga.vram_ptr + s->vga.vram_size;
+ if (dst_bits >= end ||
+ dst_bits + (s->regs.dst_y + s->regs.dst_height) * dst_stride +
+ s->regs.dst_x >= end) {
+ qemu_log_mask(LOG_UNIMP, "blt outside vram not implemented\n");
+ return;
+ }
+ pixman_fill((uint32_t *)dst_bits, dst_stride, bpp,
+ s->regs.dst_x, s->regs.dst_y,
+ s->regs.dst_width, s->regs.dst_height,
+ filler);
+ if (dst_bits >= s->vga.vram_ptr + s->vga.vbe_start_addr &&
+ dst_bits < s->vga.vram_ptr + s->vga.vbe_start_addr +
+ s->vga.vbe_regs[VBE_DISPI_INDEX_YRES] * s->vga.vbe_line_offset) {
+ memory_region_set_dirty(&s->vga.vram, s->vga.vbe_start_addr +
+ s->regs.dst_offset +
+ s->regs.dst_y * surface_stride(ds),
+ s->regs.dst_height * surface_stride(ds));
+ }
+ s->regs.dst_y += s->regs.dst_height;
+ break;
+ }
+ default:
+ qemu_log_mask(LOG_UNIMP, "Unimplemented ati_2d blt op %x\n",
+ (s->regs.dp_mix & GMC_ROP3_MASK) >> 16);
+ }
+}
diff --git a/hw/display/ati_dbg.c b/hw/display/ati_dbg.c
new file mode 100644
index 0000000000..1e6c32624e
--- /dev/null
+++ b/hw/display/ati_dbg.c
@@ -0,0 +1,259 @@
+#include "ati_int.h"
+
+#ifdef DEBUG_ATI
+struct ati_regdesc {
+ const char *name;
+ int num;
+};
+
+static struct ati_regdesc ati_reg_names[] = {
+ {"MM_INDEX", 0x0000},
+ {"MM_DATA", 0x0004},
+ {"CLOCK_CNTL_INDEX", 0x0008},
+ {"CLOCK_CNTL_DATA", 0x000c},
+ {"BIOS_0_SCRATCH", 0x0010},
+ {"BUS_CNTL", 0x0030},
+ {"BUS_CNTL1", 0x0034},
+ {"GEN_INT_CNTL", 0x0040},
+ {"CRTC_GEN_CNTL", 0x0050},
+ {"CRTC_EXT_CNTL", 0x0054},
+ {"DAC_CNTL", 0x0058},
+ {"GPIO_MONID", 0x0068},
+ {"I2C_CNTL_1", 0x0094},
+ {"PALETTE_INDEX", 0x00b0},
+ {"PALETTE_DATA", 0x00b4},
+ {"CNFG_CNTL", 0x00e0},
+ {"GEN_RESET_CNTL", 0x00f0},
+ {"CNFG_MEMSIZE", 0x00f8},
+ {"MEM_CNTL", 0x0140},
+ {"MC_FB_LOCATION", 0x0148},
+ {"MC_AGP_LOCATION", 0x014C},
+ {"MC_STATUS", 0x0150},
+ {"MEM_POWER_MISC", 0x015c},
+ {"AGP_BASE", 0x0170},
+ {"AGP_CNTL", 0x0174},
+ {"AGP_APER_OFFSET", 0x0178},
+ {"PCI_GART_PAGE", 0x017c},
+ {"PC_NGUI_MODE", 0x0180},
+ {"PC_NGUI_CTLSTAT", 0x0184},
+ {"MPP_TB_CONFIG", 0x01C0},
+ {"MPP_GP_CONFIG", 0x01C8},
+ {"VIPH_CONTROL", 0x01D0},
+ {"CRTC_H_TOTAL_DISP", 0x0200},
+ {"CRTC_H_SYNC_STRT_WID", 0x0204},
+ {"CRTC_V_TOTAL_DISP", 0x0208},
+ {"CRTC_V_SYNC_STRT_WID", 0x020c},
+ {"CRTC_VLINE_CRNT_VLINE", 0x0210},
+ {"CRTC_CRNT_FRAME", 0x0214},
+ {"CRTC_GUI_TRIG_VLINE", 0x0218},
+ {"CRTC_OFFSET", 0x0224},
+ {"CRTC_OFFSET_CNTL", 0x0228},
+ {"CRTC_PITCH", 0x022c},
+ {"OVR_CLR", 0x0230},
+ {"OVR_WID_LEFT_RIGHT", 0x0234},
+ {"OVR_WID_TOP_BOTTOM", 0x0238},
+ {"CUR_OFFSET", 0x0260},
+ {"CUR_HORZ_VERT_POSN", 0x0264},
+ {"CUR_HORZ_VERT_OFF", 0x0268},
+ {"CUR_CLR0", 0x026c},
+ {"CUR_CLR1", 0x0270},
+ {"LVDS_GEN_CNTL", 0x02d0},
+ {"DDA_CONFIG", 0x02e0},
+ {"DDA_ON_OFF", 0x02e4},
+ {"VGA_DDA_CONFIG", 0x02e8},
+ {"VGA_DDA_ON_OFF", 0x02ec},
+ {"CRTC2_H_TOTAL_DISP", 0x0300},
+ {"CRTC2_H_SYNC_STRT_WID", 0x0304},
+ {"CRTC2_V_TOTAL_DISP", 0x0308},
+ {"CRTC2_V_SYNC_STRT_WID", 0x030c},
+ {"CRTC2_VLINE_CRNT_VLINE", 0x0310},
+ {"CRTC2_CRNT_FRAME", 0x0314},
+ {"CRTC2_GUI_TRIG_VLINE", 0x0318},
+ {"CRTC2_OFFSET", 0x0324},
+ {"CRTC2_OFFSET_CNTL", 0x0328},
+ {"CRTC2_PITCH", 0x032c},
+ {"DDA2_CONFIG", 0x03e0},
+ {"DDA2_ON_OFF", 0x03e4},
+ {"CRTC2_GEN_CNTL", 0x03f8},
+ {"CRTC2_STATUS", 0x03fc},
+ {"OV0_SCALE_CNTL", 0x0420},
+ {"SUBPIC_CNTL", 0x0540},
+ {"PM4_BUFFER_OFFSET", 0x0700},
+ {"PM4_BUFFER_CNTL", 0x0704},
+ {"PM4_BUFFER_WM_CNTL", 0x0708},
+ {"PM4_BUFFER_DL_RPTR_ADDR", 0x070c},
+ {"PM4_BUFFER_DL_RPTR", 0x0710},
+ {"PM4_BUFFER_DL_WPTR", 0x0714},
+ {"PM4_VC_FPU_SETUP", 0x071c},
+ {"PM4_FPU_CNTL", 0x0720},
+ {"PM4_VC_FORMAT", 0x0724},
+ {"PM4_VC_CNTL", 0x0728},
+ {"PM4_VC_I01", 0x072c},
+ {"PM4_VC_VLOFF", 0x0730},
+ {"PM4_VC_VLSIZE", 0x0734},
+ {"PM4_IW_INDOFF", 0x0738},
+ {"PM4_IW_INDSIZE", 0x073c},
+ {"PM4_FPU_FPX0", 0x0740},
+ {"PM4_FPU_FPY0", 0x0744},
+ {"PM4_FPU_FPX1", 0x0748},
+ {"PM4_FPU_FPY1", 0x074c},
+ {"PM4_FPU_FPX2", 0x0750},
+ {"PM4_FPU_FPY2", 0x0754},
+ {"PM4_FPU_FPY3", 0x0758},
+ {"PM4_FPU_FPY4", 0x075c},
+ {"PM4_FPU_FPY5", 0x0760},
+ {"PM4_FPU_FPY6", 0x0764},
+ {"PM4_FPU_FPR", 0x0768},
+ {"PM4_FPU_FPG", 0x076c},
+ {"PM4_FPU_FPB", 0x0770},
+ {"PM4_FPU_FPA", 0x0774},
+ {"PM4_FPU_INTXY0", 0x0780},
+ {"PM4_FPU_INTXY1", 0x0784},
+ {"PM4_FPU_INTXY2", 0x0788},
+ {"PM4_FPU_INTARGB", 0x078c},
+ {"PM4_FPU_FPTWICEAREA", 0x0790},
+ {"PM4_FPU_DMAJOR01", 0x0794},
+ {"PM4_FPU_DMAJOR12", 0x0798},
+ {"PM4_FPU_DMAJOR02", 0x079c},
+ {"PM4_FPU_STAT", 0x07a0},
+ {"PM4_STAT", 0x07b8},
+ {"PM4_TEST_CNTL", 0x07d0},
+ {"PM4_MICROCODE_ADDR", 0x07d4},
+ {"PM4_MICROCODE_RADDR", 0x07d8},
+ {"PM4_MICROCODE_DATAH", 0x07dc},
+ {"PM4_MICROCODE_DATAL", 0x07e0},
+ {"PM4_CMDFIFO_ADDR", 0x07e4},
+ {"PM4_CMDFIFO_DATAH", 0x07e8},
+ {"PM4_CMDFIFO_DATAL", 0x07ec},
+ {"PM4_BUFFER_ADDR", 0x07f0},
+ {"PM4_BUFFER_DATAH", 0x07f4},
+ {"PM4_BUFFER_DATAL", 0x07f8},
+ {"PM4_MICRO_CNTL", 0x07fc},
+ {"CAP0_TRIG_CNTL", 0x0950},
+ {"CAP1_TRIG_CNTL", 0x09c0},
+ {"RBBM_STATUS", 0x0e40},
+ {"PM4_FIFO_DATA_EVEN", 0x1000},
+ {"PM4_FIFO_DATA_ODD", 0x1004},
+ {"DST_OFFSET", 0x1404},
+ {"DST_PITCH", 0x1408},
+ {"DST_WIDTH", 0x140c},
+ {"DST_HEIGHT", 0x1410},
+ {"SRC_X", 0x1414},
+ {"SRC_Y", 0x1418},
+ {"DST_X", 0x141c},
+ {"DST_Y", 0x1420},
+ {"SRC_PITCH_OFFSET", 0x1428},
+ {"DST_PITCH_OFFSET", 0x142c},
+ {"SRC_Y_X", 0x1434},
+ {"DST_Y_X", 0x1438},
+ {"DST_HEIGHT_WIDTH", 0x143c},
+ {"DP_GUI_MASTER_CNTL", 0x146c},
+ {"BRUSH_SCALE", 0x1470},
+ {"BRUSH_Y_X", 0x1474},
+ {"DP_BRUSH_BKGD_CLR", 0x1478},
+ {"DP_BRUSH_FRGD_CLR", 0x147c},
+ {"DST_WIDTH_X", 0x1588},
+ {"DST_HEIGHT_WIDTH_8", 0x158c},
+ {"SRC_X_Y", 0x1590},
+ {"DST_X_Y", 0x1594},
+ {"DST_WIDTH_HEIGHT", 0x1598},
+ {"DST_WIDTH_X_INCY", 0x159c},
+ {"DST_HEIGHT_Y", 0x15a0},
+ {"DST_X_SUB", 0x15a4},
+ {"DST_Y_SUB", 0x15a8},
+ {"SRC_OFFSET", 0x15ac},
+ {"SRC_PITCH", 0x15b0},
+ {"DST_HEIGHT_WIDTH_BW", 0x15b4},
+ {"CLR_CMP_CNTL", 0x15c0},
+ {"CLR_CMP_CLR_SRC", 0x15c4},
+ {"CLR_CMP_CLR_DST", 0x15c8},
+ {"CLR_CMP_MASK", 0x15cc},
+ {"DP_SRC_FRGD_CLR", 0x15d8},
+ {"DP_SRC_BKGD_CLR", 0x15dc},
+ {"DST_BRES_ERR", 0x1628},
+ {"DST_BRES_INC", 0x162c},
+ {"DST_BRES_DEC", 0x1630},
+ {"DST_BRES_LNTH", 0x1634},
+ {"DST_BRES_LNTH_SUB", 0x1638},
+ {"SC_LEFT", 0x1640},
+ {"SC_RIGHT", 0x1644},
+ {"SC_TOP", 0x1648},
+ {"SC_BOTTOM", 0x164c},
+ {"SRC_SC_RIGHT", 0x1654},
+ {"SRC_SC_BOTTOM", 0x165c},
+ {"GUI_DEBUG0", 0x16a0},
+ {"GUI_DEBUG1", 0x16a4},
+ {"GUI_TIMEOUT", 0x16b0},
+ {"GUI_TIMEOUT0", 0x16b4},
+ {"GUI_TIMEOUT1", 0x16b8},
+ {"GUI_PROBE", 0x16bc},
+ {"DP_CNTL", 0x16c0},
+ {"DP_DATATYPE", 0x16c4},
+ {"DP_MIX", 0x16c8},
+ {"DP_WRITE_MASK", 0x16cc},
+ {"DP_CNTL_XDIR_YDIR_YMAJOR", 0x16d0},
+ {"DEFAULT_OFFSET", 0x16e0},
+ {"DEFAULT_PITCH", 0x16e4},
+ {"DEFAULT_SC_BOTTOM_RIGHT", 0x16e8},
+ {"SC_TOP_LEFT", 0x16ec},
+ {"SC_BOTTOM_RIGHT", 0x16f0},
+ {"SRC_SC_BOTTOM_RIGHT", 0x16f4},
+ {"DST_TILE", 0x1700},
+ {"WAIT_UNTIL", 0x1720},
+ {"CACHE_CNTL", 0x1724},
+ {"GUI_STAT", 0x1740},
+ {"PC_GUI_MODE", 0x1744},
+ {"PC_GUI_CTLSTAT", 0x1748},
+ {"PC_DEBUG_MODE", 0x1760},
+ {"BRES_DST_ERR_DEC", 0x1780},
+ {"TRAIL_BRES_T12_ERR_DEC", 0x1784},
+ {"TRAIL_BRES_T12_INC", 0x1788},
+ {"DP_T12_CNTL", 0x178c},
+ {"DST_BRES_T1_LNTH", 0x1790},
+ {"DST_BRES_T2_LNTH", 0x1794},
+ {"SCALE_SRC_HEIGHT_WIDTH", 0x1994},
+ {"SCALE_OFFSET_0", 0x1998},
+ {"SCALE_PITCH", 0x199c},
+ {"SCALE_X_INC", 0x19a0},
+ {"SCALE_Y_INC", 0x19a4},
+ {"SCALE_HACC", 0x19a8},
+ {"SCALE_VACC", 0x19ac},
+ {"SCALE_DST_X_Y", 0x19b0},
+ {"SCALE_DST_HEIGHT_WIDTH", 0x19b4},
+ {"SCALE_3D_CNTL", 0x1a00},
+ {"SCALE_3D_DATATYPE", 0x1a20},
+ {"SETUP_CNTL", 0x1bc4},
+ {"SOLID_COLOR", 0x1bc8},
+ {"WINDOW_XY_OFFSET", 0x1bcc},
+ {"DRAW_LINE_POINT", 0x1bd0},
+ {"SETUP_CNTL_PM4", 0x1bd4},
+ {"DST_PITCH_OFFSET_C", 0x1c80},
+ {"DP_GUI_MASTER_CNTL_C", 0x1c84},
+ {"SC_TOP_LEFT_C", 0x1c88},
+ {"SC_BOTTOM_RIGHT_C", 0x1c8c},
+ {"CLR_CMP_MASK_3D", 0x1A28},
+ {"MISC_3D_STATE_CNTL_REG", 0x1CA0},
+ {"MC_SRC1_CNTL", 0x19D8},
+ {"TEX_CNTL", 0x1800},
+ {"RAGE128_MPP_TB_CONFIG", 0x01c0},
+ {NULL, -1}
+};
+
+const char *ati_reg_name(int num)
+{
+ int i;
+
+ num &= ~3;
+ for (i = 0; ati_reg_names[i].name; i++) {
+ if (ati_reg_names[i].num == num) {
+ return ati_reg_names[i].name;
+ }
+ }
+ return "unknown";
+}
+#else
+const char *ati_reg_name(int num)
+{
+ return "";
+}
+#endif
diff --git a/hw/display/ati_int.h b/hw/display/ati_int.h
new file mode 100644
index 0000000000..50a34e19fc
--- /dev/null
+++ b/hw/display/ati_int.h
@@ -0,0 +1,93 @@
+/*
+ * QEMU ATI SVGA emulation
+ *
+ * Copyright (c) 2019 BALATON Zoltan
+ *
+ * This work is licensed under the GNU GPL license version 2 or later.
+ */
+
+#ifndef ATI_INT_H
+#define ATI_INT_H
+
+#include "qemu/osdep.h"
+#include "hw/pci/pci.h"
+#include "vga_int.h"
+
+/*#define DEBUG_ATI*/
+
+#ifdef DEBUG_ATI
+#define DPRINTF(fmt, ...) printf("%s: " fmt, __func__, ## __VA_ARGS__)
+#else
+#define DPRINTF(fmt, ...) do {} while (0)
+#endif
+
+#define PCI_VENDOR_ID_ATI 0x1002
+/* Rage128 Pro GL */
+#define PCI_DEVICE_ID_ATI_RAGE128_PF 0x5046
+/* Radeon RV100 (VE) */
+#define PCI_DEVICE_ID_ATI_RADEON_QY 0x5159
+
+#define TYPE_ATI_VGA "ati-vga"
+#define ATI_VGA(obj) OBJECT_CHECK(ATIVGAState, (obj), TYPE_ATI_VGA)
+
+typedef struct ATIVGARegs {
+ uint32_t mm_index;
+ uint32_t bios_scratch[8];
+ uint32_t crtc_gen_cntl;
+ uint32_t crtc_ext_cntl;
+ uint32_t dac_cntl;
+ uint32_t crtc_h_total_disp;
+ uint32_t crtc_h_sync_strt_wid;
+ uint32_t crtc_v_total_disp;
+ uint32_t crtc_v_sync_strt_wid;
+ uint32_t crtc_offset;
+ uint32_t crtc_offset_cntl;
+ uint32_t crtc_pitch;
+ uint32_t cur_offset;
+ uint32_t cur_hv_pos;
+ uint32_t cur_hv_offs;
+ uint32_t cur_color0;
+ uint32_t cur_color1;
+ uint32_t dst_offset;
+ uint32_t dst_pitch;
+ uint32_t dst_tile;
+ uint32_t dst_width;
+ uint32_t dst_height;
+ uint32_t src_offset;
+ uint32_t src_pitch;
+ uint32_t src_tile;
+ uint32_t src_x;
+ uint32_t src_y;
+ uint32_t dst_x;
+ uint32_t dst_y;
+ uint32_t dp_gui_master_cntl;
+ uint32_t dp_brush_bkgd_clr;
+ uint32_t dp_brush_frgd_clr;
+ uint32_t dp_src_frgd_clr;
+ uint32_t dp_src_bkgd_clr;
+ uint32_t dp_cntl;
+ uint32_t dp_datatype;
+ uint32_t dp_mix;
+ uint32_t dp_write_mask;
+ uint32_t default_offset;
+ uint32_t default_pitch;
+ uint32_t default_sc_bottom_right;
+} ATIVGARegs;
+
+typedef struct ATIVGAState {
+ PCIDevice dev;
+ VGACommonState vga;
+ char *model;
+ uint16_t dev_id;
+ uint16_t mode;
+ QEMUCursor *cursor;
+ MemoryRegion io;
+ MemoryRegion mm;
+ ATIVGARegs regs;
+} ATIVGAState;
+
+const char *ati_reg_name(int num);
+
+void ati_2d_blt(ATIVGAState *s);
+
+#endif /* ATI_INT_H */
diff --git a/hw/display/ati_regs.h b/hw/display/ati_regs.h
new file mode 100644
index 0000000000..923bfd33ce
--- /dev/null
+++ b/hw/display/ati_regs.h
@@ -0,0 +1,461 @@
+/*
+ * ATI VGA register definitions
+ *
+ * based on:
+ * linux/include/video/aty128.h
+ * Register definitions for ATI Rage128 boards
+ * Anthony Tong <atong@uiuc.edu>, 1999
+ * Brad Douglas <brad@neruo.com>, 2000
+ *
+ * and linux/include/video/radeon.h
+ *
+ * This work is licensed under the GNU GPL license version 2.
+ */
+
+/*
+ * Register mapping:
+ * 0x0000-0x00ff Misc regs also accessible via io and mmio space
+ * 0x0100-0x0eff Misc regs only accessible via mmio
+ * 0x0f00-0x0fff Read-only copy of PCI config regs
+ * 0x1000-0x13ff Concurrent Command Engine (CCE) regs
+ * 0x1400-0x1fff GUI (drawing engine) regs
+ */
+
+#ifndef ATI_REGS_H
+#define ATI_REGS_H
+
+#undef DEFAULT_PITCH /* needed for mingw builds */
+
+#define MM_INDEX 0x0000
+#define MM_DATA 0x0004
+#define CLOCK_CNTL_INDEX 0x0008
+#define CLOCK_CNTL_DATA 0x000c
+#define BIOS_0_SCRATCH 0x0010
+#define BUS_CNTL 0x0030
+#define BUS_CNTL1 0x0034
+#define GEN_INT_CNTL 0x0040
+#define CRTC_GEN_CNTL 0x0050
+#define CRTC_EXT_CNTL 0x0054
+#define DAC_CNTL 0x0058
+#define GPIO_MONID 0x0068
+#define I2C_CNTL_1 0x0094
+#define PALETTE_INDEX 0x00b0
+#define PALETTE_DATA 0x00b4
+#define CNFG_CNTL 0x00e0
+#define GEN_RESET_CNTL 0x00f0
+#define CNFG_MEMSIZE 0x00f8
+#define MEM_CNTL 0x0140
+#define MC_FB_LOCATION 0x0148
+#define MC_AGP_LOCATION 0x014C
+#define MC_STATUS 0x0150
+#define MEM_POWER_MISC 0x015c
+#define AGP_BASE 0x0170
+#define AGP_CNTL 0x0174
+#define AGP_APER_OFFSET 0x0178
+#define PCI_GART_PAGE 0x017c
+#define PC_NGUI_MODE 0x0180
+#define PC_NGUI_CTLSTAT 0x0184
+#define MPP_TB_CONFIG 0x01C0
+#define MPP_GP_CONFIG 0x01C8
+#define VIPH_CONTROL 0x01D0
+#define CRTC_H_TOTAL_DISP 0x0200
+#define CRTC_H_SYNC_STRT_WID 0x0204
+#define CRTC_V_TOTAL_DISP 0x0208
+#define CRTC_V_SYNC_STRT_WID 0x020c
+#define CRTC_VLINE_CRNT_VLINE 0x0210
+#define CRTC_CRNT_FRAME 0x0214
+#define CRTC_GUI_TRIG_VLINE 0x0218
+#define CRTC_OFFSET 0x0224
+#define CRTC_OFFSET_CNTL 0x0228
+#define CRTC_PITCH 0x022c
+#define OVR_CLR 0x0230
+#define OVR_WID_LEFT_RIGHT 0x0234
+#define OVR_WID_TOP_BOTTOM 0x0238
+#define CUR_OFFSET 0x0260
+#define CUR_HORZ_VERT_POSN 0x0264
+#define CUR_HORZ_VERT_OFF 0x0268
+#define CUR_CLR0 0x026c
+#define CUR_CLR1 0x0270
+#define LVDS_GEN_CNTL 0x02d0
+#define DDA_CONFIG 0x02e0
+#define DDA_ON_OFF 0x02e4
+#define VGA_DDA_CONFIG 0x02e8
+#define VGA_DDA_ON_OFF 0x02ec
+#define CRTC2_H_TOTAL_DISP 0x0300
+#define CRTC2_H_SYNC_STRT_WID 0x0304
+#define CRTC2_V_TOTAL_DISP 0x0308
+#define CRTC2_V_SYNC_STRT_WID 0x030c
+#define CRTC2_VLINE_CRNT_VLINE 0x0310
+#define CRTC2_CRNT_FRAME 0x0314
+#define CRTC2_GUI_TRIG_VLINE 0x0318
+#define CRTC2_OFFSET 0x0324
+#define CRTC2_OFFSET_CNTL 0x0328
+#define CRTC2_PITCH 0x032c
+#define DDA2_CONFIG 0x03e0
+#define DDA2_ON_OFF 0x03e4
+#define CRTC2_GEN_CNTL 0x03f8
+#define CRTC2_STATUS 0x03fc
+#define OV0_SCALE_CNTL 0x0420
+#define SUBPIC_CNTL 0x0540
+#define PM4_BUFFER_OFFSET 0x0700
+#define PM4_BUFFER_CNTL 0x0704
+#define PM4_BUFFER_WM_CNTL 0x0708
+#define PM4_BUFFER_DL_RPTR_ADDR 0x070c
+#define PM4_BUFFER_DL_RPTR 0x0710
+#define PM4_BUFFER_DL_WPTR 0x0714
+#define PM4_VC_FPU_SETUP 0x071c
+#define PM4_FPU_CNTL 0x0720
+#define PM4_VC_FORMAT 0x0724
+#define PM4_VC_CNTL 0x0728
+#define PM4_VC_I01 0x072c
+#define PM4_VC_VLOFF 0x0730
+#define PM4_VC_VLSIZE 0x0734
+#define PM4_IW_INDOFF 0x0738
+#define PM4_IW_INDSIZE 0x073c
+#define PM4_FPU_FPX0 0x0740
+#define PM4_FPU_FPY0 0x0744
+#define PM4_FPU_FPX1 0x0748
+#define PM4_FPU_FPY1 0x074c
+#define PM4_FPU_FPX2 0x0750
+#define PM4_FPU_FPY2 0x0754
+#define PM4_FPU_FPY3 0x0758
+#define PM4_FPU_FPY4 0x075c
+#define PM4_FPU_FPY5 0x0760
+#define PM4_FPU_FPY6 0x0764
+#define PM4_FPU_FPR 0x0768
+#define PM4_FPU_FPG 0x076c
+#define PM4_FPU_FPB 0x0770
+#define PM4_FPU_FPA 0x0774
+#define PM4_FPU_INTXY0 0x0780
+#define PM4_FPU_INTXY1 0x0784
+#define PM4_FPU_INTXY2 0x0788
+#define PM4_FPU_INTARGB 0x078c
+#define PM4_FPU_FPTWICEAREA 0x0790
+#define PM4_FPU_DMAJOR01 0x0794
+#define PM4_FPU_DMAJOR12 0x0798
+#define PM4_FPU_DMAJOR02 0x079c
+#define PM4_FPU_STAT 0x07a0
+#define PM4_STAT 0x07b8
+#define PM4_TEST_CNTL 0x07d0
+#define PM4_MICROCODE_ADDR 0x07d4
+#define PM4_MICROCODE_RADDR 0x07d8
+#define PM4_MICROCODE_DATAH 0x07dc
+#define PM4_MICROCODE_DATAL 0x07e0
+#define PM4_CMDFIFO_ADDR 0x07e4
+#define PM4_CMDFIFO_DATAH 0x07e8
+#define PM4_CMDFIFO_DATAL 0x07ec
+#define PM4_BUFFER_ADDR 0x07f0
+#define PM4_BUFFER_DATAH 0x07f4
+#define PM4_BUFFER_DATAL 0x07f8
+#define PM4_MICRO_CNTL 0x07fc
+#define CAP0_TRIG_CNTL 0x0950
+#define CAP1_TRIG_CNTL 0x09c0
+
+#define RBBM_STATUS 0x0e40
+
+/*
+ * GUI Block Memory Mapped Registers
+ * These registers are FIFOed.
+ */
+#define PM4_FIFO_DATA_EVEN 0x1000
+#define PM4_FIFO_DATA_ODD 0x1004
+
+#define DST_OFFSET 0x1404
+#define DST_PITCH 0x1408
+#define DST_WIDTH 0x140c
+#define DST_HEIGHT 0x1410
+#define SRC_X 0x1414
+#define SRC_Y 0x1418
+#define DST_X 0x141c
+#define DST_Y 0x1420
+#define SRC_PITCH_OFFSET 0x1428
+#define DST_PITCH_OFFSET 0x142c
+#define SRC_Y_X 0x1434
+#define DST_Y_X 0x1438
+#define DST_HEIGHT_WIDTH 0x143c
+#define DP_GUI_MASTER_CNTL 0x146c
+#define BRUSH_SCALE 0x1470
+#define BRUSH_Y_X 0x1474
+#define DP_BRUSH_BKGD_CLR 0x1478
+#define DP_BRUSH_FRGD_CLR 0x147c
+#define DST_WIDTH_X 0x1588
+#define DST_HEIGHT_WIDTH_8 0x158c
+#define SRC_X_Y 0x1590
+#define DST_X_Y 0x1594
+#define DST_WIDTH_HEIGHT 0x1598
+#define DST_WIDTH_X_INCY 0x159c
+#define DST_HEIGHT_Y 0x15a0
+#define DST_X_SUB 0x15a4
+#define DST_Y_SUB 0x15a8
+#define SRC_OFFSET 0x15ac
+#define SRC_PITCH 0x15b0
+#define DST_HEIGHT_WIDTH_BW 0x15b4
+#define CLR_CMP_CNTL 0x15c0
+#define CLR_CMP_CLR_SRC 0x15c4
+#define CLR_CMP_CLR_DST 0x15c8
+#define CLR_CMP_MASK 0x15cc
+#define DP_SRC_FRGD_CLR 0x15d8
+#define DP_SRC_BKGD_CLR 0x15dc
+#define DST_BRES_ERR 0x1628
+#define DST_BRES_INC 0x162c
+#define DST_BRES_DEC 0x1630
+#define DST_BRES_LNTH 0x1634
+#define DST_BRES_LNTH_SUB 0x1638
+#define SC_LEFT 0x1640
+#define SC_RIGHT 0x1644
+#define SC_TOP 0x1648
+#define SC_BOTTOM 0x164c
+#define SRC_SC_RIGHT 0x1654
+#define SRC_SC_BOTTOM 0x165c
+#define GUI_DEBUG0 0x16a0
+#define GUI_DEBUG1 0x16a4
+#define GUI_TIMEOUT 0x16b0
+#define GUI_TIMEOUT0 0x16b4
+#define GUI_TIMEOUT1 0x16b8
+#define GUI_PROBE 0x16bc
+#define DP_CNTL 0x16c0
+#define DP_DATATYPE 0x16c4
+#define DP_MIX 0x16c8
+#define DP_WRITE_MASK 0x16cc
+#define DP_CNTL_XDIR_YDIR_YMAJOR 0x16d0
+#define DEFAULT_OFFSET 0x16e0
+#define DEFAULT_PITCH 0x16e4
+#define DEFAULT_SC_BOTTOM_RIGHT 0x16e8
+#define SC_TOP_LEFT 0x16ec
+#define SC_BOTTOM_RIGHT 0x16f0
+#define SRC_SC_BOTTOM_RIGHT 0x16f4
+#define DST_TILE 0x1700
+#define WAIT_UNTIL 0x1720
+#define CACHE_CNTL 0x1724
+#define GUI_STAT 0x1740
+#define PC_GUI_MODE 0x1744
+#define PC_GUI_CTLSTAT 0x1748
+#define PC_DEBUG_MODE 0x1760
+#define BRES_DST_ERR_DEC 0x1780
+#define TRAIL_BRES_T12_ERR_DEC 0x1784
+#define TRAIL_BRES_T12_INC 0x1788
+#define DP_T12_CNTL 0x178c
+#define DST_BRES_T1_LNTH 0x1790
+#define DST_BRES_T2_LNTH 0x1794
+#define SCALE_SRC_HEIGHT_WIDTH 0x1994
+#define SCALE_OFFSET_0 0x1998
+#define SCALE_PITCH 0x199c
+#define SCALE_X_INC 0x19a0
+#define SCALE_Y_INC 0x19a4
+#define SCALE_HACC 0x19a8
+#define SCALE_VACC 0x19ac
+#define SCALE_DST_X_Y 0x19b0
+#define SCALE_DST_HEIGHT_WIDTH 0x19b4
+#define SCALE_3D_CNTL 0x1a00
+#define SCALE_3D_DATATYPE 0x1a20
+#define SETUP_CNTL 0x1bc4
+#define SOLID_COLOR 0x1bc8
+#define WINDOW_XY_OFFSET 0x1bcc
+#define DRAW_LINE_POINT 0x1bd0
+#define SETUP_CNTL_PM4 0x1bd4
+#define DST_PITCH_OFFSET_C 0x1c80
+#define DP_GUI_MASTER_CNTL_C 0x1c84
+#define SC_TOP_LEFT_C 0x1c88
+#define SC_BOTTOM_RIGHT_C 0x1c8c
+
+#define CLR_CMP_MASK_3D 0x1A28
+#define MISC_3D_STATE_CNTL_REG 0x1CA0
+#define MC_SRC1_CNTL 0x19D8
+#define TEX_CNTL 0x1800
+
+/* CONSTANTS */
+#define GUI_ACTIVE 0x80000000
+#define ENGINE_IDLE 0x0
+
+#define PLL_WR_EN 0x00000080
+
+#define CLK_PIN_CNTL 0x01
+#define PPLL_CNTL 0x02
+#define PPLL_REF_DIV 0x03
+#define PPLL_DIV_0 0x04
+#define PPLL_DIV_1 0x05
+#define PPLL_DIV_2 0x06
+#define PPLL_DIV_3 0x07
+#define VCLK_ECP_CNTL 0x08
+#define HTOTAL_CNTL 0x09
+#define X_MPLL_REF_FB_DIV 0x0a
+#define XPLL_CNTL 0x0b
+#define XDLL_CNTL 0x0c
+#define XCLK_CNTL 0x0d
+#define MPLL_CNTL 0x0e
+#define MCLK_CNTL 0x0f
+#define AGP_PLL_CNTL 0x10
+#define FCP_CNTL 0x12
+#define PLL_TEST_CNTL 0x13
+#define P2PLL_CNTL 0x2a
+#define P2PLL_REF_DIV 0x2b
+#define P2PLL_DIV_0 0x2b
+#define POWER_MANAGEMENT 0x2f
+
+#define PPLL_RESET 0x00000001
+#define PPLL_ATOMIC_UPDATE_EN 0x00010000
+#define PPLL_VGA_ATOMIC_UPDATE_EN 0x00020000
+#define PPLL_REF_DIV_MASK 0x000003FF
+#define PPLL_FB3_DIV_MASK 0x000007FF
+#define PPLL_POST3_DIV_MASK 0x00070000
+#define PPLL_ATOMIC_UPDATE_R 0x00008000
+#define PPLL_ATOMIC_UPDATE_W 0x00008000
+#define MEM_CFG_TYPE_MASK 0x00000003
+#define XCLK_SRC_SEL_MASK 0x00000007
+#define XPLL_FB_DIV_MASK 0x0000FF00
+#define X_MPLL_REF_DIV_MASK 0x000000FF
+
+/* Config control values (CONFIG_CNTL) */
+#define CFG_VGA_IO_DIS 0x00000400
+
+/* CRTC control values (CRTC_GEN_CNTL) */
+#define CRTC_CSYNC_EN 0x00000010
+
+#define CRTC2_DBL_SCAN_EN 0x00000001
+#define CRTC2_DISPLAY_DIS 0x00800000
+#define CRTC2_FIFO_EXTSENSE 0x00200000
+#define CRTC2_ICON_EN 0x00100000
+#define CRTC2_CUR_EN 0x00010000
+#define CRTC2_EXT_DISP_EN 0x01000000
+#define CRTC2_EN 0x02000000
+#define CRTC2_DISP_REQ_EN_B 0x04000000
+
+#define CRTC_PIX_WIDTH_MASK 0x00000700
+#define CRTC_PIX_WIDTH_4BPP 0x00000100
+#define CRTC_PIX_WIDTH_8BPP 0x00000200
+#define CRTC_PIX_WIDTH_15BPP 0x00000300
+#define CRTC_PIX_WIDTH_16BPP 0x00000400
+#define CRTC_PIX_WIDTH_24BPP 0x00000500
+#define CRTC_PIX_WIDTH_32BPP 0x00000600
+
+/* DAC_CNTL bit constants */
+#define DAC_8BIT_EN 0x00000100
+#define DAC_MASK 0xFF000000
+#define DAC_BLANKING 0x00000004
+#define DAC_RANGE_CNTL 0x00000003
+#define DAC_CLK_SEL 0x00000010
+#define DAC_PALETTE_ACCESS_CNTL 0x00000020
+#define DAC_PALETTE2_SNOOP_EN 0x00000040
+#define DAC_PDWN 0x00008000
+
+/* CRTC_EXT_CNTL */
+#define CRT_CRTC_DISPLAY_DIS 0x00000400
+#define CRT_CRTC_ON 0x00008000
+
+/* GEN_RESET_CNTL bit constants */
+#define SOFT_RESET_GUI 0x00000001
+#define SOFT_RESET_VCLK 0x00000100
+#define SOFT_RESET_PCLK 0x00000200
+#define SOFT_RESET_ECP 0x00000400
+#define SOFT_RESET_DISPENG_XCLK 0x00000800
+
+/* PC_GUI_CTLSTAT bit constants */
+#define PC_BUSY_INIT 0x10000000
+#define PC_BUSY_GUI 0x20000000
+#define PC_BUSY_NGUI 0x40000000
+#define PC_BUSY 0x80000000
+
+#define BUS_MASTER_DIS 0x00000040
+#define PM4_BUFFER_CNTL_NONPM4 0x00000000
+
+/* DP_DATATYPE bit constants */
+#define DST_8BPP 0x00000002
+#define DST_15BPP 0x00000003
+#define DST_16BPP 0x00000004
+#define DST_24BPP 0x00000005
+#define DST_32BPP 0x00000006
+
+#define BRUSH_SOLIDCOLOR 0x00000d00
+
+/* DP_GUI_MASTER_CNTL bit constants */
+#define GMC_SRC_PITCH_OFFSET_DEFAULT 0x00000000
+#define GMC_DST_PITCH_OFFSET_DEFAULT 0x00000000
+#define GMC_SRC_CLIP_DEFAULT 0x00000000
+#define GMC_DST_CLIP_DEFAULT 0x00000000
+#define GMC_BRUSH_SOLIDCOLOR 0x000000d0
+#define GMC_SRC_DSTCOLOR 0x00003000
+#define GMC_BYTE_ORDER_MSB_TO_LSB 0x00000000
+#define GMC_DP_SRC_RECT 0x02000000
+#define GMC_3D_FCN_EN_CLR 0x00000000
+#define GMC_AUX_CLIP_CLEAR 0x20000000
+#define GMC_DST_CLR_CMP_FCN_CLEAR 0x10000000
+#define GMC_WRITE_MASK_SET 0x40000000
+#define GMC_DP_CONVERSION_TEMP_6500 0x00000000
+
+/* DP_GUI_MASTER_CNTL ROP3 named constants */
+#define GMC_ROP3_MASK 0x00ff0000
+#define ROP3_BLACKNESS 0x00000000
+#define ROP3_SRCCOPY 0x00cc0000
+#define ROP3_PATCOPY 0x00f00000
+#define ROP3_WHITENESS 0x00ff0000
+
+#define SRC_DSTCOLOR 0x00030000
+
+/* DP_CNTL bit constants */
+#define DST_X_RIGHT_TO_LEFT 0x00000000
+#define DST_X_LEFT_TO_RIGHT 0x00000001
+#define DST_Y_BOTTOM_TO_TOP 0x00000000
+#define DST_Y_TOP_TO_BOTTOM 0x00000002
+#define DST_X_MAJOR 0x00000000
+#define DST_Y_MAJOR 0x00000004
+#define DST_X_TILE 0x00000008
+#define DST_Y_TILE 0x00000010
+#define DST_LAST_PEL 0x00000020
+#define DST_TRAIL_X_RIGHT_TO_LEFT 0x00000000
+#define DST_TRAIL_X_LEFT_TO_RIGHT 0x00000040
+#define DST_TRAP_FILL_RIGHT_TO_LEFT 0x00000000
+#define DST_TRAP_FILL_LEFT_TO_RIGHT 0x00000080
+#define DST_BRES_SIGN 0x00000100
+#define DST_HOST_BIG_ENDIAN_EN 0x00000200
+#define DST_POLYLINE_NONLAST 0x00008000
+#define DST_RASTER_STALL 0x00010000
+#define DST_POLY_EDGE 0x00040000
+
+/* DP_MIX bit constants */
+#define DP_SRC_RECT 0x00000200
+#define DP_SRC_HOST 0x00000300
+#define DP_SRC_HOST_BYTEALIGN 0x00000400
+
+/* LVDS_GEN_CNTL constants */
+#define LVDS_BL_MOD_LEVEL_MASK 0x0000ff00
+#define LVDS_BL_MOD_LEVEL_SHIFT 8
+#define LVDS_BL_MOD_EN 0x00010000
+#define LVDS_DIGION 0x00040000
+#define LVDS_BLON 0x00080000
+#define LVDS_ON 0x00000001
+#define LVDS_DISPLAY_DIS 0x00000002
+#define LVDS_PANEL_TYPE_2PIX_PER_CLK 0x00000004
+#define LVDS_PANEL_24BITS_TFT 0x00000008
+#define LVDS_FRAME_MOD_NO 0x00000000
+#define LVDS_FRAME_MOD_2_LEVELS 0x00000010
+#define LVDS_FRAME_MOD_4_LEVELS 0x00000020
+#define LVDS_RST_FM 0x00000040
+#define LVDS_EN 0x00000080
+
+/* CRTC2_GEN_CNTL constants */
+#define CRTC2_EN 0x02000000
+
+/* POWER_MANAGEMENT constants */
+#define PWR_MGT_ON 0x00000001
+#define PWR_MGT_MODE_MASK 0x00000006
+#define PWR_MGT_MODE_PIN 0x00000000
+#define PWR_MGT_MODE_REGISTER 0x00000002
+#define PWR_MGT_MODE_TIMER 0x00000004
+#define PWR_MGT_MODE_PCI 0x00000006
+#define PWR_MGT_AUTO_PWR_UP_EN 0x00000008
+#define PWR_MGT_ACTIVITY_PIN_ON 0x00000010
+#define PWR_MGT_STANDBY_POL 0x00000020
+#define PWR_MGT_SUSPEND_POL 0x00000040
+#define PWR_MGT_SELF_REFRESH 0x00000080
+#define PWR_MGT_ACTIVITY_PIN_EN 0x00000100
+#define PWR_MGT_KEYBD_SNOOP 0x00000200
+#define PWR_MGT_TRISTATE_MEM_EN 0x00000800
+#define PWR_MGT_SELW4MS 0x00001000
+#define PWR_MGT_SLOWDOWN_MCLK 0x00002000
+
+#define PMI_PMSCR_REG 0x60
+
+/* used by ATI bug fix for hardware ROM */
+#define RAGE128_MPP_TB_CONFIG 0x01c0
+
+#endif /* ATI_REGS_H */
diff --git a/hw/display/trace-events b/hw/display/trace-events
index 37d3264bb2..80993cc4d9 100644
--- a/hw/display/trace-events
+++ b/hw/display/trace-events
@@ -138,3 +138,7 @@ vga_cirrus_write_blt(uint32_t offset, uint32_t val) "offset 0x%x, val 0x%x"
sii9022_read_reg(uint8_t addr, uint8_t val) "addr 0x%02x, val 0x%02x"
sii9022_write_reg(uint8_t addr, uint8_t val) "addr 0x%02x, val 0x%02x"
sii9022_switch_mode(const char *mode) "mode: %s"
+
+# hw/display/ati*.c
+ati_mm_read(unsigned int size, uint64_t addr, const char *name, uint64_t val) "%u 0x%"HWADDR_PRIx " %s -> 0x%"PRIx64
+ati_mm_write(unsigned int size, uint64_t addr, const char *name, uint64_t val) "%u 0x%"HWADDR_PRIx " %s <- 0x%"PRIx64
diff --git a/vl.c b/vl.c
index 4c5cc0d8ad..4ab7fb3753 100644
--- a/vl.c
+++ b/vl.c
@@ -240,6 +240,7 @@ static struct {
{ .driver = "vmware-svga", .flag = &default_vga },
{ .driver = "qxl-vga", .flag = &default_vga },
{ .driver = "virtio-vga", .flag = &default_vga },
+ { .driver = "ati-vga", .flag = &default_vga },
};
static QemuOptsList qemu_rtc_opts = {
--
2.13.7
^ permalink raw reply related [flat|nested] 14+ messages in thread
* Re: [Qemu-devel] [PATCH v5-resend 2/2] mips_fulong2e: Add on-board graphics chip
2019-03-06 20:05 ` [Qemu-devel] [PATCH v5-resend 2/2] mips_fulong2e: Add on-board graphics chip BALATON Zoltan
@ 2019-03-07 0:32 ` Philippe Mathieu-Daudé
2019-03-07 0:38 ` BALATON Zoltan
2019-03-08 7:32 ` Gerd Hoffmann
0 siblings, 2 replies; 14+ messages in thread
From: Philippe Mathieu-Daudé @ 2019-03-07 0:32 UTC (permalink / raw)
To: BALATON Zoltan, qemu-devel
Cc: Gerd Hoffmann, Mark Cave-Ayland, Aleksandar Markovic
On 3/6/19 9:05 PM, BALATON Zoltan wrote:
> Add (partial) emulation of the on-board GPU of the machine. This
> allows the PMON2000 firmware to run and should also work with Linux
> console but probably not with X yet.
>
> Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Mojibaked again :(
Aleksandar, if you take this series, do you mind fixing with:
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Thanks!
Phil.
> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
> ---
> hw/mips/mips_fulong2e.c | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/hw/mips/mips_fulong2e.c b/hw/mips/mips_fulong2e.c
> index fbbc543eed..f877693766 100644
> --- a/hw/mips/mips_fulong2e.c
> +++ b/hw/mips/mips_fulong2e.c
> @@ -287,6 +287,7 @@ static void mips_fulong2e_init(MachineState *machine)
> I2CBus *smbus;
> MIPSCPU *cpu;
> CPUMIPSState *env;
> + DeviceState *dev;
>
> /* init CPUs */
> cpu = MIPS_CPU(cpu_create(machine->cpu_type));
> @@ -347,6 +348,11 @@ static void mips_fulong2e_init(MachineState *machine)
> vt82c686b_southbridge_init(pci_bus, FULONG2E_VIA_SLOT, env->irq[5],
> &smbus, &isa_bus);
>
> + /* GPU */
> + dev = DEVICE(pci_create(pci_bus, -1, "ati-vga"));
> + qdev_prop_set_uint16(dev, "x-device-id", 0x5159);
> + qdev_init_nofail(dev);
> +
> /* Populate SPD eeprom data */
> spd_data = spd_data_generate(DDR, ram_size, &err);
> if (err) {
>
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [Qemu-devel] [PATCH v5-resend 2/2] mips_fulong2e: Add on-board graphics chip
2019-03-07 0:32 ` Philippe Mathieu-Daudé
@ 2019-03-07 0:38 ` BALATON Zoltan
2019-03-07 13:38 ` Aleksandar Markovic
2019-03-08 7:32 ` Gerd Hoffmann
1 sibling, 1 reply; 14+ messages in thread
From: BALATON Zoltan @ 2019-03-07 0:38 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: qemu-devel, Gerd Hoffmann, Mark Cave-Ayland, Aleksandar Markovic
On Thu, 7 Mar 2019, Philippe Mathieu-Daudé wrote:
> On 3/6/19 9:05 PM, BALATON Zoltan wrote:
>> Add (partial) emulation of the on-board GPU of the machine. This
>> allows the PMON2000 firmware to run and should also work with Linux
>> console but probably not with X yet.
>>
>> Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
>> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
>> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
>
> Mojibaked again :(
Sorry. Looks like my setup just can't handle your encoding. Maybe I need
an additional header to specify content encoding? Do you have a git config
to tell format-patch to generate that? Or have a way for maintainers to
correct this on merging automatically?
> Aleksandar, if you take this series, do you mind fixing with:
I think it should go via Gerd's tree together with the other patch.
Regards,
BALATON Zoltan
> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
>
> Thanks!
>
> Phil.
>
>> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
>> ---
>> hw/mips/mips_fulong2e.c | 6 ++++++
>> 1 file changed, 6 insertions(+)
>>
>> diff --git a/hw/mips/mips_fulong2e.c b/hw/mips/mips_fulong2e.c
>> index fbbc543eed..f877693766 100644
>> --- a/hw/mips/mips_fulong2e.c
>> +++ b/hw/mips/mips_fulong2e.c
>> @@ -287,6 +287,7 @@ static void mips_fulong2e_init(MachineState *machine)
>> I2CBus *smbus;
>> MIPSCPU *cpu;
>> CPUMIPSState *env;
>> + DeviceState *dev;
>>
>> /* init CPUs */
>> cpu = MIPS_CPU(cpu_create(machine->cpu_type));
>> @@ -347,6 +348,11 @@ static void mips_fulong2e_init(MachineState *machine)
>> vt82c686b_southbridge_init(pci_bus, FULONG2E_VIA_SLOT, env->irq[5],
>> &smbus, &isa_bus);
>>
>> + /* GPU */
>> + dev = DEVICE(pci_create(pci_bus, -1, "ati-vga"));
>> + qdev_prop_set_uint16(dev, "x-device-id", 0x5159);
>> + qdev_init_nofail(dev);
>> +
>> /* Populate SPD eeprom data */
>> spd_data = spd_data_generate(DDR, ram_size, &err);
>> if (err) {
>>
>
>
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [Qemu-devel] [PATCH v5-resend 2/2] mips_fulong2e: Add on-board graphics chip
2019-03-07 0:38 ` BALATON Zoltan
@ 2019-03-07 13:38 ` Aleksandar Markovic
0 siblings, 0 replies; 14+ messages in thread
From: Aleksandar Markovic @ 2019-03-07 13:38 UTC (permalink / raw)
To: BALATON Zoltan, Philippe Mathieu-Daudé
Cc: qemu-devel, Gerd Hoffmann, Mark Cave-Ayland
> From: BALATON Zoltan <balaton@eik.bme.hu>
> Subject: Re: [PATCH v5-resend 2/2] mips_fulong2e: Add on-board graphics chip
>
> > On Thu, 7 Mar 2019, Philippe Mathieu-Daudé wrote:
> > Aleksandar, if you take this series, do you mind fixing with:
>
> I think it should go via Gerd's tree together with the other patch.
>
> Regards,
> BALATON Zoltan
Yes, Gerd, should you agree with the patches, let they both go through your
tree/pull request, please.
Sincerely,
Aleksandar
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [Qemu-devel] [PATCH v5-resend 2/2] mips_fulong2e: Add on-board graphics chip
2019-03-07 0:32 ` Philippe Mathieu-Daudé
2019-03-07 0:38 ` BALATON Zoltan
@ 2019-03-08 7:32 ` Gerd Hoffmann
2019-03-08 16:22 ` BALATON Zoltan
1 sibling, 1 reply; 14+ messages in thread
From: Gerd Hoffmann @ 2019-03-08 7:32 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: BALATON Zoltan, qemu-devel, Mark Cave-Ayland, Aleksandar Markovic
On Thu, Mar 07, 2019 at 01:32:41AM +0100, Philippe Mathieu-Daudé wrote:
> On 3/6/19 9:05 PM, BALATON Zoltan wrote:
> > Add (partial) emulation of the on-board GPU of the machine. This
> > allows the PMON2000 firmware to run and should also work with Linux
> > console but probably not with X yet.
> >
> > Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
> > Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> > Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
>
> Mojibaked again :(
Mail was sent without Content-Type: header. Both mutt and "git am" on
my machine assume utf-8 and everything looks fine. I guess your mail
client assumes something else ...
"git send-email" should send the patches with correct headers, it even
asks for the charset it should use in case it finds non-ascii
characters. So BALATON, could you check your mail client config, or
switch over to "git send-email" for submitting patches?
cheers,
Gerd
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [Qemu-devel] [PATCH v5-resend 2/2] mips_fulong2e: Add on-board graphics chip
2019-03-08 7:32 ` Gerd Hoffmann
@ 2019-03-08 16:22 ` BALATON Zoltan
2019-03-08 16:35 ` Philippe Mathieu-Daudé
2019-03-11 6:38 ` Gerd Hoffmann
0 siblings, 2 replies; 14+ messages in thread
From: BALATON Zoltan @ 2019-03-08 16:22 UTC (permalink / raw)
To: Gerd Hoffmann
Cc: Philippe Mathieu-Daudé,
qemu-devel, Mark Cave-Ayland, Aleksandar Markovic
On Fri, 8 Mar 2019, Gerd Hoffmann wrote:
> On Thu, Mar 07, 2019 at 01:32:41AM +0100, Philippe Mathieu-Daudé wrote:
>> On 3/6/19 9:05 PM, BALATON Zoltan wrote:
>>> Add (partial) emulation of the on-board GPU of the machine. This
>>> allows the PMON2000 firmware to run and should also work with Linux
>>> console but probably not with X yet.
>>>
>>> Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
>>> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
>>> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
>>
>> Mojibaked again :(
>
> Mail was sent without Content-Type: header. Both mutt and "git am" on
> my machine assume utf-8 and everything looks fine. I guess your mail
> client assumes something else ...
So it came out good at the end but that depends on what maintainer's
config does by default it seems.
> "git send-email" should send the patches with correct headers, it even
> asks for the charset it should use in case it finds non-ascii
> characters. So BALATON, could you check your mail client config, or
> switch over to "git send-email" for submitting patches?
I'm sending what git format-patch is generating and that does not add
content type header by default. Is there a config option to enable that? I
can't use git send-email because I'm sending from different machine than I
use git on.
Regards,
BALATON Zoltan
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [Qemu-devel] [PATCH v5-resend 2/2] mips_fulong2e: Add on-board graphics chip
2019-03-08 16:22 ` BALATON Zoltan
@ 2019-03-08 16:35 ` Philippe Mathieu-Daudé
2019-03-08 16:40 ` Laurent Vivier
2019-03-11 6:38 ` Gerd Hoffmann
1 sibling, 1 reply; 14+ messages in thread
From: Philippe Mathieu-Daudé @ 2019-03-08 16:35 UTC (permalink / raw)
To: BALATON Zoltan, Laurent Vivier
Cc: Gerd Hoffmann, qemu-devel, Mark Cave-Ayland, Aleksandar Markovic
On 3/8/19 5:22 PM, BALATON Zoltan wrote:
> On Fri, 8 Mar 2019, Gerd Hoffmann wrote:
>> On Thu, Mar 07, 2019 at 01:32:41AM +0100, Philippe Mathieu-Daudé wrote:
>>> On 3/6/19 9:05 PM, BALATON Zoltan wrote:
>>>> Add (partial) emulation of the on-board GPU of the machine. This
>>>> allows the PMON2000 firmware to run and should also work with Linux
>>>> console but probably not with X yet.
>>>>
>>>> Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
>>>> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
>>>> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
>>>
>>> Mojibaked again :(
>>
>> Mail was sent without Content-Type: header. Both mutt and "git am" on
>> my machine assume utf-8 and everything looks fine. I guess your mail
>> client assumes something else ...
>
> So it came out good at the end but that depends on what maintainer's
> config does by default it seems.
>
>> "git send-email" should send the patches with correct headers, it even
>> asks for the charset it should use in case it finds non-ascii
>> characters. So BALATON, could you check your mail client config, or
>> switch over to "git send-email" for submitting patches?
>
> I'm sending what git format-patch is generating and that does not add
> content type header by default. Is there a config option to enable that?
> I can't use git send-email because I'm sending from different machine
> than I use git on.
On another thread Laurent Vivier found it is a copy/paste problem
between an email client and an editor (IIUC):
https://lists.gnu.org/archive/html/qemu-devel/2019-02/msg03669.html
Laurent, if you understood what's wrong, can you add en entry in the
wiki so we can refer contributors to it?
Thanks,
Phil.
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [Qemu-devel] [PATCH v5-resend 2/2] mips_fulong2e: Add on-board graphics chip
2019-03-08 16:35 ` Philippe Mathieu-Daudé
@ 2019-03-08 16:40 ` Laurent Vivier
0 siblings, 0 replies; 14+ messages in thread
From: Laurent Vivier @ 2019-03-08 16:40 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, BALATON Zoltan
Cc: Gerd Hoffmann, qemu-devel, Mark Cave-Ayland, Aleksandar Markovic
Le 08/03/2019 à 17:35, Philippe Mathieu-Daudé a écrit :
> On 3/8/19 5:22 PM, BALATON Zoltan wrote:
>> On Fri, 8 Mar 2019, Gerd Hoffmann wrote:
>>> On Thu, Mar 07, 2019 at 01:32:41AM +0100, Philippe Mathieu-Daudé wrote:
>>>> On 3/6/19 9:05 PM, BALATON Zoltan wrote:
>>>>> Add (partial) emulation of the on-board GPU of the machine. This
>>>>> allows the PMON2000 firmware to run and should also work with Linux
>>>>> console but probably not with X yet.
>>>>>
>>>>> Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
>>>>> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
>>>>> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
>>>>
>>>> Mojibaked again :(
>>>
>>> Mail was sent without Content-Type: header. Both mutt and "git am" on
>>> my machine assume utf-8 and everything looks fine. I guess your mail
>>> client assumes something else ...
>>
>> So it came out good at the end but that depends on what maintainer's
>> config does by default it seems.
>>
>>> "git send-email" should send the patches with correct headers, it even
>>> asks for the charset it should use in case it finds non-ascii
>>> characters. So BALATON, could you check your mail client config, or
>>> switch over to "git send-email" for submitting patches?
>>
>> I'm sending what git format-patch is generating and that does not add
>> content type header by default. Is there a config option to enable that?
>> I can't use git send-email because I'm sending from different machine
>> than I use git on.
>
> On another thread Laurent Vivier found it is a copy/paste problem
> between an email client and an editor (IIUC):
> https://lists.gnu.org/archive/html/qemu-devel/2019-02/msg03669.html
>
> Laurent, if you understood what's wrong, can you add en entry in the
> wiki so we can refer contributors to it?
No sure. My guess is a cut'n'paste between two windows with different
charsets doesn't work because the buffer keeps the char encoding of the
first window and put them as raw binaries in the second one, so it
encodes something else.
Thanks,
Laurent
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [Qemu-devel] [PATCH v5-resend 2/2] mips_fulong2e: Add on-board graphics chip
2019-03-08 16:22 ` BALATON Zoltan
2019-03-08 16:35 ` Philippe Mathieu-Daudé
@ 2019-03-11 6:38 ` Gerd Hoffmann
1 sibling, 0 replies; 14+ messages in thread
From: Gerd Hoffmann @ 2019-03-11 6:38 UTC (permalink / raw)
To: BALATON Zoltan
Cc: Philippe Mathieu-Daudé,
qemu-devel, Mark Cave-Ayland, Aleksandar Markovic
Hi,
> > "git send-email" should send the patches with correct headers, it even
> > asks for the charset it should use in case it finds non-ascii
> > characters. So BALATON, could you check your mail client config, or
> > switch over to "git send-email" for submitting patches?
>
> I'm sending what git format-patch is generating and that does not add
> content type header by default. Is there a config option to enable that? I
> can't use git send-email because I'm sending from different machine than I
> use git on.
git send-email also accepts files generated by git format-patch,
so you can:
(1) "git format-patch master..$branch", on machine A
(2) copy over 000*.patch from machine A to machine B
(3) "git send-email 000*.patch", on machine B
But take care that you don't have old 000*.patch files lying around on
machine B ...
HTH,
Gerd
^ permalink raw reply [flat|nested] 14+ messages in thread
* [Qemu-devel] [PATCH v5-resend 0/2] Basic ATI VGA emulation
@ 2019-03-07 16:48 Andrew Randrianasulu
0 siblings, 0 replies; 14+ messages in thread
From: Andrew Randrianasulu @ 2019-03-07 16:48 UTC (permalink / raw)
To: balaton, qemu-devel
You can have my
Tested-by: Andrew Randrianasulu, randrianasulu@gmail.com
ref: https://lists.gnu.org/archive/html/qemu-devel/2019-03/msg01728.html
https://lists.gnu.org/archive/html/qemu-devel/2019-03/msg01985.html
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [Qemu-devel] [PATCH v5-resend 0/2] Basic ATI VGA emulation
2019-03-07 3:47 [Qemu-devel] [PATCH v5-resend 0/2] Basic " Andrew Randrianasulu
@ 2019-03-07 13:55 ` BALATON Zoltan
0 siblings, 0 replies; 14+ messages in thread
From: BALATON Zoltan @ 2019-03-07 13:55 UTC (permalink / raw)
To: Andrew Randrianasulu; +Cc: Gerd Hoffmann, qemu-devel
Hello,
On Thu, 7 Mar 2019, Andrew Randrianasulu wrote:
> Tried this with mac99 machine and lubuntu 16.04 ppc.
Thanks for testing it. Do you want to add a Tested-by: tag? You can reply
to the patch (or series cover letter for all patches) with your Tested-by:
to declare that.
> After upgrading r128 driver to -hwe part to get past this bug
> https://bugs.freedesktop.org/show_bug.cgi?id=91622
>
> and disabling accel I can see some image and cursor!
Good. Accel is still not quite right, I now about that but couldn't fix it
yet. I'd need more time for that which I don't have now. So for now only
console and unaccelerated X is expected to work.
> qemu command:
>
> ppc64-softmmu/qemu-system-ppc64 -M mac99 -device ati-vga \
> -cdrom /mnt/sdb1/ISO/lubuntu-16.04-desktop-powerpc.iso -m 1G -boot d -cpu g4 -device usb-mouse -smp 1
The -cpu g4 is not needed as that's the default (it's also single core so
-smp 1 is not needed either). You're probably also better off using -M
mac99,via=pmu which is closer to real hardware and adds USB keyboard and
mouse as well instead of ADB ones so you can omit the -device usb-mouse
option with that as well.
> model rv100 doesn't recognized by openfirmware, so no output from it.
rv100 is only supported for fulong2e console at the moment because drivers
for it probably need more features of the GPU implemented (such as command
FIFO) that aren't emulated yet. At first I only target rage128p as found
in PowerMac3,1 without 3D for Linux, X, MorphOS and maybe MacOS.
> Menus in wondows still at wrong place (not shown, even), but generally speaking some image is on screen.
I wonder if it's a bug in guest or due to Linux FB using some 2D ops that
are not correct? Maybe this could be cross-checked with an Intel version
of the same lubuntu version to make sure it's not a PPC specific xorg
problem.
Regards,
BALATON Zoltan
^ permalink raw reply [flat|nested] 14+ messages in thread
* [Qemu-devel] [PATCH v5-resend 0/2] Basic ATI VGA emulation
@ 2019-03-07 3:47 Andrew Randrianasulu
2019-03-07 13:55 ` BALATON Zoltan
0 siblings, 1 reply; 14+ messages in thread
From: Andrew Randrianasulu @ 2019-03-07 3:47 UTC (permalink / raw)
To: balaton, qemu-devel
[-- Attachment #1: Type: text/plain, Size: 575 bytes --]
Tried this with mac99 machine and lubuntu 16.04 ppc.
After upgrading r128 driver to -hwe part to get past this bug
https://bugs.freedesktop.org/show_bug.cgi?id=91622
and disabling accel I can see some image and cursor!
qemu command:
ppc64-softmmu/qemu-system-ppc64 -M mac99 -device ati-vga \
-cdrom /mnt/sdb1/ISO/lubuntu-16.04-desktop-powerpc.iso -m 1G -boot d -cpu g4 -device usb-mouse -smp 1
model rv100 doesn't recognized by openfirmware, so no output from it.
Menus in wondows still at wrong place (not shown, even), but generally speaking some image is on screen.
[-- Attachment #2: Xorg.1.log --]
[-- Type: text/x-log, Size: 17727 bytes --]
[ 6238.260]
X.Org X Server 1.19.6
Release Date: 2017-12-20
[ 6238.275] X Protocol Version 11, Revision 0
[ 6238.280] Build Operating System: Linux 4.4.0-138-powerpc64-smp ppc Ubuntu
[ 6238.283] Current Operating System: Linux lubuntu 4.4.0-21-powerpc-smp #37-Ubuntu SMP Mon Apr 18 18:33:34 UTC 2016 ppc
[ 6238.284] Kernel command line: ro ramdisk_size=1048576 file=/cdrom/preseed/lubuntu.seed boot=casper quiet splash ---
[ 6238.302] Build Date: 25 October 2018 04:10:08PM
[ 6238.306] xorg-server 2:1.19.6-1ubuntu4.1~16.04.2 (For technical support please see http://www.ubuntu.com/support)
[ 6238.313] Current version of pixman: 0.33.6
[ 6238.325] Before reporting problems, check http://wiki.x.org
to make sure that you have the latest version.
[ 6238.326] Markers: (--) probed, (**) from config file, (==) default setting,
(++) from command line, (!!) notice, (II) informational,
(WW) warning, (EE) error, (NI) not implemented, (??) unknown.
[ 6238.364] (==) Log file: "/var/log/Xorg.1.log", Time: Thu Mar 7 03:12:54 2019
[ 6238.381] (==) Using config file: "/etc/X11/xorg.conf"
[ 6238.387] (==) Using system config directory "/usr/share/X11/xorg.conf.d"
[ 6238.437] (==) ServerLayout "X.org Configured"
[ 6238.439] (**) |-->Screen "Screen0" (0)
[ 6238.440] (**) | |-->Monitor "Monitor0"
[ 6238.449] (**) | |-->Device "Card0"
[ 6238.451] (**) |-->Input Device "Mouse0"
[ 6238.451] (**) |-->Input Device "Keyboard0"
[ 6238.452] (==) Automatically adding devices
[ 6238.452] (==) Automatically enabling devices
[ 6238.452] (==) Automatically adding GPU devices
[ 6238.452] (==) Automatically binding GPU devices
[ 6238.454] (==) Max clients allowed: 256, resource mask: 0x1fffff
[ 6238.456] (WW) The directory "/usr/share/fonts/X11/cyrillic" does not exist.
[ 6238.456] Entry deleted from font path.
[ 6238.456] (WW) The directory "/usr/share/fonts/X11/100dpi/" does not exist.
[ 6238.456] Entry deleted from font path.
[ 6238.456] (WW) The directory "/usr/share/fonts/X11/75dpi/" does not exist.
[ 6238.456] Entry deleted from font path.
[ 6238.456] (WW) The directory "/usr/share/fonts/X11/Type1" does not exist.
[ 6238.457] Entry deleted from font path.
[ 6238.457] (WW) The directory "/usr/share/fonts/X11/100dpi" does not exist.
[ 6238.457] Entry deleted from font path.
[ 6238.457] (WW) The directory "/usr/share/fonts/X11/75dpi" does not exist.
[ 6238.457] Entry deleted from font path.
[ 6238.457] (WW) The directory "/usr/share/fonts/X11/cyrillic" does not exist.
[ 6238.457] Entry deleted from font path.
[ 6238.457] (WW) The directory "/usr/share/fonts/X11/100dpi/" does not exist.
[ 6238.457] Entry deleted from font path.
[ 6238.457] (WW) The directory "/usr/share/fonts/X11/75dpi/" does not exist.
[ 6238.458] Entry deleted from font path.
[ 6238.458] (WW) The directory "/usr/share/fonts/X11/Type1" does not exist.
[ 6238.458] Entry deleted from font path.
[ 6238.458] (WW) The directory "/usr/share/fonts/X11/100dpi" does not exist.
[ 6238.458] Entry deleted from font path.
[ 6238.458] (WW) The directory "/usr/share/fonts/X11/75dpi" does not exist.
[ 6238.458] Entry deleted from font path.
[ 6238.458] (**) FontPath set to:
/usr/share/fonts/X11/misc,
built-ins,
/usr/share/fonts/X11/misc,
built-ins
[ 6238.458] (**) ModulePath set to "/usr/lib/xorg/modules"
[ 6238.459] (WW) Hotplugging is on, devices using drivers 'kbd', 'mouse' or 'vmmouse' will be disabled.
[ 6238.459] (WW) Disabling Mouse0
[ 6238.460] (WW) Disabling Keyboard0
[ 6238.460] (II) Loader magic: 0x202ee710
[ 6238.461] (II) Module ABI versions:
[ 6238.461] X.Org ANSI C Emulation: 0.4
[ 6238.461] X.Org Video Driver: 23.0
[ 6238.461] X.Org XInput driver : 24.1
[ 6238.461] X.Org Server Extension : 10.0
[ 6238.669] (++) using VT number 2
[ 6238.915] (II) systemd-logind: took control of session /org/freedesktop/login1/session/_31
[ 6239.091] (II) xfree86: Adding drm device (/dev/dri/card0)
[ 6239.229] (II) systemd-logind: got fd for /dev/dri/card0 226:0 fd 11 paused 0
[ 6239.328] (--) PCI:*(0:0:15:0) 1002:5046:1af4:1100 rev 0, Mem @ 0x81000000/16777216, 0x82000000/16384, I/O @ 0x00001000/256, BIOS @ 0x????????/65536
[ 6239.341] (II) "glx" will be loaded. This was enabled by default and also specified in the config file.
[ 6239.342] (II) LoadModule: "glx"
[ 6239.389] (II) Loading /usr/lib/xorg/modules/extensions/libglx.so
[ 6239.444] (II) Module glx: vendor="X.Org Foundation"
[ 6239.445] compiled for 1.19.6, module version = 1.0.0
[ 6239.446] ABI class: X.Org Server Extension, version 10.0
[ 6239.451] (II) LoadModule: "r128"
[ 6239.459] (II) Loading /usr/lib/xorg/modules/drivers/r128_drv.so
[ 6239.465] (II) Module r128: vendor="X.Org Foundation"
[ 6239.475] compiled for 1.19.3, module version = 6.10.2
[ 6239.475] Module class: X.Org Video Driver
[ 6239.476] ABI class: X.Org Video Driver, version 23.0
[ 6239.477] (II) R128: Driver for ATI Rage 128 chipsets:
ATI Rage 128 Mobility M3 LE (PCI), ATI Rage 128 Mobility M3 LF (AGP),
ATI Rage 128 Mobility M4 MF (AGP), ATI Rage 128 Mobility M4 ML (AGP),
ATI Rage 128 Pro GL PA (PCI/AGP), ATI Rage 128 Pro GL PB (PCI/AGP),
ATI Rage 128 Pro GL PC (PCI/AGP), ATI Rage 128 Pro GL PD (PCI),
ATI Rage 128 Pro GL PE (PCI/AGP), ATI Rage 128 Pro GL PF (AGP),
ATI Rage 128 Pro VR PG (PCI/AGP), ATI Rage 128 Pro VR PH (PCI/AGP),
ATI Rage 128 Pro VR PI (PCI/AGP), ATI Rage 128 Pro VR PJ (PCI/AGP),
ATI Rage 128 Pro VR PK (PCI/AGP), ATI Rage 128 Pro VR PL (PCI/AGP),
ATI Rage 128 Pro VR PM (PCI/AGP), ATI Rage 128 Pro VR PN (PCI/AGP),
ATI Rage 128 Pro VR PO (PCI/AGP), ATI Rage 128 Pro VR PP (PCI),
ATI Rage 128 Pro VR PQ (PCI/AGP), ATI Rage 128 Pro VR PR (PCI),
ATI Rage 128 Pro VR PS (PCI/AGP), ATI Rage 128 Pro VR PT (PCI/AGP),
ATI Rage 128 Pro VR PU (PCI/AGP), ATI Rage 128 Pro VR PV (PCI/AGP),
ATI Rage 128 Pro VR PW (PCI/AGP), ATI Rage 128 Pro VR PX (PCI/AGP),
ATI Rage 128 GL RE (PCI), ATI Rage 128 GL RF (AGP),
ATI Rage 128 RG (AGP), ATI Rage 128 VR RK (PCI),
ATI Rage 128 VR RL (AGP), ATI Rage 128 4X SE (PCI/AGP),
ATI Rage 128 4X SF (PCI/AGP), ATI Rage 128 4X SG (PCI/AGP),
ATI Rage 128 4X SH (PCI/AGP), ATI Rage 128 4X SK (PCI/AGP),
ATI Rage 128 4X SL (PCI/AGP), ATI Rage 128 4X SM (AGP),
ATI Rage 128 4X SN (PCI/AGP), ATI Rage 128 Pro ULTRA TF (AGP),
ATI Rage 128 Pro ULTRA TL (AGP), ATI Rage 128 Pro ULTRA TR (AGP),
ATI Rage 128 Pro ULTRA TS (AGP?), ATI Rage 128 Pro ULTRA TT (AGP?),
ATI Rage 128 Pro ULTRA TU (AGP?)
[ 6239.503] (II) R128(0): PCI bus 0 card 15 func 0
[ 6239.505] (==) R128(0): Depth 24, (--) framebuffer bpp 32
[ 6239.506] (II) R128(0): Pixel depth = 24 bits stored in 4 bytes (32 bpp pixmaps)
[ 6239.507] (==) R128(0): Default visual is TrueColor
[ 6239.508] (**) R128(0): Option "NoAccel" "1"
[ 6239.508] (**) R128(0): Option "PanelWidth" "1024"
[ 6239.509] (**) R128(0): Option "PanelHeight" "768"
[ 6239.509] (II) R128(0): VGAAccess option set to FALSE, VGA module load skipped
[ 6239.509] (==) R128(0): RGB weight 888
[ 6239.510] (II) R128(0): Using 8 bits per RGB (8 bit DAC)
[ 6239.510] (**) R128(0): Using framebuffer device
[ 6239.510] (II) Loading sub module "fbdevhw"
[ 6239.510] (II) LoadModule: "fbdevhw"
[ 6239.511] (II) Loading /usr/lib/xorg/modules/libfbdevhw.so
[ 6239.516] (II) Module fbdevhw: vendor="X.Org Foundation"
[ 6239.518] compiled for 1.19.6, module version = 0.0.2
[ 6239.519] ABI class: X.Org Video Driver, version 23.0
[ 6239.523] (--) R128(0): Chipset: "ATI Rage 128 Pro GL PF (AGP)" (ChipID = 0x5046)
[ 6239.523] (--) R128(0): Linear framebuffer at 0x80000000
[ 6239.523] (--) R128(0): MMIO registers at 0x82000000
[ 6239.525] (--) R128(0): VideoRAM: 16384 kByte (64-bit SDR SGRAM 1:1)
[ 6239.526] (II) Loading sub module "ddc"
[ 6239.526] (II) LoadModule: "ddc"
[ 6239.526] (II) Module "ddc" already built-in
[ 6239.526] (II) Loading sub module "i2c"
[ 6239.526] (II) LoadModule: "i2c"
[ 6239.526] (II) Module "i2c" already built-in
[ 6239.541] (II) R128(0): PLL parameters: rf=2950 rd=0 min=12500 max=25000; xclk=0
[ 6239.545] (II) R128(0): Output DVI-0 using monitor section Monitor0
[ 6239.546] (II) R128(0): I2C bus "DVI-0" initialized.
[ 6239.547] (**) R128(0): Option "NoDDC" "1"
[ 6239.549] (II) R128(0): EDID for output DVI-0
[ 6239.558] (II) R128(0): Not using default mode "1024x768i" (hsync out of range)
[ 6239.558] (II) R128(0): Not using default mode "1024x768" (vrefresh out of range)
[ 6239.558] (II) R128(0): Not using default mode "1024x768" (vrefresh out of range)
[ 6239.558] (II) R128(0): Not using default mode "1024x768" (hsync out of range)
[ 6239.559] (II) R128(0): Not using default mode "1024x768" (vrefresh out of range)
[ 6239.559] (II) R128(0): Not using default mode "1024x768" (hsync out of range)
[ 6239.559] (II) R128(0): Not using default mode "1024x768" (hsync out of range)
[ 6239.559] (II) R128(0): Printing probed modes for output DVI-0
[ 6239.561] (II) R128(0): Modeline "1024x768"x72.3 78.75 1024 1044 1140 1328 768 781 784 820 +hsync +vsync (59.3 kHz UP)
[ 6239.561] (II) R128(0): Modeline "1024x768"x75.0 78.75 1024 1040 1136 1312 768 769 772 800 +hsync +vsync (60.0 kHz d)
[ 6239.562] (II) R128(0): Output DVI-0 connected
[ 6239.563] (II) R128(0): Using user preference for initial modes
[ 6239.563] (II) R128(0): Output DVI-0 using initial mode 1024x768 +0+0
[ 6239.566] (==) R128(0): DPI set to (96, 96)
[ 6239.566] (II) Loading sub module "fb"
[ 6239.566] (II) LoadModule: "fb"
[ 6239.568] (II) Loading /usr/lib/xorg/modules/libfb.so
[ 6239.571] (II) Module fb: vendor="X.Org Foundation"
[ 6239.573] compiled for 1.19.6, module version = 1.0.0
[ 6239.573] ABI class: X.Org ANSI C Emulation, version 0.4
[ 6239.574] (==) R128(0): Using gamma correction (1.0, 1.0, 1.0)
[ 6239.574] (II) Loading sub module "ramdac"
[ 6239.574] (II) LoadModule: "ramdac"
[ 6239.575] (II) Module "ramdac" already built-in
[ 6239.575] (II) Loading sub module "shadowfb"
[ 6239.575] (II) LoadModule: "shadowfb"
[ 6239.577] (II) Loading /usr/lib/xorg/modules/libshadowfb.so
[ 6239.578] (II) Module shadowfb: vendor="X.Org Foundation"
[ 6239.579] compiled for 1.19.6, module version = 1.0.0
[ 6239.579] ABI class: X.Org ANSI C Emulation, version 0.4
[ 6239.580] (II) R128(0): Page flipping disabled
[ 6239.582] (--) Depth 24 pixmap format is 32 bpp
[ 6239.585] (II) R128(0): Acceleration of RENDER operations will be enabled upon successful loading of DRI and EXA
[ 6239.589] (WW) R128(0): Acceleration disabled, not initializing the DRI
[ 6239.604] (II) R128(0): Memory manager initialized to (0,0) (1024,4096)
[ 6239.607] (II) R128(0): Reserved area from (0,768) to (1024,770)
[ 6239.608] (II) R128(0): Largest offscreen area available: 1024 x 3326
[ 6239.608] (II) R128(0): Acceleration disabled
[ 6239.618] (==) R128(0): Backing store enabled
[ 6239.619] (==) R128(0): Silken mouse enabled
[ 6239.623] (II) R128(0): Will use 2 kb for hardware cursor 0 at offset 0x00302000
[ 6239.624] (II) R128(0): Largest offscreen area available: 1024 x 3325
[ 6239.627] (==) R128(0): DPMS enabled
[ 6239.632] (WW) R128(0): Option "PreferredMode" is not used
[ 6239.633] (WW) R128(0): Option "DefaultModes" is not used
[ 6239.633] (WW) R128(0): Direct rendering disabled
[ 6239.633] (II) R128(0): RandR 1.2 enabled, ignore the following RandR disabled message.
[ 6239.652] (--) RandR disabled
[ 6239.771] (II) SELinux: Disabled on system
[ 6239.784] (II) AIGLX: Screen 0 is not DRI2 capable
[ 6239.785] (EE) AIGLX: reverting to software rendering
[ 6239.898] (II) IGLX: enabled GLX_MESA_copy_sub_buffer
[ 6239.907] (II) IGLX: Loaded and initialized swrast
[ 6239.907] (II) GLX: Initialized DRISWRAST GL provider for screen 0
[ 6241.395] (II) config/udev: Adding input device QEMU QEMU USB Mouse (/dev/input/event2)
[ 6241.399] (**) QEMU QEMU USB Mouse: Applying InputClass "evdev pointer catchall"
[ 6241.401] (II) LoadModule: "evdev"
[ 6241.402] (II) Loading /usr/lib/xorg/modules/input/evdev_drv.so
[ 6241.411] (II) Module evdev: vendor="X.Org Foundation"
[ 6241.411] compiled for 1.19.3, module version = 2.10.5
[ 6241.412] Module class: X.Org XInput Driver
[ 6241.412] ABI class: X.Org XInput driver, version 24.1
[ 6241.413] (II) Using input driver 'evdev' for 'QEMU QEMU USB Mouse'
[ 6241.493] (II) systemd-logind: got fd for /dev/input/event2 13:66 fd 20 paused 0
[ 6241.500] (**) QEMU QEMU USB Mouse: always reports core events
[ 6241.502] (**) evdev: QEMU QEMU USB Mouse: Device: "/dev/input/event2"
[ 6241.508] (--) evdev: QEMU QEMU USB Mouse: Vendor 0x627 Product 0x1
[ 6241.509] (--) evdev: QEMU QEMU USB Mouse: Found 3 mouse buttons
[ 6241.509] (--) evdev: QEMU QEMU USB Mouse: Found scroll wheel(s)
[ 6241.509] (--) evdev: QEMU QEMU USB Mouse: Found relative axes
[ 6241.510] (--) evdev: QEMU QEMU USB Mouse: Found x and y relative axes
[ 6241.511] (II) evdev: QEMU QEMU USB Mouse: Configuring as mouse
[ 6241.511] (II) evdev: QEMU QEMU USB Mouse: Adding scrollwheel support
[ 6241.513] (**) evdev: QEMU QEMU USB Mouse: YAxisMapping: buttons 4 and 5
[ 6241.514] (**) evdev: QEMU QEMU USB Mouse: EmulateWheelButton: 4, EmulateWheelInertia: 10, EmulateWheelTimeout: 200
[ 6241.515] (**) Option "config_info" "udev:/sys/devices/pci0000:00/0000:00:0d.0/usb1/1-1/1-1:1.0/0003:0627:0001.0001/input/input2/event2"
[ 6241.515] (II) XINPUT: Adding extended input device "QEMU QEMU USB Mouse" (type: MOUSE, id 6)
[ 6241.526] (II) evdev: QEMU QEMU USB Mouse: initialized for relative axes.
[ 6241.541] (**) QEMU QEMU USB Mouse: (accel) keeping acceleration scheme 1
[ 6241.543] (**) QEMU QEMU USB Mouse: (accel) acceleration profile 0
[ 6241.554] (**) QEMU QEMU USB Mouse: (accel) acceleration factor: 2.000
[ 6241.555] (**) QEMU QEMU USB Mouse: (accel) acceleration threshold: 4
[ 6241.580] (II) config/udev: Adding input device QEMU QEMU USB Mouse (/dev/input/mouse1)
[ 6241.583] (II) No input driver specified, ignoring this device.
[ 6241.583] (II) This device may have been added with another device file.
[ 6241.639] (II) config/udev: Adding input device ADB keyboard (/dev/input/event0)
[ 6241.641] (**) ADB keyboard: Applying InputClass "evdev keyboard catchall"
[ 6241.642] (II) Using input driver 'evdev' for 'ADB keyboard'
[ 6241.654] (II) systemd-logind: got fd for /dev/input/event0 13:64 fd 21 paused 0
[ 6241.657] (**) ADB keyboard: always reports core events
[ 6241.658] (**) evdev: ADB keyboard: Device: "/dev/input/event0"
[ 6241.659] (--) evdev: ADB keyboard: Vendor 0x1 Product 0x2202
[ 6241.660] (--) evdev: ADB keyboard: Found keys
[ 6241.660] (II) evdev: ADB keyboard: Configuring as keyboard
[ 6241.661] (**) Option "config_info" "udev:/sys/devices/virtual/input/input0/event0"
[ 6241.662] (II) XINPUT: Adding extended input device "ADB keyboard" (type: KEYBOARD, id 7)
[ 6241.663] (**) Option "xkb_rules" "evdev"
[ 6241.663] (**) Option "xkb_model" "pc105"
[ 6241.664] (**) Option "xkb_layout" "us"
[ 6241.677] (II) config/udev: Adding input device ADB mouse (/dev/input/event1)
[ 6241.678] (**) ADB mouse: Applying InputClass "evdev pointer catchall"
[ 6241.679] (II) Using input driver 'evdev' for 'ADB mouse'
[ 6241.690] (II) systemd-logind: got fd for /dev/input/event1 13:65 fd 22 paused 0
[ 6241.691] (**) ADB mouse: always reports core events
[ 6241.693] (**) evdev: ADB mouse: Device: "/dev/input/event1"
[ 6241.694] (--) evdev: ADB mouse: Vendor 0x1 Product 0x3303
[ 6241.694] (--) evdev: ADB mouse: Found 3 mouse buttons
[ 6241.694] (--) evdev: ADB mouse: Found relative axes
[ 6241.695] (--) evdev: ADB mouse: Found x and y relative axes
[ 6241.695] (II) evdev: ADB mouse: Configuring as mouse
[ 6241.697] (**) evdev: ADB mouse: YAxisMapping: buttons 4 and 5
[ 6241.697] (**) evdev: ADB mouse: EmulateWheelButton: 4, EmulateWheelInertia: 10, EmulateWheelTimeout: 200
[ 6241.698] (**) Option "config_info" "udev:/sys/devices/virtual/input/input1/event1"
[ 6241.700] (II) XINPUT: Adding extended input device "ADB mouse" (type: MOUSE, id 8)
[ 6241.701] (II) evdev: ADB mouse: initialized for relative axes.
[ 6241.705] (**) ADB mouse: (accel) keeping acceleration scheme 1
[ 6241.706] (**) ADB mouse: (accel) acceleration profile 0
[ 6241.707] (**) ADB mouse: (accel) acceleration factor: 2.000
[ 6241.707] (**) ADB mouse: (accel) acceleration threshold: 4
[ 6241.715] (II) config/udev: Adding input device ADB mouse (/dev/input/mouse0)
[ 6241.716] (II) No input driver specified, ignoring this device.
[ 6241.717] (II) This device may have been added with another device file.
[ 6322.823] (II) systemd-logind: got pause for 13:64
[ 6322.847] (II) systemd-logind: got pause for 226:0
[ 6322.861] (II) systemd-logind: got pause for 13:66
[ 6322.868] (II) systemd-logind: got pause for 13:65
[ 6465.826] (II) systemd-logind: got resume for 13:64
[ 6466.059] (II) systemd-logind: got resume for 226:0
[ 6466.419] (II) systemd-logind: got resume for 13:66
[ 6466.447] (II) systemd-logind: got resume for 13:65
[ 6511.689] (II) systemd-logind: got pause for 13:64
[ 6511.731] (II) systemd-logind: got pause for 226:0
[ 6511.772] (II) systemd-logind: got pause for 13:66
[ 6511.808] (II) systemd-logind: got pause for 13:65
[ 6818.848] (II) systemd-logind: got resume for 13:64
[ 6819.130] (II) systemd-logind: got resume for 226:0
[ 6820.039] (II) systemd-logind: got resume for 13:66
[ 6820.134] (II) systemd-logind: got resume for 13:65
[ 6823.719] (II) systemd-logind: got pause for 13:64
[ 6823.726] (II) systemd-logind: got pause for 226:0
[ 6823.728] (II) systemd-logind: got pause for 13:66
[ 6823.731] (II) systemd-logind: got pause for 13:65
[-- Attachment #3: dmesg_ati_r128 --]
[-- Type: text/plain, Size: 21170 bytes --]
[ 0.000000] Using PowerMac machine description
[ 0.000000] Total memory = 1024MB; using 2048kB for hash table (at cfe00000)
[ 0.000000] Initializing cgroup subsys cpuset
[ 0.000000] Initializing cgroup subsys cpu
[ 0.000000] Initializing cgroup subsys cpuacct
[ 0.000000] Linux version 4.4.0-21-powerpc-smp (buildd@denneed04) (gcc version 5.3.1 20160413 (Ubuntu 5.3.1-14ubuntu2) ) #37-Ubuntu SMP Mon Apr 18 18:33:34 UTC 2016 (Ubuntu 4.4.0-21.37-powerpc-smp 4.4.6)
[ 0.000000] Found initrd at 0xc1b00000:0xc30f9ad3
[ 0.000000] Found UniNorth memory controller & host bridge @ 0xf8000000 revision: 0x07
[ 0.000000] Mapped at 0xff7c0000
[ 0.000000] Found a Keylargo mac-io controller, rev: 0, mapped at 0xff740000
[ 0.000000] Processor NAP mode on idle enabled.
[ 0.000000] PowerMac motherboard: PowerMac G4 AGP Graphics
[ 0.000000] CPU maps initialized for 1 thread per core
[ 0.000000] (thread shift is 0)
[ 0.000000] bootconsole [udbg0] enabled
[ 0.000000] Found UniNorth PCI host bridge at 0x00000000f2000000. Firmware bus number: 0->0
[ 0.000000] PCI host bridge /pci@f2000000 (primary) ranges:
[ 0.000000] IO 0x00000000f2000000..0x00000000f27fffff -> 0x0000000000000000
[ 0.000000] MEM 0x0000000080000000..0x000000008fffffff -> 0x0000000080000000
[ 0.000000] nvram: Checking bank 0...
[ 0.000000] Invalid signature
[ 0.000000] Invalid checksum
[ 0.000000] nvram: gen0=0, gen1=0
[ 0.000000] nvram: Active bank is: 0
[ 0.000000] nvram: OF partition at 0xffffffff
[ 0.000000] nvram: XP partition at 0xffffffff
[ 0.000000] nvram: NR partition at 0xffffffff
[ 0.000000] Top of RAM: 0x40000000, Total RAM: 0x40000000
[ 0.000000] Memory hole size: 0MB
[ 0.000000] Zone ranges:
[ 0.000000] DMA [mem 0x0000000000000000-0x000000002fffffff]
[ 0.000000] Normal empty
[ 0.000000] HighMem [mem 0x0000000030000000-0x000000003fffffff]
[ 0.000000] Movable zone start for each node
[ 0.000000] Early memory node ranges
[ 0.000000] node 0: [mem 0x0000000000000000-0x000000003fffffff]
[ 0.000000] Initmem setup node 0 [mem 0x0000000000000000-0x000000003fffffff]
[ 0.000000] On node 0 totalpages: 262144
[ 0.000000] free_area_init_node: node 0, pgdat c0bb0920, node_mem_map ef6ee000
[ 0.000000] DMA zone: 1728 pages used for memmap
[ 0.000000] DMA zone: 0 pages reserved
[ 0.000000] DMA zone: 196608 pages, LIFO batch:31
[ 0.000000] HighMem zone: 65536 pages, LIFO batch:15
[ 0.000000] PERCPU: Embedded 13 pages/cpu @ef6db000 s22188 r8192 d22868 u53248
[ 0.000000] pcpu-alloc: s22188 r8192 d22868 u53248 alloc=13*4096
[ 0.000000] pcpu-alloc: [0] 0
[ 0.000000] Built 1 zonelists in Zone order, mobility grouping on. Total pages: 260416
[ 0.000000] Kernel command line: ro ramdisk_size=1048576 file=/cdrom/preseed/lubuntu.seed boot=casper quiet splash ---
[ 0.000000] PID hash table entries: 4096 (order: 2, 16384 bytes)
[ 0.000000] Dentry cache hash table entries: 131072 (order: 7, 524288 bytes)
[ 0.000000] Inode-cache hash table entries: 65536 (order: 6, 262144 bytes)
[ 0.000000] Sorting __ex_table...
[ 0.000000] allocated 1048576 bytes of page_ext
[ 0.000000] Memory: 932896K/1048576K available (8204K kernel code, 564K rwdata, 2784K rodata, 536K init, 1743K bss, 115680K reserved, 0K cma-reserved, 262144K highmem)
[ 0.000000] Kernel virtual memory layout:
[ 0.000000] * 0xfff9f000..0xfffff000 : fixmap
[ 0.000000] * 0xff800000..0xffc00000 : highmem PTEs
[ 0.000000] * 0xfef37000..0xff800000 : early ioremap
[ 0.000000] * 0xf1000000..0xfef37000 : vmalloc & ioremap
[ 0.000000] SLUB: HWalign=32, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
[ 0.000000] Hierarchical RCU implementation.
[ 0.000000] Build-time adjustment of leaf fanout to 32.
[ 0.000000] RCU restricting CPUs from NR_CPUS=4 to nr_cpu_ids=1.
[ 0.000000] RCU: Adjusting geometry for rcu_fanout_leaf=32, nr_cpu_ids=1
[ 0.000000] NR_IRQS:512 nr_irqs:512 16
[ 0.000000] mpic: Resetting
[ 0.000000] mpic: Setting up MPIC " MPIC 1 " version 1.2 at 80040000, max 1 CPUs
[ 0.000000] mpic: ISU size: 64, shift: 6, mask: 3f
[ 0.000000] mpic: Initializing for 64 sources
[ 0.000000] GMT Delta read from XPRAM: 0 minutes, DST: on
[ 0.000000] time_init: decrementer frequency = 100.000000 MHz
[ 0.000000] time_init: processor frequency = 900.000000 MHz
[ 0.001095] clocksource: timebase: mask: 0xffffffffffffffff max_cycles: 0x171024e7e0, max_idle_ns: 440795205315 ns
[ 0.001390] clocksource: timebase mult[a000000] shift[24] registered
[ 0.001845] clockevent: decrementer mult[1999999a] shift[32] cpu[0]
[ 0.017324] Console: colour dummy device 80x25
[ 0.017578] console [tty0] enabled
[ 0.017734] bootconsole [udbg0] disabled
[ 0.025361] pid_max: default: 32768 minimum: 301
[ 0.027534] Security Framework initialized
[ 0.027651] Yama: becoming mindful.
[ 0.032695] AppArmor: AppArmor initialized
[ 0.036428] Mount-cache hash table entries: 2048 (order: 1, 8192 bytes)
[ 0.036486] Mountpoint-cache hash table entries: 2048 (order: 1, 8192 bytes)
[ 0.079970] Initializing cgroup subsys io
[ 0.080500] Initializing cgroup subsys memory
[ 0.080983] Initializing cgroup subsys devices
[ 0.081164] Initializing cgroup subsys freezer
[ 0.081325] Initializing cgroup subsys net_cls
[ 0.081478] Initializing cgroup subsys perf_event
[ 0.081664] Initializing cgroup subsys net_prio
[ 0.081829] Initializing cgroup subsys pids
[ 0.082751] ftrace: allocating 26562 entries in 78 pages
[ 0.210111] PowerMac SMP probe found 1 cpus
[ 0.238820] Brought up 1 CPUs
[ 0.262742] devtmpfs: initialized
[ 0.283110] evm: security.selinux
[ 0.283173] evm: security.SMACK64
[ 0.283192] evm: security.SMACK64EXEC
[ 0.283211] evm: security.SMACK64TRANSMUTE
[ 0.283229] evm: security.SMACK64MMAP
[ 0.283247] evm: security.ima
[ 0.283271] evm: security.capability
[ 0.288323] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
[ 0.314539] NET: Registered protocol family 16
[ 0.324119] cpuidle: using governor ladder
[ 0.324414] cpuidle: using governor menu
[ 0.358339] PCI: Probing PCI hardware
[ 0.363973] PCI host bridge to bus 0000:00
[ 0.364863] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff]
[ 0.365058] pci_bus 0000:00: root bus resource [mem 0x80000000-0x8fffffff]
[ 0.365507] pci_bus 0000:00: root bus resource [bus 00-ff]
[ 0.365987] pci_bus 0000:00: busn_res: [bus 00-ff] end is updated to ff
[ 0.368097] pci 0000:00:0b.0: [106b:001f] type 00 class 0x060000
[ 0.373345] pci 0000:00:0c.0: [106b:0022] type 00 class 0xff0000
[ 0.374833] pci 0000:00:0c.0: reg 0x10: [mem 0x80000000-0x8007ffff]
[ 0.394986] pci 0000:00:0d.0: [106b:003f] type 00 class 0x0c0310
[ 0.395999] pci 0000:00:0d.0: reg 0x10: [mem 0x80080000-0x800800ff]
[ 0.402045] pci 0000:00:0e.0: [106b:0021] type 00 class 0x020000
[ 0.402828] pci 0000:00:0e.0: reg 0x10: [mem 0x80200000-0x803fffff]
[ 0.407388] pci 0000:00:0f.0: [1002:5046] type 00 class 0x030000
[ 0.409097] pci 0000:00:0f.0: reg 0x10: [mem 0x81000000-0x81ffffff pref]
[ 0.411205] pci 0000:00:0f.0: reg 0x14: [io 0x1000-0x10ff]
[ 0.412979] pci 0000:00:0f.0: reg 0x18: [mem 0x82000000-0x82003fff]
[ 0.423850] pci 0000:00:0f.0: reg 0x30: [mem 0x82010000-0x8201ffff pref]
[ 0.428042] pci_bus 0000:00: busn_res: [bus 00-ff] end is updated to 00
[ 0.436557] pci_bus 0000:00: resource 4 [io 0x0000-0x7fffff]
[ 0.436676] pci_bus 0000:00: resource 5 [mem 0x80000000-0x8fffffff]
[ 0.484909] vgaarb: setting as boot device: PCI:0000:00:0f.0
[ 0.485313] vgaarb: device added: PCI:0000:00:0f.0,decodes=io+mem,owns=io+mem,locks=none
[ 0.485428] vgaarb: loaded
[ 0.485518] vgaarb: bridge control possible 0000:00:0f.0
[ 0.491977] SCSI subsystem initialized
[ 0.493404] libata version 3.00 loaded.
[ 0.495327] usbcore: registered new interface driver usbfs
[ 0.495999] usbcore: registered new interface driver hub
[ 0.496618] usbcore: registered new device driver usb
[ 0.518840] NetLabel: Initializing
[ 0.519021] NetLabel: domain hash size = 128
[ 0.519066] NetLabel: protocols = UNLABELED CIPSOv4
[ 0.522113] NetLabel: unlabeled traffic allowed by default
[ 0.528433] clocksource: Switched to clocksource timebase
[ 0.719689] AppArmor: AppArmor Filesystem Enabled
[ 0.758307] NET: Registered protocol family 2
[ 0.770664] TCP established hash table entries: 8192 (order: 3, 32768 bytes)
[ 0.771112] TCP bind hash table entries: 8192 (order: 4, 65536 bytes)
[ 0.771941] TCP: Hash tables configured (established 8192 bind 8192)
[ 0.774338] UDP hash table entries: 512 (order: 2, 16384 bytes)
[ 0.774663] UDP-Lite hash table entries: 512 (order: 2, 16384 bytes)
[ 0.777937] NET: Registered protocol family 1
[ 0.782506] PCI: CLS 0 bytes, default 32
[ 0.795575] Trying to unpack rootfs image as initramfs...
[ 42.521883] Freeing initrd memory: 22500K (c1b00000 - c30f9000)
[ 42.524139] Thermal assist unit using timers, shrink_timer: 500 jiffies
[ 42.537487] futex hash table entries: 256 (order: 1, 8192 bytes)
[ 42.538917] audit: initializing netlink subsys (disabled)
[ 42.541071] audit: type=2000 audit(1551921969.428:1): initialized
[ 42.546535] Initialise system trusted keyring
[ 42.587959] zbud: loaded
[ 42.591517] VFS: Disk quotas dquot_6.6.0
[ 42.592323] VFS: Dquot-cache hash table entries: 1024 (order 0, 4096 bytes)
[ 42.603778] fuse init (API version 7.23)
[ 42.607406] Key type big_key registered
[ 42.620971] Key type asymmetric registered
[ 42.621102] Asymmetric key parser 'x509' registered
[ 42.621458] bounce: pool size: 64 pages
[ 42.621850] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 251)
[ 42.623004] io scheduler noop registered
[ 42.623139] io scheduler deadline registered (default)
[ 42.623980] io scheduler cfq registered
[ 42.628539] pci_hotplug: PCI Hot Plug PCI Core version: 0.5
[ 42.628917] pciehp: PCI Express Hot Plug Controller Driver version: 0.4
[ 42.633997] aty128fb: Found Intel x86 BIOS ROM Image
[ 42.634043] aty128fb: Rage128 BIOS located
[ 42.637754] aty128fb: Rage128 PF PRO AGP [chip rev 0x0] 16M 128-bit SDR SGRAM (1:1)
[ 42.663788] Console: switching to colour frame buffer device 128x48
[ 42.670174] fb0: ATY Rage128 frame buffer device on Rage128 PF PRO AGP
[ 42.697145] Serial: 8250/16550 driver, 32 ports, IRQ sharing enabled
[ 42.736786] pmac_zilog: 0.6 (Benjamin Herrenschmidt <benh@kernel.crashing.org>)
[ 42.739112] Generic non-volatile memory driver v1.1
[ 42.740560] Linux agpgart interface v0.103
[ 42.849029] brd: module loaded
[ 42.872708] loop: module loaded
[ 42.877820] MacIO PCI driver attached to Keylargo chipset
[ 42.885911] 0.00013020:ch-a: ttyPZ0 at MMIO 0x80013020 (irq = 37, base_baud = 230400) is a Z85c30 ESCC - Serial port
[ 42.888183] 0.00013000:ch-b: ttyPZ1 at MMIO 0x80013000 (irq = 36, base_baud = 230400) is a Z85c30 ESCC - Serial port
[ 42.894233] Macintosh CUDA driver v0.5 for Unified ADB.
[ 42.902662] adb: starting probe task...
[ 42.928854] adb devices: [2]: 2 2 [3]: 3 3
[ 42.934108] ADB keyboard at 2, handler 1
[ 42.934745] Detected ADB keyboard, type ANSI.
[ 42.937991] input: ADB keyboard as /devices/virtual/input/input0
[ 42.947964] ADB mouse at 3, handler set to 3 (Mouse Systems A3 Mouse, or compatible)
[ 42.951599] input: ADB mouse as /devices/virtual/input/input1
[ 42.952024] adb: finished probe task...
[ 43.920429] pata-macio 0.00020000:ata-3: Activating pata-macio chipset KeyLargo ATA-3, Apple bus ID 0
[ 43.936878] scsi host0: pata_macio
[ 43.939870] ata1: PATA max MWDMA2 irq 16
[ 44.967714] pata-macio 0.00021000:ata-3: Activating pata-macio chipset KeyLargo ATA-3, Apple bus ID 1
[ 44.974119] scsi host1: pata_macio
[ 44.975918] ata2: PATA max MWDMA2 irq 18
[ 44.982042] libphy: Fixed MDIO Bus: probed
[ 44.982313] tun: Universal TUN/TAP device driver, 1.6
[ 44.982388] tun: (C) 1999-2004 Max Krasnyansky <maxk@qualcomm.com>
[ 44.984418] PPP generic driver version 2.4.2
[ 44.986191] ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver
[ 44.986883] ehci-pci: EHCI PCI platform driver
[ 44.987676] ehci-platform: EHCI generic platform driver
[ 44.987893] ohci_hcd: USB 1.1 'Open' Host Controller (OHCI) Driver
[ 44.988241] ohci-pci: OHCI PCI platform driver
[ 44.990632] ohci-pci 0000:00:0d.0: OHCI PCI host controller
[ 44.991910] ohci-pci 0000:00:0d.0: new USB bus registered, assigned bus number 1
[ 44.994302] ohci-pci 0000:00:0d.0: irq 28, io mem 0x80080000
[ 45.062034] usb usb1: New USB device found, idVendor=1d6b, idProduct=0001
[ 45.062100] usb usb1: New USB device strings: Mfr=3, Product=2, SerialNumber=1
[ 45.062157] usb usb1: Product: OHCI PCI host controller
[ 45.062214] usb usb1: Manufacturer: Linux 4.4.0-21-powerpc-smp ohci_hcd
[ 45.062269] usb usb1: SerialNumber: 0000:00:0d.0
[ 45.069026] hub 1-0:1.0: USB hub found
[ 45.070228] hub 1-0:1.0: 3 ports detected
[ 45.080545] ohci-platform: OHCI generic platform driver
[ 45.080879] uhci_hcd: USB Universal Host Controller Interface driver
[ 45.084880] mousedev: PS/2 mouse device common for all mice
[ 45.087380] i2c /dev entries driver
[ 45.089166] device-mapper: uevent: version 1.0.3
[ 45.090879] device-mapper: ioctl: 4.34.0-ioctl (2015-10-28) initialised: dm-devel@redhat.com
[ 45.092715] ledtrig-cpu: registered to indicate activity on CPUs
[ 45.097725] NET: Registered protocol family 10
[ 45.111039] NET: Registered protocol family 17
[ 45.111983] Key type dns_resolver registered
[ 45.116374] registered taskstats version 1
[ 45.116826] Loading compiled-in X.509 certificates
[ 45.147038] ata2.01: NODEV after polling detection
[ 45.149977] ata2.00: ATAPI: QEMU DVD-ROM, 2.5+, max UDMA/100
[ 45.153267] ata2.00: configured for MWDMA2
[ 45.160487] Loaded X.509 cert 'Build time autogenerated kernel key: 4be2596f661edc589a661416cf2887229e4b74d6'
[ 45.162645] zswap: loaded using pool lzo/zbud
[ 45.201636] scsi 1:0:0:0: CD-ROM QEMU QEMU DVD-ROM 2.5+ PQ: 0 ANSI: 5
[ 45.224538] sr 1:0:0:0: [sr0] scsi3-mmc drive: 4x/4x cd/rw xa/form2 tray
[ 45.224946] cdrom: Uniform CD-ROM driver Revision: 3.20
[ 45.234943] sr 1:0:0:0: Attached scsi CD-ROM sr0
[ 45.236677] sr 1:0:0:0: Attached scsi generic sg0 type 5
[ 45.467727] usb 1-1: new full-speed USB device number 2 using ohci-pci
[ 45.542304] Key type trusted registered
[ 45.707529] usb 1-1: New USB device found, idVendor=0627, idProduct=0001
[ 45.707610] usb 1-1: New USB device strings: Mfr=1, Product=2, SerialNumber=9
[ 45.707660] usb 1-1: Product: QEMU USB Mouse
[ 45.707707] usb 1-1: Manufacturer: QEMU
[ 45.707754] usb 1-1: SerialNumber: 89126-pci.2:0d.0-1
[ 46.057491] Key type encrypted registered
[ 46.057694] AppArmor: AppArmor sha1 policy hashing enabled
[ 46.058240] ima: No TPM chip found, activating TPM-bypass!
[ 46.061838] evm: HMAC attrs: 0x1
[ 46.065722] hctosys: unable to open rtc device (rtc0)
[ 46.067749] PM: Hibernation image not present or could not be loaded.
[ 46.246599] Freeing unused kernel memory: 536K (c0abf000 - c0b45000)
[ 47.721106] random: systemd-udevd urandom read with 6 bits of entropy available
[ 49.482532] sungem.c:v1.0 David S. Miller <davem@redhat.com>
[ 49.533848] hidraw: raw HID events driver (C) Jiri Kosina
[ 49.550636] gem 0000:00:0e.0 eth0: Sun GEM (PCI) 10/100/1000BaseT Ethernet 52:54:00:12:34:56
[ 49.683529] usbcore: registered new interface driver usbhid
[ 49.683618] usbhid: USB HID core driver
[ 51.146412] gem 0000:00:0e.0 enp0s14: renamed from eth0
[ 51.203558] input: QEMU QEMU USB Mouse as /devices/pci0000:00/0000:00:0d.0/usb1/1-1/1-1:1.0/0003:0627:0001.0001/input/input2
[ 51.212432] hid-generic 0003:0627:0001.0001: input,hidraw0: USB HID v0.01 Mouse [QEMU QEMU USB Mouse] on usb-0000:00:0d.0-1/input0
[ 59.567766] ISO 9660 Extensions: RRIP_1991A
[ 61.508333] squashfs: version 4.0 (2009/01/31) Phillip Lougher
[ 62.578497] random: nonblocking pool is initialized
[ 185.166818] systemd[1]: systemd 229 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ -LZ4 +SECCOMP +BLKID +ELFUTILS +KMOD -IDN)
[ 185.174700] systemd[1]: Detected architecture ppc.
[ 185.177665] systemd[1]: Set hostname to <lubuntu>.
[ 185.180941] systemd[1]: Initializing machine ID from random generator.
[ 188.513416] systemd[1]: Listening on Journal Socket (/dev/log).
[ 188.523606] systemd[1]: Created slice User and Session Slice.
[ 188.532621] systemd[1]: Set up automount Arbitrary Executable File Formats File System Automount Point.
[ 188.533578] systemd[1]: Listening on Syslog Socket.
[ 188.534075] systemd[1]: Reached target Remote File Systems (Pre).
[ 188.534369] systemd[1]: Reached target Remote File Systems.
[ 188.536739] systemd[1]: Listening on /dev/initctl Compatibility Named Pipe.
[ 188.537923] systemd[1]: Listening on Journal Socket.
[ 188.539844] systemd[1]: Listening on LVM2 metadata daemon socket.
[ 188.540169] systemd[1]: Reached target User and Group Name Lookups.
[ 188.540770] systemd[1]: Listening on LVM2 poll daemon socket.
[ 188.543828] systemd[1]: Listening on udev Kernel Socket.
[ 188.548038] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
[ 188.548596] systemd[1]: Reached target Encrypted Volumes.
[ 188.549781] systemd[1]: Listening on Device-mapper event daemon FIFOs.
[ 188.555361] systemd[1]: Listening on Journal Audit Socket.
[ 188.556406] systemd[1]: Listening on udev Control Socket.
[ 188.556614] systemd[1]: Reached target Swap.
[ 188.558477] systemd[1]: Created slice System Slice.
[ 188.609199] systemd[1]: Starting Nameserver information manager...
[ 188.626458] systemd[1]: Created slice system-serial\x2dgetty.slice.
[ 188.753461] systemd[1]: Mounting POSIX Message Queue File System...
[ 189.119604] systemd[1]: Starting Create list of required static device nodes for the current kernel...
[ 189.456628] systemd[1]: Starting LSB: controls configuration of serial ports...
[ 190.385372] systemd[1]: Started Read required files in advance.
[ 190.966494] systemd[1]: Starting Journal Service...
[ 191.392684] systemd[1]: Mounting Debug File System...
[ 191.393574] systemd[1]: Reached target Slices.
[ 191.917737] systemd[1]: Starting Monitoring of LVM2 mirrors, snapshots etc. using dmeventd or progress polling...
[ 192.874564] systemd[1]: Starting Uncomplicated firewall...
[ 193.535007] systemd[1]: Starting Load Kernel Modules...
[ 194.189287] systemd[1]: Starting Remount Root and Kernel File Systems...
[ 195.402615] systemd[1]: Mounted Debug File System.
[ 195.460432] systemd[1]: Mounted POSIX Message Queue File System.
[ 195.975801] systemd[1]: Started Create list of required static device nodes for the current kernel.
[ 196.063460] systemd[1]: Started Uncomplicated firewall.
[ 196.199635] systemd[1]: Started Load Kernel Modules.
[ 197.889482] systemd[1]: Started Nameserver information manager.
[ 198.315375] systemd[1]: Started Remount Root and Kernel File Systems.
[ 198.856837] systemd[1]: Started Journal Service.
[ 211.834600] systemd-journald[817]: Received request to flush runtime journal from PID 1
[ 230.830117] rtc-generic rtc-generic: rtc core: registered rtc-generic as rtc0
[ 255.138657] zram: Added device: zram0
[ 259.324679] zram0: detected capacity change from 0 to 523661312
[ 262.272144] Adding 511384k swap on /dev/zram0. Priority:5 extents:1 across:511384k SSFS
[ 295.870013] IPv6: ADDRCONF(NETDEV_UP): enp0s14: link is not ready
[ 296.012316] sungem_phy: PHY ID: 406210, addr: 0
[ 296.013285] gem 0000:00:0e.0 enp0s14: Found BCM5201 PHY
[ 296.015056] IPv6: ADDRCONF(NETDEV_UP): enp0s14: link is not ready
[ 297.216561] gem 0000:00:0e.0 enp0s14: Link is up at 100 Mbps, full-duplex
[ 297.217522] gem 0000:00:0e.0 enp0s14: Pause is disabled
[ 297.221530] IPv6: ADDRCONF(NETDEV_CHANGE): enp0s14: link becomes ready
[ 6065.191742] [drm] Initialized drm 1.1.0 20060810
[ 6065.459140] [drm] Supports vblank timestamp caching Rev 2 (21.10.2013).
[ 6065.459224] [drm] No driver support for vblank timestamp query.
[ 6065.459442] [drm] Initialized r128 2.5.0 20030725 for 0000:00:0f.0 on minor 0
[ 6671.391221] pcmanfm[5032]: unhandled signal 11 at 00000004 nip 1fba3bf0 lr 20539d40 code 30001
[ 6749.450215] pcmanfm[5103]: unhandled signal 11 at 00000004 nip 1fcdfbf0 lr 20675d40 code 30001
[ 6769.840585] pcmanfm[5132]: unhandled signal 11 at 00000004 nip 1f946bf0 lr 202dcd40 code 30001
[ 6783.255989] pcmanfm[5140]: unhandled signal 11 at 00000004 nip 1fd9bbf0 lr 20731d40 code 30001
[ 6794.223292] pcmanfm[5148]: unhandled signal 11 at 00000004 nip 1f88cbf0 lr 20222d40 code 30001
[ 6804.903538] pcmanfm[5156]: unhandled signal 11 at 00000004 nip 1f9afbf0 lr 20345d40 code 30001
^ permalink raw reply [flat|nested] 14+ messages in thread
end of thread, other threads:[~2019-03-11 6:52 UTC | newest]
Thread overview: 14+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-03-06 20:05 [Qemu-devel] [PATCH v5-resend 0/2] Basic ATI VGA emulation BALATON Zoltan
2019-03-06 20:05 ` [Qemu-devel] [PATCH v5-resend 2/2] mips_fulong2e: Add on-board graphics chip BALATON Zoltan
2019-03-07 0:32 ` Philippe Mathieu-Daudé
2019-03-07 0:38 ` BALATON Zoltan
2019-03-07 13:38 ` Aleksandar Markovic
2019-03-08 7:32 ` Gerd Hoffmann
2019-03-08 16:22 ` BALATON Zoltan
2019-03-08 16:35 ` Philippe Mathieu-Daudé
2019-03-08 16:40 ` Laurent Vivier
2019-03-11 6:38 ` Gerd Hoffmann
2019-03-06 20:05 ` [Qemu-devel] [PATCH v5-resend 1/2] hw/display: Add basic ATI VGA emulation BALATON Zoltan
2019-03-07 3:47 [Qemu-devel] [PATCH v5-resend 0/2] Basic " Andrew Randrianasulu
2019-03-07 13:55 ` BALATON Zoltan
2019-03-07 16:48 Andrew Randrianasulu
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