[ndctl PATCH 0/2] Add CXL XOR region test

[ndctl PATCH 0/2] Add CXL XOR region test

[alison.schofield]

From: Alison Schofield <alison.schofield@intel.com>

These patches, although not tied to each other, both depend upon
this cxl_test patch:
https://lore.kernel.org/linux-cxl/5a33e3d0b182308a3a783ac8685fd2728bb64a22.1663291370.git.alison.schofield@intel.com/

cxl/test: add cxl_xor_region test
	Depends on: tools/testing/cxl: Add XOR math support

cxl/test: allow another host bridge in cxl-topology check
	This patch syncs cxl-topology test with the cxl_test changes

Alison Schofield (2):
  cxl/test: add cxl_xor_region test
  cxl/test: allow another host bridge in cxl-topology check

 test/cxl-topology.sh   |   6 +-
 test/cxl-xor-region.sh | 126 +++++++++++++++++++++++++++++++++++++++++
 test/meson.build       |   2 +
 3 files changed, 131 insertions(+), 3 deletions(-)
 create mode 100644 test/cxl-xor-region.sh


base-commit: c9c9db39354ea0c3f737378186318e9b7908e3a7
-- 
2.31.1

[ndctl PATCH 1/2] cxl/test: add cxl_xor_region test

[alison.schofield]

From: Alison Schofield <alison.schofield@intel.com>

Exercise the kernel driver support of XOR math by creating
x1, x2, x3, x4 regions using CFMWS's that use XOR Math.

x1 - no interleave, target index is always 0
x2 - 2 way interleave uses one xormap
x3 - 3 way interleave uses no xormaps and relies on a modulo calc.
x4 - 4 way interleave uses two xormaps

Use module parameter "xor_math=1" to select the cxl_test topology
that supports XOR math. XOR math is not used in the default cxl_test
module, to avoid memory bloat.

Signed-off-by: Alison Schofield <alison.schofield@intel.com>
---
 test/cxl-xor-region.sh | 126 +++++++++++++++++++++++++++++++++++++++++
 test/meson.build       |   2 +
 2 files changed, 128 insertions(+)
 create mode 100644 test/cxl-xor-region.sh

diff --git a/test/cxl-xor-region.sh b/test/cxl-xor-region.sh
new file mode 100644
index 000000000000..6bbea9c9257e
--- /dev/null
+++ b/test/cxl-xor-region.sh
@@ -0,0 +1,126 @@
+#!/bin/bash
+# SPDX-License-Identifier: GPL-2.0
+# Copyright (C) 2022 Intel Corporation. All rights reserved.
+
+. $(dirname $0)/common
+
+rc=1
+
+set -ex
+
+trap 'err $LINENO' ERR
+
+check_prereq "jq"
+
+modprobe -r cxl_test
+# Load cxl_test with the support for XOR math.
+modprobe cxl_test interleave_arithmetic=1
+udevadm settle
+
+# THEORY OF OPERATION: Create x1,2,3,4 regions to exercise the XOR math 
+# option of the CXL driver. As with other cxl_test tests, changes to the
+# CXL topology in tools/testing/cxl/test/cxl.c may require an update here.
+
+create_region()
+{
+	region=$($CXL create-region -d $decoder -m $memdevs | jq -r ".region")
+
+	if [[ ! $region ]]; then
+		echo "create-region failed for $decoder"
+		err "$LINENO"
+	fi
+
+	$CXL destroy-region -f -b cxl_test "$region"
+}
+
+setup_x1()
+{
+        # Find an x1 decoder
+        decoder=$($CXL list -b cxl_test -D -d root | jq -r ".[] |
+          select(.pmem_capable == true) |
+          select(.nr_targets == 1) |
+          .decoder")
+
+        # Find a memdev for this host-bridge
+        port_dev0=$($CXL list -T -d $decoder | jq -r ".[] |
+            .targets | .[] | select(.position == 0) | .target")
+        mem0=$($CXL list -M -p $port_dev0 | jq -r ".[0].memdev")
+        memdevs="$mem0"
+}
+
+setup_x2()
+{
+        # Find an x2 decoder
+        decoder=$($CXL list -b cxl_test -D -d root | jq -r ".[] |
+          select(.pmem_capable == true) |
+          select(.nr_targets == 2) |
+          .decoder")
+	
+        # Find a memdev for each host-bridge interleave position
+        port_dev0=$($CXL list -T -d $decoder | jq -r ".[] |
+            .targets | .[] | select(.position == 0) | .target")
+        port_dev1=$($CXL list -T -d $decoder | jq -r ".[] |
+            .targets | .[] | select(.position == 1) | .target")
+        mem0=$($CXL list -M -p $port_dev0 | jq -r ".[0].memdev")
+        mem1=$($CXL list -M -p $port_dev1 | jq -r ".[0].memdev")
+	# Below order matters
+        memdevs="$mem0 $mem1"
+}
+
+setup_x3()
+{
+        # Find an x3 decoder
+        decoder=$($CXL list -b cxl_test -D -d root | jq -r ".[] |
+          select(.pmem_capable == true) |
+          select(.nr_targets == 3) |
+          .decoder")
+	
+        # Find a memdev for each host-bridge interleave position
+        port_dev0=$($CXL list -T -d $decoder | jq -r ".[] |
+            .targets | .[] | select(.position == 0) | .target")
+        port_dev1=$($CXL list -T -d $decoder | jq -r ".[] |
+            .targets | .[] | select(.position == 1) | .target")
+        port_dev2=$($CXL list -T -d $decoder | jq -r ".[] |
+            .targets | .[] | select(.position == 2) | .target")
+        mem0=$($CXL list -M -p $port_dev0 | jq -r ".[0].memdev")
+        mem1=$($CXL list -M -p $port_dev1 | jq -r ".[0].memdev")
+        mem2=$($CXL list -M -p $port_dev2 | jq -r ".[0].memdev")
+	# Below order matters
+        memdevs="$mem1 $mem2 $mem0"
+}
+
+setup_x4()
+{
+        # find x4 decoder
+        decoder=$($CXL list -b cxl_test -D -d root | jq -r ".[] |
+          select(.pmem_capable == true) |
+          select(.nr_targets == 4) |
+          .decoder")
+	
+        # Find a memdev for each host-bridge interleave position
+        port_dev0=$($CXL list -T -d $decoder | jq -r ".[] |
+            .targets | .[] | select(.position == 0) | .target")
+        port_dev1=$($CXL list -T -d $decoder | jq -r ".[] |
+            .targets | .[] | select(.position == 1) | .target")
+        port_dev2=$($CXL list -T -d $decoder | jq -r ".[] |
+            .targets | .[] | select(.position == 2) | .target")
+        port_dev3=$($CXL list -T -d $decoder | jq -r ".[] |
+            .targets | .[] | select(.position == 3) | .target")
+        mem0=$($CXL list -M -p $port_dev0 | jq -r ".[0].memdev")
+        mem1=$($CXL list -M -p $port_dev1 | jq -r ".[0].memdev")
+        mem2=$($CXL list -M -p $port_dev2 | jq -r ".[0].memdev")
+        mem3=$($CXL list -M -p $port_dev3 | jq -r ".[0].memdev")
+	# Below order matters
+        memdevs="$mem0 $mem1 $mem2 $mem3"
+}
+
+setup_x1
+create_region
+setup_x2
+create_region
+setup_x3
+create_region
+setup_x4
+create_region
+modprobe -r cxl_test
+
diff --git a/test/meson.build b/test/meson.build
index 5953c286d13f..89cae9e99dff 100644
--- a/test/meson.build
+++ b/test/meson.build
@@ -154,6 +154,7 @@ cxl_topo = find_program('cxl-topology.sh')
 cxl_sysfs = find_program('cxl-region-sysfs.sh')
 cxl_labels = find_program('cxl-labels.sh')
 cxl_create_region = find_program('cxl-create-region.sh')
+cxl_xor_region = find_program('cxl-xor-region.sh')
 
 tests = [
   [ 'libndctl',               libndctl,		  'ndctl' ],
@@ -182,6 +183,7 @@ tests = [
   [ 'cxl-region-sysfs.sh',    cxl_sysfs,	  'cxl'   ],
   [ 'cxl-labels.sh',          cxl_labels,	  'cxl'   ],
   [ 'cxl-create-region.sh',   cxl_create_region,  'cxl'   ],
+  [ 'cxl-xor-region.sh',      cxl_xor_region,     'cxl'   ],
 ]
 
 if get_option('destructive').enabled()
-- 
2.31.1

[ndctl PATCH 2/2] cxl/test: allow another host bridge in cxl-topology check

[alison.schofield]

From: Alison Schofield <alison.schofield@intel.com>

Update the related count checks to allow a third CXL Host
Bridge in the cxl_test topology.

Signed-off-by: Alison Schofield <alison.schofield@intel.com>
---
 test/cxl-topology.sh | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/test/cxl-topology.sh b/test/cxl-topology.sh
index 2583005fef26..11c39f61cf52 100644
--- a/test/cxl-topology.sh
+++ b/test/cxl-topology.sh
@@ -32,7 +32,7 @@ root=$(jq -r ".[] | .bus" <<< $json)
 port_sort="sort_by(.port | .[4:] | tonumber)"
 json=$($CXL list -b cxl_test -BP)
 count=$(jq ".[] | .[\"ports:$root\"] | length" <<< $json)
-((count == 2)) || err "$LINENO"
+((count == 4)) || err "$LINENO"
 
 bridge[0]=$(jq -r ".[] | .[\"ports:$root\"] | $port_sort | .[0].port" <<< $json)
 bridge[1]=$(jq -r ".[] | .[\"ports:$root\"] | $port_sort | .[1].port" <<< $json)
@@ -103,11 +103,11 @@ count=$(jq "[ $decoder_sort | .[3] |
 ((count == 1)) || err "$LINENO"
 
 
-# check that all 8 cxl_test memdevs are enabled by default and have a
+# check that all 16 cxl_test memdevs are enabled by default and have a
 # pmem size of 256M, or 1G
 json=$($CXL list -b cxl_test -M)
 count=$(jq "map(select(.pmem_size == $pmem_size)) | length" <<< $json)
-((count == 8)) || err "$LINENO"
+((count == 16 )) || err "$LINENO"
 
 
 # check that switch ports disappear after all of their memdevs have been
-- 
2.31.1