[U-Boot] Custom SPL for im.X6UL

* [U-Boot] Custom SPL for im.X6UL
@ 2019-03-08 16:58 Araya, Jose
  2019-03-09  1:11 ` Peng Fan
  0 siblings, 1 reply; 3+ messages in thread
From: Araya, Jose @ 2019-03-08 16:58 UTC (permalink / raw)
  To: u-boot

Hello everyone,

I would like to ask what would be a good starting point to have a custom multi-stage booting for the NXP i.mx6UL processor?

Basically I need to be able to configure an FPGA before the U-Boot is executed. The reason for that is that the PGA must be configured so that the im6UL can have a physical connection to the DRAM. To clarify:

-       In the circuit, the DRAM will be multiplexed by an FPGA. If the FPGA is not configured, the imx6UL has no access to the DRAM.

-       The imx6UL has a direct SPI connection to the flash and to the FPGA, so all I need is to take the bitstream from a given location in the FLASH and load it into the FPGA, then just wait for a flag (GPIO?) saying that the FPGA was successfully configured and keep the booting process in the processor as normal.

As I haven't done yet anything similar, just wanted to know if you have any recommendations regarding where to start and some  hints to proceed.

Thanks in advance!

Bests,

Jose Moises

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