From: Sricharan Ramabadhran <quic_srichara@quicinc.com> To: Bjorn Andersson <bjorn.andersson@linaro.org> Cc: <agross@kernel.org>, <robh+dt@kernel.org>, <krzysztof.kozlowski+dt@linaro.org>, <mturquette@baylibre.com>, <sboyd@kernel.org>, <linus.walleij@linaro.org>, <catalin.marinas@arm.com>, <p.zabel@pengutronix.de>, <quic_varada@quicinc.com>, <linux-arm-msm@vger.kernel.org>, <devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>, <linux-clk@vger.kernel.org>, <linux-gpio@vger.kernel.org>, <linux-arm-kernel@lists.infradead.org> Subject: Re: [PATCH V2 3/8] clk: qcom: Add Global Clock controller (GCC) driver for IPQ5018 Date: Tue, 28 Jun 2022 01:21:36 +0530 [thread overview] Message-ID: <f358606f-0dd5-7dfa-ec6b-b6ade9d5a1a0@quicinc.com> (raw) In-Reply-To: <YrU4D+eDBctFl0ZY@builder.lan> On 6/24/2022 9:35 AM, Bjorn Andersson wrote: > On Tue 21 Jun 11:11 CDT 2022, Sricharan R wrote: >> diff --git a/drivers/clk/qcom/gcc-ipq5018.c b/drivers/clk/qcom/gcc-ipq5018.c > [..] >> +static const struct clk_parent_data gcc_xo_gpll0_gpll0_out_main_div2[] = { >> + { .fw_name = "xo", .name = "xo", }, > Please replace .fw_name with .index based lookup, in line with what was > done in gcc-sc8280xp.c recently. Sure, understand will fix it. > > There's no reason to include global name lookup (.name) in new drivers, > so please omit this part. ok. >> + { .fw_name = "gpll0", .name = "gpll0", }, >> + { .fw_name = "gpll0_out_main_div2", .name = "gpll0_out_main_div2", }, >> +}; >> + > [..] >> +static struct clk_alpha_pll gpll0_main = { >> + .offset = 0x21000, >> + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], >> + .clkr = { >> + .enable_reg = 0x0b000, >> + .enable_mask = BIT(0), >> + .hw.init = &(struct clk_init_data){ >> + .name = "gpll0_main", >> + .parent_data = &(const struct clk_parent_data){ >> + .fw_name = "xo", >> + .name = "xo", > Are you referring to the board XO here, or the CXO pin on the SoC? On > many platforms these are not the same... board XO, will refer your above example and fix it here as well > Please omit the .name here as well and as this is used a few times, > please create a struct clk_parent_data for this parent. ok. >> + }, >> + .num_parents = 1, >> + .ops = &clk_alpha_pll_stromer_ops, >> + .flags = CLK_IS_CRITICAL, >> + }, >> + }, >> +}; >> + >> +static struct clk_fixed_factor gpll0_out_main_div2 = { >> + .mult = 1, >> + .div = 2, >> + .hw.init = &(struct clk_init_data){ >> + .name = "gpll0_out_main_div2", >> + .parent_data = &(const struct clk_parent_data){ > It would be nice to have a space inbetween ) and { in all these. ok. >> + .fw_name = "gpll0_main", >> + .name = "gpll0_main", >> + }, >> + .num_parents = 1, >> + .ops = &clk_fixed_factor_ops, >> + .flags = CLK_SET_RATE_PARENT, >> + }, >> +}; > [..] >> +static struct clk_branch gcc_gephy_tx_clk = { >> + .halt_reg = 0x56014, >> + .halt_check = BRANCH_HALT_DELAY, >> + .clkr = { >> + .enable_reg = 0x56014, >> + .enable_mask = BIT(0), >> + .hw.init = &(struct clk_init_data){ >> + .name = "gcc_gephy_tx_clk", >> + .parent_data = &(const struct clk_parent_data){ >> + .fw_name = "gmac0_tx_div_clk_src", >> + .name = "gmac0_tx_div_clk_src", >> + }, > This parent_data is repeated multiple times, but more importantly it's > not an external clock, so you should use .parent_hw instead of > .parent_data. > > Please review the parent for all your clocks. ok, will do. Regards, Sricharan
WARNING: multiple messages have this Message-ID (diff)
From: Sricharan Ramabadhran <quic_srichara@quicinc.com> To: Bjorn Andersson <bjorn.andersson@linaro.org> Cc: <agross@kernel.org>, <robh+dt@kernel.org>, <krzysztof.kozlowski+dt@linaro.org>, <mturquette@baylibre.com>, <sboyd@kernel.org>, <linus.walleij@linaro.org>, <catalin.marinas@arm.com>, <p.zabel@pengutronix.de>, <quic_varada@quicinc.com>, <linux-arm-msm@vger.kernel.org>, <devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>, <linux-clk@vger.kernel.org>, <linux-gpio@vger.kernel.org>, <linux-arm-kernel@lists.infradead.org> Subject: Re: [PATCH V2 3/8] clk: qcom: Add Global Clock controller (GCC) driver for IPQ5018 Date: Tue, 28 Jun 2022 01:21:36 +0530 [thread overview] Message-ID: <f358606f-0dd5-7dfa-ec6b-b6ade9d5a1a0@quicinc.com> (raw) In-Reply-To: <YrU4D+eDBctFl0ZY@builder.lan> On 6/24/2022 9:35 AM, Bjorn Andersson wrote: > On Tue 21 Jun 11:11 CDT 2022, Sricharan R wrote: >> diff --git a/drivers/clk/qcom/gcc-ipq5018.c b/drivers/clk/qcom/gcc-ipq5018.c > [..] >> +static const struct clk_parent_data gcc_xo_gpll0_gpll0_out_main_div2[] = { >> + { .fw_name = "xo", .name = "xo", }, > Please replace .fw_name with .index based lookup, in line with what was > done in gcc-sc8280xp.c recently. Sure, understand will fix it. > > There's no reason to include global name lookup (.name) in new drivers, > so please omit this part. ok. >> + { .fw_name = "gpll0", .name = "gpll0", }, >> + { .fw_name = "gpll0_out_main_div2", .name = "gpll0_out_main_div2", }, >> +}; >> + > [..] >> +static struct clk_alpha_pll gpll0_main = { >> + .offset = 0x21000, >> + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], >> + .clkr = { >> + .enable_reg = 0x0b000, >> + .enable_mask = BIT(0), >> + .hw.init = &(struct clk_init_data){ >> + .name = "gpll0_main", >> + .parent_data = &(const struct clk_parent_data){ >> + .fw_name = "xo", >> + .name = "xo", > Are you referring to the board XO here, or the CXO pin on the SoC? On > many platforms these are not the same... board XO, will refer your above example and fix it here as well > Please omit the .name here as well and as this is used a few times, > please create a struct clk_parent_data for this parent. ok. >> + }, >> + .num_parents = 1, >> + .ops = &clk_alpha_pll_stromer_ops, >> + .flags = CLK_IS_CRITICAL, >> + }, >> + }, >> +}; >> + >> +static struct clk_fixed_factor gpll0_out_main_div2 = { >> + .mult = 1, >> + .div = 2, >> + .hw.init = &(struct clk_init_data){ >> + .name = "gpll0_out_main_div2", >> + .parent_data = &(const struct clk_parent_data){ > It would be nice to have a space inbetween ) and { in all these. ok. >> + .fw_name = "gpll0_main", >> + .name = "gpll0_main", >> + }, >> + .num_parents = 1, >> + .ops = &clk_fixed_factor_ops, >> + .flags = CLK_SET_RATE_PARENT, >> + }, >> +}; > [..] >> +static struct clk_branch gcc_gephy_tx_clk = { >> + .halt_reg = 0x56014, >> + .halt_check = BRANCH_HALT_DELAY, >> + .clkr = { >> + .enable_reg = 0x56014, >> + .enable_mask = BIT(0), >> + .hw.init = &(struct clk_init_data){ >> + .name = "gcc_gephy_tx_clk", >> + .parent_data = &(const struct clk_parent_data){ >> + .fw_name = "gmac0_tx_div_clk_src", >> + .name = "gmac0_tx_div_clk_src", >> + }, > This parent_data is repeated multiple times, but more importantly it's > not an external clock, so you should use .parent_hw instead of > .parent_data. > > Please review the parent for all your clocks. ok, will do. Regards, Sricharan _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2022-06-27 19:51 UTC|newest] Thread overview: 65+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-06-21 16:11 [PATCH V2 0/8] Add minimal boot support for IPQ5018 Sricharan R 2022-06-21 16:11 ` Sricharan R 2022-06-21 16:11 ` [PATCH V2 1/8] clk: qcom: clk-alpha-pll: Add support for Stromer PLLs Sricharan R 2022-06-21 16:11 ` Sricharan R 2022-06-21 16:11 ` [PATCH V2 2/8] dt-bindings: arm64: ipq5018: Add binding descriptions for clock and reset Sricharan R 2022-06-21 16:11 ` Sricharan R 2022-06-22 15:04 ` Krzysztof Kozlowski 2022-06-22 15:04 ` Krzysztof Kozlowski 2022-06-23 6:00 ` Sricharan Ramabadhran 2022-06-23 6:00 ` Sricharan Ramabadhran 2022-06-24 17:26 ` Rob Herring 2022-06-24 17:26 ` Rob Herring 2022-06-21 16:11 ` [PATCH V2 3/8] clk: qcom: Add Global Clock controller (GCC) driver for IPQ5018 Sricharan R 2022-06-22 15:08 ` Krzysztof Kozlowski 2022-06-22 15:08 ` Krzysztof Kozlowski 2022-06-23 6:06 ` Sricharan Ramabadhran 2022-06-23 6:06 ` Sricharan Ramabadhran 2022-06-24 4:05 ` Bjorn Andersson 2022-06-24 4:05 ` Bjorn Andersson 2022-06-27 19:51 ` Sricharan Ramabadhran [this message] 2022-06-27 19:51 ` Sricharan Ramabadhran 2022-06-28 1:28 ` kernel test robot 2022-06-28 1:28 ` kernel test robot 2022-06-21 16:11 ` [PATCH V2 4/8] dt-bindings: pinctrl: qcom: Add ipq5018 pinctrl bindings Sricharan R 2022-06-21 16:11 ` Sricharan R 2022-06-22 15:13 ` Krzysztof Kozlowski 2022-06-22 15:13 ` Krzysztof Kozlowski 2022-06-23 6:28 ` Sricharan Ramabadhran 2022-06-23 6:28 ` Sricharan Ramabadhran 2022-06-24 3:44 ` Bjorn Andersson 2022-06-24 3:44 ` Bjorn Andersson 2022-06-24 17:26 ` Rob Herring 2022-06-24 17:26 ` Rob Herring 2022-06-21 16:11 ` [PATCH V2 5/8] pinctrl: qcom: Add IPQ5018 pinctrl driver Sricharan R 2022-06-21 16:11 ` Sricharan R 2022-06-24 3:54 ` Bjorn Andersson 2022-06-24 3:54 ` Bjorn Andersson 2022-06-27 19:35 ` Sricharan Ramabadhran 2022-06-27 19:35 ` Sricharan Ramabadhran 2022-06-28 3:31 ` kernel test robot 2022-06-28 3:31 ` kernel test robot 2022-06-21 16:11 ` [PATCH V2 6/8] dt-bindings: qcom: Add ipq5018 bindings Sricharan R 2022-06-21 16:11 ` Sricharan R 2022-06-22 15:14 ` Krzysztof Kozlowski 2022-06-22 15:14 ` Krzysztof Kozlowski 2022-06-23 6:28 ` Sricharan Ramabadhran 2022-06-23 6:28 ` Sricharan Ramabadhran 2022-06-21 16:11 ` [PATCH V2 7/8] arm64: dts: Add ipq5018 SoC and MP03 board support Sricharan R 2022-06-21 16:11 ` Sricharan R 2022-06-22 15:18 ` Krzysztof Kozlowski 2022-06-22 15:18 ` Krzysztof Kozlowski 2022-06-23 7:19 ` Sricharan Ramabadhran 2022-06-23 7:19 ` Sricharan Ramabadhran 2022-06-26 18:32 ` Konrad Dybcio 2022-06-26 18:32 ` Konrad Dybcio 2022-06-28 7:14 ` Sricharan Ramabadhran 2022-06-28 7:14 ` Sricharan Ramabadhran 2022-07-01 7:31 ` Konrad Dybcio 2022-07-01 7:31 ` Konrad Dybcio 2022-06-21 16:11 ` [PATCH V2 8/8] arm64: defconfig: Enable IPQ5018 SoC base configs Sricharan R 2022-06-21 16:11 ` Sricharan R 2022-06-28 12:55 ` [PATCH V2 0/8] Add minimal boot support for IPQ5018 Linus Walleij 2022-06-28 12:55 ` Linus Walleij 2022-06-29 6:51 ` Sricharan Ramabadhran 2022-06-29 6:51 ` Sricharan Ramabadhran
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