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From: tip-bot for Thomas Gleixner <tipbot@zytor.com>
To: linux-tip-commits@vger.kernel.org
Cc: mingo@kernel.org, bp@alien8.de, hpa@zytor.com,
	linux-kernel@vger.kernel.org, mroos@linux.ee, tglx@linutronix.de,
	thomas.lendacky@amd.com
Subject: [tip:x86/pti] x86/pti: Make sure the user/kernel PTEs match
Date: Wed, 3 Jan 2018 08:22:14 -0800	[thread overview]
Message-ID: <tip-52994c256df36fda9a715697431cba9daecb6b11@git.kernel.org> (raw)
In-Reply-To: <alpine.DEB.2.20.1801031407180.1957@nanos>

Commit-ID:  52994c256df36fda9a715697431cba9daecb6b11
Gitweb:     https://git.kernel.org/tip/52994c256df36fda9a715697431cba9daecb6b11
Author:     Thomas Gleixner <tglx@linutronix.de>
AuthorDate: Wed, 3 Jan 2018 15:57:59 +0100
Committer:  Thomas Gleixner <tglx@linutronix.de>
CommitDate: Wed, 3 Jan 2018 15:57:59 +0100

x86/pti: Make sure the user/kernel PTEs match

Meelis reported that his K8 Athlon64 emits MCE warnings when PTI is
enabled:

[Hardware Error]: Error Addr: 0x0000ffff81e000e0
[Hardware Error]: MC1 Error: L1 TLB multimatch.
[Hardware Error]: cache level: L1, tx: INSN

The address is in the entry area, which is mapped into kernel _AND_ user
space. That's special because we switch CR3 while we are executing
there. 

User mapping:
0xffffffff81e00000-0xffffffff82000000           2M     ro         PSE     GLB x  pmd

Kernel mapping:
0xffffffff81000000-0xffffffff82000000          16M     ro         PSE         x  pmd

So the K8 is complaining that the TLB entries differ. They differ in the
GLB bit.

Drop the GLB bit when installing the user shared mapping.

Fixes: 6dc72c3cbca0 ("x86/mm/pti: Share entry text PMD")
Reported-by: Meelis Roos <mroos@linux.ee>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Tested-by: Meelis Roos <mroos@linux.ee>
Cc: Borislav Petkov <bp@alien8.de>
Cc: Tom Lendacky <thomas.lendacky@amd.com>
Cc: stable@vger.kernel.org
Link: https://lkml.kernel.org/r/alpine.DEB.2.20.1801031407180.1957@nanos
---
 arch/x86/mm/pti.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/x86/mm/pti.c b/arch/x86/mm/pti.c
index bce8aea..2da28ba 100644
--- a/arch/x86/mm/pti.c
+++ b/arch/x86/mm/pti.c
@@ -367,7 +367,8 @@ static void __init pti_setup_espfix64(void)
 static void __init pti_clone_entry_text(void)
 {
 	pti_clone_pmds((unsigned long) __entry_text_start,
-			(unsigned long) __irqentry_text_end, _PAGE_RW);
+			(unsigned long) __irqentry_text_end,
+		       _PAGE_RW | _PAGE_GLOBAL);
 }
 
 /*

  parent reply	other threads:[~2018-01-03 16:25 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-01-02 20:49 4.15-rc6 PTI regression: L1 TLB mismatch MCE on Athlon64 Meelis Roos
2018-01-02 21:27 ` Borislav Petkov
2018-01-02 23:07   ` Thomas Gleixner
2018-01-03  9:16     ` Meelis Roos
2018-01-03 12:42       ` Borislav Petkov
2018-01-03 13:17         ` Thomas Gleixner
2018-01-03 13:17           ` Thomas Gleixner
2018-01-03 14:01           ` Meelis Roos
2018-01-03 14:01             ` mroos
2018-01-03 16:22           ` tip-bot for Thomas Gleixner [this message]
2018-02-09 23:30             ` [tip:x86/pti] x86/pti: Make sure the user/kernel PTEs match Dave Hansen
2018-02-13 15:59               ` Thomas Gleixner
2018-01-03  7:07   ` 4.15-rc6 PTI regression: L1 TLB mismatch MCE on Athlon64 Meelis Roos

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