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From: Thomas Gleixner <tglx@linutronix.de>
To: Borislav Petkov <bp@alien8.de>
Cc: Meelis Roos <mroos@linux.ee>,
	Linux Kernel list <linux-kernel@vger.kernel.org>,
	x86@kernel.org, linux-edac@vger.kernel.org,
	Tom Lendacky <thomas.lendacky@amd.com>
Subject: Re: 4.15-rc6 PTI regression: L1 TLB mismatch MCE on Athlon64
Date: Wed, 3 Jan 2018 14:17:00 +0100 (CET)	[thread overview]
Message-ID: <alpine.DEB.2.20.1801031407180.1957@nanos> (raw)
In-Reply-To: <20180103124206.sprpyz6lkwvsl7mw@pd.tnic>

On Wed, 3 Jan 2018, Borislav Petkov wrote:
> On Wed, Jan 03, 2018 at 11:16:48AM +0200, Meelis Roos wrote:
> > ---[ ESPfix Area ]---
> > 0xffffff0000000000-0xffffff1800000000          96G                               pud
> > 0xffffff1800000000-0xffffff1800009000          36K                               pte
> > 0xffffff1800009000-0xffffff180000a000           4K     ro                     NX pte
> > 0xffffff180000a000-0xffffff1800019000          60K                               pte
> > 0xffffff1800019000-0xffffff180001a000           4K     ro                     NX pte
> > 0xffffff180001a000-0xffffff1800029000          60K                               pte
> > 0xffffff1800029000-0xffffff180002a000           4K     ro                     NX pte
> > 0xffffff180002a000-0xffffff1800039000          60K                               pte
> > 0xffffff1800039000-0xffffff180003a000           4K     ro                     NX pte
> > 0xffffff180003a000-0xffffff1800049000          60K                               pte
> > 0xffffff1800049000-0xffffff180004a000           4K     ro                     NX pte
> > 0xffffff180004a000-0xffffff1800059000          60K                               pte
> > 0xffffff1800059000-0xffffff180005a000           4K     ro                     NX pte
> > 0xffffff180005a000-0xffffff1800069000          60K                               pte
> > 0xffffff1800069000-0xffffff180006a000           4K     ro                     NX pte
> > 0xffffff180006a000-0xffffff1800079000          60K                               pte
> > ... 131059 entries skipped ... 
> > ---[ High Kernel Mapping ]---
> > 0xffffffff80000000-0xffffffff81e00000          30M                               pmd
> > 0xffffffff81e00000-0xffffffff82000000           2M     ro         PSE     GLB x  pmd
> 
> Ha, this must be it. What I said yesterday about the guard hole
> hypervisor range was wrong because we're looking at VA slice [47:12] and
> this one matches:

That's the entry area, which is mapped into kernel _AND_ user space. Now
that's special because we switch CR3 while we are executing there.

And this one is:

0xffffffff81e00000-0xffffffff82000000           2M     ro         PSE     GLB x  pmd

and the one we switch to is:

0xffffffff81000000-0xffffffff82000000          16M     ro         PSE         x  pmd

Meelis, does the patch below fix it for you?

Thanks,

	tglx

8<-------------------

--- a/arch/x86/mm/pti.c
+++ b/arch/x86/mm/pti.c
@@ -367,7 +367,8 @@ static void __init pti_setup_espfix64(vo
 static void __init pti_clone_entry_text(void)
 {
 	pti_clone_pmds((unsigned long) __entry_text_start,
-			(unsigned long) __irqentry_text_end, _PAGE_RW);
+			(unsigned long) __irqentry_text_end,
+		       _PAGE_RW | _PAGE_GLOBAL);
 }
 
 /*

WARNING: multiple messages have this Message-ID (diff)
From: Thomas Gleixner <tglx@linutronix.de>
To: Borislav Petkov <bp@alien8.de>
Cc: Meelis Roos <mroos@linux.ee>,
	Linux Kernel list <linux-kernel@vger.kernel.org>,
	x86@kernel.org, linux-edac@vger.kernel.org,
	Tom Lendacky <thomas.lendacky@amd.com>
Subject: 4.15-rc6 PTI regression: L1 TLB mismatch MCE on Athlon64
Date: Wed, 3 Jan 2018 14:17:00 +0100 (CET)	[thread overview]
Message-ID: <alpine.DEB.2.20.1801031407180.1957@nanos> (raw)

On Wed, 3 Jan 2018, Borislav Petkov wrote:
> On Wed, Jan 03, 2018 at 11:16:48AM +0200, Meelis Roos wrote:
> > ---[ ESPfix Area ]---
> > 0xffffff0000000000-0xffffff1800000000          96G                               pud
> > 0xffffff1800000000-0xffffff1800009000          36K                               pte
> > 0xffffff1800009000-0xffffff180000a000           4K     ro                     NX pte
> > 0xffffff180000a000-0xffffff1800019000          60K                               pte
> > 0xffffff1800019000-0xffffff180001a000           4K     ro                     NX pte
> > 0xffffff180001a000-0xffffff1800029000          60K                               pte
> > 0xffffff1800029000-0xffffff180002a000           4K     ro                     NX pte
> > 0xffffff180002a000-0xffffff1800039000          60K                               pte
> > 0xffffff1800039000-0xffffff180003a000           4K     ro                     NX pte
> > 0xffffff180003a000-0xffffff1800049000          60K                               pte
> > 0xffffff1800049000-0xffffff180004a000           4K     ro                     NX pte
> > 0xffffff180004a000-0xffffff1800059000          60K                               pte
> > 0xffffff1800059000-0xffffff180005a000           4K     ro                     NX pte
> > 0xffffff180005a000-0xffffff1800069000          60K                               pte
> > 0xffffff1800069000-0xffffff180006a000           4K     ro                     NX pte
> > 0xffffff180006a000-0xffffff1800079000          60K                               pte
> > ... 131059 entries skipped ... 
> > ---[ High Kernel Mapping ]---
> > 0xffffffff80000000-0xffffffff81e00000          30M                               pmd
> > 0xffffffff81e00000-0xffffffff82000000           2M     ro         PSE     GLB x  pmd
> 
> Ha, this must be it. What I said yesterday about the guard hole
> hypervisor range was wrong because we're looking at VA slice [47:12] and
> this one matches:

That's the entry area, which is mapped into kernel _AND_ user space. Now
that's special because we switch CR3 while we are executing there.

And this one is:

0xffffffff81e00000-0xffffffff82000000           2M     ro         PSE     GLB x  pmd

and the one we switch to is:

0xffffffff81000000-0xffffffff82000000          16M     ro         PSE         x  pmd

Meelis, does the patch below fix it for you?

Thanks,

	tglx

8<-------------------
---
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--- a/arch/x86/mm/pti.c
+++ b/arch/x86/mm/pti.c
@@ -367,7 +367,8 @@ static void __init pti_setup_espfix64(vo
 static void __init pti_clone_entry_text(void)
 {
 	pti_clone_pmds((unsigned long) __entry_text_start,
-			(unsigned long) __irqentry_text_end, _PAGE_RW);
+			(unsigned long) __irqentry_text_end,
+		       _PAGE_RW | _PAGE_GLOBAL);
 }
 
 /*

  reply	other threads:[~2018-01-03 13:17 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-01-02 20:49 4.15-rc6 PTI regression: L1 TLB mismatch MCE on Athlon64 Meelis Roos
2018-01-02 21:27 ` Borislav Petkov
2018-01-02 23:07   ` Thomas Gleixner
2018-01-03  9:16     ` Meelis Roos
2018-01-03 12:42       ` Borislav Petkov
2018-01-03 13:17         ` Thomas Gleixner [this message]
2018-01-03 13:17           ` Thomas Gleixner
2018-01-03 14:01           ` Meelis Roos
2018-01-03 14:01             ` mroos
2018-01-03 16:22           ` [tip:x86/pti] x86/pti: Make sure the user/kernel PTEs match tip-bot for Thomas Gleixner
2018-02-09 23:30             ` Dave Hansen
2018-02-13 15:59               ` Thomas Gleixner
2018-01-03  7:07   ` 4.15-rc6 PTI regression: L1 TLB mismatch MCE on Athlon64 Meelis Roos

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