From: Aurabindo Pillai <aurabindo.pillai@amd.com>
To: <amd-gfx@lists.freedesktop.org>
Cc: stylon.wang@amd.com, chiahsuan.chung@amd.com, Sunpeng.Li@amd.com,
Rodrigo.Siqueira@amd.com, roman.li@amd.com,
Samson Tam <samson.tam@amd.com>,
jerry.zuo@amd.com, Aurabindo.Pillai@amd.com, hersenxs.wu@amd.com,
Alvin Lee <alvin.lee2@amd.com>,
wayne.lin@amd.com, Harry.Wentland@amd.com,
agustin.gutierrez@amd.com
Subject: [PATCH 11/13] drm/amd/display: Force p-state disallow if leaving no plane config
Date: Wed, 6 Dec 2023 14:52:32 -0500 [thread overview]
Message-ID: <20231206195234.182989-12-aurabindo.pillai@amd.com> (raw)
In-Reply-To: <20231206195234.182989-1-aurabindo.pillai@amd.com>
From: Alvin Lee <alvin.lee2@amd.com>
[Description]
- When we're in a no plane config, DCN is always asserting
P-State allow
- This creates a scenario where the P-State blackout can start
just as VUPDATE takes place and transitions the DCN config to
a one where one or more HUBP's are active which can result in
underflow
- To fix this issue, force p-state disallow and unforce after
the transition from no planes case -> one or more planes active
Reviewed-by: Samson Tam <samson.tam@amd.com>
Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Alvin Lee <alvin.lee2@amd.com>
---
.../amd/display/dc/hwss/dcn20/dcn20_hwseq.c | 20 +++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
index 608221b0dd5d..c3c83178eb1e 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
@@ -1877,6 +1877,8 @@ void dcn20_program_front_end_for_ctx(
int i;
struct dce_hwseq *hws = dc->hwseq;
DC_LOGGER_INIT(dc->ctx->logger);
+ unsigned int prev_hubp_count = 0;
+ unsigned int hubp_count = 0;
if (resource_is_pipe_topology_changed(dc->current_state, context))
resource_log_pipe_topology_update(dc, context);
@@ -1894,6 +1896,20 @@ void dcn20_program_front_end_for_ctx(
}
}
+ for (i = 0; i < dc->res_pool->pipe_count; i++) {
+ if (dc->current_state->res_ctx.pipe_ctx[i].plane_state)
+ prev_hubp_count++;
+ if (context->res_ctx.pipe_ctx[i].plane_state)
+ hubp_count++;
+ }
+
+ if (prev_hubp_count == 0 && hubp_count > 0) {
+ if (dc->res_pool->hubbub->funcs->force_pstate_change_control)
+ dc->res_pool->hubbub->funcs->force_pstate_change_control(
+ dc->res_pool->hubbub, true, false);
+ udelay(500);
+ }
+
/* Set pipe update flags and lock pipes */
for (i = 0; i < dc->res_pool->pipe_count; i++)
dcn20_detect_pipe_changes(&dc->current_state->res_ctx.pipe_ctx[i],
@@ -2039,6 +2055,10 @@ void dcn20_post_unlock_program_front_end(
}
}
+ if (dc->res_pool->hubbub->funcs->force_pstate_change_control)
+ dc->res_pool->hubbub->funcs->force_pstate_change_control(
+ dc->res_pool->hubbub, false, false);
+
for (i = 0; i < dc->res_pool->pipe_count; i++) {
struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
--
2.39.2
next prev parent reply other threads:[~2023-12-06 19:52 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-12-06 19:52 [PATCH 00/13] DC Patches for Dec 11, 2023 Aurabindo Pillai
2023-12-06 19:52 ` [PATCH 01/13] drm/amd/display: Remove minor revision 5 until proper parser is ready Aurabindo Pillai
2023-12-06 19:52 ` [PATCH 02/13] drm/amd/display: Use explicit size for types in DCCG's struct dp_dto_params Aurabindo Pillai
2023-12-06 19:52 ` [PATCH 03/13] drm/amd/display: allow DP40 cables to do UHBR13.5 Aurabindo Pillai
2023-12-06 19:52 ` [PATCH 04/13] drm/amd/display: Revert "Fix conversions between bytes and KB" Aurabindo Pillai
2023-12-06 19:52 ` [PATCH 05/13] drm/amd/display: trivial comment change Aurabindo Pillai
2023-12-06 19:52 ` [PATCH 06/13] drm/amd/display: Revert DP2 MST hub triple display fix Aurabindo Pillai
2023-12-06 19:52 ` [PATCH 07/13] drm/amd/display: Populate dtbclk from bounding box Aurabindo Pillai
2023-12-06 19:52 ` [PATCH 08/13] drm/amd/display: Disable OPTC pg to match DC Hubp/dpp pg Aurabindo Pillai
2023-12-06 19:52 ` [PATCH 09/13] drm/amd/display: Exit from idle state before accessing HW data Aurabindo Pillai
2023-12-06 19:52 ` [PATCH 10/13] drm/amd/display: For prefetch mode > 0, extend prefetch if possible Aurabindo Pillai
2023-12-06 19:52 ` Aurabindo Pillai [this message]
2023-12-06 19:52 ` [PATCH 12/13] drm/amd/display: fix HW block PG sequence Aurabindo Pillai
2023-12-06 19:52 ` [PATCH 13/13] drm/amd/display: 3.2.264 Aurabindo Pillai
2023-12-11 14:42 ` [PATCH 00/13] DC Patches for Dec 11, 2023 Wheeler, Daniel
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20231206195234.182989-12-aurabindo.pillai@amd.com \
--to=aurabindo.pillai@amd.com \
--cc=Harry.Wentland@amd.com \
--cc=Rodrigo.Siqueira@amd.com \
--cc=Sunpeng.Li@amd.com \
--cc=agustin.gutierrez@amd.com \
--cc=alvin.lee2@amd.com \
--cc=amd-gfx@lists.freedesktop.org \
--cc=chiahsuan.chung@amd.com \
--cc=hersenxs.wu@amd.com \
--cc=jerry.zuo@amd.com \
--cc=roman.li@amd.com \
--cc=samson.tam@amd.com \
--cc=stylon.wang@amd.com \
--cc=wayne.lin@amd.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).