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From: Aurabindo Pillai <aurabindo.pillai@amd.com>
To: <amd-gfx@lists.freedesktop.org>
Cc: stylon.wang@amd.com, Charlene Liu <charlene.liu@amd.com>,
	chiahsuan.chung@amd.com, Sunpeng.Li@amd.com,
	Rodrigo.Siqueira@amd.com, roman.li@amd.com, jerry.zuo@amd.com,
	Aurabindo.Pillai@amd.com, hersenxs.wu@amd.com, wayne.lin@amd.com,
	Harry.Wentland@amd.com, agustin.gutierrez@amd.com
Subject: [PATCH 07/13] drm/amd/display: Populate dtbclk from bounding box
Date: Wed, 6 Dec 2023 14:52:28 -0500	[thread overview]
Message-ID: <20231206195234.182989-8-aurabindo.pillai@amd.com> (raw)
In-Reply-To: <20231206195234.182989-1-aurabindo.pillai@amd.com>

From: Fangzhi Zuo <jerry.zuo@amd.com>

dtbclk is unavaliable from pmfw. Try to grab the value from bounding box

Reviewed-by: Charlene Liu <charlene.liu@amd.com>
Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Fangzhi Zuo <jerry.zuo@amd.com>
---
 .../gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c   | 14 +++++++++-----
 .../amd/display/dc/dml2/dml2_translation_helper.c  |  5 +++--
 2 files changed, 12 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c
index e9d88f52717b..3d12dabd39e4 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c
@@ -124,7 +124,7 @@ struct _vcs_dpi_soc_bounding_box_st dcn3_5_soc = {
 			.phyclk_mhz = 600.0,
 			.phyclk_d18_mhz = 667.0,
 			.dscclk_mhz = 186.0,
-			.dtbclk_mhz = 625.0,
+			.dtbclk_mhz = 600.0,
 		},
 		{
 			.state = 1,
@@ -133,7 +133,7 @@ struct _vcs_dpi_soc_bounding_box_st dcn3_5_soc = {
 			.phyclk_mhz = 810.0,
 			.phyclk_d18_mhz = 667.0,
 			.dscclk_mhz = 209.0,
-			.dtbclk_mhz = 625.0,
+			.dtbclk_mhz = 600.0,
 		},
 		{
 			.state = 2,
@@ -142,7 +142,7 @@ struct _vcs_dpi_soc_bounding_box_st dcn3_5_soc = {
 			.phyclk_mhz = 810.0,
 			.phyclk_d18_mhz = 667.0,
 			.dscclk_mhz = 209.0,
-			.dtbclk_mhz = 625.0,
+			.dtbclk_mhz = 600.0,
 		},
 		{
 			.state = 3,
@@ -151,7 +151,7 @@ struct _vcs_dpi_soc_bounding_box_st dcn3_5_soc = {
 			.phyclk_mhz = 810.0,
 			.phyclk_d18_mhz = 667.0,
 			.dscclk_mhz = 371.0,
-			.dtbclk_mhz = 625.0,
+			.dtbclk_mhz = 600.0,
 		},
 		{
 			.state = 4,
@@ -160,7 +160,7 @@ struct _vcs_dpi_soc_bounding_box_st dcn3_5_soc = {
 			.phyclk_mhz = 810.0,
 			.phyclk_d18_mhz = 667.0,
 			.dscclk_mhz = 417.0,
-			.dtbclk_mhz = 625.0,
+			.dtbclk_mhz = 600.0,
 		},
 	},
 	.num_states = 5,
@@ -367,6 +367,8 @@ void dcn35_update_bw_bounding_box_fpu(struct dc *dc,
 				clock_limits[i].socclk_mhz;
 			dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].memclk_mhz =
 				clk_table->entries[i].memclk_mhz * clk_table->entries[i].wck_ratio;
+			dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].dtbclk_mhz =
+				clock_limits[i].dtbclk_mhz;
 			dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_dcfclk_levels =
 				clk_table->num_entries;
 			dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_fclk_levels =
@@ -379,6 +381,8 @@ void dcn35_update_bw_bounding_box_fpu(struct dc *dc,
 				clk_table->num_entries;
 			dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_memclk_levels =
 				clk_table->num_entries;
+			dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_dtbclk_levels =
+				clk_table->num_entries;
 		}
 	}
 
diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.c b/drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.c
index 255af7875c08..279e7605a0a2 100644
--- a/drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.c
+++ b/drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.c
@@ -425,8 +425,9 @@ void dml2_init_soc_states(struct dml2_context *dml2, const struct dc *in_dc,
 		}
 
 		for (i = 0; i < dml2->config.bbox_overrides.clks_table.num_entries_per_clk.num_dtbclk_levels; i++) {
-			p->in_states->state_array[i].dtbclk_mhz =
-				dml2->config.bbox_overrides.clks_table.clk_entries[i].dtbclk_mhz;
+			if (dml2->config.bbox_overrides.clks_table.clk_entries[i].dtbclk_mhz > 0)
+				p->in_states->state_array[i].dtbclk_mhz =
+					dml2->config.bbox_overrides.clks_table.clk_entries[i].dtbclk_mhz;
 		}
 
 		for (i = 0; i < dml2->config.bbox_overrides.clks_table.num_entries_per_clk.num_dispclk_levels; i++) {
-- 
2.39.2


  parent reply	other threads:[~2023-12-06 19:52 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-12-06 19:52 [PATCH 00/13] DC Patches for Dec 11, 2023 Aurabindo Pillai
2023-12-06 19:52 ` [PATCH 01/13] drm/amd/display: Remove minor revision 5 until proper parser is ready Aurabindo Pillai
2023-12-06 19:52 ` [PATCH 02/13] drm/amd/display: Use explicit size for types in DCCG's struct dp_dto_params Aurabindo Pillai
2023-12-06 19:52 ` [PATCH 03/13] drm/amd/display: allow DP40 cables to do UHBR13.5 Aurabindo Pillai
2023-12-06 19:52 ` [PATCH 04/13] drm/amd/display: Revert "Fix conversions between bytes and KB" Aurabindo Pillai
2023-12-06 19:52 ` [PATCH 05/13] drm/amd/display: trivial comment change Aurabindo Pillai
2023-12-06 19:52 ` [PATCH 06/13] drm/amd/display: Revert DP2 MST hub triple display fix Aurabindo Pillai
2023-12-06 19:52 ` Aurabindo Pillai [this message]
2023-12-06 19:52 ` [PATCH 08/13] drm/amd/display: Disable OPTC pg to match DC Hubp/dpp pg Aurabindo Pillai
2023-12-06 19:52 ` [PATCH 09/13] drm/amd/display: Exit from idle state before accessing HW data Aurabindo Pillai
2023-12-06 19:52 ` [PATCH 10/13] drm/amd/display: For prefetch mode > 0, extend prefetch if possible Aurabindo Pillai
2023-12-06 19:52 ` [PATCH 11/13] drm/amd/display: Force p-state disallow if leaving no plane config Aurabindo Pillai
2023-12-06 19:52 ` [PATCH 12/13] drm/amd/display: fix HW block PG sequence Aurabindo Pillai
2023-12-06 19:52 ` [PATCH 13/13] drm/amd/display: 3.2.264 Aurabindo Pillai
2023-12-11 14:42 ` [PATCH 00/13] DC Patches for Dec 11, 2023 Wheeler, Daniel

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