* [PATCH 00/25] DC Patches April 10, 2024
@ 2024-04-10 21:25 Rodrigo Siqueira
2024-04-10 21:25 ` [PATCH 01/25] drm/amd/display: Modify power sequence Rodrigo Siqueira
` (25 more replies)
0 siblings, 26 replies; 28+ messages in thread
From: Rodrigo Siqueira @ 2024-04-10 21:25 UTC (permalink / raw)
To: amd-gfx
Cc: Harry.Wentland, Sunpeng.Li, Rodrigo.Siqueira, Aurabindo.Pillai,
roman.li, wayne.lin, agustin.gutierrez, chiahsuan.chung,
hersenxs.wu, jerry.zuo, Daniel Wheeler
This DC patchset brings improvements in multiple areas. In summary, we
have:
* Expand dmub_cmd operations.
* Update DVI configuration.
* Modify power sequence.
* Enable Z10 flag for IPS.
* Multiple code cleanups.
Cc: Daniel Wheeler <daniel.wheeler@amd.com>
Thanks
Siqueira
Anthony Koo (1):
drm/amd/display: Expand dmub_cmd operations
Aric Cyr (1):
drm/amd/display: 3.2.281
Bitnun, Ethan (1):
drm/amd/display: Improve the log precision
Chaitanya Dhere (1):
drm/amd/display: Fix incorrect pointer assignment
Charlene Liu (1):
drm/amd/display: limit the code change to ips enabled asic
Chris Park (1):
drm/amd/display: Add a function for checking tmds mode
Eric Bernstein (1):
drm/amd/display: Update FMT settings for 4:2:0
Mikita Lipski (1):
drm/amd/display: Fix PSR command version passed
Nicholas Kazlauskas (1):
drm/amd/display: Pass sequential ONO bit to DMCUB boot options
Rodrigo Siqueira (11):
drm/amd/display: Use dce_version instead of chip_id
drm/amd/display: Adjust headers
drm/amd/display: Group scl_data together in
resource_build_scaling_params
drm/amd/display: Replace int with unsigned int
drm/amd/display: Update some comments to improve the code readability
drm/amd/display: Remove unnecessary code
drm/amd/display: Rework dcn10_stream_encoder header
drm/amd/display: Move REG sequence from program ogam to idle before
connect
drm/amd/display: Update DCN201 link encoder registers
drm/amd/display: Add missing callback for init_watermarks in DCN 301
drm/amd/display: Add missing replay field
Samson Tam (1):
drm/amd/display: add support for chroma offset
Sung Joon Kim (4):
drm/amd/display: Modify power sequence
drm/amd/display: Modify resource allocation logic
drm/amd/display: Enable Z10 flag for IPS FSM
drm/amd/display: Rework power sequence and resource allocation logic
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 9 +
.../gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c | 2 +-
.../display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c | 3 +-
drivers/gpu/drm/amd/display/dc/core/dc.c | 8 +-
.../gpu/drm/amd/display/dc/core/dc_resource.c | 5 +-
.../gpu/drm/amd/display/dc/core/dc_state.c | 10 +-
.../gpu/drm/amd/display/dc/core/dc_stream.c | 2 +-
drivers/gpu/drm/amd/display/dc/dc.h | 16 +-
drivers/gpu/drm/amd/display/dc/dc_hw_types.h | 7 +
drivers/gpu/drm/amd/display/dc/dc_types.h | 2 +
.../gpu/drm/amd/display/dc/dce/dce_i2c_hw.c | 6 -
.../amd/display/dc/dcn10/dcn10_link_encoder.h | 6 -
.../gpu/drm/amd/display/dc/dcn10/dcn10_opp.c | 9 +-
.../gpu/drm/amd/display/dc/dcn10/dcn10_opp.h | 2 +
.../display/dc/dcn10/dcn10_stream_encoder.h | 10 +-
.../gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h | 2 +-
.../gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c | 10 +-
.../drm/amd/display/dc/dcn201/dcn201_hubp.c | 5 +
.../display/dc/dcn201/dcn201_link_encoder.h | 14 +-
.../gpu/drm/amd/display/dc/dcn30/dcn30_dccg.h | 18 --
.../dc/dcn30/dcn30_dio_stream_encoder.c | 1 -
.../gpu/drm/amd/display/dc/dcn30/dcn30_dwb.c | 2 -
.../drm/amd/display/dc/dcn301/dcn301_hubbub.c | 1 +
drivers/gpu/drm/amd/display/dc/hwss/Makefile | 2 +-
.../drm/amd/display/dc/hwss/dcn351/Makefile | 25 ++-
.../amd/display/dc/hwss/dcn351/dcn351_hwseq.c | 182 ++++++++++++++++++
.../amd/display/dc/hwss/dcn351/dcn351_hwseq.h | 41 ++++
.../amd/display/dc/hwss/dcn351/dcn351_init.c | 1 +
.../dc/resource/dcn32/dcn32_resource.c | 4 +-
.../dc/resource/dcn32/dcn32_resource.h | 6 +
.../dc/resource/dcn351/dcn351_resource.c | 5 +-
drivers/gpu/drm/amd/display/dmub/dmub_srv.h | 1 +
.../gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 53 ++++-
.../gpu/drm/amd/display/dmub/src/dmub_dcn35.c | 1 +
.../drm/amd/display/include/signal_types.h | 13 ++
35 files changed, 402 insertions(+), 82 deletions(-)
create mode 100644 drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.c
create mode 100644 drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.h
--
2.43.0
^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH 01/25] drm/amd/display: Modify power sequence
2024-04-10 21:25 [PATCH 00/25] DC Patches April 10, 2024 Rodrigo Siqueira
@ 2024-04-10 21:25 ` Rodrigo Siqueira
2024-04-10 21:25 ` [PATCH 02/25] drm/amd/display: Add a function for checking tmds mode Rodrigo Siqueira
` (24 subsequent siblings)
25 siblings, 0 replies; 28+ messages in thread
From: Rodrigo Siqueira @ 2024-04-10 21:25 UTC (permalink / raw)
To: amd-gfx
Cc: Harry.Wentland, Sunpeng.Li, Rodrigo.Siqueira, Aurabindo.Pillai,
roman.li, wayne.lin, agustin.gutierrez, chiahsuan.chung,
hersenxs.wu, jerry.zuo, Sung Joon Kim, Duncan Ma,
Rodrigo Siqueira
From: Sung Joon Kim <sungjoon.kim@amd.com>
Need to update the power sequence to help prevent potential issues like
multi-display or multi-plane.
Reviewed-by: Duncan Ma <duncan.ma@amd.com>
Acked-by: Rodrigo Siqueira <rodrigo.siqueira@amd.com>
Signed-off-by: Sung Joon Kim <sungjoon.kim@amd.com>
---
drivers/gpu/drm/amd/display/dc/hwss/Makefile | 2 +-
.../drm/amd/display/dc/hwss/dcn351/Makefile | 25 ++-
.../amd/display/dc/hwss/dcn351/dcn351_hwseq.c | 182 ++++++++++++++++++
.../amd/display/dc/hwss/dcn351/dcn351_hwseq.h | 41 ++++
.../amd/display/dc/hwss/dcn351/dcn351_init.c | 9 +-
5 files changed, 247 insertions(+), 12 deletions(-)
create mode 100644 drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.c
create mode 100644 drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.h
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/Makefile b/drivers/gpu/drm/amd/display/dc/hwss/Makefile
index 9e8e9de51a92..cf8aa23b4415 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/hwss/Makefile
@@ -180,7 +180,7 @@ AMD_DISPLAY_FILES += $(AMD_DAL_HWSS_DCN35)
###############################################################################
-HWSS_DCN351 = dcn351_init.o
+HWSS_DCN351 = dcn351_hwseq.o dcn351_init.o
AMD_DAL_HWSS_DCN351 = $(addprefix $(AMDDALPATH)/dc/hwss/dcn351/,$(HWSS_DCN351))
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn351/Makefile b/drivers/gpu/drm/amd/display/dc/hwss/dcn351/Makefile
index b24ad27fe6ef..a4b3c1e99ec6 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn351/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn351/Makefile
@@ -1,16 +1,27 @@
#
-# (c) Copyright 2022 Advanced Micro Devices, Inc. All the rights reserved
+# Copyright (c) 2022-2024 Advanced Micro Devices, Inc.
#
-# All rights reserved. This notice is intended as a precaution against
-# inadvertent publication and does not imply publication or any waiver
-# of confidentiality. The year included in the foregoing notice is the
-# year of creation of the work.
+# Permission is hereby granted, free of charge, to any person obtaining a
+# copy of this software and associated documentation files (the "Software"),
+# to deal in the Software without restriction, including without limitation
+# the rights to use, copy, modify, merge, publish, distribute, sublicense,
+# and/or sell copies of the Software, and to permit persons to whom the
+# Software is furnished to do so, subject to the following conditions:
#
-# Authors: AMD
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+# THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+# OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+# ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+# OTHER DEALINGS IN THE SOFTWARE.
#
# Makefile for DCN351.
-DCN351 = dcn351_init.o
+DCN351 = dcn351_hwseq.o dcn351_init.o
AMD_DAL_DCN351 = $(addprefix $(AMDDALPATH)/dc/dcn351/,$(DCN351))
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.c
new file mode 100644
index 000000000000..93fe5b262a3d
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.c
@@ -0,0 +1,182 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright 2024 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "core_types.h"
+#include "resource.h"
+#include "dcn351_hwseq.h"
+#include "dcn35/dcn35_hwseq.h"
+
+#define DC_LOGGER_INIT(logger) \
+ struct dal_logger *dc_logger = logger
+
+#define DC_LOGGER \
+ dc_logger
+
+void dcn351_calc_blocks_to_gate(struct dc *dc, struct dc_state *context,
+ struct pg_block_update *update_state)
+{
+ int i, j;
+
+ dcn35_calc_blocks_to_gate(dc, context, update_state);
+
+ for (i = dc->res_pool->pipe_count - 1; i >= 0; i--) {
+ if (!update_state->pg_pipe_res_update[PG_HUBP][i] &&
+ !update_state->pg_pipe_res_update[PG_DPP][i]) {
+ for (j = i - 1; j >= 0; j--) {
+ update_state->pg_pipe_res_update[PG_HUBP][j] = false;
+ update_state->pg_pipe_res_update[PG_DPP][j] = false;
+ }
+
+ break;
+ }
+ }
+}
+
+void dcn351_calc_blocks_to_ungate(struct dc *dc, struct dc_state *context,
+ struct pg_block_update *update_state)
+{
+ int i, j;
+
+ dcn35_calc_blocks_to_ungate(dc, context, update_state);
+
+ for (i = dc->res_pool->pipe_count - 1; i >= 0; i--) {
+ if (update_state->pg_pipe_res_update[PG_HUBP][i] &&
+ update_state->pg_pipe_res_update[PG_DPP][i]) {
+ for (j = i - 1; j >= 0; j--) {
+ update_state->pg_pipe_res_update[PG_HUBP][j] = true;
+ update_state->pg_pipe_res_update[PG_DPP][j] = true;
+ }
+
+ break;
+ }
+ }
+}
+
+/**
+ * dcn351_hw_block_power_down() - power down sequence
+ *
+ * The following sequence describes the ON-OFF (ONO) for power down:
+ *
+ * ONO Region 11, DCPG 19: dsc3
+ * ONO Region 10, DCPG 3: dchubp3, dpp3
+ * ONO Region 9, DCPG 18: dsc2
+ * ONO Region 8, DCPG 2: dchubp2, dpp2
+ * ONO Region 7, DCPG 17: dsc1
+ * ONO Region 6, DCPG 1: dchubp1, dpp1
+ * ONO Region 5, DCPG 16: dsc0
+ * ONO Region 4, DCPG 0: dchubp0, dpp0
+ * ONO Region 3, DCPG 25: hpo - SKIPPED. Should be kept on
+ * ONO Region 2, DCPG 24: mpc opp optc dwb
+ * ONO Region 1, DCPG 23: dchubbub dchvm dchubbubmem - SKIPPED. PMFW will pwr dwn at IPS2 entry
+ * ONO Region 0, DCPG 22: dccg dio dcio - SKIPPED. will be pwr dwn after lono timer is armed
+ *
+ * @dc: Current DC state
+ * @update_state: update PG sequence states for HW block
+ */
+void dcn351_hw_block_power_down(struct dc *dc,
+ struct pg_block_update *update_state)
+{
+ int i = 0;
+ struct pg_cntl *pg_cntl = dc->res_pool->pg_cntl;
+
+ if (!pg_cntl || dc->debug.ignore_pg)
+ return;
+
+ for (i = dc->res_pool->pipe_count - 1; i >= 0; i--) {
+ if (update_state->pg_pipe_res_update[PG_DSC][i]) {
+ if (pg_cntl->funcs->dsc_pg_control)
+ pg_cntl->funcs->dsc_pg_control(pg_cntl, i, false);
+ }
+
+ if (update_state->pg_pipe_res_update[PG_HUBP][i] &&
+ update_state->pg_pipe_res_update[PG_DPP][i]) {
+ if (pg_cntl->funcs->hubp_dpp_pg_control)
+ pg_cntl->funcs->hubp_dpp_pg_control(pg_cntl, i, false);
+ }
+ }
+
+ // domain25 currently always on.
+
+ /* this will need all the clients to unregister optc interrupts, let dmubfw handle this */
+ if (pg_cntl->funcs->plane_otg_pg_control)
+ pg_cntl->funcs->plane_otg_pg_control(pg_cntl, false);
+
+ // domain23 currently always on.
+ // domain22 currently always on.
+}
+
+/**
+ * dcn351_hw_block_power_up() - power up sequence
+ *
+ * The following sequence describes the ON-OFF (ONO) for power up:
+ *
+ * ONO Region 0, DCPG 22: dccg dio dcio - SKIPPED
+ * ONO Region 1, DCPG 23: dchubbub dchvm dchubbubmem - SKIPPED. PMFW will power up at IPS2 exit
+ * ONO Region 2, DCPG 24: mpc opp optc dwb
+ * ONO Region 3, DCPG 25: hpo - SKIPPED
+ * ONO Region 4, DCPG 0: dchubp0, dpp0
+ * ONO Region 5, DCPG 16: dsc0
+ * ONO Region 6, DCPG 1: dchubp1, dpp1
+ * ONO Region 7, DCPG 17: dsc1
+ * ONO Region 8, DCPG 2: dchubp2, dpp2
+ * ONO Region 9, DCPG 18: dsc2
+ * ONO Region 10, DCPG 3: dchubp3, dpp3
+ * ONO Region 11, DCPG 19: dsc3
+ *
+ * @dc: Current DC state
+ * @update_state: update PG sequence states for HW block
+ */
+void dcn351_hw_block_power_up(struct dc *dc,
+ struct pg_block_update *update_state)
+{
+ int i = 0;
+ struct pg_cntl *pg_cntl = dc->res_pool->pg_cntl;
+
+ if (!pg_cntl || dc->debug.ignore_pg)
+ return;
+
+ // domain22 currently always on.
+ // domain23 currently always on.
+
+ /* this will need all the clients to unregister optc interrupts, let dmubfw handle this */
+ if (pg_cntl->funcs->plane_otg_pg_control)
+ pg_cntl->funcs->plane_otg_pg_control(pg_cntl, true);
+
+ // domain25 currently always on.
+
+ for (i = 0; i < dc->res_pool->pipe_count; i++) {
+ if (update_state->pg_pipe_res_update[PG_HUBP][i] &&
+ update_state->pg_pipe_res_update[PG_DPP][i]) {
+ if (pg_cntl->funcs->hubp_dpp_pg_control)
+ pg_cntl->funcs->hubp_dpp_pg_control(pg_cntl, i, true);
+ }
+
+ if (update_state->pg_pipe_res_update[PG_DSC][i]) {
+ if (pg_cntl->funcs->dsc_pg_control)
+ pg_cntl->funcs->dsc_pg_control(pg_cntl, i, true);
+ }
+ }
+}
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.h b/drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.h
new file mode 100644
index 000000000000..6d8f3bfb668e
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.h
@@ -0,0 +1,41 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright 2024 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef __DC_HWSS_DCN351_H__
+#define __DC_HWSS_DCN351_H__
+
+#include "hw_sequencer_private.h"
+
+void dcn351_calc_blocks_to_gate(struct dc *dc, struct dc_state *context,
+ struct pg_block_update *update_state);
+void dcn351_calc_blocks_to_ungate(struct dc *dc, struct dc_state *context,
+ struct pg_block_update *update_state);
+void dcn351_hw_block_power_up(struct dc *dc,
+ struct pg_block_update *update_state);
+void dcn351_hw_block_power_down(struct dc *dc,
+ struct pg_block_update *update_state);
+
+#endif /* __DC_HWSS_DCN351_H__ */
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_init.c
index c54f3518c947..c4944478ed91 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_init.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_init.c
@@ -32,6 +32,7 @@
#include "dcn31/dcn31_hwseq.h"
#include "dcn32/dcn32_hwseq.h"
#include "dcn35/dcn35_hwseq.h"
+#include "dcn351/dcn351_hwseq.h"
#include "dcn351_init.h"
@@ -115,10 +116,10 @@ static const struct hw_sequencer_funcs dcn351_funcs = {
.update_visual_confirm_color = dcn10_update_visual_confirm_color,
.apply_idle_power_optimizations = dcn35_apply_idle_power_optimizations,
.update_dsc_pg = dcn32_update_dsc_pg,
- .calc_blocks_to_gate = dcn35_calc_blocks_to_gate,
- .calc_blocks_to_ungate = dcn35_calc_blocks_to_ungate,
- .hw_block_power_up = dcn35_hw_block_power_up,
- .hw_block_power_down = dcn35_hw_block_power_down,
+ .calc_blocks_to_gate = dcn351_calc_blocks_to_gate,
+ .calc_blocks_to_ungate = dcn351_calc_blocks_to_ungate,
+ .hw_block_power_up = dcn351_hw_block_power_up,
+ .hw_block_power_down = dcn351_hw_block_power_down,
.root_clock_control = dcn35_root_clock_control,
};
--
2.43.0
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 02/25] drm/amd/display: Add a function for checking tmds mode
2024-04-10 21:25 [PATCH 00/25] DC Patches April 10, 2024 Rodrigo Siqueira
2024-04-10 21:25 ` [PATCH 01/25] drm/amd/display: Modify power sequence Rodrigo Siqueira
@ 2024-04-10 21:25 ` Rodrigo Siqueira
2024-04-15 19:16 ` Melissa Wen
2024-04-10 21:25 ` [PATCH 03/25] drm/amd/display: Modify resource allocation logic Rodrigo Siqueira
` (23 subsequent siblings)
25 siblings, 1 reply; 28+ messages in thread
From: Rodrigo Siqueira @ 2024-04-10 21:25 UTC (permalink / raw)
To: amd-gfx
Cc: Harry.Wentland, Sunpeng.Li, Rodrigo.Siqueira, Aurabindo.Pillai,
roman.li, wayne.lin, agustin.gutierrez, chiahsuan.chung,
hersenxs.wu, jerry.zuo, Chris Park, Dillon Varone,
Rodrigo Siqueira
From: Chris Park <chris.park@amd.com>
[Why]
DVI is TMDS signal like HDMI but without audio. Current signal check
does not correctly reflect DVI clock programming.
[How]
Define a new signal check for TMDS that includes DVI to HDMI TMDS
programming.
Reviewed-by: Dillon Varone <dillon.varone@amd.com>
Acked-by: Rodrigo Siqueira <rodrigo.siqueira@amd.com>
Signed-off-by: Chris Park <chris.park@amd.com>
---
drivers/gpu/drm/amd/display/include/signal_types.h | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/include/signal_types.h b/drivers/gpu/drm/amd/display/include/signal_types.h
index 1b14b17a79c7..a10d6b988aab 100644
--- a/drivers/gpu/drm/amd/display/include/signal_types.h
+++ b/drivers/gpu/drm/amd/display/include/signal_types.h
@@ -118,6 +118,19 @@ static inline bool dc_is_dvi_signal(enum signal_type signal)
}
}
+static inline bool dc_is_tmds_signal(enum signal_type signal)
+{
+ switch (signal) {
+ case SIGNAL_TYPE_DVI_SINGLE_LINK:
+ case SIGNAL_TYPE_DVI_DUAL_LINK:
+ case SIGNAL_TYPE_HDMI_TYPE_A:
+ return true;
+ break;
+ default:
+ return false;
+ }
+}
+
static inline bool dc_is_dvi_single_link_signal(enum signal_type signal)
{
return (signal == SIGNAL_TYPE_DVI_SINGLE_LINK);
--
2.43.0
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 03/25] drm/amd/display: Modify resource allocation logic
2024-04-10 21:25 [PATCH 00/25] DC Patches April 10, 2024 Rodrigo Siqueira
2024-04-10 21:25 ` [PATCH 01/25] drm/amd/display: Modify power sequence Rodrigo Siqueira
2024-04-10 21:25 ` [PATCH 02/25] drm/amd/display: Add a function for checking tmds mode Rodrigo Siqueira
@ 2024-04-10 21:25 ` Rodrigo Siqueira
2024-04-10 21:25 ` [PATCH 04/25] drm/amd/display: limit the code change to ips enabled asic Rodrigo Siqueira
` (22 subsequent siblings)
25 siblings, 0 replies; 28+ messages in thread
From: Rodrigo Siqueira @ 2024-04-10 21:25 UTC (permalink / raw)
To: amd-gfx
Cc: Harry.Wentland, Sunpeng.Li, Rodrigo.Siqueira, Aurabindo.Pillai,
roman.li, wayne.lin, agustin.gutierrez, chiahsuan.chung,
hersenxs.wu, jerry.zuo, Sung Joon Kim, Wenjing Liu,
Rodrigo Siqueira
From: Sung Joon Kim <sungjoon.kim@amd.com>
To reduce the complexity of pipe resource allocation for different
use-cases, now we search for any free pipe sequentially rather than from
bottom up.
Reviewed-by: Wenjing Liu <wenjing.liu@amd.com>
Acked-by: Rodrigo Siqueira <rodrigo.siqueira@amd.com>
Signed-off-by: Sung Joon Kim <sungjoon.kim@amd.com>
---
.../dc/resource/dcn32/dcn32_resource.c | 4 +--
.../dc/resource/dcn32/dcn32_resource.h | 6 ++++
.../dc/resource/dcn351/dcn351_resource.c | 35 ++++++++++++++++++-
.../dc/resource/dcn351/dcn351_resource.h | 6 ++++
4 files changed, 48 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
index 9aa39bd25be9..c16e915686fc 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
@@ -2547,7 +2547,7 @@ struct resource_pool *dcn32_create_resource_pool(
* full update which delays the flip for 1 frame. If we use the original pipe
* we don't have to toggle its power. So we can flip faster.
*/
-static int find_optimal_free_pipe_as_secondary_dpp_pipe(
+int dcn32_find_optimal_free_pipe_as_secondary_dpp_pipe(
const struct resource_context *cur_res_ctx,
struct resource_context *new_res_ctx,
const struct resource_pool *pool,
@@ -2730,7 +2730,7 @@ struct pipe_ctx *dcn32_acquire_free_pipe_as_secondary_dpp_pipe(
return dcn32_acquire_idle_pipe_for_head_pipe_in_layer(
new_ctx, pool, opp_head_pipe->stream, opp_head_pipe);
- free_pipe_idx = find_optimal_free_pipe_as_secondary_dpp_pipe(
+ free_pipe_idx = dcn32_find_optimal_free_pipe_as_secondary_dpp_pipe(
&cur_ctx->res_ctx, &new_ctx->res_ctx,
pool, opp_head_pipe);
if (free_pipe_idx >= 0) {
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h b/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
index 286e20ad46ed..fee67fbab8e2 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
@@ -137,6 +137,12 @@ bool dcn32_any_surfaces_rotated(struct dc *dc, struct dc_state *context);
bool dcn32_is_center_timing(struct pipe_ctx *pipe);
bool dcn32_is_psr_capable(struct pipe_ctx *pipe);
+int dcn32_find_optimal_free_pipe_as_secondary_dpp_pipe(
+ const struct resource_context *cur_res_ctx,
+ struct resource_context *new_res_ctx,
+ const struct resource_pool *pool,
+ const struct pipe_ctx *new_opp_head);
+
struct pipe_ctx *dcn32_acquire_free_pipe_as_secondary_dpp_pipe(
const struct dc_state *cur_ctx,
struct dc_state *new_ctx,
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
index 8a57adb27264..cc1a44a890b5 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
@@ -1728,6 +1728,37 @@ static bool dcn351_validate_bandwidth(struct dc *dc,
return out;
}
+struct pipe_ctx *dcn351_acquire_free_pipe_as_secondary_dpp_pipe(
+ const struct dc_state *cur_ctx,
+ struct dc_state *new_ctx,
+ const struct resource_pool *pool,
+ const struct pipe_ctx *opp_head_pipe)
+{
+ int free_pipe_idx;
+ struct pipe_ctx *free_pipe;
+
+ free_pipe_idx = dcn32_find_optimal_free_pipe_as_secondary_dpp_pipe(
+ &cur_ctx->res_ctx, &new_ctx->res_ctx,
+ pool, opp_head_pipe);
+ if (free_pipe_idx >= 0) {
+ free_pipe = &new_ctx->res_ctx.pipe_ctx[free_pipe_idx];
+ free_pipe->pipe_idx = free_pipe_idx;
+ free_pipe->stream = opp_head_pipe->stream;
+ free_pipe->stream_res.tg = opp_head_pipe->stream_res.tg;
+ free_pipe->stream_res.opp = opp_head_pipe->stream_res.opp;
+
+ free_pipe->plane_res.hubp = pool->hubps[free_pipe->pipe_idx];
+ free_pipe->plane_res.ipp = pool->ipps[free_pipe->pipe_idx];
+ free_pipe->plane_res.dpp = pool->dpps[free_pipe->pipe_idx];
+ free_pipe->plane_res.mpcc_inst =
+ pool->dpps[free_pipe->pipe_idx]->inst;
+ } else {
+ ASSERT(opp_head_pipe);
+ free_pipe = NULL;
+ }
+
+ return free_pipe;
+}
static struct resource_funcs dcn351_res_pool_funcs = {
.destroy = dcn351_destroy_resource_pool,
@@ -1740,7 +1771,8 @@ static struct resource_funcs dcn351_res_pool_funcs = {
.calculate_wm_and_dlg = NULL,
.update_soc_for_wm_a = dcn31_update_soc_for_wm_a,
.populate_dml_pipes = dcn351_populate_dml_pipes_from_context_fpu,
- .acquire_free_pipe_as_secondary_dpp_pipe = dcn20_acquire_free_pipe_for_layer,
+ .acquire_free_pipe_as_secondary_dpp_pipe = dcn351_acquire_free_pipe_as_secondary_dpp_pipe,
+ .acquire_free_pipe_as_secondary_opp_head = dcn32_acquire_free_pipe_as_secondary_opp_head,
.release_pipe = dcn20_release_pipe,
.add_stream_to_ctx = dcn30_add_stream_to_ctx,
.add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,
@@ -2130,6 +2162,7 @@ static bool dcn351_resource_construct(
dc->dml2_options.max_segments_per_hubp = 24;
dc->dml2_options.det_segment_size = DCN3_2_DET_SEG_SIZE;/*todo*/
+ dc->dml2_options.map_dc_pipes_with_callbacks = true;
if (dc->config.sdpif_request_limit_words_per_umc == 0)
dc->config.sdpif_request_limit_words_per_umc = 16;/*todo*/
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.h b/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.h
index f3e045777a3d..e4553c5100f8 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.h
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.h
@@ -20,4 +20,10 @@ struct resource_pool *dcn351_create_resource_pool(
const struct dc_init_data *init_data,
struct dc *dc);
+struct pipe_ctx *dcn351_acquire_free_pipe_as_secondary_dpp_pipe(
+ const struct dc_state *cur_ctx,
+ struct dc_state *new_ctx,
+ const struct resource_pool *pool,
+ const struct pipe_ctx *opp_head_pipe);
+
#endif /* _DCN351_RESOURCE_H_ */
--
2.43.0
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 04/25] drm/amd/display: limit the code change to ips enabled asic
2024-04-10 21:25 [PATCH 00/25] DC Patches April 10, 2024 Rodrigo Siqueira
` (2 preceding siblings ...)
2024-04-10 21:25 ` [PATCH 03/25] drm/amd/display: Modify resource allocation logic Rodrigo Siqueira
@ 2024-04-10 21:25 ` Rodrigo Siqueira
2024-04-10 21:25 ` [PATCH 05/25] drm/amd/display: add support for chroma offset Rodrigo Siqueira
` (21 subsequent siblings)
25 siblings, 0 replies; 28+ messages in thread
From: Rodrigo Siqueira @ 2024-04-10 21:25 UTC (permalink / raw)
To: amd-gfx
Cc: Harry.Wentland, Sunpeng.Li, Rodrigo.Siqueira, Aurabindo.Pillai,
roman.li, wayne.lin, agustin.gutierrez, chiahsuan.chung,
hersenxs.wu, jerry.zuo, Charlene Liu, Chris Park,
Rodrigo Siqueira
From: Charlene Liu <charlene.liu@amd.com>
Limit the code change for ips enable to reduce the impact for now. Also
exit_ips first before dc_power_down to avoid 0x9f.
Reviewed-by: Chris Park <chris.park@amd.com>
Acked-by: Rodrigo Siqueira <rodrigo.siqueira@amd.com>
Signed-off-by: Charlene Liu <charlene.liu@amd.com>
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 145cdab92ca0..01c75b66e8f1 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -5042,8 +5042,13 @@ void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src)
void dc_power_down_on_boot(struct dc *dc)
{
if (dc->ctx->dce_environment != DCE_ENV_VIRTUAL_HW &&
- dc->hwss.power_down_on_boot)
+ dc->hwss.power_down_on_boot) {
+
+ if (dc->caps.ips_support)
+ dc_exit_ips_for_hw_access(dc);
+
dc->hwss.power_down_on_boot(dc);
+ }
}
void dc_set_power_state(
--
2.43.0
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 05/25] drm/amd/display: add support for chroma offset
2024-04-10 21:25 [PATCH 00/25] DC Patches April 10, 2024 Rodrigo Siqueira
` (3 preceding siblings ...)
2024-04-10 21:25 ` [PATCH 04/25] drm/amd/display: limit the code change to ips enabled asic Rodrigo Siqueira
@ 2024-04-10 21:25 ` Rodrigo Siqueira
2024-04-10 21:25 ` [PATCH 06/25] drm/amd/display: Pass sequential ONO bit to DMCUB boot options Rodrigo Siqueira
` (20 subsequent siblings)
25 siblings, 0 replies; 28+ messages in thread
From: Rodrigo Siqueira @ 2024-04-10 21:25 UTC (permalink / raw)
To: amd-gfx
Cc: Harry.Wentland, Sunpeng.Li, Rodrigo.Siqueira, Aurabindo.Pillai,
roman.li, wayne.lin, agustin.gutierrez, chiahsuan.chung,
hersenxs.wu, jerry.zuo, Samson Tam, Jun Lei, Rodrigo Siqueira
From: Samson Tam <samson.tam@amd.com>
[Why]
Adding support for chroma subsampling offset (cositing) in scaler
calculations to adjust reference point where we determine post-scaling
chroma value in YUV420 surfaces.
[How]
Add support for cositing options: NONE, LEFT and TOPLEFT Add debug
option force_cositing and set default to TOPLEFT to maintain same
behaviour as without offset support.
Reviewed-by: Jun Lei <jun.lei@amd.com>
Acked-by: Rodrigo Siqueira <rodrigo.siqueira@amd.com>
Signed-off-by: Samson Tam <samson.tam@amd.com>
---
drivers/gpu/drm/amd/display/dc/dc.h | 3 +++
drivers/gpu/drm/amd/display/dc/dc_hw_types.h | 7 +++++++
2 files changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index 54534df73e83..188f2d401124 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -1003,6 +1003,7 @@ struct dc_debug_options {
unsigned int static_screen_wait_frames;
bool force_chroma_subsampling_1tap;
bool disable_422_left_edge_pixel;
+ unsigned int force_cositing;
};
struct gpu_info_soc_bounding_box_v1_0;
@@ -1285,6 +1286,7 @@ struct dc_plane_state {
struct tg_color visual_confirm_color;
bool is_statically_allocated;
+ enum chroma_cositing cositing;
};
struct dc_plane_info {
@@ -1303,6 +1305,7 @@ struct dc_plane_info {
int global_alpha_value;
bool input_csc_enabled;
int layer_index;
+ enum chroma_cositing cositing;
};
#include "dc_stream.h"
diff --git a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
index 465e15f57f93..2ad7f60805f5 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
@@ -738,6 +738,13 @@ enum scanning_type {
SCANNING_TYPE_UNDEFINED
};
+enum chroma_cositing {
+ CHROMA_COSITING_NONE,
+ CHROMA_COSITING_LEFT,
+ CHROMA_COSITING_TOPLEFT,
+ CHROMA_COSITING_COUNT
+};
+
struct dc_crtc_timing_flags {
uint32_t INTERLACE :1;
uint32_t HSYNC_POSITIVE_POLARITY :1; /* when set to 1,
--
2.43.0
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 06/25] drm/amd/display: Pass sequential ONO bit to DMCUB boot options
2024-04-10 21:25 [PATCH 00/25] DC Patches April 10, 2024 Rodrigo Siqueira
` (4 preceding siblings ...)
2024-04-10 21:25 ` [PATCH 05/25] drm/amd/display: add support for chroma offset Rodrigo Siqueira
@ 2024-04-10 21:25 ` Rodrigo Siqueira
2024-04-10 21:25 ` [PATCH 07/25] drm/amd/display: Fix incorrect pointer assignment Rodrigo Siqueira
` (19 subsequent siblings)
25 siblings, 0 replies; 28+ messages in thread
From: Rodrigo Siqueira @ 2024-04-10 21:25 UTC (permalink / raw)
To: amd-gfx
Cc: Harry.Wentland, Sunpeng.Li, Rodrigo.Siqueira, Aurabindo.Pillai,
roman.li, wayne.lin, agustin.gutierrez, chiahsuan.chung,
hersenxs.wu, jerry.zuo, Nicholas Kazlauskas, Sung joon Kim,
Rodrigo Siqueira
From: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
[Why]
IPS ono sequence ordering differs based on the ASIC.
[How]
Detect the ASIC ID revision and set the boot option accordingly. Feed
it through the DCN35 DMUB functions.
Reviewed-by: Sung joon Kim <sungjoon.kim@amd.com>
Acked-by: Rodrigo Siqueira <rodrigo.siqueira@amd.com>
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 9 +++++++++
drivers/gpu/drm/amd/display/dmub/dmub_srv.h | 1 +
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c | 1 +
3 files changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index d52701f6d1d0..2c06f2bee4a5 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -1230,6 +1230,15 @@ static int dm_dmub_hw_init(struct amdgpu_device *adev)
break;
}
+ switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) {
+ case IP_VERSION(3, 5, 0):
+ case IP_VERSION(3, 5, 1):
+ hw_params.ips_sequential_ono = adev->external_rev_id > 0x10;
+ break;
+ default:
+ break;
+ }
+
status = dmub_srv_hw_init(dmub_srv, &hw_params);
if (status != DMUB_STATUS_OK) {
DRM_ERROR("Error initializing DMUB HW: %d\n", status);
diff --git a/drivers/gpu/drm/amd/display/dmub/dmub_srv.h b/drivers/gpu/drm/amd/display/dmub/dmub_srv.h
index 662bdb0e5d3d..2fde1f043d50 100644
--- a/drivers/gpu/drm/amd/display/dmub/dmub_srv.h
+++ b/drivers/gpu/drm/amd/display/dmub/dmub_srv.h
@@ -297,6 +297,7 @@ struct dmub_srv_hw_params {
bool dpia_hpd_int_enable_supported;
bool disable_clock_gate;
bool disallow_dispclk_dppclk_ds;
+ bool ips_sequential_ono;
enum dmub_memory_access_type mem_access_type;
enum dmub_ips_disable_type disable_ips;
};
diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c
index 98afaecd3984..70e63aeb8f89 100644
--- a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c
+++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c
@@ -420,6 +420,7 @@ void dmub_dcn35_enable_dmub_boot_options(struct dmub_srv *dmub, const struct dmu
boot_options.bits.disable_clk_ds = params->disallow_dispclk_dppclk_ds;
boot_options.bits.disable_clk_gate = params->disable_clock_gate;
boot_options.bits.ips_disable = params->disable_ips;
+ boot_options.bits.ips_sequential_ono = params->ips_sequential_ono;
REG_WRITE(DMCUB_SCRATCH14, boot_options.all);
}
--
2.43.0
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 07/25] drm/amd/display: Fix incorrect pointer assignment
2024-04-10 21:25 [PATCH 00/25] DC Patches April 10, 2024 Rodrigo Siqueira
` (5 preceding siblings ...)
2024-04-10 21:25 ` [PATCH 06/25] drm/amd/display: Pass sequential ONO bit to DMCUB boot options Rodrigo Siqueira
@ 2024-04-10 21:25 ` Rodrigo Siqueira
2024-04-10 21:25 ` [PATCH 08/25] drm/amd/display: Enable Z10 flag for IPS FSM Rodrigo Siqueira
` (18 subsequent siblings)
25 siblings, 0 replies; 28+ messages in thread
From: Rodrigo Siqueira @ 2024-04-10 21:25 UTC (permalink / raw)
To: amd-gfx
Cc: Harry.Wentland, Sunpeng.Li, Rodrigo.Siqueira, Aurabindo.Pillai,
roman.li, wayne.lin, agustin.gutierrez, chiahsuan.chung,
hersenxs.wu, jerry.zuo, Chaitanya Dhere, Aurabindo Pillai,
Rodrigo Siqueira
From: Chaitanya Dhere <chaitanya.dhere@amd.com>
[Why]
Pointer initialization and assignment for dml2_options is not done
correctly. While this works for some compilers, others give an error.
[How]
Modify dc_state_create code to correctly initialize the dml2_opt pointer
and pass it to dml2_create. Also update the code with correct derefrence
operations.
Reviewed-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Acked-by: Rodrigo Siqueira <rodrigo.siqueira@amd.com>
Signed-off-by: Chaitanya Dhere <chaitanya.dhere@amd.com>
---
drivers/gpu/drm/amd/display/dc/core/dc_state.c | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_state.c b/drivers/gpu/drm/amd/display/dc/core/dc_state.c
index bf889bdd3925..76bb05f4d6bf 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_state.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_state.c
@@ -191,7 +191,7 @@ static void init_state(struct dc *dc, struct dc_state *state)
struct dc_state *dc_state_create(struct dc *dc, struct dc_state_create_params *params)
{
#ifdef CONFIG_DRM_AMD_DC_FP
- struct dml2_configuration_options dml2_opt = dc->dml2_options;
+ struct dml2_configuration_options *dml2_opt = &dc->dml2_options;
#endif
struct dc_state *state = kvzalloc(sizeof(struct dc_state),
GFP_KERNEL);
@@ -205,11 +205,11 @@ struct dc_state *dc_state_create(struct dc *dc, struct dc_state_create_params *p
#ifdef CONFIG_DRM_AMD_DC_FP
if (dc->debug.using_dml2) {
- dml2_opt.use_clock_dc_limits = false;
- dml2_create(dc, &dml2_opt, &state->bw_ctx.dml2);
+ dml2_opt->use_clock_dc_limits = false;
+ dml2_create(dc, dml2_opt, &state->bw_ctx.dml2);
- dml2_opt.use_clock_dc_limits = true;
- dml2_create(dc, &dml2_opt, &state->bw_ctx.dml2_dc_power_source);
+ dml2_opt->use_clock_dc_limits = true;
+ dml2_create(dc, dml2_opt, &state->bw_ctx.dml2_dc_power_source);
}
#endif
--
2.43.0
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 08/25] drm/amd/display: Enable Z10 flag for IPS FSM
2024-04-10 21:25 [PATCH 00/25] DC Patches April 10, 2024 Rodrigo Siqueira
` (6 preceding siblings ...)
2024-04-10 21:25 ` [PATCH 07/25] drm/amd/display: Fix incorrect pointer assignment Rodrigo Siqueira
@ 2024-04-10 21:25 ` Rodrigo Siqueira
2024-04-10 21:25 ` [PATCH 09/25] drm/amd/display: Rework power sequence and resource allocation logic Rodrigo Siqueira
` (17 subsequent siblings)
25 siblings, 0 replies; 28+ messages in thread
From: Rodrigo Siqueira @ 2024-04-10 21:25 UTC (permalink / raw)
To: amd-gfx
Cc: Harry.Wentland, Sunpeng.Li, Rodrigo.Siqueira, Aurabindo.Pillai,
roman.li, wayne.lin, agustin.gutierrez, chiahsuan.chung,
hersenxs.wu, jerry.zuo, Sung Joon Kim, Nicholas Kazlauskas,
Rodrigo Siqueira
From: Sung Joon Kim <sungjoon.kim@amd.com>
[why]
IPS FSM requires Z10 flag to be enabled to do save and restore the
registers properly.
[how]
Enable Z10 and use the correct function to determine Z10 capability
Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Acked-by: Rodrigo Siqueira <rodrigo.siqueira@amd.com>
Signed-off-by: Sung Joon Kim <sungjoon.kim@amd.com>
---
.../gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
index cc1a44a890b5..b29d7d47552b 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
@@ -758,7 +758,7 @@ static const struct dc_debug_options debug_defaults_drv = {
//must match enable_single_display_2to1_odm_policy to support dynamic ODM transitions
.enable_double_buffered_dsc_pg_support = true,
.enable_dp_dig_pixel_rate_div_policy = 1,
- .disable_z10 = true,
+ .disable_z10 = false,
.ignore_pg = true,
.psp_disabled_wa = true,
.ips2_eval_delay_us = 2000,
@@ -1722,7 +1722,7 @@ static bool dcn351_validate_bandwidth(struct dc *dc,
return out;
DC_FP_START();
- dcn351_decide_zstate_support(dc, context);
+ dcn35_decide_zstate_support(dc, context);
DC_FP_END();
return out;
--
2.43.0
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 09/25] drm/amd/display: Rework power sequence and resource allocation logic
2024-04-10 21:25 [PATCH 00/25] DC Patches April 10, 2024 Rodrigo Siqueira
` (7 preceding siblings ...)
2024-04-10 21:25 ` [PATCH 08/25] drm/amd/display: Enable Z10 flag for IPS FSM Rodrigo Siqueira
@ 2024-04-10 21:25 ` Rodrigo Siqueira
2024-04-10 21:25 ` [PATCH 10/25] drm/amd/display: Expand dmub_cmd operations Rodrigo Siqueira
` (16 subsequent siblings)
25 siblings, 0 replies; 28+ messages in thread
From: Rodrigo Siqueira @ 2024-04-10 21:25 UTC (permalink / raw)
To: amd-gfx
Cc: Harry.Wentland, Sunpeng.Li, Rodrigo.Siqueira, Aurabindo.Pillai,
roman.li, wayne.lin, agustin.gutierrez, chiahsuan.chung,
hersenxs.wu, jerry.zuo, Sung Joon Kim, Xi Liu, Rodrigo Siqueira
From: Sung Joon Kim <sungjoon.kim@amd.com>
Rework part of the modifications made to the power sequence and resource
allocation logic.
Reviewed-by: Xi (Alex) Liu <xi.liu@amd.com>
Acked-by: Rodrigo Siqueira <rodrigo.siqueira@amd.com>
Signed-off-by: Sung Joon Kim <sungjoon.kim@amd.com>
---
.../amd/display/dc/hwss/dcn351/dcn351_init.c | 8 ++---
.../dc/resource/dcn351/dcn351_resource.c | 36 +------------------
.../dc/resource/dcn351/dcn351_resource.h | 6 ----
3 files changed, 5 insertions(+), 45 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_init.c
index c4944478ed91..a53092cd619b 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_init.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_init.c
@@ -116,10 +116,10 @@ static const struct hw_sequencer_funcs dcn351_funcs = {
.update_visual_confirm_color = dcn10_update_visual_confirm_color,
.apply_idle_power_optimizations = dcn35_apply_idle_power_optimizations,
.update_dsc_pg = dcn32_update_dsc_pg,
- .calc_blocks_to_gate = dcn351_calc_blocks_to_gate,
- .calc_blocks_to_ungate = dcn351_calc_blocks_to_ungate,
- .hw_block_power_up = dcn351_hw_block_power_up,
- .hw_block_power_down = dcn351_hw_block_power_down,
+ .calc_blocks_to_gate = dcn35_calc_blocks_to_gate,
+ .calc_blocks_to_ungate = dcn35_calc_blocks_to_ungate,
+ .hw_block_power_up = dcn35_hw_block_power_up,
+ .hw_block_power_down = dcn35_hw_block_power_down,
.root_clock_control = dcn35_root_clock_control,
};
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
index b29d7d47552b..3acfbbac8538 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
@@ -1728,38 +1728,6 @@ static bool dcn351_validate_bandwidth(struct dc *dc,
return out;
}
-struct pipe_ctx *dcn351_acquire_free_pipe_as_secondary_dpp_pipe(
- const struct dc_state *cur_ctx,
- struct dc_state *new_ctx,
- const struct resource_pool *pool,
- const struct pipe_ctx *opp_head_pipe)
-{
- int free_pipe_idx;
- struct pipe_ctx *free_pipe;
-
- free_pipe_idx = dcn32_find_optimal_free_pipe_as_secondary_dpp_pipe(
- &cur_ctx->res_ctx, &new_ctx->res_ctx,
- pool, opp_head_pipe);
- if (free_pipe_idx >= 0) {
- free_pipe = &new_ctx->res_ctx.pipe_ctx[free_pipe_idx];
- free_pipe->pipe_idx = free_pipe_idx;
- free_pipe->stream = opp_head_pipe->stream;
- free_pipe->stream_res.tg = opp_head_pipe->stream_res.tg;
- free_pipe->stream_res.opp = opp_head_pipe->stream_res.opp;
-
- free_pipe->plane_res.hubp = pool->hubps[free_pipe->pipe_idx];
- free_pipe->plane_res.ipp = pool->ipps[free_pipe->pipe_idx];
- free_pipe->plane_res.dpp = pool->dpps[free_pipe->pipe_idx];
- free_pipe->plane_res.mpcc_inst =
- pool->dpps[free_pipe->pipe_idx]->inst;
- } else {
- ASSERT(opp_head_pipe);
- free_pipe = NULL;
- }
-
- return free_pipe;
-}
-
static struct resource_funcs dcn351_res_pool_funcs = {
.destroy = dcn351_destroy_resource_pool,
.link_enc_create = dcn35_link_encoder_create,
@@ -1771,8 +1739,7 @@ static struct resource_funcs dcn351_res_pool_funcs = {
.calculate_wm_and_dlg = NULL,
.update_soc_for_wm_a = dcn31_update_soc_for_wm_a,
.populate_dml_pipes = dcn351_populate_dml_pipes_from_context_fpu,
- .acquire_free_pipe_as_secondary_dpp_pipe = dcn351_acquire_free_pipe_as_secondary_dpp_pipe,
- .acquire_free_pipe_as_secondary_opp_head = dcn32_acquire_free_pipe_as_secondary_opp_head,
+ .acquire_free_pipe_as_secondary_dpp_pipe = dcn20_acquire_free_pipe_for_layer,
.release_pipe = dcn20_release_pipe,
.add_stream_to_ctx = dcn30_add_stream_to_ctx,
.add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,
@@ -2162,7 +2129,6 @@ static bool dcn351_resource_construct(
dc->dml2_options.max_segments_per_hubp = 24;
dc->dml2_options.det_segment_size = DCN3_2_DET_SEG_SIZE;/*todo*/
- dc->dml2_options.map_dc_pipes_with_callbacks = true;
if (dc->config.sdpif_request_limit_words_per_umc == 0)
dc->config.sdpif_request_limit_words_per_umc = 16;/*todo*/
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.h b/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.h
index e4553c5100f8..f3e045777a3d 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.h
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.h
@@ -20,10 +20,4 @@ struct resource_pool *dcn351_create_resource_pool(
const struct dc_init_data *init_data,
struct dc *dc);
-struct pipe_ctx *dcn351_acquire_free_pipe_as_secondary_dpp_pipe(
- const struct dc_state *cur_ctx,
- struct dc_state *new_ctx,
- const struct resource_pool *pool,
- const struct pipe_ctx *opp_head_pipe);
-
#endif /* _DCN351_RESOURCE_H_ */
--
2.43.0
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 10/25] drm/amd/display: Expand dmub_cmd operations
2024-04-10 21:25 [PATCH 00/25] DC Patches April 10, 2024 Rodrigo Siqueira
` (8 preceding siblings ...)
2024-04-10 21:25 ` [PATCH 09/25] drm/amd/display: Rework power sequence and resource allocation logic Rodrigo Siqueira
@ 2024-04-10 21:25 ` Rodrigo Siqueira
2024-04-10 21:26 ` [PATCH 11/25] drm/amd/display: Use dce_version instead of chip_id Rodrigo Siqueira
` (15 subsequent siblings)
25 siblings, 0 replies; 28+ messages in thread
From: Rodrigo Siqueira @ 2024-04-10 21:25 UTC (permalink / raw)
To: amd-gfx
Cc: Harry.Wentland, Sunpeng.Li, Rodrigo.Siqueira, Aurabindo.Pillai,
roman.li, wayne.lin, agustin.gutierrez, chiahsuan.chung,
hersenxs.wu, jerry.zuo, Anthony Koo, Rodrigo Siqueira
From: Anthony Koo <anthony.koo@amd.com>
Update dmub_cmd to manipulate SDP control in replay FSM, add command
for panel_cntl, expand link rate enum, and increase the reserve byte.
Acked-by: Rodrigo Siqueira <rodrigo.siqueira@amd.com>
Signed-off-by: Anthony Koo <anthony.koo@amd.com>
---
.../gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 53 ++++++++++++++++++-
1 file changed, 52 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
index 944f14307517..e85fd3ac52c7 100644
--- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
+++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
@@ -1614,7 +1614,7 @@ struct dmub_rb_cmd_idle_opt_dcn_restore {
*/
struct dmub_dcn_notify_idle_cntl_data {
uint8_t driver_idle;
- uint8_t pad[1];
+ uint8_t reserved[59];
};
/**
@@ -2335,6 +2335,11 @@ enum phy_link_rate {
* UHBR10 - 20.0 Gbps/Lane
*/
PHY_RATE_2000 = 11,
+
+ PHY_RATE_675 = 12,
+ /**
+ * Rate 12 - 6.75 Gbps/Lane
+ */
};
/**
@@ -3062,6 +3067,11 @@ enum dmub_cmd_replay_type {
* Set pseudo vtotal
*/
DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL = 7,
+ /**
+ * Set adaptive sync sdp enabled
+ */
+ DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP = 8,
+
};
/**
@@ -3263,6 +3273,20 @@ struct dmub_cmd_replay_set_pseudo_vtotal {
*/
uint8_t pad;
};
+struct dmub_cmd_replay_disabled_adaptive_sync_sdp_data {
+ /**
+ * Panel Instance.
+ * Panel isntance to identify which replay_state to use
+ * Currently the support is only for 0 or 1
+ */
+ uint8_t panel_inst;
+ /**
+ * enabled: set adaptive sync sdp enabled
+ */
+ uint8_t force_disabled;
+
+ uint8_t pad[2];
+};
/**
* Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command.
@@ -3366,6 +3390,20 @@ struct dmub_rb_cmd_replay_set_pseudo_vtotal {
struct dmub_cmd_replay_set_pseudo_vtotal data;
};
+/**
+ * Definition of a DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP command.
+ */
+struct dmub_rb_cmd_replay_disabled_adaptive_sync_sdp {
+ /**
+ * Command header.
+ */
+ struct dmub_cmd_header header;
+ /**
+ * Definition of DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP command.
+ */
+ struct dmub_cmd_replay_disabled_adaptive_sync_sdp_data data;
+};
+
/**
* Data passed from driver to FW in DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER command.
*/
@@ -3421,6 +3459,11 @@ union dmub_replay_cmd_set {
* Definition of DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command data.
*/
struct dmub_cmd_replay_set_pseudo_vtotal pseudo_vtotal_data;
+ /**
+ * Definition of DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP command data.
+ */
+ struct dmub_cmd_replay_disabled_adaptive_sync_sdp_data disabled_adaptive_sync_sdp_data;
+
};
/**
@@ -4096,6 +4139,10 @@ enum dmub_cmd_panel_cntl_type {
* Queries backlight info for the embedded panel.
*/
DMUB_CMD__PANEL_CNTL_QUERY_BACKLIGHT_INFO = 1,
+ /**
+ * Sets the PWM Freq as per user's requirement.
+ */
+ DMUB_CMD__PANEL_DEBUG_PWM_FREQ = 2,
};
/**
@@ -4667,6 +4714,10 @@ union dmub_rb_cmd {
* Definition of a DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command.
*/
struct dmub_rb_cmd_replay_set_pseudo_vtotal replay_set_pseudo_vtotal;
+ /**
+ * Definition of a DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP command.
+ */
+ struct dmub_rb_cmd_replay_disabled_adaptive_sync_sdp replay_disabled_adaptive_sync_sdp;
/**
* Definition of a DMUB_CMD__PSP_ASSR_ENABLE command.
*/
--
2.43.0
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 11/25] drm/amd/display: Use dce_version instead of chip_id
2024-04-10 21:25 [PATCH 00/25] DC Patches April 10, 2024 Rodrigo Siqueira
` (9 preceding siblings ...)
2024-04-10 21:25 ` [PATCH 10/25] drm/amd/display: Expand dmub_cmd operations Rodrigo Siqueira
@ 2024-04-10 21:26 ` Rodrigo Siqueira
2024-04-10 21:26 ` [PATCH 12/25] drm/amd/display: Adjust headers Rodrigo Siqueira
` (14 subsequent siblings)
25 siblings, 0 replies; 28+ messages in thread
From: Rodrigo Siqueira @ 2024-04-10 21:26 UTC (permalink / raw)
To: amd-gfx
Cc: Harry.Wentland, Sunpeng.Li, Rodrigo.Siqueira, Aurabindo.Pillai,
roman.li, wayne.lin, agustin.gutierrez, chiahsuan.chung,
hersenxs.wu, jerry.zuo
The chip ID DEVICE_ID_NV_13FE is not meaningful and represents a legacy
way of dealing with chip ID. This commit uses dc_version instead of
chip_id and also DCN_VERSION_2_01 instead of DEVICE_ID_NV_13FE.
Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
---
drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c
index c1a5908b97c8..a2b4ff2cff16 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c
@@ -272,7 +272,7 @@ struct clk_mgr *dc_clk_mgr_create(struct dc_context *ctx, struct pp_smu_funcs *p
dcn3_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);
return &clk_mgr->base;
}
- if (asic_id.chip_id == DEVICE_ID_NV_13FE) {
+ if (ctx->dce_version == DCN_VERSION_2_01) {
dcn201_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);
return &clk_mgr->base;
}
--
2.43.0
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 12/25] drm/amd/display: Adjust headers
2024-04-10 21:25 [PATCH 00/25] DC Patches April 10, 2024 Rodrigo Siqueira
` (10 preceding siblings ...)
2024-04-10 21:26 ` [PATCH 11/25] drm/amd/display: Use dce_version instead of chip_id Rodrigo Siqueira
@ 2024-04-10 21:26 ` Rodrigo Siqueira
2024-04-10 21:26 ` [PATCH 13/25] drm/amd/display: Improve the log precision Rodrigo Siqueira
` (13 subsequent siblings)
25 siblings, 0 replies; 28+ messages in thread
From: Rodrigo Siqueira @ 2024-04-10 21:26 UTC (permalink / raw)
To: amd-gfx
Cc: Harry.Wentland, Sunpeng.Li, Rodrigo.Siqueira, Aurabindo.Pillai,
roman.li, wayne.lin, agustin.gutierrez, chiahsuan.chung,
hersenxs.wu, jerry.zuo
Update headers by removing two unecessary headers and include a new one.
Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
---
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c | 1 +
drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c | 3 ---
.../gpu/drm/amd/display/dc/dcn30/dcn30_dio_stream_encoder.c | 1 -
3 files changed, 1 insertion(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
index bec252e1dd27..358a83b1114b 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
@@ -29,6 +29,7 @@
#include "dcn20/dcn20_clk_mgr.h"
#include "dce100/dce_clk_mgr.h"
#include "dcn31/dcn31_clk_mgr.h"
+#include "dcn32/dcn32_clk_mgr.h"
#include "reg_helper.h"
#include "core_types.h"
#include "dm_helpers.h"
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c b/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c
index a2f48d46d199..744c335718a7 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c
@@ -22,9 +22,6 @@
* Authors: AMD
*
*/
-
-#include <linux/delay.h>
-
#include "resource.h"
#include "dce_i2c.h"
#include "dce_i2c_hw.h"
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dio_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dio_stream_encoder.c
index 8ed7125d230d..425b830b88d2 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dio_stream_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dio_stream_encoder.c
@@ -29,7 +29,6 @@
#include "reg_helper.h"
#include "hw_shared.h"
#include "dc.h"
-#include "core_types.h"
#define DC_LOGGER \
enc1->base.ctx->logger
--
2.43.0
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 13/25] drm/amd/display: Improve the log precision
2024-04-10 21:25 [PATCH 00/25] DC Patches April 10, 2024 Rodrigo Siqueira
` (11 preceding siblings ...)
2024-04-10 21:26 ` [PATCH 12/25] drm/amd/display: Adjust headers Rodrigo Siqueira
@ 2024-04-10 21:26 ` Rodrigo Siqueira
2024-04-10 21:26 ` [PATCH 14/25] drm/amd/display: Fix PSR command version passed Rodrigo Siqueira
` (12 subsequent siblings)
25 siblings, 0 replies; 28+ messages in thread
From: Rodrigo Siqueira @ 2024-04-10 21:26 UTC (permalink / raw)
To: amd-gfx
Cc: Harry.Wentland, Sunpeng.Li, Rodrigo.Siqueira, Aurabindo.Pillai,
roman.li, wayne.lin, agustin.gutierrez, chiahsuan.chung,
hersenxs.wu, jerry.zuo, Bitnun, Ethan, Ethan Bitnun
From: "Bitnun, Ethan" <Ethan.Bitnun@amd.com>
The previous assumption that there will be an optimize_bandwidth call
following every prepare_bandwidth call was incorrect and caused small
inaccuracies in logging, as some info was only updated in later prepare
calls.
Signed-off-by: Ethan Bitnun <etbitnun@amd.com>
Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
---
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
index 358a83b1114b..7eecb3403f74 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
@@ -830,7 +830,7 @@ static void dcn32_update_clocks(struct clk_mgr *clk_mgr_base,
dmcu->funcs->set_psr_wait_loop(dmcu,
clk_mgr_base->clks.dispclk_khz / 1000 / 7);
- if (dc->config.enable_auto_dpm_test_logs && safe_to_lower) {
+ if (dc->config.enable_auto_dpm_test_logs) {
dcn32_auto_dpm_test_log(new_clocks, clk_mgr, context);
}
}
--
2.43.0
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 14/25] drm/amd/display: Fix PSR command version passed
2024-04-10 21:25 [PATCH 00/25] DC Patches April 10, 2024 Rodrigo Siqueira
` (12 preceding siblings ...)
2024-04-10 21:26 ` [PATCH 13/25] drm/amd/display: Improve the log precision Rodrigo Siqueira
@ 2024-04-10 21:26 ` Rodrigo Siqueira
2024-04-10 21:26 ` [PATCH 15/25] drm/amd/display: Group scl_data together in resource_build_scaling_params Rodrigo Siqueira
` (11 subsequent siblings)
25 siblings, 0 replies; 28+ messages in thread
From: Rodrigo Siqueira @ 2024-04-10 21:26 UTC (permalink / raw)
To: amd-gfx
Cc: Harry.Wentland, Sunpeng.Li, Rodrigo.Siqueira, Aurabindo.Pillai,
roman.li, wayne.lin, agustin.gutierrez, chiahsuan.chung,
hersenxs.wu, jerry.zuo, Mikita Lipski
From: Mikita Lipski <mikita.lipski@amd.com>
[why]
Driver was passing a wrong command version which to DMCUB which caused
the DMCUB to treat it as 0, so it wouldn't support dual eDP and would
override the panel index to 0 instead of choosing between 0/1.
[how]
Use DMUB_CMD_PSR_CONTROL_VERSION_1 instead of PSR_VERSION_1.
Signed-off-by: Mikita Lipski <mikita.lipski@amd.com>
Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 01c75b66e8f1..8eefba757da4 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -3446,6 +3446,7 @@ void dc_dmub_update_dirty_rect(struct dc *dc,
if (srf_updates[i].surface->flip_immediate)
continue;
+ update_dirty_rect->cmd_version = DMUB_CMD_PSR_CONTROL_VERSION_1;
update_dirty_rect->dirty_rect_count = flip_addr->dirty_rect_count;
memcpy(update_dirty_rect->src_dirty_rects, flip_addr->dirty_rects,
sizeof(flip_addr->dirty_rects));
--
2.43.0
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 15/25] drm/amd/display: Group scl_data together in resource_build_scaling_params
2024-04-10 21:25 [PATCH 00/25] DC Patches April 10, 2024 Rodrigo Siqueira
` (13 preceding siblings ...)
2024-04-10 21:26 ` [PATCH 14/25] drm/amd/display: Fix PSR command version passed Rodrigo Siqueira
@ 2024-04-10 21:26 ` Rodrigo Siqueira
2024-04-10 21:26 ` [PATCH 16/25] drm/amd/display: Replace int with unsigned int Rodrigo Siqueira
` (10 subsequent siblings)
25 siblings, 0 replies; 28+ messages in thread
From: Rodrigo Siqueira @ 2024-04-10 21:26 UTC (permalink / raw)
To: amd-gfx
Cc: Harry.Wentland, Sunpeng.Li, Rodrigo.Siqueira, Aurabindo.Pillai,
roman.li, wayne.lin, agustin.gutierrez, chiahsuan.chung,
hersenxs.wu, jerry.zuo
Move the scl_data.format to be close to other similar parts.
Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
---
drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index 2633e481234f..876b0e5eda95 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -1500,9 +1500,6 @@ bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx)
return false;
}
- pipe_ctx->plane_res.scl_data.format = convert_pixel_format_to_dalsurface(
- pipe_ctx->plane_state->format);
-
/* Timing borders are part of vactive that we are also supposed to skip in addition
* to any stream dst offset. Since dm logic assumes dst is in addressable
* space we need to add the left and top borders to dst offsets temporarily.
@@ -1514,6 +1511,8 @@ bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx)
/* Calculate H and V active size */
pipe_ctx->plane_res.scl_data.h_active = odm_slice_rec.width;
pipe_ctx->plane_res.scl_data.v_active = odm_slice_rec.height;
+ pipe_ctx->plane_res.scl_data.format = convert_pixel_format_to_dalsurface(
+ pipe_ctx->plane_state->format);
/* depends on h_active */
calculate_recout(pipe_ctx);
--
2.43.0
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 16/25] drm/amd/display: Replace int with unsigned int
2024-04-10 21:25 [PATCH 00/25] DC Patches April 10, 2024 Rodrigo Siqueira
` (14 preceding siblings ...)
2024-04-10 21:26 ` [PATCH 15/25] drm/amd/display: Group scl_data together in resource_build_scaling_params Rodrigo Siqueira
@ 2024-04-10 21:26 ` Rodrigo Siqueira
2024-04-10 21:26 ` [PATCH 17/25] drm/amd/display: Update some comments to improve the code readability Rodrigo Siqueira
` (9 subsequent siblings)
25 siblings, 0 replies; 28+ messages in thread
From: Rodrigo Siqueira @ 2024-04-10 21:26 UTC (permalink / raw)
To: amd-gfx
Cc: Harry.Wentland, Sunpeng.Li, Rodrigo.Siqueira, Aurabindo.Pillai,
roman.li, wayne.lin, agustin.gutierrez, chiahsuan.chung,
hersenxs.wu, jerry.zuo
Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
---
drivers/gpu/drm/amd/display/dc/core/dc_stream.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
index ee6493a9a79c..5c7e4884cac2 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
@@ -495,7 +495,7 @@ bool dc_stream_remove_writeback(struct dc *dc,
struct dc_stream_state *stream,
uint32_t dwb_pipe_inst)
{
- int i = 0, j = 0;
+ unsigned int i, j;
if (stream == NULL) {
dm_error("DC: dc_stream is NULL!\n");
return false;
--
2.43.0
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 17/25] drm/amd/display: Update some comments to improve the code readability
2024-04-10 21:25 [PATCH 00/25] DC Patches April 10, 2024 Rodrigo Siqueira
` (15 preceding siblings ...)
2024-04-10 21:26 ` [PATCH 16/25] drm/amd/display: Replace int with unsigned int Rodrigo Siqueira
@ 2024-04-10 21:26 ` Rodrigo Siqueira
2024-04-10 21:26 ` [PATCH 18/25] drm/amd/display: Remove unnecessary code Rodrigo Siqueira
` (8 subsequent siblings)
25 siblings, 0 replies; 28+ messages in thread
From: Rodrigo Siqueira @ 2024-04-10 21:26 UTC (permalink / raw)
To: amd-gfx
Cc: Harry.Wentland, Sunpeng.Li, Rodrigo.Siqueira, Aurabindo.Pillai,
roman.li, wayne.lin, agustin.gutierrez, chiahsuan.chung,
hersenxs.wu, jerry.zuo
This commit updates some comments to be more precise and adds another
small comment to some other parts to improve the code readability.
Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
---
drivers/gpu/drm/amd/display/dc/dc.h | 10 +++++-----
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h | 2 +-
drivers/gpu/drm/amd/display/dc/dcn201/dcn201_hubp.c | 5 +++++
3 files changed, 11 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index 188f2d401124..4e36a4f9a4a8 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -309,12 +309,12 @@ struct dc_dcc_setting {
unsigned int max_compressed_blk_size;
unsigned int max_uncompressed_blk_size;
bool independent_64b_blks;
- //These bitfields to be used starting with DCN
+ //These bitfields to be used starting with DCN 3.0
struct {
- uint32_t dcc_256_64_64 : 1;//available in ASICs before DCN (the worst compression case)
- uint32_t dcc_128_128_uncontrained : 1; //available in ASICs before DCN
- uint32_t dcc_256_128_128 : 1; //available starting with DCN
- uint32_t dcc_256_256_unconstrained : 1; //available in ASICs before DCN (the best compression case)
+ uint32_t dcc_256_64_64 : 1;//available in ASICs before DCN 3.0 (the worst compression case)
+ uint32_t dcc_128_128_uncontrained : 1; //available in ASICs before DCN 3.0
+ uint32_t dcc_256_128_128 : 1; //available starting with DCN 3.0
+ uint32_t dcc_256_256_unconstrained : 1; //available in ASICs before DCN 3.0 (the best compression case)
} dcc_controls;
};
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h
index efa2adf4f83d..8da3084d933f 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h
@@ -147,7 +147,7 @@
uint32_t DCN_CUR1_TTU_CNTL1;\
uint32_t VMID_SETTINGS_0
-
+/*shared with dcn3.x*/
#define DCN21_HUBP_REG_COMMON_VARIABLE_LIST \
DCN2_HUBP_REG_COMMON_VARIABLE_LIST; \
uint32_t FLIP_PARAMETERS_3;\
diff --git a/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_hubp.c b/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_hubp.c
index 35dd4bac242a..cd2bfcc51276 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_hubp.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_hubp.c
@@ -77,6 +77,7 @@ static void hubp201_program_requestor(struct hubp *hubp,
MRQ_EXPANSION_MODE, rq_regs->mrq_expansion_mode,
CRQ_EXPANSION_MODE, rq_regs->crq_expansion_mode);
+ /* no need to program PTE */
REG_SET_5(DCHUBP_REQ_SIZE_CONFIG, 0,
CHUNK_SIZE, rq_regs->rq_regs_l.chunk_size,
MIN_CHUNK_SIZE, rq_regs->rq_regs_l.min_chunk_size,
@@ -99,6 +100,10 @@ static void hubp201_setup(
struct _vcs_dpi_display_rq_regs_st *rq_regs,
struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest)
{
+ /*
+ * otg is locked when this func is called. Register are double buffered.
+ * disable the requestors is not needed
+ */
hubp2_vready_at_or_After_vsync(hubp, pipe_dest);
hubp201_program_requestor(hubp, rq_regs);
hubp201_program_deadline(hubp, dlg_attr, ttu_attr);
--
2.43.0
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 18/25] drm/amd/display: Remove unnecessary code
2024-04-10 21:25 [PATCH 00/25] DC Patches April 10, 2024 Rodrigo Siqueira
` (16 preceding siblings ...)
2024-04-10 21:26 ` [PATCH 17/25] drm/amd/display: Update some comments to improve the code readability Rodrigo Siqueira
@ 2024-04-10 21:26 ` Rodrigo Siqueira
2024-04-10 21:26 ` [PATCH 19/25] drm/amd/display: Update FMT settings for 4:2:0 Rodrigo Siqueira
` (7 subsequent siblings)
25 siblings, 0 replies; 28+ messages in thread
From: Rodrigo Siqueira @ 2024-04-10 21:26 UTC (permalink / raw)
To: amd-gfx
Cc: Harry.Wentland, Sunpeng.Li, Rodrigo.Siqueira, Aurabindo.Pillai,
roman.li, wayne.lin, agustin.gutierrez, chiahsuan.chung,
hersenxs.wu, jerry.zuo
This commit groups many parts of the code that are redundant or not used
and drops all of them.
Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
---
drivers/gpu/drm/amd/display/dc/dc.h | 1 -
.../gpu/drm/amd/display/dc/dce/dce_i2c_hw.c | 3 ---
.../amd/display/dc/dcn10/dcn10_link_encoder.h | 6 ------
.../gpu/drm/amd/display/dc/dcn30/dcn30_dccg.h | 18 ------------------
.../gpu/drm/amd/display/dc/dcn30/dcn30_dwb.c | 2 --
5 files changed, 30 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index 4e36a4f9a4a8..6a88423b7188 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -1006,7 +1006,6 @@ struct dc_debug_options {
unsigned int force_cositing;
};
-struct gpu_info_soc_bounding_box_v1_0;
/* Generic structure that can be used to query properties of DC. More fields
* can be added as required.
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c b/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c
index 744c335718a7..ee601a6897a1 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c
@@ -312,9 +312,6 @@ static bool setup_engine(
/* we have checked I2c not used by DMCU, set SW use I2C REQ to 1 to indicate SW using it*/
REG_UPDATE(DC_I2C_ARBITRATION, DC_I2C_SW_USE_I2C_REG_REQ, 1);
- /* we have checked I2c not used by DMCU, set SW use I2C REQ to 1 to indicate SW using it*/
- REG_UPDATE(DC_I2C_ARBITRATION, DC_I2C_SW_USE_I2C_REG_REQ, 1);
-
/*set SW requested I2c speed to default, if API calls in it will be override later*/
set_speed(dce_i2c_hw, dce_i2c_hw->ctx->dc->caps.i2c_speed_in_khz);
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h
index d980e6bd6c66..b7a89c39f445 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h
@@ -167,7 +167,6 @@ struct dcn10_link_enc_registers {
uint32_t DIO_LINKD_CNTL;
uint32_t DIO_LINKE_CNTL;
uint32_t DIO_LINKF_CNTL;
- uint32_t DIG_FIFO_CTRL0;
uint32_t DIO_CLK_CNTL;
uint32_t DIG_BE_CLK_CNTL;
};
@@ -475,9 +474,6 @@ struct dcn10_link_enc_registers {
type HPO_DP_ENC_SEL;\
type HPO_HDMI_ENC_SEL
-#define DCN32_LINK_ENCODER_REG_FIELD_LIST(type) \
- type DIG_FIFO_OUTPUT_PIXEL_MODE
-
#define DCN35_LINK_ENCODER_REG_FIELD_LIST(type) \
type DIG_BE_ENABLE;\
type DIG_RB_SWITCH_EN;\
@@ -512,7 +508,6 @@ struct dcn10_link_enc_shift {
DCN20_LINK_ENCODER_REG_FIELD_LIST(uint8_t);
DCN30_LINK_ENCODER_REG_FIELD_LIST(uint8_t);
DCN31_LINK_ENCODER_REG_FIELD_LIST(uint8_t);
- DCN32_LINK_ENCODER_REG_FIELD_LIST(uint8_t);
DCN35_LINK_ENCODER_REG_FIELD_LIST(uint8_t);
};
@@ -521,7 +516,6 @@ struct dcn10_link_enc_mask {
DCN20_LINK_ENCODER_REG_FIELD_LIST(uint32_t);
DCN30_LINK_ENCODER_REG_FIELD_LIST(uint32_t);
DCN31_LINK_ENCODER_REG_FIELD_LIST(uint32_t);
- DCN32_LINK_ENCODER_REG_FIELD_LIST(uint32_t);
DCN35_LINK_ENCODER_REG_FIELD_LIST(uint32_t);
};
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dccg.h b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dccg.h
index 35a613bb08bf..08a57ea4591c 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dccg.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dccg.h
@@ -29,13 +29,6 @@
#include "dcn20/dcn20_dccg.h"
-#define DCCG_REG_LIST_DCN3AG() \
- DCCG_COMMON_REG_LIST_DCN_BASE(),\
- SR(PHYASYMCLK_CLOCK_CNTL),\
- SR(PHYBSYMCLK_CLOCK_CNTL),\
- SR(PHYCSYMCLK_CLOCK_CNTL)
-
-
#define DCCG_REG_LIST_DCN30() \
DCCG_REG_LIST_DCN2(),\
DCCG_SRII(PIXEL_RATE_CNTL, OTG, 2),\
@@ -46,17 +39,6 @@
SR(PHYBSYMCLK_CLOCK_CNTL),\
SR(PHYCSYMCLK_CLOCK_CNTL)
-#define DCCG_MASK_SH_LIST_DCN3AG(mask_sh) \
- DCCG_MASK_SH_LIST_DCN2_1(mask_sh),\
- DCCG_SF(HDMICHARCLK0_CLOCK_CNTL, HDMICHARCLK0_EN, mask_sh),\
- DCCG_SF(HDMICHARCLK0_CLOCK_CNTL, HDMICHARCLK0_SRC_SEL, mask_sh),\
- DCCG_SF(PHYASYMCLK_CLOCK_CNTL, PHYASYMCLK_FORCE_EN, mask_sh),\
- DCCG_SF(PHYASYMCLK_CLOCK_CNTL, PHYASYMCLK_FORCE_SRC_SEL, mask_sh),\
- DCCG_SF(PHYBSYMCLK_CLOCK_CNTL, PHYBSYMCLK_FORCE_EN, mask_sh),\
- DCCG_SF(PHYBSYMCLK_CLOCK_CNTL, PHYBSYMCLK_FORCE_SRC_SEL, mask_sh),\
- DCCG_SF(PHYCSYMCLK_CLOCK_CNTL, PHYCSYMCLK_FORCE_EN, mask_sh),\
- DCCG_SF(PHYCSYMCLK_CLOCK_CNTL, PHYCSYMCLK_FORCE_SRC_SEL, mask_sh)
-
#define DCCG_MASK_SH_LIST_DCN3(mask_sh) \
DCCG_MASK_SH_LIST_DCN2(mask_sh),\
DCCG_SF(PHYASYMCLK_CLOCK_CNTL, PHYASYMCLK_FORCE_EN, mask_sh),\
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dwb.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dwb.c
index 1b9d9495f76d..fae98cf52020 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dwb.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dwb.c
@@ -251,9 +251,7 @@ static const struct dwbc_funcs dcn30_dwbc_funcs = {
.set_fc_enable = dwb3_set_fc_enable,
.set_stereo = dwb3_set_stereo,
.set_new_content = dwb3_set_new_content,
- .dwb_program_output_csc = NULL,
.dwb_ogam_set_input_transfer_func = dwb3_ogam_set_input_transfer_func, //TODO: rename
- .dwb_set_scaler = NULL,
};
void dcn30_dwbc_construct(struct dcn30_dwbc *dwbc30,
--
2.43.0
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 19/25] drm/amd/display: Update FMT settings for 4:2:0
2024-04-10 21:25 [PATCH 00/25] DC Patches April 10, 2024 Rodrigo Siqueira
` (17 preceding siblings ...)
2024-04-10 21:26 ` [PATCH 18/25] drm/amd/display: Remove unnecessary code Rodrigo Siqueira
@ 2024-04-10 21:26 ` Rodrigo Siqueira
2024-04-10 21:26 ` [PATCH 20/25] drm/amd/display: Rework dcn10_stream_encoder header Rodrigo Siqueira
` (6 subsequent siblings)
25 siblings, 0 replies; 28+ messages in thread
From: Rodrigo Siqueira @ 2024-04-10 21:26 UTC (permalink / raw)
To: amd-gfx
Cc: Harry.Wentland, Sunpeng.Li, Rodrigo.Siqueira, Aurabindo.Pillai,
roman.li, wayne.lin, agustin.gutierrez, chiahsuan.chung,
hersenxs.wu, jerry.zuo, Eric Bernstein
From: Eric Bernstein <eric.bernstein@amd.com>
[Why] Update FMT_CONTROL settings based on HW spec
[How] Update FMT settings for 4:2:0
Signed-off-by: Eric Bernstein <eric.bernstein@amd.com>
Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
---
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c | 9 ++++++++-
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h | 2 ++
2 files changed, 10 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c
index 5838a11efd00..71e9288d60ed 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c
@@ -168,6 +168,10 @@ static void opp1_set_pixel_encoding(
case PIXEL_ENCODING_RGB:
case PIXEL_ENCODING_YCBCR444:
+ REG_UPDATE_3(FMT_CONTROL,
+ FMT_PIXEL_ENCODING, 0,
+ FMT_SUBSAMPLING_MODE, 0,
+ FMT_CBCR_BIT_REDUCTION_BYPASS, 0);
REG_UPDATE(FMT_CONTROL, FMT_PIXEL_ENCODING, 0);
break;
case PIXEL_ENCODING_YCBCR422:
@@ -177,7 +181,10 @@ static void opp1_set_pixel_encoding(
FMT_CBCR_BIT_REDUCTION_BYPASS, 0);
break;
case PIXEL_ENCODING_YCBCR420:
- REG_UPDATE(FMT_CONTROL, FMT_PIXEL_ENCODING, 2);
+ REG_UPDATE_3(FMT_CONTROL,
+ FMT_PIXEL_ENCODING, 2,
+ FMT_SUBSAMPLING_MODE, 2,
+ FMT_CBCR_BIT_REDUCTION_BYPASS, 1);
break;
default:
break;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h
index 2c0ecfa5a643..c87de68a509e 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h
@@ -79,6 +79,8 @@
OPP_SF(FMT0_FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX, mask_sh), \
OPP_SF(FMT0_FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP, mask_sh), \
OPP_SF(FMT0_FMT_CONTROL, FMT_PIXEL_ENCODING, mask_sh), \
+ OPP_SF(FMT0_FMT_CONTROL, FMT_SUBSAMPLING_MODE, mask_sh), \
+ OPP_SF(FMT0_FMT_CONTROL, FMT_CBCR_BIT_REDUCTION_BYPASS, mask_sh), \
OPP_SF(FMT0_FMT_CONTROL, FMT_STEREOSYNC_OVERRIDE, mask_sh), \
OPP_SF(FMT0_FMT_DITHER_RAND_R_SEED, FMT_RAND_R_SEED, mask_sh), \
OPP_SF(FMT0_FMT_DITHER_RAND_G_SEED, FMT_RAND_G_SEED, mask_sh), \
--
2.43.0
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 20/25] drm/amd/display: Rework dcn10_stream_encoder header
2024-04-10 21:25 [PATCH 00/25] DC Patches April 10, 2024 Rodrigo Siqueira
` (18 preceding siblings ...)
2024-04-10 21:26 ` [PATCH 19/25] drm/amd/display: Update FMT settings for 4:2:0 Rodrigo Siqueira
@ 2024-04-10 21:26 ` Rodrigo Siqueira
2024-04-10 21:26 ` [PATCH 21/25] drm/amd/display: Move REG sequence from program ogam to idle before connect Rodrigo Siqueira
` (5 subsequent siblings)
25 siblings, 0 replies; 28+ messages in thread
From: Rodrigo Siqueira @ 2024-04-10 21:26 UTC (permalink / raw)
To: amd-gfx
Cc: Harry.Wentland, Sunpeng.Li, Rodrigo.Siqueira, Aurabindo.Pillai,
roman.li, wayne.lin, agustin.gutierrez, chiahsuan.chung,
hersenxs.wu, jerry.zuo
This commit remove some unused code and also rename one of the define.
Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
---
.../drm/amd/display/dc/dcn10/dcn10_stream_encoder.h | 10 +++-------
1 file changed, 3 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
index c429590f1298..1b96972b9d0f 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
@@ -127,7 +127,6 @@ struct dcn10_stream_enc_registers {
uint32_t AFMT_60958_1;
uint32_t AFMT_60958_2;
uint32_t DIG_FE_CNTL;
- uint32_t DIG_FE_CNTL2;
uint32_t DIG_FIFO_STATUS;
uint32_t DP_MSE_RATE_CNTL;
uint32_t DP_MSE_RATE_UPDATE;
@@ -570,7 +569,7 @@ struct dcn10_stream_enc_registers {
type DP_SEC_GSP11_ENABLE;\
type DP_SEC_GSP11_LINE_NUM
-#define SE_REG_FIELD_LIST_DCN3_2(type) \
+#define SE_REG_FIELD_LIST_DCN3_1_COMMON(type) \
type DIG_FIFO_OUTPUT_PIXEL_MODE;\
type DP_PIXEL_PER_CYCLE_PROCESSING_MODE;\
type DIG_SYMCLK_FE_ON;\
@@ -599,7 +598,7 @@ struct dcn10_stream_encoder_shift {
uint8_t HDMI_ACP_SEND;
SE_REG_FIELD_LIST_DCN2_0(uint8_t);
SE_REG_FIELD_LIST_DCN3_0(uint8_t);
- SE_REG_FIELD_LIST_DCN3_2(uint8_t);
+ SE_REG_FIELD_LIST_DCN3_1_COMMON(uint8_t);
SE_REG_FIELD_LIST_DCN3_5_COMMON(uint8_t);
};
@@ -608,7 +607,7 @@ struct dcn10_stream_encoder_mask {
uint32_t HDMI_ACP_SEND;
SE_REG_FIELD_LIST_DCN2_0(uint32_t);
SE_REG_FIELD_LIST_DCN3_0(uint32_t);
- SE_REG_FIELD_LIST_DCN3_2(uint32_t);
+ SE_REG_FIELD_LIST_DCN3_1_COMMON(uint32_t);
SE_REG_FIELD_LIST_DCN3_5_COMMON(uint32_t);
};
@@ -667,9 +666,6 @@ void enc1_stream_encoder_send_immediate_sdp_message(
void enc1_stream_encoder_stop_dp_info_packets(
struct stream_encoder *enc);
-void enc1_stream_encoder_reset_fifo(
- struct stream_encoder *enc);
-
void enc1_stream_encoder_dp_blank(
struct dc_link *link,
struct stream_encoder *enc);
--
2.43.0
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 21/25] drm/amd/display: Move REG sequence from program ogam to idle before connect
2024-04-10 21:25 [PATCH 00/25] DC Patches April 10, 2024 Rodrigo Siqueira
` (19 preceding siblings ...)
2024-04-10 21:26 ` [PATCH 20/25] drm/amd/display: Rework dcn10_stream_encoder header Rodrigo Siqueira
@ 2024-04-10 21:26 ` Rodrigo Siqueira
2024-04-10 21:26 ` [PATCH 22/25] drm/amd/display: Update DCN201 link encoder registers Rodrigo Siqueira
` (4 subsequent siblings)
25 siblings, 0 replies; 28+ messages in thread
From: Rodrigo Siqueira @ 2024-04-10 21:26 UTC (permalink / raw)
To: amd-gfx
Cc: Harry.Wentland, Sunpeng.Li, Rodrigo.Siqueira, Aurabindo.Pillai,
roman.li, wayne.lin, agustin.gutierrez, chiahsuan.chung,
hersenxs.wu, jerry.zuo
Fill ring buffer before offload.
Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
---
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c | 10 ++++------
1 file changed, 4 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c
index 16b5ff208d14..ea73473b970a 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c
@@ -395,9 +395,12 @@ static void mpc20_program_ogam_pwl(
MPCC_OGAM_LUT_DATA, rgb[i].delta_green_reg);
REG_SET(MPCC_OGAM_LUT_DATA[mpcc_id], 0,
MPCC_OGAM_LUT_DATA, rgb[i].delta_blue_reg);
-
}
+ REG_SEQ_SUBMIT();
+ PERF_TRACE();
+ REG_SEQ_WAIT_DONE();
+ PERF_TRACE();
}
static void apply_DEDCN20_305_wa(struct mpc *mpc, int mpcc_id,
@@ -501,11 +504,6 @@ void mpc2_assert_mpcc_idle_before_connect(struct mpc *mpc, int mpcc_id)
ASSERT(!mpc_disabled);
ASSERT(!mpc_idle);
}
-
- REG_SEQ_SUBMIT();
- PERF_TRACE();
- REG_SEQ_WAIT_DONE();
- PERF_TRACE();
}
static void mpc2_init_mpcc(struct mpcc *mpcc, int mpcc_inst)
--
2.43.0
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 22/25] drm/amd/display: Update DCN201 link encoder registers
2024-04-10 21:25 [PATCH 00/25] DC Patches April 10, 2024 Rodrigo Siqueira
` (20 preceding siblings ...)
2024-04-10 21:26 ` [PATCH 21/25] drm/amd/display: Move REG sequence from program ogam to idle before connect Rodrigo Siqueira
@ 2024-04-10 21:26 ` Rodrigo Siqueira
2024-04-10 21:26 ` [PATCH 23/25] drm/amd/display: Add missing callback for init_watermarks in DCN 301 Rodrigo Siqueira
` (3 subsequent siblings)
25 siblings, 0 replies; 28+ messages in thread
From: Rodrigo Siqueira @ 2024-04-10 21:26 UTC (permalink / raw)
To: amd-gfx
Cc: Harry.Wentland, Sunpeng.Li, Rodrigo.Siqueira, Aurabindo.Pillai,
roman.li, wayne.lin, agustin.gutierrez, chiahsuan.chung,
hersenxs.wu, jerry.zuo
Add some missing registers expansion in the dcn201_link_encoder file.
Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
---
.../amd/display/dc/dcn201/dcn201_link_encoder.h | 14 +++++++++++++-
1 file changed, 13 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_link_encoder.h b/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_link_encoder.h
index 8b95ef251332..be25e8dc0636 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_link_encoder.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_link_encoder.h
@@ -30,6 +30,10 @@
#define DPCS_DCN201_MASK_SH_LIST(mask_sh)\
DPCS_MASK_SH_LIST(mask_sh),\
+ LE_SF(DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2, VCO_LD_VAL_OVRD, mask_sh),\
+ LE_SF(DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2, VCO_LD_VAL_OVRD_EN, mask_sh),\
+ LE_SF(DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3, REF_LD_VAL_OVRD, mask_sh),\
+ LE_SF(DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3, REF_LD_VAL_OVRD_EN, mask_sh),\
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL2, RDPCS_PHY_DPALT_DISABLE_ACK, mask_sh),\
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL2, RDPCS_PHY_DPALT_DISABLE, mask_sh),\
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL2, RDPCS_PHY_DPALT_DP4, mask_sh),\
@@ -44,7 +48,15 @@
LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL11, RDPCS_PHY_DP_REF_CLK_EN, mask_sh)
#define DPCS_DCN201_REG_LIST(id) \
- DPCS_DCN2_CMN_REG_LIST(id)
+ DPCS_DCN2_CMN_REG_LIST(id), \
+ SRI_IX(RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2, DPCSSYS_CR, id), \
+ SRI_IX(RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3, DPCSSYS_CR, id), \
+ SRI_IX(RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2, DPCSSYS_CR, id), \
+ SRI_IX(RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3, DPCSSYS_CR, id), \
+ SRI_IX(RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2, DPCSSYS_CR, id), \
+ SRI_IX(RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3, DPCSSYS_CR, id), \
+ SRI_IX(RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2, DPCSSYS_CR, id), \
+ SRI_IX(RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3, DPCSSYS_CR, id)
void dcn201_link_encoder_construct(
struct dcn20_link_encoder *enc20,
--
2.43.0
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 23/25] drm/amd/display: Add missing callback for init_watermarks in DCN 301
2024-04-10 21:25 [PATCH 00/25] DC Patches April 10, 2024 Rodrigo Siqueira
` (21 preceding siblings ...)
2024-04-10 21:26 ` [PATCH 22/25] drm/amd/display: Update DCN201 link encoder registers Rodrigo Siqueira
@ 2024-04-10 21:26 ` Rodrigo Siqueira
2024-04-10 21:26 ` [PATCH 24/25] drm/amd/display: Add missing replay field Rodrigo Siqueira
` (2 subsequent siblings)
25 siblings, 0 replies; 28+ messages in thread
From: Rodrigo Siqueira @ 2024-04-10 21:26 UTC (permalink / raw)
To: amd-gfx
Cc: Harry.Wentland, Sunpeng.Li, Rodrigo.Siqueira, Aurabindo.Pillai,
roman.li, wayne.lin, agustin.gutierrez, chiahsuan.chung,
hersenxs.wu, jerry.zuo
Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
---
drivers/gpu/drm/amd/display/dc/dcn301/dcn301_hubbub.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_hubbub.c b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_hubbub.c
index a046664e2031..c1959672df50 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_hubbub.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_hubbub.c
@@ -63,6 +63,7 @@ static const struct hubbub_funcs hubbub301_funcs = {
.verify_allow_pstate_change_high = hubbub1_verify_allow_pstate_change_high,
.force_wm_propagate_to_pipes = hubbub3_force_wm_propagate_to_pipes,
.force_pstate_change_control = hubbub3_force_pstate_change_control,
+ .init_watermarks = hubbub3_init_watermarks,
.hubbub_read_state = hubbub2_read_state,
};
--
2.43.0
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 24/25] drm/amd/display: Add missing replay field
2024-04-10 21:25 [PATCH 00/25] DC Patches April 10, 2024 Rodrigo Siqueira
` (22 preceding siblings ...)
2024-04-10 21:26 ` [PATCH 23/25] drm/amd/display: Add missing callback for init_watermarks in DCN 301 Rodrigo Siqueira
@ 2024-04-10 21:26 ` Rodrigo Siqueira
2024-04-10 21:26 ` [PATCH 25/25] drm/amd/display: 3.2.281 Rodrigo Siqueira
2024-04-15 13:02 ` [PATCH 00/25] DC Patches April 10, 2024 Wheeler, Daniel
25 siblings, 0 replies; 28+ messages in thread
From: Rodrigo Siqueira @ 2024-04-10 21:26 UTC (permalink / raw)
To: amd-gfx
Cc: Harry.Wentland, Sunpeng.Li, Rodrigo.Siqueira, Aurabindo.Pillai,
roman.li, wayne.lin, agustin.gutierrez, chiahsuan.chung,
hersenxs.wu, jerry.zuo
Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
---
drivers/gpu/drm/amd/display/dc/dc_types.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dc_types.h b/drivers/gpu/drm/amd/display/dc/dc_types.h
index 614d7c27c759..0f66d00ef80f 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_types.h
@@ -1050,6 +1050,8 @@ union replay_error_status {
struct replay_config {
/* Replay feature is supported */
bool replay_supported;
+ /* Replay caps support DPCD & EDID caps*/
+ bool replay_cap_support;
/* Power opt flags that are supported */
unsigned int replay_power_opt_supported;
/* SMU optimization is supported */
--
2.43.0
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 25/25] drm/amd/display: 3.2.281
2024-04-10 21:25 [PATCH 00/25] DC Patches April 10, 2024 Rodrigo Siqueira
` (23 preceding siblings ...)
2024-04-10 21:26 ` [PATCH 24/25] drm/amd/display: Add missing replay field Rodrigo Siqueira
@ 2024-04-10 21:26 ` Rodrigo Siqueira
2024-04-15 13:02 ` [PATCH 00/25] DC Patches April 10, 2024 Wheeler, Daniel
25 siblings, 0 replies; 28+ messages in thread
From: Rodrigo Siqueira @ 2024-04-10 21:26 UTC (permalink / raw)
To: amd-gfx
Cc: Harry.Wentland, Sunpeng.Li, Rodrigo.Siqueira, Aurabindo.Pillai,
roman.li, wayne.lin, agustin.gutierrez, chiahsuan.chung,
hersenxs.wu, jerry.zuo, Aric Cyr, Rodrigo Siqueira
From: Aric Cyr <aric.cyr@amd.com>
This version brings along following fixes:
* Expand dmub_cmd operations.
* Update DVI configuration.
* Modify power sequence.
* Enable Z10 flag for IPS.
* Multiple code cleanups.
Acked-by: Rodrigo Siqueira <rodrigo.siqueira@amd.com>
Signed-off-by: Aric Cyr <aric.cyr@amd.com>
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index 6a88423b7188..3c33c3bcbe2c 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -53,7 +53,7 @@ struct aux_payload;
struct set_config_cmd_payload;
struct dmub_notification;
-#define DC_VER "3.2.279"
+#define DC_VER "3.2.281"
#define MAX_SURFACES 3
#define MAX_PLANES 6
--
2.43.0
^ permalink raw reply related [flat|nested] 28+ messages in thread
* RE: [PATCH 00/25] DC Patches April 10, 2024
2024-04-10 21:25 [PATCH 00/25] DC Patches April 10, 2024 Rodrigo Siqueira
` (24 preceding siblings ...)
2024-04-10 21:26 ` [PATCH 25/25] drm/amd/display: 3.2.281 Rodrigo Siqueira
@ 2024-04-15 13:02 ` Wheeler, Daniel
25 siblings, 0 replies; 28+ messages in thread
From: Wheeler, Daniel @ 2024-04-15 13:02 UTC (permalink / raw)
To: Siqueira, Rodrigo, amd-gfx
Cc: Wentland, Harry, Li, Sun peng (Leo),
Pillai, Aurabindo, Li, Roman, Lin, Wayne, Gutierrez, Agustin,
Chung, ChiaHsuan (Tom),
Wu, Hersen, Zuo, Jerry
[Public]
Hi all,
This week this patchset was tested on the following systems:
* Lenovo ThinkBook T13s Gen4 with AMD Ryzen 5 6600U
* MSI Gaming X Trio RX 6800
* Gigabyte Gaming OC RX 7900 XTX
These systems were tested on the following display/connection types:
* eDP, (1080p 60hz [5650U]) (1920x1200 60hz [6600U]) (2560x1600 120hz[6600U])
* VGA and DVI (1680x1050 60hz [DP to VGA/DVI, USB-C to VGA/DVI])
* DP/HDMI/USB-C (1440p 170hz, 4k 60hz, 4k 144hz, 4k 240hz [Includes USB-C to DP/HDMI adapters])
* Thunderbolt (LG Ultrafine 5k)
* MST (Startech MST14DP123DP [DP to 3x DP] and 2x 4k 60Hz displays)
* DSC (with Cable Matters 101075 [DP to 3x DP] with 3x 4k60 displays, and HP Hook G2 with 1 4k60 display)
* USB 4 (Kensington SD5700T and 1x 4k 60Hz display)
* PCON (Club3D CAC-1085 and 1x 4k 144Hz display [at 4k 120HZ, as that is the max the adapter supports])
The testing is a mix of automated and manual tests. Manual testing includes (but is not limited to):
* Changing display configurations and settings
* Benchmark testing
* Feature testing (Freesync, etc.)
Automated testing includes (but is not limited to):
* Script testing (scripts to automate some of the manual checks)
* IGT testing
The patchset consists of the amd-staging-drm-next branch (Head commit - 9ef923c9f876 drm/amd/display: 3.2.280) with new patches added on top of it.
Tested on Ubuntu 22.04.3, on Wayland and X11, using KDE Plasma and Gnome.
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Thank you,
Dan Wheeler
Sr. Technologist | AMD
SW Display
------------------------------------------------------------------------------------------------------------------
1 Commerce Valley Dr E, Thornhill, ON L3T 7X6
amd.com
-----Original Message-----
From: Siqueira, Rodrigo <Rodrigo.Siqueira@amd.com>
Sent: Wednesday, April 10, 2024 5:26 PM
To: amd-gfx@lists.freedesktop.org
Cc: Wentland, Harry <Harry.Wentland@amd.com>; Li, Sun peng (Leo) <Sunpeng.Li@amd.com>; Siqueira, Rodrigo <Rodrigo.Siqueira@amd.com>; Pillai, Aurabindo <Aurabindo.Pillai@amd.com>; Li, Roman <Roman.Li@amd.com>; Lin, Wayne <Wayne.Lin@amd.com>; Gutierrez, Agustin <Agustin.Gutierrez@amd.com>; Chung, ChiaHsuan (Tom) <ChiaHsuan.Chung@amd.com>; Wu, Hersen <hersenxs.wu@amd.com>; Zuo, Jerry <Jerry.Zuo@amd.com>; Wheeler, Daniel <Daniel.Wheeler@amd.com>
Subject: [PATCH 00/25] DC Patches April 10, 2024
This DC patchset brings improvements in multiple areas. In summary, we
have:
* Expand dmub_cmd operations.
* Update DVI configuration.
* Modify power sequence.
* Enable Z10 flag for IPS.
* Multiple code cleanups.
Cc: Daniel Wheeler <daniel.wheeler@amd.com>
Thanks
Siqueira
Anthony Koo (1):
drm/amd/display: Expand dmub_cmd operations
Aric Cyr (1):
drm/amd/display: 3.2.281
Bitnun, Ethan (1):
drm/amd/display: Improve the log precision
Chaitanya Dhere (1):
drm/amd/display: Fix incorrect pointer assignment
Charlene Liu (1):
drm/amd/display: limit the code change to ips enabled asic
Chris Park (1):
drm/amd/display: Add a function for checking tmds mode
Eric Bernstein (1):
drm/amd/display: Update FMT settings for 4:2:0
Mikita Lipski (1):
drm/amd/display: Fix PSR command version passed
Nicholas Kazlauskas (1):
drm/amd/display: Pass sequential ONO bit to DMCUB boot options
Rodrigo Siqueira (11):
drm/amd/display: Use dce_version instead of chip_id
drm/amd/display: Adjust headers
drm/amd/display: Group scl_data together in
resource_build_scaling_params
drm/amd/display: Replace int with unsigned int
drm/amd/display: Update some comments to improve the code readability
drm/amd/display: Remove unnecessary code
drm/amd/display: Rework dcn10_stream_encoder header
drm/amd/display: Move REG sequence from program ogam to idle before
connect
drm/amd/display: Update DCN201 link encoder registers
drm/amd/display: Add missing callback for init_watermarks in DCN 301
drm/amd/display: Add missing replay field
Samson Tam (1):
drm/amd/display: add support for chroma offset
Sung Joon Kim (4):
drm/amd/display: Modify power sequence
drm/amd/display: Modify resource allocation logic
drm/amd/display: Enable Z10 flag for IPS FSM
drm/amd/display: Rework power sequence and resource allocation logic
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 9 +
.../gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c | 2 +-
.../display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c | 3 +-
drivers/gpu/drm/amd/display/dc/core/dc.c | 8 +-
.../gpu/drm/amd/display/dc/core/dc_resource.c | 5 +-
.../gpu/drm/amd/display/dc/core/dc_state.c | 10 +-
.../gpu/drm/amd/display/dc/core/dc_stream.c | 2 +-
drivers/gpu/drm/amd/display/dc/dc.h | 16 +-
drivers/gpu/drm/amd/display/dc/dc_hw_types.h | 7 +
drivers/gpu/drm/amd/display/dc/dc_types.h | 2 +
.../gpu/drm/amd/display/dc/dce/dce_i2c_hw.c | 6 -
.../amd/display/dc/dcn10/dcn10_link_encoder.h | 6 -
.../gpu/drm/amd/display/dc/dcn10/dcn10_opp.c | 9 +-
.../gpu/drm/amd/display/dc/dcn10/dcn10_opp.h | 2 +
.../display/dc/dcn10/dcn10_stream_encoder.h | 10 +-
.../gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h | 2 +-
.../gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c | 10 +-
.../drm/amd/display/dc/dcn201/dcn201_hubp.c | 5 +
.../display/dc/dcn201/dcn201_link_encoder.h | 14 +-
.../gpu/drm/amd/display/dc/dcn30/dcn30_dccg.h | 18 --
.../dc/dcn30/dcn30_dio_stream_encoder.c | 1 -
.../gpu/drm/amd/display/dc/dcn30/dcn30_dwb.c | 2 -
.../drm/amd/display/dc/dcn301/dcn301_hubbub.c | 1 +
drivers/gpu/drm/amd/display/dc/hwss/Makefile | 2 +-
.../drm/amd/display/dc/hwss/dcn351/Makefile | 25 ++-
.../amd/display/dc/hwss/dcn351/dcn351_hwseq.c | 182 ++++++++++++++++++ .../amd/display/dc/hwss/dcn351/dcn351_hwseq.h | 41 ++++
.../amd/display/dc/hwss/dcn351/dcn351_init.c | 1 +
.../dc/resource/dcn32/dcn32_resource.c | 4 +-
.../dc/resource/dcn32/dcn32_resource.h | 6 +
.../dc/resource/dcn351/dcn351_resource.c | 5 +-
drivers/gpu/drm/amd/display/dmub/dmub_srv.h | 1 +
.../gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 53 ++++-
.../gpu/drm/amd/display/dmub/src/dmub_dcn35.c | 1 +
.../drm/amd/display/include/signal_types.h | 13 ++
35 files changed, 402 insertions(+), 82 deletions(-) create mode 100644 drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.c
create mode 100644 drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.h
--
2.43.0
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH 02/25] drm/amd/display: Add a function for checking tmds mode
2024-04-10 21:25 ` [PATCH 02/25] drm/amd/display: Add a function for checking tmds mode Rodrigo Siqueira
@ 2024-04-15 19:16 ` Melissa Wen
0 siblings, 0 replies; 28+ messages in thread
From: Melissa Wen @ 2024-04-15 19:16 UTC (permalink / raw)
To: Rodrigo Siqueira, amd-gfx
Cc: Harry.Wentland, Sunpeng.Li, Aurabindo.Pillai, roman.li,
wayne.lin, agustin.gutierrez, chiahsuan.chung, hersenxs.wu,
jerry.zuo, Chris Park, Dillon Varone
On 10/04/2024 18:25, Rodrigo Siqueira wrote:
> From: Chris Park <chris.park@amd.com>
>
> [Why]
> DVI is TMDS signal like HDMI but without audio. Current signal check
> does not correctly reflect DVI clock programming.
>
> [How]
> Define a new signal check for TMDS that includes DVI to HDMI TMDS
> programming.
>
> Reviewed-by: Dillon Varone <dillon.varone@amd.com>
> Acked-by: Rodrigo Siqueira <rodrigo.siqueira@amd.com>
> Signed-off-by: Chris Park <chris.park@amd.com>
> ---
> drivers/gpu/drm/amd/display/include/signal_types.h | 13 +++++++++++++
> 1 file changed, 13 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/display/include/signal_types.h b/drivers/gpu/drm/amd/display/include/signal_types.h
> index 1b14b17a79c7..a10d6b988aab 100644
> --- a/drivers/gpu/drm/amd/display/include/signal_types.h
> +++ b/drivers/gpu/drm/amd/display/include/signal_types.h
> @@ -118,6 +118,19 @@ static inline bool dc_is_dvi_signal(enum signal_type signal)
> }
> }
>
> +static inline bool dc_is_tmds_signal(enum signal_type signal)
> +{
> + switch (signal) {
> + case SIGNAL_TYPE_DVI_SINGLE_LINK:
> + case SIGNAL_TYPE_DVI_DUAL_LINK:
> + case SIGNAL_TYPE_HDMI_TYPE_A:
> + return true;
> + break;
> + default:
> + return false;
> + }
> +}
> +
> static inline bool dc_is_dvi_single_link_signal(enum signal_type signal)
> {
> return (signal == SIGNAL_TYPE_DVI_SINGLE_LINK);
Is this patch complete? It creates a helper that isn't used anywhere (?)
BR,
Melissa
^ permalink raw reply [flat|nested] 28+ messages in thread
end of thread, other threads:[~2024-04-15 19:17 UTC | newest]
Thread overview: 28+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2024-04-10 21:25 [PATCH 00/25] DC Patches April 10, 2024 Rodrigo Siqueira
2024-04-10 21:25 ` [PATCH 01/25] drm/amd/display: Modify power sequence Rodrigo Siqueira
2024-04-10 21:25 ` [PATCH 02/25] drm/amd/display: Add a function for checking tmds mode Rodrigo Siqueira
2024-04-15 19:16 ` Melissa Wen
2024-04-10 21:25 ` [PATCH 03/25] drm/amd/display: Modify resource allocation logic Rodrigo Siqueira
2024-04-10 21:25 ` [PATCH 04/25] drm/amd/display: limit the code change to ips enabled asic Rodrigo Siqueira
2024-04-10 21:25 ` [PATCH 05/25] drm/amd/display: add support for chroma offset Rodrigo Siqueira
2024-04-10 21:25 ` [PATCH 06/25] drm/amd/display: Pass sequential ONO bit to DMCUB boot options Rodrigo Siqueira
2024-04-10 21:25 ` [PATCH 07/25] drm/amd/display: Fix incorrect pointer assignment Rodrigo Siqueira
2024-04-10 21:25 ` [PATCH 08/25] drm/amd/display: Enable Z10 flag for IPS FSM Rodrigo Siqueira
2024-04-10 21:25 ` [PATCH 09/25] drm/amd/display: Rework power sequence and resource allocation logic Rodrigo Siqueira
2024-04-10 21:25 ` [PATCH 10/25] drm/amd/display: Expand dmub_cmd operations Rodrigo Siqueira
2024-04-10 21:26 ` [PATCH 11/25] drm/amd/display: Use dce_version instead of chip_id Rodrigo Siqueira
2024-04-10 21:26 ` [PATCH 12/25] drm/amd/display: Adjust headers Rodrigo Siqueira
2024-04-10 21:26 ` [PATCH 13/25] drm/amd/display: Improve the log precision Rodrigo Siqueira
2024-04-10 21:26 ` [PATCH 14/25] drm/amd/display: Fix PSR command version passed Rodrigo Siqueira
2024-04-10 21:26 ` [PATCH 15/25] drm/amd/display: Group scl_data together in resource_build_scaling_params Rodrigo Siqueira
2024-04-10 21:26 ` [PATCH 16/25] drm/amd/display: Replace int with unsigned int Rodrigo Siqueira
2024-04-10 21:26 ` [PATCH 17/25] drm/amd/display: Update some comments to improve the code readability Rodrigo Siqueira
2024-04-10 21:26 ` [PATCH 18/25] drm/amd/display: Remove unnecessary code Rodrigo Siqueira
2024-04-10 21:26 ` [PATCH 19/25] drm/amd/display: Update FMT settings for 4:2:0 Rodrigo Siqueira
2024-04-10 21:26 ` [PATCH 20/25] drm/amd/display: Rework dcn10_stream_encoder header Rodrigo Siqueira
2024-04-10 21:26 ` [PATCH 21/25] drm/amd/display: Move REG sequence from program ogam to idle before connect Rodrigo Siqueira
2024-04-10 21:26 ` [PATCH 22/25] drm/amd/display: Update DCN201 link encoder registers Rodrigo Siqueira
2024-04-10 21:26 ` [PATCH 23/25] drm/amd/display: Add missing callback for init_watermarks in DCN 301 Rodrigo Siqueira
2024-04-10 21:26 ` [PATCH 24/25] drm/amd/display: Add missing replay field Rodrigo Siqueira
2024-04-10 21:26 ` [PATCH 25/25] drm/amd/display: 3.2.281 Rodrigo Siqueira
2024-04-15 13:02 ` [PATCH 00/25] DC Patches April 10, 2024 Wheeler, Daniel
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