Re: [PATCH v3 2/5] drm:amdgpu: Enable IH ring1 for IH v6.1

[Friedrich Vock <friedrich.vock@gmx.de>]

On 16.04.24 15:34, Sunil Khatri wrote:
> We need IH ring1 for handling the pagefault
> interrupts which over flow in default
> ring for specific usecases.
>
> Signed-off-by: Sunil Khatri<sunil.khatri@amd.com>
> ---
>   drivers/gpu/drm/amd/amdgpu/ih_v6_1.c | 11 +++++++++--
>   1 file changed, 9 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/ih_v6_1.c b/drivers/gpu/drm/amd/amdgpu/ih_v6_1.c
> index b8da0fc29378..73dba180fabd 100644
> --- a/drivers/gpu/drm/amd/amdgpu/ih_v6_1.c
> +++ b/drivers/gpu/drm/amd/amdgpu/ih_v6_1.c
> @@ -550,8 +550,15 @@ static int ih_v6_1_sw_init(void *handle)
>   	adev->irq.ih.use_doorbell = true;
>   	adev->irq.ih.doorbell_index = adev->doorbell_index.ih << 1;
>
> -	adev->irq.ih1.ring_size = 0;
> -	adev->irq.ih2.ring_size = 0;
> +	if (!(adev->flags & AMD_IS_APU)) {

Why restrict this to dGPUs? Page faults can overflow the default ring on
APUs too (e.g. for Vangogh).

Regards,
Friedrich

> +		r = amdgpu_ih_ring_init(adev, &adev->irq.ih1, IH_RING_SIZE,
> +					use_bus_addr);
> +		if (r)
> +			return r;
> +
> +		adev->irq.ih1.use_doorbell = true;
> +		adev->irq.ih1.doorbell_index = (adev->doorbell_index.ih + 1) << 1;
> +	}
>
>   	/* initialize ih control register offset */
>   	ih_v6_1_init_register_offset(adev);