From: Alex Deucher <alexdeucher@gmail.com>
To: Sunil Khatri <sunil.khatri@amd.com>
Cc: "Alex Deucher" <alexander.deucher@amd.com>,
"Christian König" <christian.koenig@amd.com>,
amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH v3 4/5] drm/amdgpu: enable redirection of irq's for IH V6.0
Date: Tue, 16 Apr 2024 10:26:42 -0400 [thread overview]
Message-ID: <CADnq5_NMw0c5X4MqiFA6Zoyx2NFn1aKffjEun_w7onT6O10UUw@mail.gmail.com> (raw)
In-Reply-To: <20240416133423.3346-4-sunil.khatri@amd.com>
On Tue, Apr 16, 2024 at 9:34 AM Sunil Khatri <sunil.khatri@amd.com> wrote:
>
> Enable redirection of irq for pagefaults for specific
> clients to avoid overflow without dropping interrupts.
>
> So here we redirect the interrupts to another IH ring
> i.e ring1 where only these interrupts are processed.
>
> Signed-off-by: Sunil Khatri <sunil.khatri@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/ih_v6_0.c | 15 +++++++++++++++
> 1 file changed, 15 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/ih_v6_0.c b/drivers/gpu/drm/amd/amdgpu/ih_v6_0.c
> index 26dc99232eb6..8869aac03b82 100644
> --- a/drivers/gpu/drm/amd/amdgpu/ih_v6_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/ih_v6_0.c
> @@ -346,6 +346,21 @@ static int ih_v6_0_irq_init(struct amdgpu_device *adev)
> DELAY, 3);
> WREG32_SOC15(OSSSYS, 0, regIH_MSI_STORM_CTRL, tmp);
>
> + /* Redirect the interrupts to IH RB1 fpr dGPU */
fpr -> for
Alex
> + if (adev->irq.ih1.ring_size) {
> + tmp = RREG32_SOC15(OSSSYS, 0, regIH_RING1_CLIENT_CFG_INDEX);
> + tmp = REG_SET_FIELD(tmp, IH_RING1_CLIENT_CFG_INDEX, INDEX, 0);
> + WREG32_SOC15(OSSSYS, 0, regIH_RING1_CLIENT_CFG_INDEX, tmp);
> +
> + tmp = RREG32_SOC15(OSSSYS, 0, regIH_RING1_CLIENT_CFG_DATA);
> + tmp = REG_SET_FIELD(tmp, IH_RING1_CLIENT_CFG_DATA, CLIENT_ID, 0xa);
> + tmp = REG_SET_FIELD(tmp, IH_RING1_CLIENT_CFG_DATA, SOURCE_ID, 0x0);
> + tmp = REG_SET_FIELD(tmp, IH_RING1_CLIENT_CFG_DATA,
> + SOURCE_ID_MATCH_ENABLE, 0x1);
> +
> + WREG32_SOC15(OSSSYS, 0, regIH_RING1_CLIENT_CFG_DATA, tmp);
> + }
> +
> pci_set_master(adev->pdev);
>
> /* enable interrupts */
> --
> 2.34.1
>
next prev parent reply other threads:[~2024-04-16 14:26 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-04-16 13:34 [PATCH v3 1/5] drm:amdgpu: enable IH RB ring1 for IH v6.0 Sunil Khatri
2024-04-16 13:34 ` [PATCH v3 2/5] drm:amdgpu: Enable IH ring1 for IH v6.1 Sunil Khatri
2024-04-17 6:43 ` Friedrich Vock
2024-04-17 6:52 ` Christian König
2024-04-16 13:34 ` [PATCH v3 3/5] drm/amdgpu: Add IH_RING1_CFG headers for IH v6.0 Sunil Khatri
2024-04-16 13:34 ` [PATCH v3 4/5] drm/amdgpu: enable redirection of irq's for IH V6.0 Sunil Khatri
2024-04-16 14:26 ` Alex Deucher [this message]
2024-04-16 15:43 ` Khatri, Sunil
2024-04-16 13:34 ` [PATCH v3 5/5] drm/amdgpu: enable redirection of irq's for IH V6.1 Sunil Khatri
2024-04-16 13:36 ` [PATCH v3 1/5] drm:amdgpu: enable IH RB ring1 for IH v6.0 Christian König
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=CADnq5_NMw0c5X4MqiFA6Zoyx2NFn1aKffjEun_w7onT6O10UUw@mail.gmail.com \
--to=alexdeucher@gmail.com \
--cc=alexander.deucher@amd.com \
--cc=amd-gfx@lists.freedesktop.org \
--cc=christian.koenig@amd.com \
--cc=sunil.khatri@amd.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).