From: Kishon Vijay Abraham I <kishon@ti.com>
To: Vinod Koul <vkoul@kernel.org>, Rob Herring <robh+dt@kernel.org>,
Swapnil Jakhade <sjakhade@cadence.com>,
<linux-kernel@vger.kernel.org>, <devicetree@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>
Cc: Nishanth Menon <nm@ti.com>, Philipp Zabel <p.zabel@pengutronix.de>
Subject: Re: [PATCH v2 00/14] PHY: Add support in Sierra to use external clock
Date: Mon, 25 Jan 2021 17:01:17 +0530 [thread overview]
Message-ID: <ba7beace-e5b2-5020-2857-069de6aef6a6@ti.com> (raw)
In-Reply-To: <20201222070520.28132-1-kishon@ti.com>
On 22/12/20 12:35 pm, Kishon Vijay Abraham I wrote:
> The previous version of the patch series can be found @ [1]
>
> Changes from v1:
> 1) Remove the part that prevents configuration if the SERDES is already
> configured and focus only on using external clock and the associated
> cleanups
> 2) Change patch ordering
> 3) Use exclusive reset control APIs
> 4) Fix error handling code
> 5) Include DT patches in this series (I can send this separately to DT
> MAINTAINER once the driver patches are merged)
>
> [1] -> http://lore.kernel.org/r/20201103035556.21260-1-kishon@ti.com
>
I have couple of reports from kernel test robot. If there are any other
comments on this series, I can fix them.
Thanks
Kishon
> Kishon Vijay Abraham I (14):
> phy: cadence: Sierra: Fix PHY power_on sequence
> phy: ti: j721e-wiz: Invoke wiz_init() before
> of_platform_device_create()
> dt-bindings: phy: cadence-sierra: Add bindings for the PLLs within
> SERDES
> phy: ti: j721e-wiz: Get PHY properties only for "phy" or "link"
> subnode
> phy: cadence: cadence-sierra: Create PHY only for "phy" or "link"
> sub-nodes
> phy: cadence: cadence-sierra: Move all clk_get_*() to a separate
> function
> phy: cadence: cadence-sierra: Move all reset_control_get*() to a
> separate function
> phy: cadence: cadence-sierra: Explicitly request exclusive reset
> control
> phy: cadence: sierra: Model reference receiver as clocks (gate clocks)
> phy: cadence: sierra: Enable pll_cmnlc and pll_cmnlc1 clocks
> arm64: dts: ti: k3-j721e-main: Add DT nodes for clocks within Sierra
> SERDES
> arm64: dts: ti: k3-j721e-main: Fix external refclk input to SERDES
> arm64: dts: ti: k3-j721e-common-proc-board: Use external clock for
> SERDES
> arm64: dts: ti: k3-j721e-common-proc-board: Re-name "link" name as
> "phy"
>
> .../bindings/phy/phy-cadence-sierra.yaml | 89 ++-
> .../dts/ti/k3-j721e-common-proc-board.dts | 57 +-
> arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 186 ++++--
> drivers/phy/cadence/phy-cadence-sierra.c | 543 ++++++++++++++++--
> drivers/phy/ti/phy-j721e-wiz.c | 21 +-
> 5 files changed, 808 insertions(+), 88 deletions(-)
>
WARNING: multiple messages have this Message-ID (diff)
From: Kishon Vijay Abraham I <kishon@ti.com>
To: Vinod Koul <vkoul@kernel.org>, Rob Herring <robh+dt@kernel.org>,
Swapnil Jakhade <sjakhade@cadence.com>,
<linux-kernel@vger.kernel.org>, <devicetree@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>
Cc: Nishanth Menon <nm@ti.com>, Philipp Zabel <p.zabel@pengutronix.de>
Subject: Re: [PATCH v2 00/14] PHY: Add support in Sierra to use external clock
Date: Mon, 25 Jan 2021 17:01:17 +0530 [thread overview]
Message-ID: <ba7beace-e5b2-5020-2857-069de6aef6a6@ti.com> (raw)
In-Reply-To: <20201222070520.28132-1-kishon@ti.com>
On 22/12/20 12:35 pm, Kishon Vijay Abraham I wrote:
> The previous version of the patch series can be found @ [1]
>
> Changes from v1:
> 1) Remove the part that prevents configuration if the SERDES is already
> configured and focus only on using external clock and the associated
> cleanups
> 2) Change patch ordering
> 3) Use exclusive reset control APIs
> 4) Fix error handling code
> 5) Include DT patches in this series (I can send this separately to DT
> MAINTAINER once the driver patches are merged)
>
> [1] -> http://lore.kernel.org/r/20201103035556.21260-1-kishon@ti.com
>
I have couple of reports from kernel test robot. If there are any other
comments on this series, I can fix them.
Thanks
Kishon
> Kishon Vijay Abraham I (14):
> phy: cadence: Sierra: Fix PHY power_on sequence
> phy: ti: j721e-wiz: Invoke wiz_init() before
> of_platform_device_create()
> dt-bindings: phy: cadence-sierra: Add bindings for the PLLs within
> SERDES
> phy: ti: j721e-wiz: Get PHY properties only for "phy" or "link"
> subnode
> phy: cadence: cadence-sierra: Create PHY only for "phy" or "link"
> sub-nodes
> phy: cadence: cadence-sierra: Move all clk_get_*() to a separate
> function
> phy: cadence: cadence-sierra: Move all reset_control_get*() to a
> separate function
> phy: cadence: cadence-sierra: Explicitly request exclusive reset
> control
> phy: cadence: sierra: Model reference receiver as clocks (gate clocks)
> phy: cadence: sierra: Enable pll_cmnlc and pll_cmnlc1 clocks
> arm64: dts: ti: k3-j721e-main: Add DT nodes for clocks within Sierra
> SERDES
> arm64: dts: ti: k3-j721e-main: Fix external refclk input to SERDES
> arm64: dts: ti: k3-j721e-common-proc-board: Use external clock for
> SERDES
> arm64: dts: ti: k3-j721e-common-proc-board: Re-name "link" name as
> "phy"
>
> .../bindings/phy/phy-cadence-sierra.yaml | 89 ++-
> .../dts/ti/k3-j721e-common-proc-board.dts | 57 +-
> arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 186 ++++--
> drivers/phy/cadence/phy-cadence-sierra.c | 543 ++++++++++++++++--
> drivers/phy/ti/phy-j721e-wiz.c | 21 +-
> 5 files changed, 808 insertions(+), 88 deletions(-)
>
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next prev parent reply other threads:[~2021-01-26 6:19 UTC|newest]
Thread overview: 38+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-12-22 7:05 [PATCH v2 00/14] PHY: Add support in Sierra to use external clock Kishon Vijay Abraham I
2020-12-22 7:05 ` Kishon Vijay Abraham I
2020-12-22 7:05 ` [PATCH v2 01/14] phy: cadence: Sierra: Fix PHY power_on sequence Kishon Vijay Abraham I
2020-12-22 7:05 ` Kishon Vijay Abraham I
2020-12-22 7:05 ` [PATCH v2 02/14] phy: ti: j721e-wiz: Invoke wiz_init() before of_platform_device_create() Kishon Vijay Abraham I
2020-12-22 7:05 ` Kishon Vijay Abraham I
2020-12-22 7:05 ` [PATCH v2 03/14] dt-bindings: phy: cadence-sierra: Add bindings for the PLLs within SERDES Kishon Vijay Abraham I
2020-12-22 7:05 ` Kishon Vijay Abraham I
2020-12-22 7:05 ` [PATCH v2 04/14] phy: ti: j721e-wiz: Get PHY properties only for "phy" or "link" subnode Kishon Vijay Abraham I
2020-12-22 7:05 ` Kishon Vijay Abraham I
2020-12-22 7:05 ` [PATCH v2 05/14] phy: cadence: cadence-sierra: Create PHY only for "phy" or "link" sub-nodes Kishon Vijay Abraham I
2020-12-22 7:05 ` Kishon Vijay Abraham I
2020-12-22 7:05 ` [PATCH v2 06/14] phy: cadence: cadence-sierra: Move all clk_get_*() to a separate function Kishon Vijay Abraham I
2020-12-22 7:05 ` Kishon Vijay Abraham I
2020-12-22 7:05 ` [PATCH v2 07/14] phy: cadence: cadence-sierra: Move all reset_control_get*() " Kishon Vijay Abraham I
2020-12-22 7:05 ` Kishon Vijay Abraham I
2020-12-22 7:05 ` [PATCH v2 08/14] phy: cadence: cadence-sierra: Explicitly request exclusive reset control Kishon Vijay Abraham I
2020-12-22 7:05 ` Kishon Vijay Abraham I
2020-12-22 7:05 ` [PATCH v2 09/14] phy: cadence: sierra: Model reference receiver as clocks (gate clocks) Kishon Vijay Abraham I
2020-12-22 7:05 ` Kishon Vijay Abraham I
2020-12-23 19:00 ` kernel test robot
2020-12-23 19:00 ` kernel test robot
2020-12-23 19:00 ` kernel test robot
2020-12-23 22:45 ` kernel test robot
2020-12-23 22:45 ` kernel test robot
2020-12-23 22:45 ` kernel test robot
2020-12-22 7:05 ` [PATCH v2 10/14] phy: cadence: sierra: Enable pll_cmnlc and pll_cmnlc1 clocks Kishon Vijay Abraham I
2020-12-22 7:05 ` Kishon Vijay Abraham I
2020-12-22 7:05 ` [PATCH v2 11/14] arm64: dts: ti: k3-j721e-main: Add DT nodes for clocks within Sierra SERDES Kishon Vijay Abraham I
2020-12-22 7:05 ` Kishon Vijay Abraham I
2020-12-22 7:05 ` [PATCH v2 12/14] arm64: dts: ti: k3-j721e-main: Fix external refclk input to SERDES Kishon Vijay Abraham I
2020-12-22 7:05 ` Kishon Vijay Abraham I
2020-12-22 7:05 ` [PATCH v2 13/14] arm64: dts: ti: k3-j721e-common-proc-board: Use external clock for SERDES Kishon Vijay Abraham I
2020-12-22 7:05 ` Kishon Vijay Abraham I
2020-12-22 7:05 ` [PATCH v2 14/14] arm64: dts: ti: k3-j721e-common-proc-board: Re-name "link" name as "phy" Kishon Vijay Abraham I
2020-12-22 7:05 ` Kishon Vijay Abraham I
2021-01-25 11:31 ` Kishon Vijay Abraham I [this message]
2021-01-25 11:31 ` [PATCH v2 00/14] PHY: Add support in Sierra to use external clock Kishon Vijay Abraham I
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