[cip-dev] [PATCH 4.19.y-cip v2 00/57] Add basic RZ/G2M SoC support

[cip-dev] [PATCH 4.19.y-cip v2 00/57] Add basic RZ/G2M SoC support

[Fabrizio Castro]

Dear All,

this series aims at providing basic RZ/G2M SoC dtsi support.

v1->v2:
* dropped "serial: sh-sci: Fix TX DMA buffer flushing and workqueue races"
* dropped "serial: sh-sci: Terminate TX DMA during buffer flushing"
* dropped "dmaengine: rcar-dmac: Reject zero-length slave DMA requests"

Thanks,
Fab

Biju Das (13):
  dt-bindings: dmaengine: usb-dmac: Add binding for r8a774a1
  arm64: dts: renesas: Initial r8a774a1 SoC device tree
  arm64: dts: renesas: r8a774a1: Add SYS-DMAC controller nodes
  arm64: dts: renesas: r8a774a1: Add INTC-EX device node
  arm64: dts: renesas: r8a774a1: Add RWDT node
  arm64: dts: renesas: r8a774a1: Add I2C and IIC-DVFS support
  arm64: dts: renesas: r8a774a1: Add RZ/G2M thermal support
  arm64: dts: renesas: r8a774a1: Add all MSIOF nodes
  arm64: dts: renesas: r8a774a1: Add Cortex-A53 CPU cores
  arm64: dts: renesas: r8a774a1: Add audio support
  arm64: dts: renesas: r8a774a1: Add USB2.0 phy and host(EHCI/OHCI)
    device nodes
  arm64: dts: renesas: r8a774a1: Add USB-DMAC and HSUSB device nodes
  arm64: dts: renesas: r8a774a1: Add USB3.0 device nodes

Chris Paterson (1):
  arm64: dts: renesas: r8a774a1: Add CAN nodes

Enrico Weigelt, metux IT consult (1):
  gpio: rcar: Pedantic formatting

Fabrizio Castro (21):
  dt-bindings: can: rcar_can: Add r8a774a1 support
  dt-bindings: can: rcar_can: Fix RZ/G2 CAN clocks
  dt-bindings: can: rcar_can: Add r8a774c0 support
  dt-bindings: rcar-gen3-phy-usb3: Add r8a774a1 support
  dt-bindings: usb-xhci: Add r8a774a1 support
  dt-bindings: usb-xhci: Add r8a774c0 support
  dt-bindings: usb: renesas_usbhs: Add r8a774a1 support
  dt-bindings: thermal: rcar-gen3-thermal: Add r8a774a1 support
  thermal: rcar_gen3_thermal: Add r8a774a1 support
  arm64: dts: renesas: r8a774a1: Add SCIF and HSCIF nodes
  arm64: dts: renesas: r8a774a1: Add Ethernet AVB node
  arm64: dts: renesas: r8a774a1: Add pinctrl device node
  arm64: dts: renesas: r8a774a1: Add GPIO device nodes
  arm64: dts: renesas: r8a774a1: Add SDHI nodes
  arm64: dts: renesas: r8a774a1: Add IPMMU device nodes
  arm64: dts: renesas: r8a774a1: Add PWM device nodes
  arm64: dts: renesas: r8a774a1: Add FCPF and FCPV instances
  arm64: dts: renesas: r8a774a1: Replace power magic numbers
  arm64: dts: renesas: r8a774a1: Replace clock magic numbers
  arm64: dts: renesas: r8a774a1: Fix hsusb reg size
  arm64: dts: renesas: r8a774a1: Add clkp2 clock to CAN nodes

Geert Uytterhoeven (12):
  clk: renesas: cpg-mssr: Use genpd of_node instead of local copy
  clk: renesas: cpg-mssr: Remove error messages on out-of-memory
    conditions
  soc: renesas: rcar-sysc: Remove rcar_sysc_power_{down,up}() helpers
  soc: renesas: rcar-sysc: Merge PM Domain registration and linking
  soc: renesas: rcar-sysc: Fix power domain control after system resume
  serial: sh-sci: Fix crash in rx_timer_fn() on PIO fallback
  serial: sh-sci: Extract sci_dma_rx_chan_invalidate()
  serial: sh-sci: Extract sci_dma_rx_reenable_irq()
  serial: sh-sci: Fix fallback to PIO in sci_dma_rx_complete()
  arm64: dts: renesas: Fix whitespace around assignments
  arm64: dts: renesas: Remove unneeded status from thermal nodes
  arm64: dts: renesas: r8a774a1: Enable DMA for SCIF2

Hiroyuki Yokoyama (1):
  dmaengine: rcar-dmac: Update copyright information

Kazuya Mizuguchi (1):
  ravb: remove tx buffer addr 4byte alilgnment restriction for R-Car
    Gen3

Niklas S?derlund (1):
  mmc: renesas_sdhi_internal_dmac: set scatter/gather max segment size

Rob Herring (1):
  arm64: dts: Remove inconsistent use of 'arm,armv8' compatible string

Sergei Shtylyov (1):
  spi: sh-msiof: fix deferred probing

Simon Horman (1):
  ravb: Avoid unsupported internal delay mode for R-Car E3/D3

Vladimir Zapolskiy (2):
  gpio: rcar: reference device instead of platform device
  gpio: rcar: select General Output Register to set output states

Wolfram Sang (1):
  dmaengine: rcar-dmac: set scatter/gather max segment size

 .../devicetree/bindings/dma/renesas,usb-dmac.txt   |    1 +
 .../devicetree/bindings/net/can/rcar_can.txt       |    9 +-
 .../devicetree/bindings/phy/rcar-gen3-phy-usb3.txt |   10 +-
 .../bindings/thermal/rcar-gen3-thermal.txt         |    1 +
 .../devicetree/bindings/usb/renesas_usbhs.txt      |    3 +-
 Documentation/devicetree/bindings/usb/usb-xhci.txt |    5 +-
 arch/arm64/boot/dts/renesas/r8a774a1.dtsi          | 1695 ++++++++++++++++++++
 drivers/clk/renesas/renesas-cpg-mssr.c             |   12 +-
 drivers/dma/sh/rcar-dmac.c                         |    7 +-
 drivers/gpio/gpio-rcar.c                           |   38 +-
 drivers/mmc/host/renesas_sdhi_internal_dmac.c      |    8 +
 drivers/net/ethernet/renesas/ravb.h                |    6 +-
 drivers/net/ethernet/renesas/ravb_main.c           |  158 +-
 drivers/soc/renesas/rcar-sysc.c                    |   65 +-
 drivers/spi/spi-sh-msiof.c                         |    4 +-
 drivers/thermal/rcar_gen3_thermal.c                |    1 +
 drivers/tty/serial/sh-sci.c                        |   47 +-
 17 files changed, 1911 insertions(+), 159 deletions(-)
 create mode 100644 arch/arm64/boot/dts/renesas/r8a774a1.dtsi

-- 
2.7.4

[cip-dev] [PATCH 4.19.y-cip v2 01/57] dt-bindings: can: rcar_can: Add r8a774a1 support

[Fabrizio Castro]

commit 868b7c0f43e61f227bf3d7f7d6134bb3c67bb0e8 upstream.

Document RZ/G2M (r8a774a1) SoC specific bindings.

Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Signed-off-by: Chris Paterson <Chris.Paterson2@renesas.com>
Reviewed-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
---
 Documentation/devicetree/bindings/net/can/rcar_can.txt | 18 +++++++++++++-----
 1 file changed, 13 insertions(+), 5 deletions(-)

diff --git a/Documentation/devicetree/bindings/net/can/rcar_can.txt b/Documentation/devicetree/bindings/net/can/rcar_can.txt
index 94a7f33..f3b160c 100644
--- a/Documentation/devicetree/bindings/net/can/rcar_can.txt
+++ b/Documentation/devicetree/bindings/net/can/rcar_can.txt
@@ -4,6 +4,7 @@ Renesas R-Car CAN controller Device Tree Bindings
 Required properties:
 - compatible: "renesas,can-r8a7743" if CAN controller is a part of R8A7743 SoC.
 	      "renesas,can-r8a7745" if CAN controller is a part of R8A7745 SoC.
+	      "renesas,can-r8a774a1" if CAN controller is a part of R8A774A1 SoC.
 	      "renesas,can-r8a7778" if CAN controller is a part of R8A7778 SoC.
 	      "renesas,can-r8a7779" if CAN controller is a part of R8A7779 SoC.
 	      "renesas,can-r8a7790" if CAN controller is a part of R8A7790 SoC.
@@ -16,15 +17,21 @@ Required properties:
 	      "renesas,rcar-gen1-can" for a generic R-Car Gen1 compatible device.
 	      "renesas,rcar-gen2-can" for a generic R-Car Gen2 or RZ/G1
 	      compatible device.
-	      "renesas,rcar-gen3-can" for a generic R-Car Gen3 compatible device.
+	      "renesas,rcar-gen3-can" for a generic R-Car Gen3 or RZ/G2
+	      compatible device.
 	      When compatible with the generic version, nodes must list the
 	      SoC-specific version corresponding to the platform first
 	      followed by the generic version.
 
 - reg: physical base address and size of the R-Car CAN register map.
 - interrupts: interrupt specifier for the sole interrupt.
-- clocks: phandles and clock specifiers for 3 CAN clock inputs.
-- clock-names: 3 clock input name strings: "clkp1", "clkp2", "can_clk".
+- clocks: phandles and clock specifiers for 2 CAN clock inputs for RZ/G2
+	  devices.
+	  phandles and clock specifiers for 3 CAN clock inputs for every other
+	  SoC.
+- clock-names: 2 clock input name strings for RZ/G2: "clkp1", "can_clk".
+	       3 clock input name strings for every other SoC: "clkp1", "clkp2",
+	       "can_clk".
 - pinctrl-0: pin control group to be used for this controller.
 - pinctrl-names: must be "default".
 
@@ -41,8 +48,9 @@ using the below properties:
 Optional properties:
 - renesas,can-clock-select: R-Car CAN Clock Source Select. Valid values are:
 			    <0x0> (default) : Peripheral clock (clkp1)
-			    <0x1> : Peripheral clock (clkp2)
-			    <0x3> : Externally input clock
+			    <0x1> : Peripheral clock (clkp2) (not supported by
+				    RZ/G2 devices)
+			    <0x3> : External input clock
 
 Example
 -------
-- 
2.7.4

[cip-dev] [PATCH 4.19.y-cip v2 02/57] dt-bindings: can: rcar_can: Fix RZ/G2 CAN clocks

[Fabrizio Castro]

commit e6aacf9a52e0b013835c7e33538bcdf0703bbe2e upstream.

According to the latest information, the clock options for CAN on RZ/G2
are the same as the ones available on R-Car Gen3

Fixes: 868b7c0f43e6 ("dt-bindings: can: rcar_can: Add r8a774a1 support")
Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Chris Paterson <Chris.Paterson2@renesas.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Acked-by: David S. Miller <davem@davemloft.net>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 Documentation/devicetree/bindings/net/can/rcar_can.txt | 12 +++---------
 1 file changed, 3 insertions(+), 9 deletions(-)

diff --git a/Documentation/devicetree/bindings/net/can/rcar_can.txt b/Documentation/devicetree/bindings/net/can/rcar_can.txt
index f3b160c..a7b01bf 100644
--- a/Documentation/devicetree/bindings/net/can/rcar_can.txt
+++ b/Documentation/devicetree/bindings/net/can/rcar_can.txt
@@ -25,13 +25,8 @@ Required properties:
 
 - reg: physical base address and size of the R-Car CAN register map.
 - interrupts: interrupt specifier for the sole interrupt.
-- clocks: phandles and clock specifiers for 2 CAN clock inputs for RZ/G2
-	  devices.
-	  phandles and clock specifiers for 3 CAN clock inputs for every other
-	  SoC.
-- clock-names: 2 clock input name strings for RZ/G2: "clkp1", "can_clk".
-	       3 clock input name strings for every other SoC: "clkp1", "clkp2",
-	       "can_clk".
+- clocks: phandles and clock specifiers for 3 CAN clock inputs.
+- clock-names: 3 clock input name strings: "clkp1", "clkp2", and "can_clk".
 - pinctrl-0: pin control group to be used for this controller.
 - pinctrl-names: must be "default".
 
@@ -48,8 +43,7 @@ using the below properties:
 Optional properties:
 - renesas,can-clock-select: R-Car CAN Clock Source Select. Valid values are:
 			    <0x0> (default) : Peripheral clock (clkp1)
-			    <0x1> : Peripheral clock (clkp2) (not supported by
-				    RZ/G2 devices)
+			    <0x1> : Peripheral clock (clkp2)
 			    <0x3> : External input clock
 
 Example
-- 
2.7.4

[cip-dev] [PATCH 4.19.y-cip v2 03/57] dt-bindings: can: rcar_can: Add r8a774c0 support

[Fabrizio Castro]

commit d703a52eb1ebeeba42f2385bbe84f1dc86f4353c upstream.

Document RZ/G2E (r8a774c0) SoC specific bindings.

Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Rob Herring <robh@kernel.org>
Acked-by: David S. Miller <davem@davemloft.net>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 Documentation/devicetree/bindings/net/can/rcar_can.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/net/can/rcar_can.txt b/Documentation/devicetree/bindings/net/can/rcar_can.txt
index a7b01bf..e1d428a 100644
--- a/Documentation/devicetree/bindings/net/can/rcar_can.txt
+++ b/Documentation/devicetree/bindings/net/can/rcar_can.txt
@@ -5,6 +5,7 @@ Required properties:
 - compatible: "renesas,can-r8a7743" if CAN controller is a part of R8A7743 SoC.
 	      "renesas,can-r8a7745" if CAN controller is a part of R8A7745 SoC.
 	      "renesas,can-r8a774a1" if CAN controller is a part of R8A774A1 SoC.
+	      "renesas,can-r8a774c0" if CAN controller is a part of R8A774C0 SoC.
 	      "renesas,can-r8a7778" if CAN controller is a part of R8A7778 SoC.
 	      "renesas,can-r8a7779" if CAN controller is a part of R8A7779 SoC.
 	      "renesas,can-r8a7790" if CAN controller is a part of R8A7790 SoC.
-- 
2.7.4

[cip-dev] [PATCH 4.19.y-cip v2 04/57] dt-bindings: rcar-gen3-phy-usb3: Add r8a774a1 support

[Fabrizio Castro]

commit fcd0eec4f54f1a8627a2d7fcbaaeed18261276a4 upstream.

Document RZ/G2M (R8A774A1) SoC bindings.

Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
---
 Documentation/devicetree/bindings/phy/rcar-gen3-phy-usb3.txt | 10 ++++++----
 1 file changed, 6 insertions(+), 4 deletions(-)

diff --git a/Documentation/devicetree/bindings/phy/rcar-gen3-phy-usb3.txt b/Documentation/devicetree/bindings/phy/rcar-gen3-phy-usb3.txt
index 47dd296..9d98266 100644
--- a/Documentation/devicetree/bindings/phy/rcar-gen3-phy-usb3.txt
+++ b/Documentation/devicetree/bindings/phy/rcar-gen3-phy-usb3.txt
@@ -1,20 +1,22 @@
 * Renesas R-Car generation 3 USB 3.0 PHY
 
 This file provides information on what the device node for the R-Car generation
-3 USB 3.0 PHY contains.
+3 and RZ/G2 USB 3.0 PHY contain.
 If you want to enable spread spectrum clock (ssc), you should use USB_EXTAL
 instead of USB3_CLK. However, if you don't want to these features, you don't
 need this driver.
 
 Required properties:
-- compatible: "renesas,r8a7795-usb3-phy" if the device is a part of an R8A7795
+- compatible: "renesas,r8a774a1-usb3-phy" if the device is a part of an R8A774A1
+	      SoC.
+	      "renesas,r8a7795-usb3-phy" if the device is a part of an R8A7795
 	      SoC.
 	      "renesas,r8a7796-usb3-phy" if the device is a part of an R8A7796
 	      SoC.
 	      "renesas,r8a77965-usb3-phy" if the device is a part of an
 	      R8A77965 SoC.
-	      "renesas,rcar-gen3-usb3-phy" for a generic R-Car Gen3 compatible
-	      device.
+	      "renesas,rcar-gen3-usb3-phy" for a generic R-Car Gen3 or RZ/G2
+	      compatible device.
 
 	      When compatible with the generic version, nodes must list the
 	      SoC-specific version corresponding to the platform first
-- 
2.7.4

[cip-dev] [PATCH 4.19.y-cip v2 05/57] dt-bindings: usb-xhci: Add r8a774a1 support

[Fabrizio Castro]

commit c49234a054719d39bbd48e35342add3ba3276405 upstream.

Document RZ/G2M (R8A774A1) SoC bindings.

Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
 Documentation/devicetree/bindings/usb/usb-xhci.txt | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/usb/usb-xhci.txt b/Documentation/devicetree/bindings/usb/usb-xhci.txt
index ac4cd0d..fb564e7 100644
--- a/Documentation/devicetree/bindings/usb/usb-xhci.txt
+++ b/Documentation/devicetree/bindings/usb/usb-xhci.txt
@@ -8,6 +8,7 @@ Required properties:
     - "marvell,armada-375-xhci" for Armada 375 SoCs
     - "marvell,armada-380-xhci" for Armada 38x SoCs
     - "renesas,xhci-r8a7743" for r8a7743 SoC
+    - "renesas,xhci-r8a774a1" for r8a774a1 SoC
     - "renesas,xhci-r8a7790" for r8a7790 SoC
     - "renesas,xhci-r8a7791" for r8a7791 SoC
     - "renesas,xhci-r8a7793" for r8a7793 SoC
@@ -17,7 +18,8 @@ Required properties:
     - "renesas,xhci-r8a77990" for r8a77990 SoC
     - "renesas,rcar-gen2-xhci" for a generic R-Car Gen2 or RZ/G1 compatible
       device
-    - "renesas,rcar-gen3-xhci" for a generic R-Car Gen3 compatible device
+    - "renesas,rcar-gen3-xhci" for a generic R-Car Gen3 or RZ/G2 compatible
+      device
     - "xhci-platform" (deprecated)
 
     When compatible with the generic version, nodes must list the
-- 
2.7.4

[cip-dev] [PATCH 4.19.y-cip v2 06/57] dt-bindings: usb-xhci: Add r8a774c0 support

[Fabrizio Castro]

commit 6fee3787ea7aebf25fecdce325ee9b2150c5727b upstream.

Document RZ/G2E (R8A774C0) SoC bindings.

Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
[fab: backported to 4.19.y-cip]
Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
---
 Documentation/devicetree/bindings/usb/usb-xhci.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/usb/usb-xhci.txt b/Documentation/devicetree/bindings/usb/usb-xhci.txt
index fb564e7..53a3f68 100644
--- a/Documentation/devicetree/bindings/usb/usb-xhci.txt
+++ b/Documentation/devicetree/bindings/usb/usb-xhci.txt
@@ -9,6 +9,7 @@ Required properties:
     - "marvell,armada-380-xhci" for Armada 38x SoCs
     - "renesas,xhci-r8a7743" for r8a7743 SoC
     - "renesas,xhci-r8a774a1" for r8a774a1 SoC
+    - "renesas,xhci-r8a774c0" for r8a774c0 SoC
     - "renesas,xhci-r8a7790" for r8a7790 SoC
     - "renesas,xhci-r8a7791" for r8a7791 SoC
     - "renesas,xhci-r8a7793" for r8a7793 SoC
-- 
2.7.4

[cip-dev] [PATCH 4.19.y-cip v2 07/57] dt-bindings: usb: renesas_usbhs: Add r8a774a1 support

[Fabrizio Castro]

commit 3938e13e98f97b22a89e5aefe5fbef54d91673a3 upstream.

Document RZ/G2M (R8A774A1) SoC bindings.

Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
 Documentation/devicetree/bindings/usb/renesas_usbhs.txt | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/usb/renesas_usbhs.txt b/Documentation/devicetree/bindings/usb/renesas_usbhs.txt
index 616c6c4..8126486 100644
--- a/Documentation/devicetree/bindings/usb/renesas_usbhs.txt
+++ b/Documentation/devicetree/bindings/usb/renesas_usbhs.txt
@@ -5,6 +5,7 @@ Required properties:
 
 	- "renesas,usbhs-r8a7743" for r8a7743 (RZ/G1M) compatible device
 	- "renesas,usbhs-r8a7745" for r8a7745 (RZ/G1E) compatible device
+	- "renesas,usbhs-r8a774a1" for r8a774a1 (RZ/G2M) compatible device
 	- "renesas,usbhs-r8a774c0" for r8a774c0 (RZ/G2E) compatible device
 	- "renesas,usbhs-r8a7790" for r8a7790 (R-Car H2) compatible device
 	- "renesas,usbhs-r8a7791" for r8a7791 (R-Car M2-W) compatible device
@@ -17,7 +18,7 @@ Required properties:
 	- "renesas,usbhs-r8a77995" for r8a77995 (R-Car D3) compatible device
 	- "renesas,usbhs-r7s72100" for r7s72100 (RZ/A1) compatible device
 	- "renesas,rcar-gen2-usbhs" for R-Car Gen2 or RZ/G1 compatible devices
-	- "renesas,rcar-gen3-usbhs" for R-Car Gen3 compatible device
+	- "renesas,rcar-gen3-usbhs" for R-Car Gen3 or RZ/G2 compatible devices
 	- "renesas,rza1-usbhs" for RZ/A1 compatible device
 
 	When compatible with the generic version, nodes must list the
-- 
2.7.4

[cip-dev] [PATCH 4.19.y-cip v2 08/57] dt-bindings: thermal: rcar-gen3-thermal: Add r8a774a1 support

[Fabrizio Castro]

commit be6af481f3b2d5084c4e70684eaa962602f94707 upstream.

Document RZ/G2M (R8A774A1) SoC bindings.

Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Eduardo Valentin <edubezval@gmail.com>
---
 Documentation/devicetree/bindings/thermal/rcar-gen3-thermal.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/thermal/rcar-gen3-thermal.txt b/Documentation/devicetree/bindings/thermal/rcar-gen3-thermal.txt
index cfa154b..098bf95 100644
--- a/Documentation/devicetree/bindings/thermal/rcar-gen3-thermal.txt
+++ b/Documentation/devicetree/bindings/thermal/rcar-gen3-thermal.txt
@@ -7,6 +7,7 @@ inside the LSI.
 Required properties:
 - compatible		: "renesas,<soctype>-thermal",
 			  Examples with soctypes are:
+			    - "renesas,r8a774a1-thermal" (RZ/G2M)
 			    - "renesas,r8a7795-thermal" (R-Car H3)
 			    - "renesas,r8a7796-thermal" (R-Car M3-W)
 			    - "renesas,r8a77965-thermal" (R-Car M3-N)
-- 
2.7.4

[cip-dev] [PATCH 4.19.y-cip v2 09/57] dt-bindings: dmaengine: usb-dmac: Add binding for r8a774a1

[Fabrizio Castro]

From: Biju Das <biju.das@bp.renesas.com>

commit b9b4ed210380e51f5c5960dcbceedcc0bbe28408 upstream.

This patch adds binding for r8a774a1 (RZ/G2M).

Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
---
 Documentation/devicetree/bindings/dma/renesas,usb-dmac.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/dma/renesas,usb-dmac.txt b/Documentation/devicetree/bindings/dma/renesas,usb-dmac.txt
index 4354ed6..5e82a93 100644
--- a/Documentation/devicetree/bindings/dma/renesas,usb-dmac.txt
+++ b/Documentation/devicetree/bindings/dma/renesas,usb-dmac.txt
@@ -5,6 +5,7 @@ Required Properties:
 	Examples with soctypes are:
 	  - "renesas,r8a7743-usb-dmac" (RZ/G1M)
 	  - "renesas,r8a7745-usb-dmac" (RZ/G1E)
+	  - "renesas,r8a774a1-usb-dmac" (RZ/G2M)
 	  - "renesas,r8a774c0-usb-dmac" (RZ/G2E)
 	  - "renesas,r8a7790-usb-dmac" (R-Car H2)
 	  - "renesas,r8a7791-usb-dmac" (R-Car M2-W)
-- 
2.7.4

[cip-dev] [PATCH 4.19.y-cip v2 10/57] thermal: rcar_gen3_thermal: Add r8a774a1 support

[Fabrizio Castro]

commit 1d9e6cf3c8537c14ad979a9c02ce4e674e5f50e8 upstream.

Add r8a774a1 specific compatible string.

Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Eduardo Valentin <edubezval@gmail.com>
---
 drivers/thermal/rcar_gen3_thermal.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/thermal/rcar_gen3_thermal.c b/drivers/thermal/rcar_gen3_thermal.c
index 704c8ad..393ed96 100644
--- a/drivers/thermal/rcar_gen3_thermal.c
+++ b/drivers/thermal/rcar_gen3_thermal.c
@@ -318,6 +318,7 @@ static void rcar_gen3_thermal_init(struct rcar_gen3_thermal_tsc *tsc)
 }
 
 static const struct of_device_id rcar_gen3_thermal_dt_ids[] = {
+	{ .compatible = "renesas,r8a774a1-thermal", },
 	{ .compatible = "renesas,r8a7795-thermal", },
 	{ .compatible = "renesas,r8a7796-thermal", },
 	{ .compatible = "renesas,r8a77965-thermal", },
-- 
2.7.4

[cip-dev] [PATCH 4.19.y-cip v2 11/57] gpio: rcar: reference device instead of platform device

[Fabrizio Castro]

From: Vladimir Zapolskiy <vz@mleia.com>

commit a53f79534f4ef418640b0f5c61500069de442e16 upstream.

The change simplifies dereferences to the mediated struct device, also
it allows to limit the scope of the platform device usage to probe and
remove functions only.

Non-functional change.

Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
---
 drivers/gpio/gpio-rcar.c | 24 +++++++++++-------------
 1 file changed, 11 insertions(+), 13 deletions(-)

diff --git a/drivers/gpio/gpio-rcar.c b/drivers/gpio/gpio-rcar.c
index 55cc610..3aad2b5 100644
--- a/drivers/gpio/gpio-rcar.c
+++ b/drivers/gpio/gpio-rcar.c
@@ -43,7 +43,7 @@ struct gpio_rcar_bank_info {
 struct gpio_rcar_priv {
 	void __iomem *base;
 	spinlock_t lock;
-	struct platform_device *pdev;
+	struct device *dev;
 	struct gpio_chip gpio_chip;
 	struct irq_chip irq_chip;
 	unsigned int irq_parent;
@@ -148,7 +148,7 @@ static int gpio_rcar_irq_set_type(struct irq_data *d, unsigned int type)
 	struct gpio_rcar_priv *p = gpiochip_get_data(gc);
 	unsigned int hwirq = irqd_to_hwirq(d);
 
-	dev_dbg(&p->pdev->dev, "sense irq = %d, type = %d\n", hwirq, type);
+	dev_dbg(p->dev, "sense irq = %d, type = %d\n", hwirq, type);
 
 	switch (type & IRQ_TYPE_SENSE_MASK) {
 	case IRQ_TYPE_LEVEL_HIGH:
@@ -188,8 +188,7 @@ static int gpio_rcar_irq_set_wake(struct irq_data *d, unsigned int on)
 	if (p->irq_parent) {
 		error = irq_set_irq_wake(p->irq_parent, on);
 		if (error) {
-			dev_dbg(&p->pdev->dev,
-				"irq %u doesn't support irq_set_wake\n",
+			dev_dbg(p->dev, "irq %u doesn't support irq_set_wake\n",
 				p->irq_parent);
 			p->irq_parent = 0;
 		}
@@ -252,13 +251,13 @@ static int gpio_rcar_request(struct gpio_chip *chip, unsigned offset)
 	struct gpio_rcar_priv *p = gpiochip_get_data(chip);
 	int error;
 
-	error = pm_runtime_get_sync(&p->pdev->dev);
+	error = pm_runtime_get_sync(p->dev);
 	if (error < 0)
 		return error;
 
 	error = pinctrl_gpio_request(chip->base + offset);
 	if (error)
-		pm_runtime_put(&p->pdev->dev);
+		pm_runtime_put(p->dev);
 
 	return error;
 }
@@ -275,7 +274,7 @@ static void gpio_rcar_free(struct gpio_chip *chip, unsigned offset)
 	 */
 	gpio_rcar_config_general_input_output_mode(chip, offset, false);
 
-	pm_runtime_put(&p->pdev->dev);
+	pm_runtime_put(p->dev);
 }
 
 static int gpio_rcar_get_direction(struct gpio_chip *chip, unsigned int offset)
@@ -403,21 +402,20 @@ MODULE_DEVICE_TABLE(of, gpio_rcar_of_table);
 
 static int gpio_rcar_parse_dt(struct gpio_rcar_priv *p, unsigned int *npins)
 {
-	struct device_node *np = p->pdev->dev.of_node;
+	struct device_node *np = p->dev->of_node;
 	const struct gpio_rcar_info *info;
 	struct of_phandle_args args;
 	int ret;
 
-	info = of_device_get_match_data(&p->pdev->dev);
+	info = of_device_get_match_data(p->dev);
 
 	ret = of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0, &args);
 	*npins = ret == 0 ? args.args[2] : RCAR_MAX_GPIO_PER_BANK;
 	p->has_both_edge_trigger = info->has_both_edge_trigger;
 
 	if (*npins == 0 || *npins > RCAR_MAX_GPIO_PER_BANK) {
-		dev_warn(&p->pdev->dev,
-			 "Invalid number of gpio lines %u, using %u\n", *npins,
-			 RCAR_MAX_GPIO_PER_BANK);
+		dev_warn(p->dev, "Invalid number of gpio lines %u, using %u\n",
+			 *npins, RCAR_MAX_GPIO_PER_BANK);
 		*npins = RCAR_MAX_GPIO_PER_BANK;
 	}
 
@@ -439,7 +437,7 @@ static int gpio_rcar_probe(struct platform_device *pdev)
 	if (!p)
 		return -ENOMEM;
 
-	p->pdev = pdev;
+	p->dev = dev;
 	spin_lock_init(&p->lock);
 
 	/* Get device configuration from DT node */
-- 
2.7.4

[cip-dev] [PATCH 4.19.y-cip v2 12/57] gpio: rcar: select General Output Register to set output states

[Fabrizio Castro]

From: Vladimir Zapolskiy <vladimir_zapolskiy@mentor.com>

commit 3ae4f3aac05ab9cc7d93ef3e87bb0bd159cb6bfa upstream.

R-Car GPIO controller provides two interfaces to set GPIO line output
signal state, and for a particular GPIO line the selected interface is
determined by OUTDTSEL bit value.

At the moment the driver supports only one of two interfaces, namely
OUTDT General Output Register is used to control the output signal.

While this selection is the default one on reset, it is not explicitly
configured on probe, thus it might be possible that kernel and userspace
consumers of a GPIO won't be able to set the wanted GPIO output signal.

Below is a simple test case to reproduce the described problem and
verify this fix in the kernel on H3 ULCB by setting non-default OUTDTSEL
configuration from a bootloader:

  u-boot    > mw.l 0xe6055440 0x3000 1
  ...
  userspace > echo default-on > /sys/devices/platform/leds/leds/led5/trigger
  userspace > echo default-on > /sys/devices/platform/leds/leds/led6/trigger

Signed-off-by: Vladimir Zapolskiy <vladimir_zapolskiy@mentor.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
---
 drivers/gpio/gpio-rcar.c | 12 +++++++++++-
 1 file changed, 11 insertions(+), 1 deletion(-)

diff --git a/drivers/gpio/gpio-rcar.c b/drivers/gpio/gpio-rcar.c
index 3aad2b5..74489c1 100644
--- a/drivers/gpio/gpio-rcar.c
+++ b/drivers/gpio/gpio-rcar.c
@@ -48,6 +48,7 @@ struct gpio_rcar_priv {
 	struct irq_chip irq_chip;
 	unsigned int irq_parent;
 	atomic_t wakeup_path;
+	bool has_outdtsel;
 	bool has_both_edge_trigger;
 	struct gpio_rcar_bank_info bank_info;
 };
@@ -63,6 +64,7 @@ struct gpio_rcar_priv {
 #define POSNEG 0x20	/* Positive/Negative Logic Select Register */
 #define EDGLEVEL 0x24	/* Edge/level Select Register */
 #define FILONOFF 0x28	/* Chattering Prevention On/Off Register */
+#define OUTDTSEL 0x40	/* Output Data Select Register */
 #define BOTHEDGE 0x4c	/* One Edge/Both Edge Select Register */
 
 #define RCAR_MAX_GPIO_PER_BANK		32
@@ -243,6 +245,10 @@ static void gpio_rcar_config_general_input_output_mode(struct gpio_chip *chip,
 	/* Select Input Mode or Output Mode in INOUTSEL */
 	gpio_rcar_modify_bit(p, INOUTSEL, gpio, output);
 
+	/* Select General Output Register to output data in OUTDTSEL */
+	if (p->has_outdtsel && output)
+		gpio_rcar_modify_bit(p, OUTDTSEL, gpio, false);
+
 	spin_unlock_irqrestore(&p->lock, flags);
 }
 
@@ -341,14 +347,17 @@ static int gpio_rcar_direction_output(struct gpio_chip *chip, unsigned offset,
 }
 
 struct gpio_rcar_info {
+	bool has_outdtsel;
 	bool has_both_edge_trigger;
 };
 
 static const struct gpio_rcar_info gpio_rcar_info_gen1 = {
+	.has_outdtsel = false,
 	.has_both_edge_trigger = false,
 };
 
 static const struct gpio_rcar_info gpio_rcar_info_gen2 = {
+	.has_outdtsel = true,
 	.has_both_edge_trigger = true,
 };
 
@@ -408,10 +417,11 @@ static int gpio_rcar_parse_dt(struct gpio_rcar_priv *p, unsigned int *npins)
 	int ret;
 
 	info = of_device_get_match_data(p->dev);
+	p->has_outdtsel = info->has_outdtsel;
+	p->has_both_edge_trigger = info->has_both_edge_trigger;
 
 	ret = of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0, &args);
 	*npins = ret == 0 ? args.args[2] : RCAR_MAX_GPIO_PER_BANK;
-	p->has_both_edge_trigger = info->has_both_edge_trigger;
 
 	if (*npins == 0 || *npins > RCAR_MAX_GPIO_PER_BANK) {
 		dev_warn(p->dev, "Invalid number of gpio lines %u, using %u\n",
-- 
2.7.4

[cip-dev] [PATCH 4.19.y-cip v2 13/57] gpio: rcar: Pedantic formatting

[Fabrizio Castro]

From: "Enrico Weigelt, metux IT consult" <info@metux.net>

commit b183cab7fdf79843f79398af139e02186692c6c7 upstream.

A tab sneaked in, where it shouldn't be.

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Enrico Weigelt, metux IT consult <info@metux.net>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
---
 drivers/gpio/gpio-rcar.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpio/gpio-rcar.c b/drivers/gpio/gpio-rcar.c
index 74489c1..c8d526a 100644
--- a/drivers/gpio/gpio-rcar.c
+++ b/drivers/gpio/gpio-rcar.c
@@ -495,7 +495,7 @@ static int gpio_rcar_probe(struct platform_device *pdev)
 	irq_chip->irq_unmask = gpio_rcar_irq_enable;
 	irq_chip->irq_set_type = gpio_rcar_irq_set_type;
 	irq_chip->irq_set_wake = gpio_rcar_irq_set_wake;
-	irq_chip->flags	= IRQCHIP_SET_TYPE_MASKED | IRQCHIP_MASK_ON_SUSPEND;
+	irq_chip->flags = IRQCHIP_SET_TYPE_MASKED | IRQCHIP_MASK_ON_SUSPEND;
 
 	ret = gpiochip_add_data(gpio_chip, p);
 	if (ret) {
-- 
2.7.4

[cip-dev] [PATCH 4.19.y-cip v2 14/57] clk: renesas: cpg-mssr: Use genpd of_node instead of local copy

[Fabrizio Castro]

From: Geert Uytterhoeven <geert+renesas@glider.be>

commit f243220e674c61ae6434209e25c25c12cada4e4e upstream.

Since commit 6a0ae73d95956f7e ("PM / Domain: Add support to parse
domain's OPP table"), of_genpd_add_provider_simple() fills in
the dev.of_node field in the generic_pm_domain structure.

Hence cpg_mssr_is_pm_clk() can use that instead of its own copy in the
driver-private cpg_mssr_clk_domain structure.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Reviewed-by: Niklas S?derlund <niklas.soderlund+renesas@ragnatech.se>
Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
---
 drivers/clk/renesas/renesas-cpg-mssr.c | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/drivers/clk/renesas/renesas-cpg-mssr.c b/drivers/clk/renesas/renesas-cpg-mssr.c
index 3a23456..3fe648a 100644
--- a/drivers/clk/renesas/renesas-cpg-mssr.c
+++ b/drivers/clk/renesas/renesas-cpg-mssr.c
@@ -411,7 +411,6 @@ static void __init cpg_mssr_register_mod_clk(const struct mssr_mod_clk *mod,
 
 struct cpg_mssr_clk_domain {
 	struct generic_pm_domain genpd;
-	struct device_node *np;
 	unsigned int num_core_pm_clks;
 	unsigned int core_pm_clks[0];
 };
@@ -423,7 +422,7 @@ static bool cpg_mssr_is_pm_clk(const struct of_phandle_args *clkspec,
 {
 	unsigned int i;
 
-	if (clkspec->np != pd->np || clkspec->args_count != 2)
+	if (clkspec->np != pd->genpd.dev.of_node || clkspec->args_count != 2)
 		return false;
 
 	switch (clkspec->args[0]) {
@@ -513,7 +512,6 @@ static int __init cpg_mssr_add_clk_domain(struct device *dev,
 	if (!pd)
 		return -ENOMEM;
 
-	pd->np = np;
 	pd->num_core_pm_clks = num_core_pm_clks;
 	memcpy(pd->core_pm_clks, core_pm_clks, pm_size);
 
-- 
2.7.4

[cip-dev] [PATCH 4.19.y-cip v2 15/57] clk: renesas: cpg-mssr: Remove error messages on out-of-memory conditions

[Fabrizio Castro]

From: Geert Uytterhoeven <geert+renesas@glider.be>

commit ed04e6288ac59a59a2e9265194a6be892f708c66 upstream.

pm_clk_create() and pm_clk_add_clk() can fail only when running out of
memory.  Hence there is no need to print error messages on failure, as
the memory allocation core already takes care of that.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Reviewed-by: Niklas S?derlund <niklas.soderlund+renesas@ragnatech.se>
Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
---
 drivers/clk/renesas/renesas-cpg-mssr.c | 8 ++------
 1 file changed, 2 insertions(+), 6 deletions(-)

diff --git a/drivers/clk/renesas/renesas-cpg-mssr.c b/drivers/clk/renesas/renesas-cpg-mssr.c
index 3fe648a..d9541e1 100644
--- a/drivers/clk/renesas/renesas-cpg-mssr.c
+++ b/drivers/clk/renesas/renesas-cpg-mssr.c
@@ -473,16 +473,12 @@ int cpg_mssr_attach_dev(struct generic_pm_domain *unused, struct device *dev)
 		return PTR_ERR(clk);
 
 	error = pm_clk_create(dev);
-	if (error) {
-		dev_err(dev, "pm_clk_create failed %d\n", error);
+	if (error)
 		goto fail_put;
-	}
 
 	error = pm_clk_add_clk(dev, clk);
-	if (error) {
-		dev_err(dev, "pm_clk_add_clk %pC failed %d\n", clk, error);
+	if (error)
 		goto fail_destroy;
-	}
 
 	return 0;
 
-- 
2.7.4

[cip-dev] [PATCH 4.19.y-cip v2 16/57] soc: renesas: rcar-sysc: Remove rcar_sysc_power_{down, up}() helpers

[Fabrizio Castro]

From: Geert Uytterhoeven <geert+renesas@glider.be>

commit 319c84090696517f377a80225534677adf192e92 upstream.

Until commit 7e8a50df26f4e700 ("soc: renesas: rcar-sysc: Drop legacy
handling"), the rcar_sysc_power_{down,up}() helpers were public, as they
were called by the legacy (pre-DT) CPU power management code on R-Car H1
and R-Car Gen2 before.

As they are just one-line wrappers around rcar_sysc_power(), it makes
sense to just remove them.

This also avoids a bool/helper/bool conversion in rcar_sysc_power_cpu(),
where a bool is checked to call one of two helper functions, which
just call rcar_sysc_power() with hardcoded boolean values again.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
---
 drivers/soc/renesas/rcar-sysc.c | 19 ++++---------------
 1 file changed, 4 insertions(+), 15 deletions(-)

diff --git a/drivers/soc/renesas/rcar-sysc.c b/drivers/soc/renesas/rcar-sysc.c
index e63d7a2..a71852f 100644
--- a/drivers/soc/renesas/rcar-sysc.c
+++ b/drivers/soc/renesas/rcar-sysc.c
@@ -149,16 +149,6 @@ static int rcar_sysc_power(const struct rcar_sysc_ch *sysc_ch, bool on)
 	return ret;
 }
 
-static int rcar_sysc_power_down(const struct rcar_sysc_ch *sysc_ch)
-{
-	return rcar_sysc_power(sysc_ch, false);
-}
-
-static int rcar_sysc_power_up(const struct rcar_sysc_ch *sysc_ch)
-{
-	return rcar_sysc_power(sysc_ch, true);
-}
-
 static bool rcar_sysc_power_is_off(const struct rcar_sysc_ch *sysc_ch)
 {
 	unsigned int st;
@@ -187,7 +177,7 @@ static int rcar_sysc_pd_power_off(struct generic_pm_domain *genpd)
 	struct rcar_sysc_pd *pd = to_rcar_pd(genpd);
 
 	pr_debug("%s: %s\n", __func__, genpd->name);
-	return rcar_sysc_power_down(&pd->ch);
+	return rcar_sysc_power(&pd->ch, false);
 }
 
 static int rcar_sysc_pd_power_on(struct generic_pm_domain *genpd)
@@ -195,7 +185,7 @@ static int rcar_sysc_pd_power_on(struct generic_pm_domain *genpd)
 	struct rcar_sysc_pd *pd = to_rcar_pd(genpd);
 
 	pr_debug("%s: %s\n", __func__, genpd->name);
-	return rcar_sysc_power_up(&pd->ch);
+	return rcar_sysc_power(&pd->ch, true);
 }
 
 static bool has_cpg_mstp;
@@ -255,7 +245,7 @@ static int __init rcar_sysc_pd_setup(struct rcar_sysc_pd *pd)
 		goto finalize;
 	}
 
-	rcar_sysc_power_up(&pd->ch);
+	rcar_sysc_power(&pd->ch, true);
 
 finalize:
 	error = pm_genpd_init(genpd, gov, false);
@@ -479,8 +469,7 @@ static int rcar_sysc_power_cpu(unsigned int idx, bool on)
 		if (!(pd->flags & PD_CPU) || pd->ch.chan_bit != idx)
 			continue;
 
-		return on ? rcar_sysc_power_up(&pd->ch)
-			  : rcar_sysc_power_down(&pd->ch);
+		return rcar_sysc_power(&pd->ch, on);
 	}
 
 	return -ENOENT;
-- 
2.7.4

[cip-dev] [PATCH 4.19.y-cip v2 17/57] soc: renesas: rcar-sysc: Merge PM Domain registration and linking

[Fabrizio Castro]

From: Geert Uytterhoeven <geert+renesas@glider.be>

commit 1585124d9563da64f481dc0e7c568c344002bc13 upstream.

Commit 977d5ba4507dfe5b ("soc: renesas: rcar-sysc: Make PM domain
initialization more robust") split PM Domain registration and the
linking of children to their parents, to accommodate PM Domain tables
that list child domains before their parents.

However, this failed to realize that parent power domains must be
powered up before their children anyway, and that this thus must be
reflected by the order in the PM Domain tables.

Revert the split, as it did not help anyway.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
---
 drivers/soc/renesas/rcar-sysc.c | 18 +++++-------------
 1 file changed, 5 insertions(+), 13 deletions(-)

diff --git a/drivers/soc/renesas/rcar-sysc.c b/drivers/soc/renesas/rcar-sysc.c
index a71852f..c3805fc 100644
--- a/drivers/soc/renesas/rcar-sysc.c
+++ b/drivers/soc/renesas/rcar-sysc.c
@@ -382,9 +382,6 @@ static int __init rcar_sysc_pd_init(void)
 	pr_debug("%pOF: syscier = 0x%08x\n", np, syscier);
 	iowrite32(syscier, base + SYSCIER);
 
-	/*
-	 * First, create all PM domains
-	 */
 	for (i = 0; i < info->num_areas; i++) {
 		const struct rcar_sysc_area *area = &info->areas[i];
 		struct rcar_sysc_pd *pd;
@@ -412,22 +409,17 @@ static int __init rcar_sysc_pd_init(void)
 			goto out_put;
 
 		domains->domains[area->isr_bit] = &pd->genpd;
-	}
 
-	/*
-	 * Second, link all PM domains to their parents
-	 */
-	for (i = 0; i < info->num_areas; i++) {
-		const struct rcar_sysc_area *area = &info->areas[i];
-
-		if (!area->name || area->parent < 0)
+		if (area->parent < 0)
 			continue;
 
 		error = pm_genpd_add_subdomain(domains->domains[area->parent],
-					       domains->domains[area->isr_bit]);
-		if (error)
+					       &pd->genpd);
+		if (error) {
 			pr_warn("Failed to add PM subdomain %s to parent %u\n",
 				area->name, area->parent);
+			goto out_put;
+		}
 	}
 
 	error = of_genpd_add_provider_onecell(np, &domains->onecell_data);
-- 
2.7.4

[cip-dev] [PATCH 4.19.y-cip v2 18/57] soc: renesas: rcar-sysc: Fix power domain control after system resume

[Fabrizio Castro]

From: Geert Uytterhoeven <geert+renesas@glider.be>

commit 7fc4650cc2417d7a2907a000f6f88240baa42018 upstream.

To control power to a power domain, the System Controller (SYSC) needs
the corresponding interrupt source to be enabled, but masked, to prevent
the CPU from receiving it.

Currently this is handled in the driver's probe() routine, and set up
for every domain present, even if it will not be controlled directly by
SYSC (CPU domains are powered through the APMU on R-Car Gen2 and later).

On R-Car Gen3, PSCI powers down the SoC during system suspend, thus
losing any configured interrupt state.  Hence after system resume, power
domains not controlled through the APMU (e.g. A3IR, A3VC, A3VP) fail to
power up.

Fix this by replacing the global interrupt setup in the probe() routine
by a domain-specific interrupt setup in rcar_sysc_power(), where the
domain's power is actually controlled.  This brings the code more in
line with the flowchart in the Hardware User's Manual.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
---
 drivers/soc/renesas/rcar-sysc.c | 28 +++++++++-------------------
 1 file changed, 9 insertions(+), 19 deletions(-)

diff --git a/drivers/soc/renesas/rcar-sysc.c b/drivers/soc/renesas/rcar-sysc.c
index c3805fc..3fc5937 100644
--- a/drivers/soc/renesas/rcar-sysc.c
+++ b/drivers/soc/renesas/rcar-sysc.c
@@ -108,6 +108,15 @@ static int rcar_sysc_power(const struct rcar_sysc_ch *sysc_ch, bool on)
 
 	spin_lock_irqsave(&rcar_sysc_lock, flags);
 
+	/*
+	 * The interrupt source needs to be enabled, but masked, to prevent the
+	 * CPU from receiving it.
+	 */
+	iowrite32(ioread32(rcar_sysc_base + SYSCIMR) | isr_mask,
+		  rcar_sysc_base + SYSCIMR);
+	iowrite32(ioread32(rcar_sysc_base + SYSCIER) | isr_mask,
+		  rcar_sysc_base + SYSCIER);
+
 	iowrite32(isr_mask, rcar_sysc_base + SYSCISCR);
 
 	/* Submit power shutoff or resume request until it was accepted */
@@ -325,7 +334,6 @@ static int __init rcar_sysc_pd_init(void)
 	const struct of_device_id *match;
 	struct rcar_pm_domains *domains;
 	struct device_node *np;
-	u32 syscier, syscimr;
 	void __iomem *base;
 	unsigned int i;
 	int error;
@@ -364,24 +372,6 @@ static int __init rcar_sysc_pd_init(void)
 	domains->onecell_data.num_domains = ARRAY_SIZE(domains->domains);
 	rcar_sysc_onecell_data = &domains->onecell_data;
 
-	for (i = 0, syscier = 0; i < info->num_areas; i++)
-		syscier |= BIT(info->areas[i].isr_bit);
-
-	/*
-	 * Mask all interrupt sources to prevent the CPU from receiving them.
-	 * Make sure not to clear reserved bits that were set before.
-	 */
-	syscimr = ioread32(base + SYSCIMR);
-	syscimr |= syscier;
-	pr_debug("%pOF: syscimr = 0x%08x\n", np, syscimr);
-	iowrite32(syscimr, base + SYSCIMR);
-
-	/*
-	 * SYSC needs all interrupt sources enabled to control power.
-	 */
-	pr_debug("%pOF: syscier = 0x%08x\n", np, syscier);
-	iowrite32(syscier, base + SYSCIER);
-
 	for (i = 0; i < info->num_areas; i++) {
 		const struct rcar_sysc_area *area = &info->areas[i];
 		struct rcar_sysc_pd *pd;
-- 
2.7.4

[cip-dev] [PATCH 4.19.y-cip v2 19/57] serial: sh-sci: Fix crash in rx_timer_fn() on PIO fallback

[Fabrizio Castro]

From: Geert Uytterhoeven <geert+renesas@glider.be>

commit 2e948218b7c1262a3830823d6620eb227e3d4e3a upstream.

When falling back to PIO, active_rx must be set to a different value
than cookie_rx[i], else sci_dma_rx_find_active() will incorrectly find a
match, leading to a NULL pointer dereference in rx_timer_fn() later.

Use zero instead, which is the same value as after driver
initialization.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
---
 drivers/tty/serial/sh-sci.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c
index 5550289..9e1a6af 100644
--- a/drivers/tty/serial/sh-sci.c
+++ b/drivers/tty/serial/sh-sci.c
@@ -1359,7 +1359,7 @@ static int sci_submit_rx(struct sci_port *s, bool port_lock_held)
 		dmaengine_terminate_async(chan);
 	for (i = 0; i < 2; i++)
 		s->cookie_rx[i] = -EINVAL;
-	s->active_rx = -EINVAL;
+	s->active_rx = 0;
 	s->chan_rx = NULL;
 	sci_start_rx(port);
 	if (!port_lock_held)
-- 
2.7.4

[cip-dev] [PATCH 4.19.y-cip v2 20/57] serial: sh-sci: Extract sci_dma_rx_chan_invalidate()

[Fabrizio Castro]

From: Geert Uytterhoeven <geert+renesas@glider.be>

commit 11b3770d54b28dcd905155a6d4aa551187ff00eb upstream.

The cookies and channel pointer for the DMA receive channel are
invalidated in two places, and one more is planned.
Extract this functionality in a common helper.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
---
 drivers/tty/serial/sh-sci.c | 19 +++++++++++++------
 1 file changed, 13 insertions(+), 6 deletions(-)

diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c
index 9e1a6af..2632bb2 100644
--- a/drivers/tty/serial/sh-sci.c
+++ b/drivers/tty/serial/sh-sci.c
@@ -1233,12 +1233,22 @@ static int sci_dma_rx_find_active(struct sci_port *s)
 	return -1;
 }
 
+static void sci_dma_rx_chan_invalidate(struct sci_port *s)
+{
+	unsigned int i;
+
+	s->chan_rx = NULL;
+	for (i = 0; i < ARRAY_SIZE(s->cookie_rx); i++)
+		s->cookie_rx[i] = -EINVAL;
+	s->active_rx = 0;
+}
+
 static void sci_rx_dma_release(struct sci_port *s)
 {
 	struct dma_chan *chan = s->chan_rx_saved;
 
-	s->chan_rx_saved = s->chan_rx = NULL;
-	s->cookie_rx[0] = s->cookie_rx[1] = -EINVAL;
+	s->chan_rx_saved = NULL;
+	sci_dma_rx_chan_invalidate(s);
 	dmaengine_terminate_sync(chan);
 	dma_free_coherent(chan->device->dev, s->buf_len_rx * 2, s->rx_buf[0],
 			  sg_dma_address(&s->sg_rx[0]));
@@ -1357,10 +1367,7 @@ static int sci_submit_rx(struct sci_port *s, bool port_lock_held)
 		spin_lock_irqsave(&port->lock, flags);
 	if (i)
 		dmaengine_terminate_async(chan);
-	for (i = 0; i < 2; i++)
-		s->cookie_rx[i] = -EINVAL;
-	s->active_rx = 0;
-	s->chan_rx = NULL;
+	sci_dma_rx_chan_invalidate(s);
 	sci_start_rx(port);
 	if (!port_lock_held)
 		spin_unlock_irqrestore(&port->lock, flags);
-- 
2.7.4

[cip-dev] [PATCH 4.19.y-cip v2 21/57] serial: sh-sci: Extract sci_dma_rx_reenable_irq()

[Fabrizio Castro]

From: Geert Uytterhoeven <geert+renesas@glider.be>

commit 38766e4b612ba10844afadf2fce12f8f90465c64 upstream.

Extract the functionality to direct new serial port interrupts back to
the CPU into its own helper, to prepare for using it from a second
callsite.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
---
 drivers/tty/serial/sh-sci.c | 23 +++++++++++++++--------
 1 file changed, 15 insertions(+), 8 deletions(-)

diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c
index 2632bb2..d5bd3f7 100644
--- a/drivers/tty/serial/sh-sci.c
+++ b/drivers/tty/serial/sh-sci.c
@@ -1264,6 +1264,20 @@ static void start_hrtimer_us(struct hrtimer *hrt, unsigned long usec)
 	hrtimer_start(hrt, t, HRTIMER_MODE_REL);
 }
 
+static void sci_dma_rx_reenable_irq(struct sci_port *s)
+{
+	struct uart_port *port = &s->port;
+	u16 scr;
+
+	/* Direct new serial port interrupts back to CPU */
+	scr = serial_port_in(port, SCSCR);
+	if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
+		scr &= ~SCSCR_RDRQE;
+		enable_irq(s->irqs[SCIx_RXI_IRQ]);
+	}
+	serial_port_out(port, SCSCR, scr | SCSCR_RIE);
+}
+
 static void sci_dma_rx_complete(void *arg)
 {
 	struct sci_port *s = arg;
@@ -1451,7 +1465,6 @@ static enum hrtimer_restart rx_timer_fn(struct hrtimer *t)
 	unsigned long flags;
 	unsigned int read;
 	int active, count;
-	u16 scr;
 
 	dev_dbg(port->dev, "DMA Rx timed out\n");
 
@@ -1501,13 +1514,7 @@ static enum hrtimer_restart rx_timer_fn(struct hrtimer *t)
 	if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
 		sci_submit_rx(s, true);
 
-	/* Direct new serial port interrupts back to CPU */
-	scr = serial_port_in(port, SCSCR);
-	if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
-		scr &= ~SCSCR_RDRQE;
-		enable_irq(s->irqs[SCIx_RXI_IRQ]);
-	}
-	serial_port_out(port, SCSCR, scr | SCSCR_RIE);
+	sci_dma_rx_reenable_irq(s);
 
 	spin_unlock_irqrestore(&port->lock, flags);
 
-- 
2.7.4

[cip-dev] [PATCH 4.19.y-cip v2 22/57] serial: sh-sci: Fix fallback to PIO in sci_dma_rx_complete()

[Fabrizio Castro]

From: Geert Uytterhoeven <geert+renesas@glider.be>

commit 26f073993665683f1debf4d66d8bc274ac6df771 upstream.

When submitting a DMA request fails in sci_dma_rx_complete(), the driver
tries to fall back to PIO, but that does not work: no more data will be
received, or the kernel will even crash.

Fix this similar as in (but not identical to) sci_submit_rx():
  - On SCIF, PIO cannot take over if any DMA transactions are pending,
    hence they must be terminated first.
  - All active cookies must be invalidated, else rx_timer_fn() may
    trigger a NULL pointer dereference.
  - Restarting the port is not needed, as it is already running, but
    serial port interrupts must be directed back from the DMA engine to
    the CPU.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
---
 drivers/tty/serial/sh-sci.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c
index d5bd3f7..29dce54 100644
--- a/drivers/tty/serial/sh-sci.c
+++ b/drivers/tty/serial/sh-sci.c
@@ -1327,8 +1327,9 @@ static void sci_dma_rx_complete(void *arg)
 	dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n");
 	/* Switch to PIO */
 	spin_lock_irqsave(&port->lock, flags);
-	s->chan_rx = NULL;
-	sci_start_rx(port);
+	dmaengine_terminate_async(chan);
+	sci_dma_rx_chan_invalidate(s);
+	sci_dma_rx_reenable_irq(s);
 	spin_unlock_irqrestore(&port->lock, flags);
 }
 
-- 
2.7.4

[cip-dev] [PATCH 4.19.y-cip v2 23/57] dmaengine: rcar-dmac: set scatter/gather max segment size

[Fabrizio Castro]

From: Wolfram Sang <wsa+renesas@sang-engineering.com>

commit 97d49c59e219acac576e16293a6b8cb99302f62f upstream.

Fix warning when running with CONFIG_DMA_API_DEBUG_SG=y by allocating a
device_dma_parameters structure and filling in the max segment size.

Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
---
 drivers/dma/sh/rcar-dmac.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/dma/sh/rcar-dmac.c b/drivers/dma/sh/rcar-dmac.c
index 041ce86..80ff95f 100644
--- a/drivers/dma/sh/rcar-dmac.c
+++ b/drivers/dma/sh/rcar-dmac.c
@@ -198,6 +198,7 @@ struct rcar_dmac {
 	struct dma_device engine;
 	struct device *dev;
 	void __iomem *iomem;
+	struct device_dma_parameters parms;
 
 	unsigned int n_channels;
 	struct rcar_dmac_chan *channels;
@@ -1814,6 +1815,8 @@ static int rcar_dmac_probe(struct platform_device *pdev)
 
 	dmac->dev = &pdev->dev;
 	platform_set_drvdata(pdev, dmac);
+	dmac->dev->dma_parms = &dmac->parms;
+	dma_set_max_seg_size(dmac->dev, RCAR_DMATCR_MASK);
 	dma_set_mask_and_coherent(dmac->dev, DMA_BIT_MASK(40));
 
 	ret = rcar_dmac_parse_of(&pdev->dev, dmac);
-- 
2.7.4

[cip-dev] [PATCH 4.19.y-cip v2 24/57] dmaengine: rcar-dmac: Update copyright information

[Fabrizio Castro]

From: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com>

commit 8a6061c34a54a997db1ded6d89b7db6cbe3f359e upstream.

Update copyright and string for Gen3.

Signed-off-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com>
Signed-off-by: Niklas S?derlund <niklas.soderlund+renesas@ragnatech.se>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
---
 drivers/dma/sh/rcar-dmac.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/dma/sh/rcar-dmac.c b/drivers/dma/sh/rcar-dmac.c
index 80ff95f..cf71a73 100644
--- a/drivers/dma/sh/rcar-dmac.c
+++ b/drivers/dma/sh/rcar-dmac.c
@@ -1,8 +1,8 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
- * Renesas R-Car Gen2 DMA Controller Driver
+ * Renesas R-Car Gen2/Gen3 DMA Controller Driver
  *
- * Copyright (C) 2014 Renesas Electronics Inc.
+ * Copyright (C) 2014-2019 Renesas Electronics Inc.
  *
  * Author: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
  */
-- 
2.7.4

[cip-dev] [PATCH 4.19.y-cip v2 25/57] spi: sh-msiof: fix deferred probing

[Fabrizio Castro]

From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>

commit f34c6e6257aa477cdfe7e9bbbecd3c5648ecda69 upstream.

Since commit 9ec36cafe43b ("of/irq: do irq resolution in platform_get_irq")
platform_get_irq() can return -EPROBE_DEFER. However, the driver overrides
an error returned by that function with -ENOENT which breaks the deferred
probing. Propagate upstream an error code returned by platform_get_irq()
and remove the bogus "platform" from the error message, while at it...

Fixes: 9ec36cafe43b ("of/irq: do irq resolution in platform_get_irq")
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
---
 drivers/spi/spi-sh-msiof.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/spi/spi-sh-msiof.c b/drivers/spi/spi-sh-msiof.c
index 101cd6a..30ea0a2 100644
--- a/drivers/spi/spi-sh-msiof.c
+++ b/drivers/spi/spi-sh-msiof.c
@@ -1343,8 +1343,8 @@ static int sh_msiof_spi_probe(struct platform_device *pdev)
 
 	i = platform_get_irq(pdev, 0);
 	if (i < 0) {
-		dev_err(&pdev->dev, "cannot get platform IRQ\n");
-		ret = -ENOENT;
+		dev_err(&pdev->dev, "cannot get IRQ\n");
+		ret = i;
 		goto err1;
 	}
 
-- 
2.7.4

[cip-dev] [PATCH 4.19.y-cip v2 26/57] ravb: remove tx buffer addr 4byte alilgnment restriction for R-Car Gen3

[Fabrizio Castro]

From: Kazuya Mizuguchi <kazuya.mizuguchi.ks@renesas.com>

commit f543305da9b5a5efaf6fa61606e8bbc8977f406d upstream.

This patch sets from two descriptor to one descriptor because R-Car Gen3
does not have the 4 bytes alignment restriction of the transmission buffer.

Signed-off-by: Kazuya Mizuguchi <kazuya.mizuguchi.ks@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
---
 drivers/net/ethernet/renesas/ravb.h      |   6 +-
 drivers/net/ethernet/renesas/ravb_main.c | 143 +++++++++++++++++++------------
 2 files changed, 92 insertions(+), 57 deletions(-)

diff --git a/drivers/net/ethernet/renesas/ravb.h b/drivers/net/ethernet/renesas/ravb.h
index 9b6bf55..1c6e4df 100644
--- a/drivers/net/ethernet/renesas/ravb.h
+++ b/drivers/net/ethernet/renesas/ravb.h
@@ -959,7 +959,10 @@ enum RAVB_QUEUE {
 #define RX_QUEUE_OFFSET	4
 #define NUM_RX_QUEUE	2
 #define NUM_TX_QUEUE	2
-#define NUM_TX_DESC	2	/* TX descriptors per packet */
+
+/* TX descriptors per packet */
+#define NUM_TX_DESC_GEN2	2
+#define NUM_TX_DESC_GEN3	1
 
 struct ravb_tstamp_skb {
 	struct list_head list;
@@ -1038,6 +1041,7 @@ struct ravb_private {
 	unsigned no_avb_link:1;
 	unsigned avb_link_active_low:1;
 	unsigned wol_enabled:1;
+	int num_tx_desc;	/* TX descriptors per packet */
 };
 
 static inline u32 ravb_read(struct net_device *ndev, enum ravb_reg reg)
diff --git a/drivers/net/ethernet/renesas/ravb_main.c b/drivers/net/ethernet/renesas/ravb_main.c
index 5f092bb..037a0ad 100644
--- a/drivers/net/ethernet/renesas/ravb_main.c
+++ b/drivers/net/ethernet/renesas/ravb_main.c
@@ -182,6 +182,7 @@ static int ravb_tx_free(struct net_device *ndev, int q, bool free_txed_only)
 {
 	struct ravb_private *priv = netdev_priv(ndev);
 	struct net_device_stats *stats = &priv->stats[q];
+	int num_tx_desc = priv->num_tx_desc;
 	struct ravb_tx_desc *desc;
 	int free_num = 0;
 	int entry;
@@ -191,7 +192,7 @@ static int ravb_tx_free(struct net_device *ndev, int q, bool free_txed_only)
 		bool txed;
 
 		entry = priv->dirty_tx[q] % (priv->num_tx_ring[q] *
-					     NUM_TX_DESC);
+					     num_tx_desc);
 		desc = &priv->tx_ring[q][entry];
 		txed = desc->die_dt == DT_FEMPTY;
 		if (free_txed_only && !txed)
@@ -200,12 +201,12 @@ static int ravb_tx_free(struct net_device *ndev, int q, bool free_txed_only)
 		dma_rmb();
 		size = le16_to_cpu(desc->ds_tagl) & TX_DS;
 		/* Free the original skb. */
-		if (priv->tx_skb[q][entry / NUM_TX_DESC]) {
+		if (priv->tx_skb[q][entry / num_tx_desc]) {
 			dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr),
 					 size, DMA_TO_DEVICE);
 			/* Last packet descriptor? */
-			if (entry % NUM_TX_DESC == NUM_TX_DESC - 1) {
-				entry /= NUM_TX_DESC;
+			if (entry % num_tx_desc == num_tx_desc - 1) {
+				entry /= num_tx_desc;
 				dev_kfree_skb_any(priv->tx_skb[q][entry]);
 				priv->tx_skb[q][entry] = NULL;
 				if (txed)
@@ -224,6 +225,7 @@ static int ravb_tx_free(struct net_device *ndev, int q, bool free_txed_only)
 static void ravb_ring_free(struct net_device *ndev, int q)
 {
 	struct ravb_private *priv = netdev_priv(ndev);
+	int num_tx_desc = priv->num_tx_desc;
 	int ring_size;
 	int i;
 
@@ -249,7 +251,7 @@ static void ravb_ring_free(struct net_device *ndev, int q)
 		ravb_tx_free(ndev, q, false);
 
 		ring_size = sizeof(struct ravb_tx_desc) *
-			    (priv->num_tx_ring[q] * NUM_TX_DESC + 1);
+			    (priv->num_tx_ring[q] * num_tx_desc + 1);
 		dma_free_coherent(ndev->dev.parent, ring_size, priv->tx_ring[q],
 				  priv->tx_desc_dma[q]);
 		priv->tx_ring[q] = NULL;
@@ -278,12 +280,13 @@ static void ravb_ring_free(struct net_device *ndev, int q)
 static void ravb_ring_format(struct net_device *ndev, int q)
 {
 	struct ravb_private *priv = netdev_priv(ndev);
+	int num_tx_desc = priv->num_tx_desc;
 	struct ravb_ex_rx_desc *rx_desc;
 	struct ravb_tx_desc *tx_desc;
 	struct ravb_desc *desc;
 	int rx_ring_size = sizeof(*rx_desc) * priv->num_rx_ring[q];
 	int tx_ring_size = sizeof(*tx_desc) * priv->num_tx_ring[q] *
-			   NUM_TX_DESC;
+			   num_tx_desc;
 	dma_addr_t dma_addr;
 	int i;
 
@@ -318,8 +321,10 @@ static void ravb_ring_format(struct net_device *ndev, int q)
 	for (i = 0, tx_desc = priv->tx_ring[q]; i < priv->num_tx_ring[q];
 	     i++, tx_desc++) {
 		tx_desc->die_dt = DT_EEMPTY;
-		tx_desc++;
-		tx_desc->die_dt = DT_EEMPTY;
+		if (num_tx_desc > 1) {
+			tx_desc++;
+			tx_desc->die_dt = DT_EEMPTY;
+		}
 	}
 	tx_desc->dptr = cpu_to_le32((u32)priv->tx_desc_dma[q]);
 	tx_desc->die_dt = DT_LINKFIX; /* type */
@@ -339,6 +344,7 @@ static void ravb_ring_format(struct net_device *ndev, int q)
 static int ravb_ring_init(struct net_device *ndev, int q)
 {
 	struct ravb_private *priv = netdev_priv(ndev);
+	int num_tx_desc = priv->num_tx_desc;
 	struct sk_buff *skb;
 	int ring_size;
 	int i;
@@ -362,11 +368,13 @@ static int ravb_ring_init(struct net_device *ndev, int q)
 		priv->rx_skb[q][i] = skb;
 	}
 
-	/* Allocate rings for the aligned buffers */
-	priv->tx_align[q] = kmalloc(DPTR_ALIGN * priv->num_tx_ring[q] +
-				    DPTR_ALIGN - 1, GFP_KERNEL);
-	if (!priv->tx_align[q])
-		goto error;
+	if (num_tx_desc > 1) {
+		/* Allocate rings for the aligned buffers */
+		priv->tx_align[q] = kmalloc(DPTR_ALIGN * priv->num_tx_ring[q] +
+					    DPTR_ALIGN - 1, GFP_KERNEL);
+		if (!priv->tx_align[q])
+			goto error;
+	}
 
 	/* Allocate all RX descriptors. */
 	ring_size = sizeof(struct ravb_ex_rx_desc) * (priv->num_rx_ring[q] + 1);
@@ -380,7 +388,7 @@ static int ravb_ring_init(struct net_device *ndev, int q)
 
 	/* Allocate all TX descriptors. */
 	ring_size = sizeof(struct ravb_tx_desc) *
-		    (priv->num_tx_ring[q] * NUM_TX_DESC + 1);
+		    (priv->num_tx_ring[q] * num_tx_desc + 1);
 	priv->tx_ring[q] = dma_alloc_coherent(ndev->dev.parent, ring_size,
 					      &priv->tx_desc_dma[q],
 					      GFP_KERNEL);
@@ -1487,6 +1495,7 @@ static void ravb_tx_timeout_work(struct work_struct *work)
 static netdev_tx_t ravb_start_xmit(struct sk_buff *skb, struct net_device *ndev)
 {
 	struct ravb_private *priv = netdev_priv(ndev);
+	int num_tx_desc = priv->num_tx_desc;
 	u16 q = skb_get_queue_mapping(skb);
 	struct ravb_tstamp_skb *ts_skb;
 	struct ravb_tx_desc *desc;
@@ -1498,7 +1507,7 @@ static netdev_tx_t ravb_start_xmit(struct sk_buff *skb, struct net_device *ndev)
 
 	spin_lock_irqsave(&priv->lock, flags);
 	if (priv->cur_tx[q] - priv->dirty_tx[q] > (priv->num_tx_ring[q] - 1) *
-	    NUM_TX_DESC) {
+	    num_tx_desc) {
 		netif_err(priv, tx_queued, ndev,
 			  "still transmitting with the full ring!\n");
 		netif_stop_subqueue(ndev, q);
@@ -1509,41 +1518,55 @@ static netdev_tx_t ravb_start_xmit(struct sk_buff *skb, struct net_device *ndev)
 	if (skb_put_padto(skb, ETH_ZLEN))
 		goto exit;
 
-	entry = priv->cur_tx[q] % (priv->num_tx_ring[q] * NUM_TX_DESC);
-	priv->tx_skb[q][entry / NUM_TX_DESC] = skb;
-
-	buffer = PTR_ALIGN(priv->tx_align[q], DPTR_ALIGN) +
-		 entry / NUM_TX_DESC * DPTR_ALIGN;
-	len = PTR_ALIGN(skb->data, DPTR_ALIGN) - skb->data;
-	/* Zero length DMA descriptors are problematic as they seem to
-	 * terminate DMA transfers. Avoid them by simply using a length of
-	 * DPTR_ALIGN (4) when skb data is aligned to DPTR_ALIGN.
-	 *
-	 * As skb is guaranteed to have at least ETH_ZLEN (60) bytes of
-	 * data by the call to skb_put_padto() above this is safe with
-	 * respect to both the length of the first DMA descriptor (len)
-	 * overflowing the available data and the length of the second DMA
-	 * descriptor (skb->len - len) being negative.
-	 */
-	if (len == 0)
-		len = DPTR_ALIGN;
+	entry = priv->cur_tx[q] % (priv->num_tx_ring[q] * num_tx_desc);
+	priv->tx_skb[q][entry / num_tx_desc] = skb;
+
+	if (num_tx_desc > 1) {
+		buffer = PTR_ALIGN(priv->tx_align[q], DPTR_ALIGN) +
+			 entry / num_tx_desc * DPTR_ALIGN;
+		len = PTR_ALIGN(skb->data, DPTR_ALIGN) - skb->data;
+
+		/* Zero length DMA descriptors are problematic as they seem
+		 * to terminate DMA transfers. Avoid them by simply using a
+		 * length of DPTR_ALIGN (4) when skb data is aligned to
+		 * DPTR_ALIGN.
+		 *
+		 * As skb is guaranteed to have at least ETH_ZLEN (60)
+		 * bytes of data by the call to skb_put_padto() above this
+		 * is safe with respect to both the length of the first DMA
+		 * descriptor (len) overflowing the available data and the
+		 * length of the second DMA descriptor (skb->len - len)
+		 * being negative.
+		 */
+		if (len == 0)
+			len = DPTR_ALIGN;
 
-	memcpy(buffer, skb->data, len);
-	dma_addr = dma_map_single(ndev->dev.parent, buffer, len, DMA_TO_DEVICE);
-	if (dma_mapping_error(ndev->dev.parent, dma_addr))
-		goto drop;
+		memcpy(buffer, skb->data, len);
+		dma_addr = dma_map_single(ndev->dev.parent, buffer, len,
+					  DMA_TO_DEVICE);
+		if (dma_mapping_error(ndev->dev.parent, dma_addr))
+			goto drop;
 
-	desc = &priv->tx_ring[q][entry];
-	desc->ds_tagl = cpu_to_le16(len);
-	desc->dptr = cpu_to_le32(dma_addr);
+		desc = &priv->tx_ring[q][entry];
+		desc->ds_tagl = cpu_to_le16(len);
+		desc->dptr = cpu_to_le32(dma_addr);
 
-	buffer = skb->data + len;
-	len = skb->len - len;
-	dma_addr = dma_map_single(ndev->dev.parent, buffer, len, DMA_TO_DEVICE);
-	if (dma_mapping_error(ndev->dev.parent, dma_addr))
-		goto unmap;
+		buffer = skb->data + len;
+		len = skb->len - len;
+		dma_addr = dma_map_single(ndev->dev.parent, buffer, len,
+					  DMA_TO_DEVICE);
+		if (dma_mapping_error(ndev->dev.parent, dma_addr))
+			goto unmap;
 
-	desc++;
+		desc++;
+	} else {
+		desc = &priv->tx_ring[q][entry];
+		len = skb->len;
+		dma_addr = dma_map_single(ndev->dev.parent, skb->data, skb->len,
+					  DMA_TO_DEVICE);
+		if (dma_mapping_error(ndev->dev.parent, dma_addr))
+			goto drop;
+	}
 	desc->ds_tagl = cpu_to_le16(len);
 	desc->dptr = cpu_to_le32(dma_addr);
 
@@ -1551,9 +1574,11 @@ static netdev_tx_t ravb_start_xmit(struct sk_buff *skb, struct net_device *ndev)
 	if (q == RAVB_NC) {
 		ts_skb = kmalloc(sizeof(*ts_skb), GFP_ATOMIC);
 		if (!ts_skb) {
-			desc--;
-			dma_unmap_single(ndev->dev.parent, dma_addr, len,
-					 DMA_TO_DEVICE);
+			if (num_tx_desc > 1) {
+				desc--;
+				dma_unmap_single(ndev->dev.parent, dma_addr,
+						 len, DMA_TO_DEVICE);
+			}
 			goto unmap;
 		}
 		ts_skb->skb = skb;
@@ -1570,15 +1595,18 @@ static netdev_tx_t ravb_start_xmit(struct sk_buff *skb, struct net_device *ndev)
 	skb_tx_timestamp(skb);
 	/* Descriptor type must be set after all the above writes */
 	dma_wmb();
-	desc->die_dt = DT_FEND;
-	desc--;
-	desc->die_dt = DT_FSTART;
-
+	if (num_tx_desc > 1) {
+		desc->die_dt = DT_FEND;
+		desc--;
+		desc->die_dt = DT_FSTART;
+	} else {
+		desc->die_dt = DT_FSINGLE;
+	}
 	ravb_modify(ndev, TCCR, TCCR_TSRQ0 << q, TCCR_TSRQ0 << q);
 
-	priv->cur_tx[q] += NUM_TX_DESC;
+	priv->cur_tx[q] += num_tx_desc;
 	if (priv->cur_tx[q] - priv->dirty_tx[q] >
-	    (priv->num_tx_ring[q] - 1) * NUM_TX_DESC &&
+	    (priv->num_tx_ring[q] - 1) * num_tx_desc &&
 	    !ravb_tx_free(ndev, q, true))
 		netif_stop_subqueue(ndev, q);
 
@@ -1592,7 +1620,7 @@ static netdev_tx_t ravb_start_xmit(struct sk_buff *skb, struct net_device *ndev)
 			 le16_to_cpu(desc->ds_tagl), DMA_TO_DEVICE);
 drop:
 	dev_kfree_skb_any(skb);
-	priv->tx_skb[q][entry / NUM_TX_DESC] = NULL;
+	priv->tx_skb[q][entry / num_tx_desc] = NULL;
 	goto exit;
 }
 
@@ -2078,6 +2106,9 @@ static int ravb_probe(struct platform_device *pdev)
 	ndev->max_mtu = 2048 - (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN);
 	ndev->min_mtu = ETH_MIN_MTU;
 
+	priv->num_tx_desc = chip_id == RCAR_GEN2 ?
+		NUM_TX_DESC_GEN2 : NUM_TX_DESC_GEN3;
+
 	/* Set function */
 	ndev->netdev_ops = &ravb_netdev_ops;
 	ndev->ethtool_ops = &ravb_ethtool_ops;
-- 
2.7.4

[cip-dev] [PATCH 4.19.y-cip v2 27/57] ravb: Avoid unsupported internal delay mode for R-Car E3/D3

[Fabrizio Castro]

From: Simon Horman <horms+renesas@verge.net.au>

commit 0a5d329ffd1be394e3e4176eb11ca51dfde03c40 upstream.

According to the R-Car Gen3 Hardware Manual Rev 1.50 of Nov 30, 2018, the
TX clock internal delay mode isn't supported on R-Car E3 (r8a77990) or D3
(r8a77995). And by extension it is also not supported by RZ/G2E (r9a774c0).

This matches all ES versions of the affected SoCs as it is
not clear if this problem will be resolved in newer chips.
This can be revisited, as necessary.

This patch does not error-out if PHY_INTERFACE_MODE_RGMII_ID or
PHY_INTERFACE_MODE_RGMII_TXID are used on SoCs where TX clock delay
mode is not supported as there is a risk of introducing a regression
when used in conjunction with older DT blobs present in the field.
Rather, a warning is logged in such cases.

Based on work by Kazuya Mizuguchi.

Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Reviewed-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
---
 drivers/net/ethernet/renesas/ravb_main.c | 15 +++++++++++++--
 1 file changed, 13 insertions(+), 2 deletions(-)

diff --git a/drivers/net/ethernet/renesas/ravb_main.c b/drivers/net/ethernet/renesas/ravb_main.c
index 037a0ad..7ed70b7 100644
--- a/drivers/net/ethernet/renesas/ravb_main.c
+++ b/drivers/net/ethernet/renesas/ravb_main.c
@@ -1980,6 +1980,13 @@ static void ravb_set_config_mode(struct net_device *ndev)
 	}
 }
 
+static const struct soc_device_attribute ravb_delay_mode_quirk_match[] = {
+	{ .soc_id = "r8a774c0" },
+	{ .soc_id = "r8a77990" },
+	{ .soc_id = "r8a77995" },
+	{ /* sentinel */ }
+};
+
 /* Set tx and rx clock internal delay modes */
 static void ravb_set_delay_mode(struct net_device *ndev)
 {
@@ -1991,8 +1998,12 @@ static void ravb_set_delay_mode(struct net_device *ndev)
 		set |= APSR_DM_RDM;
 
 	if (priv->phy_interface == PHY_INTERFACE_MODE_RGMII_ID ||
-	    priv->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID)
-		set |= APSR_DM_TDM;
+	    priv->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID) {
+		if (!WARN(soc_device_match(ravb_delay_mode_quirk_match),
+			  "phy-mode %s requires TX clock internal delay mode which is not supported by this hardware revision. Please update device tree",
+			  phy_modes(priv->phy_interface)))
+			set |= APSR_DM_TDM;
+	}
 
 	ravb_modify(ndev, APSR, APSR_DM, set);
 }
-- 
2.7.4

[cip-dev] [PATCH 4.19.y-cip v2 28/57] mmc: renesas_sdhi_internal_dmac: set scatter/gather max segment size

[Fabrizio Castro]

From: Niklas S?derlund <niklas.soderlund+renesas@ragnatech.se>

commit 54541815b43f4e49c82628bf28bbb31d86d2f58a upstream.

Fix warning when running with CONFIG_DMA_API_DEBUG_SG=y by allocating a
device_dma_parameters structure and filling in the max segment size. The
size used is the result of a discussion with Renesas hardware engineers
and unfortunately not found in the datasheet.

  renesas_sdhi_internal_dmac ee140000.sd: DMA-API: mapping sg segment
  longer than device claims to support [len=126976] [max=65536]

Reported-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Niklas S?derlund <niklas.soderlund+renesas@ragnatech.se>
[wsa: simplified some logic after validating intended dma_parms life cycle
      and added comment]
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
---
 drivers/mmc/host/renesas_sdhi_internal_dmac.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/drivers/mmc/host/renesas_sdhi_internal_dmac.c b/drivers/mmc/host/renesas_sdhi_internal_dmac.c
index 0129837..fb7adcb 100644
--- a/drivers/mmc/host/renesas_sdhi_internal_dmac.c
+++ b/drivers/mmc/host/renesas_sdhi_internal_dmac.c
@@ -311,12 +311,20 @@ static const struct soc_device_attribute gen3_soc_whitelist[] = {
 static int renesas_sdhi_internal_dmac_probe(struct platform_device *pdev)
 {
 	const struct soc_device_attribute *soc = soc_device_match(gen3_soc_whitelist);
+	struct device *dev = &pdev->dev;
 
 	if (!soc)
 		return -ENODEV;
 
 	global_flags |= (unsigned long)soc->data;
 
+	dev->dma_parms = devm_kzalloc(dev, sizeof(*dev->dma_parms), GFP_KERNEL);
+	if (!dev->dma_parms)
+		return -ENOMEM;
+
+	/* value is max of SD_SECCNT. Confirmed by HW engineers */
+	dma_set_max_seg_size(dev, 0xffffffff);
+
 	return renesas_sdhi_probe(pdev, &renesas_sdhi_internal_dmac_dma_ops);
 }
 
-- 
2.7.4

[cip-dev] [PATCH 4.19.y-cip v2 29/57] arm64: dts: renesas: Initial r8a774a1 SoC device tree

[Fabrizio Castro]

From: Biju Das <biju.das@bp.renesas.com>

commit 90493b09df41a9c1dd0bf315e81d03b4212384f9 upstream.

Basic support for the RZ/G2M SoC.

Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
---
 arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 190 ++++++++++++++++++++++++++++++
 1 file changed, 190 insertions(+)
 create mode 100644 arch/arm64/boot/dts/renesas/r8a774a1.dtsi

diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
new file mode 100644
index 0000000..8e63e9a
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
@@ -0,0 +1,190 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the r8a774a1 SoC
+ *
+ * Copyright (C) 2018 Renesas Electronics Corp.
+ */
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/renesas-cpg-mssr.h>
+
+/ {
+	compatible = "renesas,r8a774a1";
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	/*
+	 * The external audio clocks are configured as 0 Hz fixed frequency
+	 * clocks by default.
+	 * Boards that provide audio clocks should override them.
+	 */
+	audio_clk_a: audio_clk_a {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <0>;
+	};
+
+	audio_clk_b: audio_clk_b {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <0>;
+	};
+
+	audio_clk_c: audio_clk_c {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <0>;
+	};
+
+	/* External CAN clock - to be overridden by boards that provide it */
+	can_clk: can {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <0>;
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		a57_0: cpu at 0 {
+			compatible = "arm,cortex-a57", "arm,armv8";
+			reg = <0x0>;
+			device_type = "cpu";
+			power-domains = <&sysc 0>;
+			next-level-cache = <&L2_CA57>;
+			enable-method = "psci";
+			clocks =<&cpg CPG_CORE 0>;
+		};
+
+		a57_1: cpu at 1 {
+			compatible = "arm,cortex-a57", "arm,armv8";
+			reg = <0x1>;
+			device_type = "cpu";
+			power-domains = <&sysc 1>;
+			next-level-cache = <&L2_CA57>;
+			enable-method = "psci";
+			clocks =<&cpg CPG_CORE 0>;
+		};
+
+		L2_CA57: cache-controller-0 {
+			compatible = "cache";
+			power-domains = <&sysc 12>;
+			cache-unified;
+			cache-level = <2>;
+		};
+	};
+
+	extal_clk: extal {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		/* This value must be overridden by the board */
+		clock-frequency = <0>;
+	};
+
+	extalr_clk: extalr {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		/* This value must be overridden by the board */
+		clock-frequency = <0>;
+	};
+
+	/* External PCIe clock - can be overridden by the board */
+	pcie_bus_clk: pcie_bus {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <0>;
+	};
+
+	pmu_a57 {
+		compatible = "arm,cortex-a57-pmu";
+		interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
+				      <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-affinity = <&a57_0>, <&a57_1>;
+	};
+
+	psci {
+		compatible = "arm,psci-1.0", "arm,psci-0.2";
+		method = "smc";
+	};
+
+	/* External SCIF clock - to be overridden by boards that provide it */
+	scif_clk: scif {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <0>;
+	};
+
+	soc {
+		compatible = "simple-bus";
+		interrupt-parent = <&gic>;
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		cpg: clock-controller at e6150000 {
+			compatible = "renesas,r8a774a1-cpg-mssr";
+			reg = <0 0xe6150000 0 0x0bb0>;
+			clocks = <&extal_clk>, <&extalr_clk>;
+			clock-names = "extal", "extalr";
+			#clock-cells = <2>;
+			#power-domain-cells = <0>;
+			#reset-cells = <1>;
+		};
+
+		rst: reset-controller at e6160000 {
+			compatible = "renesas,r8a774a1-rst";
+			reg = <0 0xe6160000 0 0x018c>;
+		};
+
+		sysc: system-controller at e6180000 {
+			compatible = "renesas,r8a774a1-sysc";
+			reg = <0 0xe6180000 0 0x0400>;
+			#power-domain-cells = <1>;
+		};
+
+		gic: interrupt-controller at f1010000 {
+			compatible = "arm,gic-400";
+			#interrupt-cells = <3>;
+			#address-cells = <0>;
+			interrupt-controller;
+			reg = <0x0 0xf1010000 0 0x1000>,
+			      <0x0 0xf1020000 0 0x20000>,
+			      <0x0 0xf1040000 0 0x20000>,
+			      <0x0 0xf1060000 0 0x20000>;
+			interrupts = <GIC_PPI 9
+					(GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
+			clocks = <&cpg CPG_MOD 408>;
+			clock-names = "clk";
+			power-domains = <&sysc 32>;
+			resets = <&cpg 408>;
+		};
+
+		prr: chipid at fff00044 {
+			compatible = "renesas,prr";
+			reg = <0 0xfff00044 0 4>;
+		};
+	};
+
+	timer {
+		compatible = "arm,armv8-timer";
+		interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+				      <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+				      <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+				      <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
+	};
+
+	/* External USB clocks - can be overridden by the board */
+	usb3s0_clk: usb3s0 {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <0>;
+	};
+
+	usb_extal_clk: usb_extal {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <0>;
+	};
+};
-- 
2.7.4

[cip-dev] [PATCH 4.19.y-cip v2 30/57] arm64: dts: renesas: r8a774a1: Add SYS-DMAC controller nodes

[Fabrizio Castro]

From: Biju Das <biju.das@bp.renesas.com>

commit 37a61e4d9f9486bfccd699bb1d52ebbea0019ac4 upstream.

Add sys-dmac[0-2] device nodes for RZ/G2M (r8a774a1) SoC.

Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
---
 arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 102 ++++++++++++++++++++++++++++++
 1 file changed, 102 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
index 8e63e9a..4a4cf35 100644
--- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
@@ -144,6 +144,108 @@
 			#power-domain-cells = <1>;
 		};
 
+		dmac0: dma-controller at e6700000 {
+			compatible = "renesas,dmac-r8a774a1",
+				     "renesas,rcar-dmac";
+			reg = <0 0xe6700000 0 0x10000>;
+			interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH
+				      GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
+				      GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
+				      GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
+				      GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
+				      GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
+				      GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
+				      GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
+				      GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
+				      GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
+				      GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
+				      GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
+				      GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
+				      GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
+				      GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
+				      GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH
+				      GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "error",
+					"ch0", "ch1", "ch2", "ch3",
+					"ch4", "ch5", "ch6", "ch7",
+					"ch8", "ch9", "ch10", "ch11",
+					"ch12", "ch13", "ch14", "ch15";
+			clocks = <&cpg CPG_MOD 219>;
+			clock-names = "fck";
+			power-domains = <&sysc 32>;
+			resets = <&cpg 219>;
+			#dma-cells = <1>;
+			dma-channels = <16>;
+		};
+
+		dmac1: dma-controller at e7300000 {
+			compatible = "renesas,dmac-r8a774a1",
+				     "renesas,rcar-dmac";
+			reg = <0 0xe7300000 0 0x10000>;
+			interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
+				      GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
+				      GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
+				      GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
+				      GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
+				      GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
+				      GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
+				      GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
+				      GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
+				      GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
+				      GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
+				      GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
+				      GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
+				      GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
+				      GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
+				      GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH
+				      GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "error",
+					"ch0", "ch1", "ch2", "ch3",
+					"ch4", "ch5", "ch6", "ch7",
+					"ch8", "ch9", "ch10", "ch11",
+					"ch12", "ch13", "ch14", "ch15";
+			clocks = <&cpg CPG_MOD 218>;
+			clock-names = "fck";
+			power-domains = <&sysc 32>;
+			resets = <&cpg 218>;
+			#dma-cells = <1>;
+			dma-channels = <16>;
+		};
+
+		dmac2: dma-controller at e7310000 {
+			compatible = "renesas,dmac-r8a774a1",
+				     "renesas,rcar-dmac";
+			reg = <0 0xe7310000 0 0x10000>;
+			interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH
+				      GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH
+				      GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH
+				      GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH
+				      GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH
+				      GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH
+				      GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH
+				      GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH
+				      GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH
+				      GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH
+				      GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH
+				      GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH
+				      GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH
+				      GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH
+				      GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH
+				      GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH
+				      GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "error",
+					"ch0", "ch1", "ch2", "ch3",
+					"ch4", "ch5", "ch6", "ch7",
+					"ch8", "ch9", "ch10", "ch11",
+					"ch12", "ch13", "ch14", "ch15";
+			clocks = <&cpg CPG_MOD 217>;
+			clock-names = "fck";
+			power-domains = <&sysc 32>;
+			resets = <&cpg 217>;
+			#dma-cells = <1>;
+			dma-channels = <16>;
+		};
+
 		gic: interrupt-controller at f1010000 {
 			compatible = "arm,gic-400";
 			#interrupt-cells = <3>;
-- 
2.7.4

[cip-dev] [PATCH 4.19.y-cip v2 31/57] arm64: dts: renesas: r8a774a1: Add SCIF and HSCIF nodes

[Fabrizio Castro]

commit 3a3933a4fa36430a46fa7a6f9bfa7eaa19dd9dfe upstream.

Add the device nodes for all RZ/G2M SCIF and HSCIF serial ports,
incl. clocks, power domains and DMAs.
According to the HW user manual, SCIF[015] and HSCIF[012] are
connected to both SYS-DMAC1 and SYS-DMAC2, while SCIF[34] and
HSCIF[34] are connected to SYS-DMAC0.

Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Biju Das <biju.das@bp.renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 185 ++++++++++++++++++++++++++++++
 1 file changed, 185 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
index 4a4cf35..81fba7f 100644
--- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
@@ -144,6 +144,94 @@
 			#power-domain-cells = <1>;
 		};
 
+		hscif0: serial at e6540000 {
+			compatible = "renesas,hscif-r8a774a1",
+				     "renesas,rcar-gen3-hscif",
+				     "renesas,hscif";
+			reg = <0 0xe6540000 0 0x60>;
+			interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 520>,
+				 <&cpg CPG_CORE 19>,
+				 <&scif_clk>;
+			clock-names = "fck", "brg_int", "scif_clk";
+			dmas = <&dmac1 0x31>, <&dmac1 0x30>,
+			       <&dmac2 0x31>, <&dmac2 0x30>;
+			dma-names = "tx", "rx", "tx", "rx";
+			power-domains = <&sysc 32>;
+			resets = <&cpg 520>;
+			status = "disabled";
+		};
+
+		hscif1: serial at e6550000 {
+			compatible = "renesas,hscif-r8a774a1",
+				     "renesas,rcar-gen3-hscif",
+				     "renesas,hscif";
+			reg = <0 0xe6550000 0 0x60>;
+			interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 519>,
+				 <&cpg CPG_CORE 19>,
+				 <&scif_clk>;
+			clock-names = "fck", "brg_int", "scif_clk";
+			dmas = <&dmac1 0x33>, <&dmac1 0x32>,
+			       <&dmac2 0x33>, <&dmac2 0x32>;
+			dma-names = "tx", "rx", "tx", "rx";
+			power-domains = <&sysc 32>;
+			resets = <&cpg 519>;
+			status = "disabled";
+		};
+
+		hscif2: serial at e6560000 {
+			compatible = "renesas,hscif-r8a774a1",
+				     "renesas,rcar-gen3-hscif",
+				     "renesas,hscif";
+			reg = <0 0xe6560000 0 0x60>;
+			interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 518>,
+				 <&cpg CPG_CORE 19>,
+				 <&scif_clk>;
+			clock-names = "fck", "brg_int", "scif_clk";
+			dmas = <&dmac1 0x35>, <&dmac1 0x34>,
+			       <&dmac2 0x35>, <&dmac2 0x34>;
+			dma-names = "tx", "rx", "tx", "rx";
+			power-domains = <&sysc 32>;
+			resets = <&cpg 518>;
+			status = "disabled";
+		};
+
+		hscif3: serial at e66a0000 {
+			compatible = "renesas,hscif-r8a774a1",
+				     "renesas,rcar-gen3-hscif",
+				     "renesas,hscif";
+			reg = <0 0xe66a0000 0 0x60>;
+			interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 517>,
+				 <&cpg CPG_CORE 19>,
+				 <&scif_clk>;
+			clock-names = "fck", "brg_int", "scif_clk";
+			dmas = <&dmac0 0x37>, <&dmac0 0x36>;
+			dma-names = "tx", "rx";
+			power-domains = <&sysc 32>;
+			resets = <&cpg 517>;
+			status = "disabled";
+		};
+
+		hscif4: serial at e66b0000 {
+			compatible = "renesas,hscif-r8a774a1",
+				     "renesas,rcar-gen3-hscif",
+				     "renesas,hscif";
+			reg = <0 0xe66b0000 0 0x60>;
+			interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 516>,
+				 <&cpg CPG_CORE 19>,
+				 <&scif_clk>;
+			clock-names = "fck", "brg_int", "scif_clk";
+			dmas = <&dmac0 0x39>, <&dmac0 0x38>;
+			dma-names = "tx", "rx";
+			power-domains = <&sysc 32>;
+			resets = <&cpg 516>;
+			status = "disabled";
+		};
+
 		dmac0: dma-controller at e6700000 {
 			compatible = "renesas,dmac-r8a774a1",
 				     "renesas,rcar-dmac";
@@ -246,6 +334,103 @@
 			dma-channels = <16>;
 		};
 
+		scif0: serial at e6e60000 {
+			compatible = "renesas,scif-r8a774a1",
+				     "renesas,rcar-gen3-scif", "renesas,scif";
+			reg = <0 0xe6e60000 0 0x40>;
+			interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 207>,
+				 <&cpg CPG_CORE 19>,
+				 <&scif_clk>;
+			clock-names = "fck", "brg_int", "scif_clk";
+			dmas = <&dmac1 0x51>, <&dmac1 0x50>,
+			       <&dmac2 0x51>, <&dmac2 0x50>;
+			dma-names = "tx", "rx", "tx", "rx";
+			power-domains = <&sysc 32>;
+			resets = <&cpg 207>;
+			status = "disabled";
+		};
+
+		scif1: serial at e6e68000 {
+			compatible = "renesas,scif-r8a774a1",
+				     "renesas,rcar-gen3-scif", "renesas,scif";
+			reg = <0 0xe6e68000 0 0x40>;
+			interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 206>,
+				 <&cpg CPG_CORE 19>,
+				 <&scif_clk>;
+			clock-names = "fck", "brg_int", "scif_clk";
+			dmas = <&dmac1 0x53>, <&dmac1 0x52>,
+			       <&dmac2 0x53>, <&dmac2 0x52>;
+			dma-names = "tx", "rx", "tx", "rx";
+			power-domains = <&sysc 32>;
+			resets = <&cpg 206>;
+			status = "disabled";
+		};
+
+		scif2: serial at e6e88000 {
+			compatible = "renesas,scif-r8a774a1",
+				     "renesas,rcar-gen3-scif", "renesas,scif";
+			reg = <0 0xe6e88000 0 0x40>;
+			interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 310>,
+				 <&cpg CPG_CORE 19>,
+				 <&scif_clk>;
+			clock-names = "fck", "brg_int", "scif_clk";
+			power-domains = <&sysc 32>;
+			resets = <&cpg 310>;
+			status = "disabled";
+		};
+
+		scif3: serial at e6c50000 {
+			compatible = "renesas,scif-r8a774a1",
+				     "renesas,rcar-gen3-scif", "renesas,scif";
+			reg = <0 0xe6c50000 0 0x40>;
+			interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 204>,
+				 <&cpg CPG_CORE 19>,
+				 <&scif_clk>;
+			clock-names = "fck", "brg_int", "scif_clk";
+			dmas = <&dmac0 0x57>, <&dmac0 0x56>;
+			dma-names = "tx", "rx";
+			power-domains = <&sysc 32>;
+			resets = <&cpg 204>;
+			status = "disabled";
+		};
+
+		scif4: serial at e6c40000 {
+			compatible = "renesas,scif-r8a774a1",
+				     "renesas,rcar-gen3-scif", "renesas,scif";
+			reg = <0 0xe6c40000 0 0x40>;
+			interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 203>,
+				 <&cpg CPG_CORE 19>,
+				 <&scif_clk>;
+			clock-names = "fck", "brg_int", "scif_clk";
+			dmas = <&dmac0 0x59>, <&dmac0 0x58>;
+			dma-names = "tx", "rx";
+			power-domains = <&sysc 32>;
+			resets = <&cpg 203>;
+			status = "disabled";
+		};
+
+		scif5: serial at e6f30000 {
+			compatible = "renesas,scif-r8a774a1",
+				     "renesas,rcar-gen3-scif", "renesas,scif";
+			reg = <0 0xe6f30000 0 0x40>;
+			interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 202>,
+				 <&cpg CPG_CORE 19>,
+				 <&scif_clk>;
+			clock-names = "fck", "brg_int", "scif_clk";
+			dmas = <&dmac1 0x5b>, <&dmac1 0x5a>,
+			       <&dmac2 0x5b>, <&dmac2 0x5a>;
+			dma-names = "tx", "rx", "tx", "rx";
+			power-domains = <&sysc 32>;
+			resets = <&cpg 202>;
+			status = "disabled";
+		};
+
 		gic: interrupt-controller at f1010000 {
 			compatible = "arm,gic-400";
 			#interrupt-cells = <3>;
-- 
2.7.4

[cip-dev] [PATCH 4.19.y-cip v2 32/57] arm64: dts: renesas: r8a774a1: Add INTC-EX device node

[Fabrizio Castro]

From: Biju Das <biju.das@bp.renesas.com>

commit a21c572ce8bc7466816ea8601d7eb0b4ca12d40c upstream.

Add support for the Interrupt Controller for External Devices
(INTC-EX) on RZ/G2M.

Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
---
 arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
index 81fba7f..15d7785 100644
--- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
@@ -144,6 +144,22 @@
 			#power-domain-cells = <1>;
 		};
 
+		intc_ex: interrupt-controller at e61c0000 {
+			compatible = "renesas,intc-ex-r8a774a1", "renesas,irqc";
+			#interrupt-cells = <2>;
+			interrupt-controller;
+			reg = <0 0xe61c0000 0 0x200>;
+			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH
+				      GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH
+				      GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH
+				      GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH
+				      GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH
+				      GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 407>;
+			power-domains = <&sysc 32>;
+			resets = <&cpg 407>;
+		};
+
 		hscif0: serial at e6540000 {
 			compatible = "renesas,hscif-r8a774a1",
 				     "renesas,rcar-gen3-hscif",
-- 
2.7.4

[cip-dev] [PATCH 4.19.y-cip v2 33/57] arm64: dts: renesas: r8a774a1: Add Ethernet AVB node

[Fabrizio Castro]

commit 71bddde2a2dfcba2c2caad35d6933345960907e5 upstream.

This patch adds the SoC specific part of the Ethernet AVB
device tree node.

Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Biju Das <biju.das@bp.renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 45 +++++++++++++++++++++++++++++++
 1 file changed, 45 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
index 15d7785..b771211 100644
--- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
@@ -350,6 +350,51 @@
 			dma-channels = <16>;
 		};
 
+		avb: ethernet at e6800000 {
+			compatible = "renesas,etheravb-r8a774a1",
+				     "renesas,etheravb-rcar-gen3";
+			reg = <0 0xe6800000 0 0x800>;
+			interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "ch0", "ch1", "ch2", "ch3",
+					  "ch4", "ch5", "ch6", "ch7",
+					  "ch8", "ch9", "ch10", "ch11",
+					  "ch12", "ch13", "ch14", "ch15",
+					  "ch16", "ch17", "ch18", "ch19",
+					  "ch20", "ch21", "ch22", "ch23",
+					  "ch24";
+			clocks = <&cpg CPG_MOD 812>;
+			power-domains = <&sysc 32>;
+			resets = <&cpg 812>;
+			phy-mode = "rgmii";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
 		scif0: serial at e6e60000 {
 			compatible = "renesas,scif-r8a774a1",
 				     "renesas,rcar-gen3-scif", "renesas,scif";
-- 
2.7.4

[cip-dev] [PATCH 4.19.y-cip v2 34/57] arm64: dts: renesas: r8a774a1: Add RWDT node

[Fabrizio Castro]

From: Biju Das <biju.das@bp.renesas.com>

commit 426f0b95af0dfe4f33db6c5ef0a64b1ddcd27053 upstream.

Add a device node for the Watchdog Timer (RWDT) controller on the Renesas
RZ/G2M (r8a774a1) SoC.

Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
---
 arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
index b771211..b9a3818 100644
--- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
@@ -123,6 +123,16 @@
 		#size-cells = <2>;
 		ranges;
 
+		rwdt: watchdog at e6020000 {
+			compatible = "renesas,r8a774a1-wdt",
+				     "renesas,rcar-gen3-wdt";
+			reg = <0 0xe6020000 0 0x0c>;
+			clocks = <&cpg CPG_MOD 402>;
+			power-domains = <&sysc 32>;
+			resets = <&cpg 402>;
+			status = "disabled";
+		};
+
 		cpg: clock-controller at e6150000 {
 			compatible = "renesas,r8a774a1-cpg-mssr";
 			reg = <0 0xe6150000 0 0x0bb0>;
-- 
2.7.4

[cip-dev] [PATCH 4.19.y-cip v2 35/57] arm64: dts: renesas: r8a774a1: Add pinctrl device node

[Fabrizio Castro]

commit 3698dbd02c93545f08dd309d159ef20956e07355 upstream.

This patch adds pinctrl device node for R8A774A1 SoC.

Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Biju Das <biju.das@bp.renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
index b9a3818..c956bf7 100644
--- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
@@ -133,6 +133,11 @@
 			status = "disabled";
 		};
 
+		pfc: pin-controller at e6060000 {
+			compatible = "renesas,pfc-r8a774a1";
+			reg = <0 0xe6060000 0 0x50c>;
+		};
+
 		cpg: clock-controller at e6150000 {
 			compatible = "renesas,r8a774a1-cpg-mssr";
 			reg = <0 0xe6150000 0 0x0bb0>;
-- 
2.7.4

[cip-dev] [PATCH 4.19.y-cip v2 36/57] arm64: dts: renesas: r8a774a1: Add GPIO device nodes

[Fabrizio Castro]

commit 53ae5809d306bca13b2d444871374515e08c7dff upstream.

Add GPIO device nodes to the DT of the r8a774a1 SoC.

Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Biju Das <biju.das@bp.renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 120 ++++++++++++++++++++++++++++++
 1 file changed, 120 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
index c956bf7..4c251c4 100644
--- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
@@ -133,6 +133,126 @@
 			status = "disabled";
 		};
 
+		gpio0: gpio at e6050000 {
+			compatible = "renesas,gpio-r8a774a1",
+				     "renesas,rcar-gen3-gpio";
+			reg = <0 0xe6050000 0 0x50>;
+			interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+			#gpio-cells = <2>;
+			gpio-controller;
+			gpio-ranges = <&pfc 0 0 16>;
+			#interrupt-cells = <2>;
+			interrupt-controller;
+			clocks = <&cpg CPG_MOD 912>;
+			power-domains = <&sysc 32>;
+			resets = <&cpg 912>;
+		};
+
+		gpio1: gpio at e6051000 {
+			compatible = "renesas,gpio-r8a774a1",
+				     "renesas,rcar-gen3-gpio";
+			reg = <0 0xe6051000 0 0x50>;
+			interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+			#gpio-cells = <2>;
+			gpio-controller;
+			gpio-ranges = <&pfc 0 32 29>;
+			#interrupt-cells = <2>;
+			interrupt-controller;
+			clocks = <&cpg CPG_MOD 911>;
+			power-domains = <&sysc 32>;
+			resets = <&cpg 911>;
+		};
+
+		gpio2: gpio at e6052000 {
+			compatible = "renesas,gpio-r8a774a1",
+				     "renesas,rcar-gen3-gpio";
+			reg = <0 0xe6052000 0 0x50>;
+			interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+			#gpio-cells = <2>;
+			gpio-controller;
+			gpio-ranges = <&pfc 0 64 15>;
+			#interrupt-cells = <2>;
+			interrupt-controller;
+			clocks = <&cpg CPG_MOD 910>;
+			power-domains = <&sysc 32>;
+			resets = <&cpg 910>;
+		};
+
+		gpio3: gpio at e6053000 {
+			compatible = "renesas,gpio-r8a774a1",
+				     "renesas,rcar-gen3-gpio";
+			reg = <0 0xe6053000 0 0x50>;
+			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+			#gpio-cells = <2>;
+			gpio-controller;
+			gpio-ranges = <&pfc 0 96 16>;
+			#interrupt-cells = <2>;
+			interrupt-controller;
+			clocks = <&cpg CPG_MOD 909>;
+			power-domains = <&sysc 32>;
+			resets = <&cpg 909>;
+		};
+
+		gpio4: gpio at e6054000 {
+			compatible = "renesas,gpio-r8a774a1",
+				     "renesas,rcar-gen3-gpio";
+			reg = <0 0xe6054000 0 0x50>;
+			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+			#gpio-cells = <2>;
+			gpio-controller;
+			gpio-ranges = <&pfc 0 128 18>;
+			#interrupt-cells = <2>;
+			interrupt-controller;
+			clocks = <&cpg CPG_MOD 908>;
+			power-domains = <&sysc 32>;
+			resets = <&cpg 908>;
+		};
+
+		gpio5: gpio at e6055000 {
+			compatible = "renesas,gpio-r8a774a1",
+				     "renesas,rcar-gen3-gpio";
+			reg = <0 0xe6055000 0 0x50>;
+			interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+			#gpio-cells = <2>;
+			gpio-controller;
+			gpio-ranges = <&pfc 0 160 26>;
+			#interrupt-cells = <2>;
+			interrupt-controller;
+			clocks = <&cpg CPG_MOD 907>;
+			power-domains = <&sysc 32>;
+			resets = <&cpg 907>;
+		};
+
+		gpio6: gpio at e6055400 {
+			compatible = "renesas,gpio-r8a774a1",
+				     "renesas,rcar-gen3-gpio";
+			reg = <0 0xe6055400 0 0x50>;
+			interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+			#gpio-cells = <2>;
+			gpio-controller;
+			gpio-ranges = <&pfc 0 192 32>;
+			#interrupt-cells = <2>;
+			interrupt-controller;
+			clocks = <&cpg CPG_MOD 906>;
+			power-domains = <&sysc 32>;
+			resets = <&cpg 906>;
+		};
+
+		gpio7: gpio at e6055800 {
+			compatible = "renesas,gpio-r8a774a1",
+				     "renesas,rcar-gen3-gpio";
+			reg = <0 0xe6055800 0 0x50>;
+			interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+			#gpio-cells = <2>;
+			gpio-controller;
+			gpio-ranges = <&pfc 0 224 4>;
+			#interrupt-cells = <2>;
+			interrupt-controller;
+			clocks = <&cpg CPG_MOD 905>;
+			power-domains = <&sysc 32>;
+			resets = <&cpg 905>;
+		};
+
 		pfc: pin-controller at e6060000 {
 			compatible = "renesas,pfc-r8a774a1";
 			reg = <0 0xe6060000 0 0x50c>;
-- 
2.7.4

[cip-dev] [PATCH 4.19.y-cip v2 37/57] arm64: dts: renesas: r8a774a1: Add SDHI nodes

[Fabrizio Castro]

commit 663386c3e1aa2771e237acd4b412b17ece19af01 upstream.

Add SDHI nodes to the DT of the r8a774a1 SoC.

Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Biju Das <biju.das@bp.renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 48 +++++++++++++++++++++++++++++++
 1 file changed, 48 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
index 4c251c4..51ac94f 100644
--- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
@@ -627,6 +627,54 @@
 			status = "disabled";
 		};
 
+		sdhi0: sd at ee100000 {
+			compatible = "renesas,sdhi-r8a774a1",
+				     "renesas,rcar-gen3-sdhi";
+			reg = <0 0xee100000 0 0x2000>;
+			interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 314>;
+			max-frequency = <200000000>;
+			power-domains = <&sysc 32>;
+			resets = <&cpg 314>;
+			status = "disabled";
+		};
+
+		sdhi1: sd at ee120000 {
+			compatible = "renesas,sdhi-r8a774a1",
+				     "renesas,rcar-gen3-sdhi";
+			reg = <0 0xee120000 0 0x2000>;
+			interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 313>;
+			max-frequency = <200000000>;
+			power-domains = <&sysc 32>;
+			resets = <&cpg 313>;
+			status = "disabled";
+		};
+
+		sdhi2: sd at ee140000 {
+			compatible = "renesas,sdhi-r8a774a1",
+				     "renesas,rcar-gen3-sdhi";
+			reg = <0 0xee140000 0 0x2000>;
+			interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 312>;
+			max-frequency = <200000000>;
+			power-domains = <&sysc 32>;
+			resets = <&cpg 312>;
+			status = "disabled";
+		};
+
+		sdhi3: sd at ee160000 {
+			compatible = "renesas,sdhi-r8a774a1",
+				     "renesas,rcar-gen3-sdhi";
+			reg = <0 0xee160000 0 0x2000>;
+			interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 311>;
+			max-frequency = <200000000>;
+			power-domains = <&sysc 32>;
+			resets = <&cpg 311>;
+			status = "disabled";
+		};
+
 		gic: interrupt-controller at f1010000 {
 			compatible = "arm,gic-400";
 			#interrupt-cells = <3>;
-- 
2.7.4

[cip-dev] [PATCH 4.19.y-cip v2 38/57] arm64: dts: renesas: r8a774a1: Add I2C and IIC-DVFS support

[Fabrizio Castro]

From: Biju Das <biju.das@bp.renesas.com>

commit c674e8a78c6cda14ab83c8d4342e96893c465cb3 upstream.

Add the I2C[0-6] and IIC Bus Interface for DVFS (IIC for DVFS)
devices nodes to the r8a774a1 device tree.

Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
---
 arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 142 ++++++++++++++++++++++++++++++
 1 file changed, 142 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
index 51ac94f..ced2546 100644
--- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
@@ -14,6 +14,17 @@
 	#address-cells = <2>;
 	#size-cells = <2>;
 
+	aliases {
+		i2c0 = &i2c0;
+		i2c1 = &i2c1;
+		i2c2 = &i2c2;
+		i2c3 = &i2c3;
+		i2c4 = &i2c4;
+		i2c5 = &i2c5;
+		i2c6 = &i2c6;
+		i2c7 = &i2c_dvfs;
+	};
+
 	/*
 	 * The external audio clocks are configured as 0 Hz fixed frequency
 	 * clocks by default.
@@ -295,6 +306,137 @@
 			resets = <&cpg 407>;
 		};
 
+		i2c0: i2c at e6500000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "renesas,i2c-r8a774a1",
+				     "renesas,rcar-gen3-i2c";
+			reg = <0 0xe6500000 0 0x40>;
+			interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 931>;
+			power-domains = <&sysc 32>;
+			resets = <&cpg 931>;
+			dmas = <&dmac1 0x91>, <&dmac1 0x90>,
+			       <&dmac2 0x91>, <&dmac2 0x90>;
+			dma-names = "tx", "rx", "tx", "rx";
+			i2c-scl-internal-delay-ns = <110>;
+			status = "disabled";
+		};
+
+		i2c1: i2c at e6508000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "renesas,i2c-r8a774a1",
+				     "renesas,rcar-gen3-i2c";
+			reg = <0 0xe6508000 0 0x40>;
+			interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 930>;
+			power-domains = <&sysc 32>;
+			resets = <&cpg 930>;
+			dmas = <&dmac1 0x93>, <&dmac1 0x92>,
+			       <&dmac2 0x93>, <&dmac2 0x92>;
+			dma-names = "tx", "rx", "tx", "rx";
+			i2c-scl-internal-delay-ns = <6>;
+			status = "disabled";
+		};
+
+		i2c2: i2c at e6510000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "renesas,i2c-r8a774a1",
+				     "renesas,rcar-gen3-i2c";
+			reg = <0 0xe6510000 0 0x40>;
+			interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 929>;
+			power-domains = <&sysc 32>;
+			resets = <&cpg 929>;
+			dmas = <&dmac1 0x95>, <&dmac1 0x94>,
+			       <&dmac2 0x95>, <&dmac2 0x94>;
+			dma-names = "tx", "rx", "tx", "rx";
+			i2c-scl-internal-delay-ns = <6>;
+			status = "disabled";
+		};
+
+		i2c3: i2c at e66d0000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "renesas,i2c-r8a774a1",
+				     "renesas,rcar-gen3-i2c";
+			reg = <0 0xe66d0000 0 0x40>;
+			interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 928>;
+			power-domains = <&sysc 32>;
+			resets = <&cpg 928>;
+			dmas = <&dmac0 0x97>, <&dmac0 0x96>;
+			dma-names = "tx", "rx";
+			i2c-scl-internal-delay-ns = <110>;
+			status = "disabled";
+		};
+
+		i2c4: i2c at e66d8000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "renesas,i2c-r8a774a1",
+				     "renesas,rcar-gen3-i2c";
+			reg = <0 0xe66d8000 0 0x40>;
+			interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 927>;
+			power-domains = <&sysc 32>;
+			resets = <&cpg 927>;
+			dmas = <&dmac0 0x99>, <&dmac0 0x98>;
+			dma-names = "tx", "rx";
+			i2c-scl-internal-delay-ns = <110>;
+			status = "disabled";
+		};
+
+		i2c5: i2c at e66e0000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "renesas,i2c-r8a774a1",
+				     "renesas,rcar-gen3-i2c";
+			reg = <0 0xe66e0000 0 0x40>;
+			interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 919>;
+			power-domains = <&sysc 32>;
+			resets = <&cpg 919>;
+			dmas = <&dmac0 0x9b>, <&dmac0 0x9a>;
+			dma-names = "tx", "rx";
+			i2c-scl-internal-delay-ns = <110>;
+			status = "disabled";
+		};
+
+		i2c6: i2c at e66e8000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "renesas,i2c-r8a774a1",
+				     "renesas,rcar-gen3-i2c";
+			reg = <0 0xe66e8000 0 0x40>;
+			interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 918>;
+			power-domains = <&sysc 32>;
+			resets = <&cpg 918>;
+			dmas = <&dmac0 0x9d>, <&dmac0 0x9c>;
+			dma-names = "tx", "rx";
+			i2c-scl-internal-delay-ns = <6>;
+			status = "disabled";
+		};
+
+		i2c_dvfs: i2c at e60b0000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "renesas,iic-r8a774a1",
+				     "renesas,rcar-gen3-iic",
+				     "renesas,rmobile-iic";
+			reg = <0 0xe60b0000 0 0x425>;
+			interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 926>;
+			power-domains = <&sysc 32>;
+			resets = <&cpg 926>;
+			dmas = <&dmac0 0x11>, <&dmac0 0x10>;
+			dma-names = "tx", "rx";
+			status = "disabled";
+		};
+
 		hscif0: serial at e6540000 {
 			compatible = "renesas,hscif-r8a774a1",
 				     "renesas,rcar-gen3-hscif",
-- 
2.7.4

[cip-dev] [PATCH 4.19.y-cip v2 39/57] arm64: dts: renesas: r8a774a1: Add RZ/G2M thermal support

[Fabrizio Castro]

From: Biju Das <biju.das@bp.renesas.com>

commit a4165904fd346e13d84bb67b0072e24ecd7f1937 upstream.

Add thermal support for R8A774A1 (RZ/G2M) SoC.

Based on the work done for r8a7796 SoC.

Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
---
 arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 60 +++++++++++++++++++++++++++++++
 1 file changed, 60 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
index ced2546..02620c8 100644
--- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
@@ -290,6 +290,21 @@
 			#power-domain-cells = <1>;
 		};
 
+		tsc: thermal at e6198000 {
+			compatible = "renesas,r8a774a1-thermal";
+			reg = <0 0xe6198000 0 0x100>,
+			      <0 0xe61a0000 0 0x100>,
+			      <0 0xe61a8000 0 0x100>;
+			interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 522>;
+			power-domains = <&sysc 32>;
+			resets = <&cpg 522>;
+			#thermal-sensor-cells = <1>;
+			status = "okay";
+		};
+
 		intc_ex: interrupt-controller at e61c0000 {
 			compatible = "renesas,intc-ex-r8a774a1", "renesas,irqc";
 			#interrupt-cells = <2>;
@@ -840,6 +855,51 @@
 		};
 	};
 
+	thermal-zones {
+		sensor_thermal1: sensor-thermal1 {
+			polling-delay-passive = <250>;
+			polling-delay = <1000>;
+			thermal-sensors = <&tsc 0>;
+
+			trips {
+				sensor1_crit: sensor1-crit {
+					temperature = <120000>;
+					hysteresis = <1000>;
+					type = "critical";
+				};
+			};
+		};
+
+		sensor_thermal2: sensor-thermal2 {
+			polling-delay-passive = <250>;
+			polling-delay = <1000>;
+			thermal-sensors = <&tsc 1>;
+
+			trips {
+				sensor2_crit: sensor2-crit {
+					temperature = <120000>;
+					hysteresis = <1000>;
+					type = "critical";
+				};
+			};
+
+		};
+
+		sensor_thermal3: sensor-thermal3 {
+			polling-delay-passive = <250>;
+			polling-delay = <1000>;
+			thermal-sensors = <&tsc 2>;
+
+			trips {
+				sensor3_crit: sensor3-crit {
+					temperature = <120000>;
+					hysteresis = <1000>;
+					type = "critical";
+				};
+			};
+		};
+	};
+
 	timer {
 		compatible = "arm,armv8-timer";
 		interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
-- 
2.7.4

[cip-dev] [PATCH 4.19.y-cip v2 40/57] arm64: dts: renesas: r8a774a1: Add IPMMU device nodes

[Fabrizio Castro]

commit 8f507babc617050e7502849d008ddab548efa9c1 upstream.

Add r8a774a1 IPMMU nodes.

Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Biju Das <biju.das@bp.renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 73 +++++++++++++++++++++++++++++++
 1 file changed, 73 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
index 02620c8..8589122 100644
--- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
@@ -642,6 +642,79 @@
 			dma-channels = <16>;
 		};
 
+		ipmmu_ds0: mmu at e6740000 {
+			compatible = "renesas,ipmmu-r8a774a1";
+			reg = <0 0xe6740000 0 0x1000>;
+			renesas,ipmmu-main = <&ipmmu_mm 0>;
+			power-domains = <&sysc 32>;
+			#iommu-cells = <1>;
+		};
+
+		ipmmu_ds1: mmu at e7740000 {
+			compatible = "renesas,ipmmu-r8a774a1";
+			reg = <0 0xe7740000 0 0x1000>;
+			renesas,ipmmu-main = <&ipmmu_mm 1>;
+			power-domains = <&sysc 32>;
+			#iommu-cells = <1>;
+		};
+
+		ipmmu_hc: mmu at e6570000 {
+			compatible = "renesas,ipmmu-r8a774a1";
+			reg = <0 0xe6570000 0 0x1000>;
+			renesas,ipmmu-main = <&ipmmu_mm 2>;
+			power-domains = <&sysc 32>;
+			#iommu-cells = <1>;
+		};
+
+		ipmmu_mm: mmu at e67b0000 {
+			compatible = "renesas,ipmmu-r8a774a1";
+			reg = <0 0xe67b0000 0 0x1000>;
+			interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
+			power-domains = <&sysc 32>;
+			#iommu-cells = <1>;
+		};
+
+		ipmmu_mp: mmu at ec670000 {
+			compatible = "renesas,ipmmu-r8a774a1";
+			reg = <0 0xec670000 0 0x1000>;
+			renesas,ipmmu-main = <&ipmmu_mm 4>;
+			power-domains = <&sysc 32>;
+			#iommu-cells = <1>;
+		};
+
+		ipmmu_pv0: mmu at fd800000 {
+			compatible = "renesas,ipmmu-r8a774a1";
+			reg = <0 0xfd800000 0 0x1000>;
+			renesas,ipmmu-main = <&ipmmu_mm 5>;
+			power-domains = <&sysc 32>;
+			#iommu-cells = <1>;
+		};
+
+		ipmmu_pv1: mmu at fd950000 {
+			compatible = "renesas,ipmmu-r8a774a1";
+			reg = <0 0xfd950000 0 0x1000>;
+			renesas,ipmmu-main = <&ipmmu_mm 6>;
+			power-domains = <&sysc 32>;
+			#iommu-cells = <1>;
+		};
+
+		ipmmu_vc0: mmu at fe6b0000 {
+			compatible = "renesas,ipmmu-r8a774a1";
+			reg = <0 0xfe6b0000 0 0x1000>;
+			renesas,ipmmu-main = <&ipmmu_mm 8>;
+			power-domains = <&sysc 14>;
+			#iommu-cells = <1>;
+		};
+
+		ipmmu_vi0: mmu at febd0000 {
+			compatible = "renesas,ipmmu-r8a774a1";
+			reg = <0 0xfebd0000 0 0x1000>;
+			renesas,ipmmu-main = <&ipmmu_mm 9>;
+			power-domains = <&sysc 32>;
+			#iommu-cells = <1>;
+		};
+
 		avb: ethernet at e6800000 {
 			compatible = "renesas,etheravb-r8a774a1",
 				     "renesas,etheravb-rcar-gen3";
-- 
2.7.4

[cip-dev] [PATCH 4.19.y-cip v2 41/57] arm64: dts: renesas: r8a774a1: Add all MSIOF nodes

[Fabrizio Castro]

From: Biju Das <biju.das@bp.renesas.com>

commit c512110d64a00cc0714061d54261b0f03c7202be upstream.

Add the device nodes for all MSIOF SPI controllers on RZ/G2M SoC.

Based on several similar patches of the R8A7796 device tree
by Geert Uytterhoeven <geert+renesas@glider.be>
and Simon Horman <horms+renesas@verge.net.au>.

Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
---
 arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 62 +++++++++++++++++++++++++++++++
 1 file changed, 62 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
index 8589122..f379de8 100644
--- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
@@ -857,6 +857,68 @@
 			status = "disabled";
 		};
 
+		msiof0: spi at e6e90000 {
+			compatible = "renesas,msiof-r8a774a1",
+				     "renesas,rcar-gen3-msiof";
+			reg = <0 0xe6e90000 0 0x0064>;
+			interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 211>;
+			dmas = <&dmac1 0x41>, <&dmac1 0x40>,
+			       <&dmac2 0x41>, <&dmac2 0x40>;
+			dma-names = "tx", "rx", "tx", "rx";
+			power-domains = <&sysc 32>;
+			resets = <&cpg 211>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		msiof1: spi at e6ea0000 {
+			compatible = "renesas,msiof-r8a774a1",
+				     "renesas,rcar-gen3-msiof";
+			reg = <0 0xe6ea0000 0 0x0064>;
+			interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 210>;
+			dmas = <&dmac1 0x43>, <&dmac1 0x42>,
+			       <&dmac2 0x43>, <&dmac2 0x42>;
+			dma-names = "tx", "rx", "tx", "rx";
+			power-domains = <&sysc 32>;
+			resets = <&cpg 210>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		msiof2: spi at e6c00000 {
+			compatible = "renesas,msiof-r8a774a1",
+				     "renesas,rcar-gen3-msiof";
+			reg = <0 0xe6c00000 0 0x0064>;
+			interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 209>;
+			dmas = <&dmac0 0x45>, <&dmac0 0x44>;
+			dma-names = "tx", "rx";
+			power-domains = <&sysc 32>;
+			resets = <&cpg 209>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		msiof3: spi at e6c10000 {
+			compatible = "renesas,msiof-r8a774a1",
+				     "renesas,rcar-gen3-msiof";
+			reg = <0 0xe6c10000 0 0x0064>;
+			interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 208>;
+			dmas = <&dmac0 0x47>, <&dmac0 0x46>;
+			dma-names = "tx", "rx";
+			power-domains = <&sysc 32>;
+			resets = <&cpg 208>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
 		sdhi0: sd at ee100000 {
 			compatible = "renesas,sdhi-r8a774a1",
 				     "renesas,rcar-gen3-sdhi";
-- 
2.7.4

[cip-dev] [PATCH 4.19.y-cip v2 42/57] arm64: dts: renesas: r8a774a1: Add Cortex-A53 CPU cores

[Fabrizio Castro]

From: Biju Das <biju.das@bp.renesas.com>

commit 09f49bcf6f5a62467f4fcda59d6bc38f24d97c36 upstream.

This patch adds definitions for L2 cache for the Cortex-A53 CPU
cores (512 KiB in size, organized as 32 KiB x 16 ways), adds
Cortex-A53 CPU cores (setting a total of 6 cores, 2 x Cortex-A57
+ 4 x Cortex-A53), and finally enables the performance monitor
unit for the Cortex-A53 cores on the R8A774A1 SoC.

Based on work done for r8a7796 SoC.

Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
---
 arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 66 ++++++++++++++++++++++++++++---
 1 file changed, 61 insertions(+), 5 deletions(-)

diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
index f379de8..dde1880 100644
--- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
@@ -79,12 +79,59 @@
 			clocks =<&cpg CPG_CORE 0>;
 		};
 
+		a53_0: cpu at 100 {
+			compatible = "arm,cortex-a53", "arm,armv8";
+			reg = <0x100>;
+			device_type = "cpu";
+			power-domains = <&sysc 5>;
+			next-level-cache = <&L2_CA53>;
+			enable-method = "psci";
+			clocks =<&cpg CPG_CORE 1>;
+		};
+
+		a53_1: cpu at 101 {
+			compatible = "arm,cortex-a53", "arm,armv8";
+			reg = <0x101>;
+			device_type = "cpu";
+			power-domains = <&sysc 6>;
+			next-level-cache = <&L2_CA53>;
+			enable-method = "psci";
+			clocks =<&cpg CPG_CORE 1>;
+		};
+
+		a53_2: cpu at 102 {
+			compatible = "arm,cortex-a53", "arm,armv8";
+			reg = <0x102>;
+			device_type = "cpu";
+			power-domains = <&sysc 7>;
+			next-level-cache = <&L2_CA53>;
+			enable-method = "psci";
+			clocks =<&cpg CPG_CORE 1>;
+		};
+
+		a53_3: cpu at 103 {
+			compatible = "arm,cortex-a53", "arm,armv8";
+			reg = <0x103>;
+			device_type = "cpu";
+			power-domains = <&sysc 8>;
+			next-level-cache = <&L2_CA53>;
+			enable-method = "psci";
+			clocks =<&cpg CPG_CORE 1>;
+		};
+
 		L2_CA57: cache-controller-0 {
 			compatible = "cache";
 			power-domains = <&sysc 12>;
 			cache-unified;
 			cache-level = <2>;
 		};
+
+		L2_CA53: cache-controller-1 {
+			compatible = "cache";
+			power-domains = <&sysc 21>;
+			cache-unified;
+			cache-level = <2>;
+		};
 	};
 
 	extal_clk: extal {
@@ -108,6 +155,15 @@
 		clock-frequency = <0>;
 	};
 
+	pmu_a53 {
+		compatible = "arm,cortex-a53-pmu";
+		interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
+				      <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
+				      <&gic GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
+				      <&gic GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-affinity = <&a53_0>, <&a53_1>, <&a53_2>, <&a53_3>;
+	};
+
 	pmu_a57 {
 		compatible = "arm,cortex-a57-pmu";
 		interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
@@ -977,7 +1033,7 @@
 			      <0x0 0xf1040000 0 0x20000>,
 			      <0x0 0xf1060000 0 0x20000>;
 			interrupts = <GIC_PPI 9
-					(GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
+					(GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>;
 			clocks = <&cpg CPG_MOD 408>;
 			clock-names = "clk";
 			power-domains = <&sysc 32>;
@@ -1037,10 +1093,10 @@
 
 	timer {
 		compatible = "arm,armv8-timer";
-		interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
-				      <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
-				      <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
-				      <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
+		interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
+				      <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
+				      <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
+				      <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>;
 	};
 
 	/* External USB clocks - can be overridden by the board */
-- 
2.7.4

[cip-dev] [PATCH 4.19.y-cip v2 43/57] arm64: dts: renesas: r8a774a1: Add PWM device nodes

[Fabrizio Castro]

commit 9567a8566850936688c08a6392a3324631f9daeb upstream.

This patch adds PWM[0123456] device nodes to the RZ/G2M (a.k.a R8A774A1)
device tree.

Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Biju Das <biju.das@bp.renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 70 +++++++++++++++++++++++++++++++
 1 file changed, 70 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
index dde1880..c9ac545 100644
--- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
@@ -816,6 +816,76 @@
 			status = "disabled";
 		};
 
+		pwm0: pwm at e6e30000 {
+			compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar";
+			reg = <0 0xe6e30000 0 0x8>;
+			#pwm-cells = <2>;
+			clocks = <&cpg CPG_MOD 523>;
+			resets = <&cpg 523>;
+			power-domains = <&sysc 32>;
+			status = "disabled";
+		};
+
+		pwm1: pwm at e6e31000 {
+			compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar";
+			reg = <0 0xe6e31000 0 0x8>;
+			#pwm-cells = <2>;
+			clocks = <&cpg CPG_MOD 523>;
+			resets = <&cpg 523>;
+			power-domains = <&sysc 32>;
+			status = "disabled";
+		};
+
+		pwm2: pwm at e6e32000 {
+			compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar";
+			reg = <0 0xe6e32000 0 0x8>;
+			#pwm-cells = <2>;
+			clocks = <&cpg CPG_MOD 523>;
+			resets = <&cpg 523>;
+			power-domains = <&sysc 32>;
+			status = "disabled";
+		};
+
+		pwm3: pwm at e6e33000 {
+			compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar";
+			reg = <0 0xe6e33000 0 0x8>;
+			#pwm-cells = <2>;
+			clocks = <&cpg CPG_MOD 523>;
+			resets = <&cpg 523>;
+			power-domains = <&sysc 32>;
+			status = "disabled";
+		};
+
+		pwm4: pwm at e6e34000 {
+			compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar";
+			reg = <0 0xe6e34000 0 0x8>;
+			#pwm-cells = <2>;
+			clocks = <&cpg CPG_MOD 523>;
+			resets = <&cpg 523>;
+			power-domains = <&sysc 32>;
+			status = "disabled";
+		};
+
+		pwm5: pwm at e6e35000 {
+			compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar";
+			reg = <0 0xe6e35000 0 0x8>;
+			#pwm-cells = <2>;
+			clocks = <&cpg CPG_MOD 523>;
+			resets = <&cpg 523>;
+			power-domains = <&sysc 32>;
+			status = "disabled";
+		};
+
+		pwm6: pwm at e6e36000 {
+			compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar";
+			reg = <0 0xe6e36000 0 0x8>;
+			#pwm-cells = <2>;
+			clocks = <&cpg CPG_MOD 523>;
+			resets = <&cpg 523>;
+			power-domains = <&sysc 32>;
+			status = "disabled";
+		};
+
 		scif0: serial at e6e60000 {
 			compatible = "renesas,scif-r8a774a1",
 				     "renesas,rcar-gen3-scif", "renesas,scif";
-- 
2.7.4

[cip-dev] [PATCH 4.19.y-cip v2 44/57] arm64: dts: renesas: r8a774a1: Add audio support

[Fabrizio Castro]

From: Biju Das <biju.das@bp.renesas.com>

commit e2f04248fcd47bdc037b4bfe7864ebd0a807e30c upstream.

Add sound support for the RZ/G2M SoC (a.k.a. R8A774A1).

This work is based on similar work done on the R8A7796 SoC
by Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>.

Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
---
 arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 275 ++++++++++++++++++++++++++++++
 1 file changed, 275 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
index c9ac545..50c9265 100644
--- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
@@ -1045,6 +1045,281 @@
 			status = "disabled";
 		};
 
+		rcar_sound: sound at ec500000 {
+			/*
+			 * #sound-dai-cells is required
+			 *
+			 * Single DAI : #sound-dai-cells = <0>;	<&rcar_sound>;
+			 * Multi  DAI : #sound-dai-cells = <1>;	<&rcar_sound N>;
+			 */
+			/*
+			 * #clock-cells is required for audio_clkout0/1/2/3
+			 *
+			 * clkout	: #clock-cells = <0>;	<&rcar_sound>;
+			 * clkout0/1/2/3: #clock-cells = <1>;	<&rcar_sound N>;
+			 */
+			compatible =  "renesas,rcar_sound-r8a774a1", "renesas,rcar_sound-gen3";
+			reg =	<0 0xec500000 0 0x1000>, /* SCU */
+				<0 0xec5a0000 0 0x100>,  /* ADG */
+				<0 0xec540000 0 0x1000>, /* SSIU */
+				<0 0xec541000 0 0x280>,  /* SSI */
+				<0 0xec740000 0 0x200>;  /* Audio DMAC peri peri*/
+			reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
+
+			clocks = <&cpg CPG_MOD 1005>,
+				 <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
+				 <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
+				 <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
+				 <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
+				 <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
+				 <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
+				 <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
+				 <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
+				 <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
+				 <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
+				 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
+				 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
+				 <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
+				 <&audio_clk_a>, <&audio_clk_b>,
+				 <&audio_clk_c>,
+				 <&cpg CPG_CORE 10>;
+			clock-names = "ssi-all",
+				      "ssi.9", "ssi.8", "ssi.7", "ssi.6",
+				      "ssi.5", "ssi.4", "ssi.3", "ssi.2",
+				      "ssi.1", "ssi.0",
+				      "src.9", "src.8", "src.7", "src.6",
+				      "src.5", "src.4", "src.3", "src.2",
+				      "src.1", "src.0",
+				      "mix.1", "mix.0",
+				      "ctu.1", "ctu.0",
+				      "dvc.0", "dvc.1",
+				      "clk_a", "clk_b", "clk_c", "clk_i";
+			power-domains = <&sysc 32>;
+			resets = <&cpg 1005>,
+				 <&cpg 1006>, <&cpg 1007>,
+				 <&cpg 1008>, <&cpg 1009>,
+				 <&cpg 1010>, <&cpg 1011>,
+				 <&cpg 1012>, <&cpg 1013>,
+				 <&cpg 1014>, <&cpg 1015>;
+			reset-names = "ssi-all",
+				      "ssi.9", "ssi.8", "ssi.7", "ssi.6",
+				      "ssi.5", "ssi.4", "ssi.3", "ssi.2",
+				      "ssi.1", "ssi.0";
+			status = "disabled";
+
+			rcar_sound,dvc {
+				dvc0: dvc-0 {
+					dmas = <&audma1 0xbc>;
+					dma-names = "tx";
+				};
+				dvc1: dvc-1 {
+					dmas = <&audma1 0xbe>;
+					dma-names = "tx";
+				};
+			};
+
+			rcar_sound,mix {
+				mix0: mix-0 { };
+				mix1: mix-1 { };
+			};
+
+			rcar_sound,ctu {
+				ctu00: ctu-0 { };
+				ctu01: ctu-1 { };
+				ctu02: ctu-2 { };
+				ctu03: ctu-3 { };
+				ctu10: ctu-4 { };
+				ctu11: ctu-5 { };
+				ctu12: ctu-6 { };
+				ctu13: ctu-7 { };
+			};
+
+			rcar_sound,src {
+				src0: src-0 {
+					interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
+					dmas = <&audma0 0x85>, <&audma1 0x9a>;
+					dma-names = "rx", "tx";
+				};
+				src1: src-1 {
+					interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
+					dmas = <&audma0 0x87>, <&audma1 0x9c>;
+					dma-names = "rx", "tx";
+				};
+				src2: src-2 {
+					interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
+					dmas = <&audma0 0x89>, <&audma1 0x9e>;
+					dma-names = "rx", "tx";
+				};
+				src3: src-3 {
+					interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
+					dmas = <&audma0 0x8b>, <&audma1 0xa0>;
+					dma-names = "rx", "tx";
+				};
+				src4: src-4 {
+					interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
+					dmas = <&audma0 0x8d>, <&audma1 0xb0>;
+					dma-names = "rx", "tx";
+				};
+				src5: src-5 {
+					interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
+					dmas = <&audma0 0x8f>, <&audma1 0xb2>;
+					dma-names = "rx", "tx";
+				};
+				src6: src-6 {
+					interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
+					dmas = <&audma0 0x91>, <&audma1 0xb4>;
+					dma-names = "rx", "tx";
+				};
+				src7: src-7 {
+					interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
+					dmas = <&audma0 0x93>, <&audma1 0xb6>;
+					dma-names = "rx", "tx";
+				};
+				src8: src-8 {
+					interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
+					dmas = <&audma0 0x95>, <&audma1 0xb8>;
+					dma-names = "rx", "tx";
+				};
+				src9: src-9 {
+					interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;
+					dmas = <&audma0 0x97>, <&audma1 0xba>;
+					dma-names = "rx", "tx";
+				};
+			};
+
+			rcar_sound,ssi {
+				ssi0: ssi-0 {
+					interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
+					dmas = <&audma0 0x01>, <&audma1 0x02>, <&audma0 0x15>, <&audma1 0x16>;
+					dma-names = "rx", "tx", "rxu", "txu";
+				};
+				ssi1: ssi-1 {
+					interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
+					dmas = <&audma0 0x03>, <&audma1 0x04>, <&audma0 0x49>, <&audma1 0x4a>;
+					dma-names = "rx", "tx", "rxu", "txu";
+				};
+				ssi2: ssi-2 {
+					interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
+					dmas = <&audma0 0x05>, <&audma1 0x06>, <&audma0 0x63>, <&audma1 0x64>;
+					dma-names = "rx", "tx", "rxu", "txu";
+				};
+				ssi3: ssi-3 {
+					interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
+					dmas = <&audma0 0x07>, <&audma1 0x08>, <&audma0 0x6f>, <&audma1 0x70>;
+					dma-names = "rx", "tx", "rxu", "txu";
+				};
+				ssi4: ssi-4 {
+					interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
+					dmas = <&audma0 0x09>, <&audma1 0x0a>, <&audma0 0x71>, <&audma1 0x72>;
+					dma-names = "rx", "tx", "rxu", "txu";
+				};
+				ssi5: ssi-5 {
+					interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
+					dmas = <&audma0 0x0b>, <&audma1 0x0c>, <&audma0 0x73>, <&audma1 0x74>;
+					dma-names = "rx", "tx", "rxu", "txu";
+				};
+				ssi6: ssi-6 {
+					interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
+					dmas = <&audma0 0x0d>, <&audma1 0x0e>, <&audma0 0x75>, <&audma1 0x76>;
+					dma-names = "rx", "tx", "rxu", "txu";
+				};
+				ssi7: ssi-7 {
+					interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
+					dmas = <&audma0 0x0f>, <&audma1 0x10>, <&audma0 0x79>, <&audma1 0x7a>;
+					dma-names = "rx", "tx", "rxu", "txu";
+				};
+				ssi8: ssi-8 {
+					interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
+					dmas = <&audma0 0x11>, <&audma1 0x12>, <&audma0 0x7b>, <&audma1 0x7c>;
+					dma-names = "rx", "tx", "rxu", "txu";
+				};
+				ssi9: ssi-9 {
+					interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
+					dmas = <&audma0 0x13>, <&audma1 0x14>, <&audma0 0x7d>, <&audma1 0x7e>;
+					dma-names = "rx", "tx", "rxu", "txu";
+				};
+			};
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				port at 0 {
+					reg = <0>;
+				};
+				port at 1 {
+					reg = <1>;
+				};
+			};
+		};
+
+		audma0: dma-controller at ec700000 {
+			compatible = "renesas,dmac-r8a774a1",
+				     "renesas,rcar-dmac";
+			reg = <0 0xec700000 0 0x10000>;
+			interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH
+				      GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH
+				      GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH
+				      GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH
+				      GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH
+				      GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH
+				      GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH
+				      GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH
+				      GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH
+				      GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH
+				      GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH
+				      GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH
+				      GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH
+				      GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH
+				      GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH
+				      GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH
+				      GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "error",
+					"ch0", "ch1", "ch2", "ch3",
+					"ch4", "ch5", "ch6", "ch7",
+					"ch8", "ch9", "ch10", "ch11",
+					"ch12", "ch13", "ch14", "ch15";
+			clocks = <&cpg CPG_MOD 502>;
+			clock-names = "fck";
+			power-domains = <&sysc 32>;
+			resets = <&cpg 502>;
+			#dma-cells = <1>;
+			dma-channels = <16>;
+		};
+
+		audma1: dma-controller at ec720000 {
+			compatible = "renesas,dmac-r8a774a1",
+				     "renesas,rcar-dmac";
+			reg = <0 0xec720000 0 0x10000>;
+			interrupts = <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH
+				      GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH
+				      GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH
+				      GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH
+				      GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH
+				      GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH
+				      GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH
+				      GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH
+				      GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH
+				      GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH
+				      GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH
+				      GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH
+				      GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH
+				      GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH
+				      GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH
+				      GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH
+				      GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "error",
+					"ch0", "ch1", "ch2", "ch3",
+					"ch4", "ch5", "ch6", "ch7",
+					"ch8", "ch9", "ch10", "ch11",
+					"ch12", "ch13", "ch14", "ch15";
+			clocks = <&cpg CPG_MOD 501>;
+			clock-names = "fck";
+			power-domains = <&sysc 32>;
+			resets = <&cpg 501>;
+			#dma-cells = <1>;
+			dma-channels = <16>;
+		};
+
 		sdhi0: sd at ee100000 {
 			compatible = "renesas,sdhi-r8a774a1",
 				     "renesas,rcar-gen3-sdhi";
-- 
2.7.4

[cip-dev] [PATCH 4.19.y-cip v2 45/57] arm64: dts: renesas: r8a774a1: Add FCPF and FCPV instances

[Fabrizio Castro]

commit 282419526ad7ba3d0ff5e53c20a5f4f5a273197f upstream.

Add FCPF and FCPV instances to the r8a774a1 dtsi, similarly
to what was done for the r8a7796 with commit 41dbbf0c5b4e
("arm64: dts: r8a7796: Add FCPF and FCPV instances"),
commit 69490bc9665d ("arm64: dts: renesas: r8a7796: Point
FDP1 via FCPF to IPMMU-VI0"), and commit cef942d0bd89 ("arm64:
dts: renesas: r8a7796: Point VSPI via FCPVI to IPMMU-VC0").

Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Biju Das <biju.das@bp.renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 52 +++++++++++++++++++++++++++++++
 1 file changed, 52 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
index 50c9265..5d0109a 100644
--- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
@@ -1385,6 +1385,58 @@
 			resets = <&cpg 408>;
 		};
 
+		fcpf0: fcp at fe950000 {
+			compatible = "renesas,fcpf";
+			reg = <0 0xfe950000 0 0x200>;
+			clocks = <&cpg CPG_MOD 615>;
+			power-domains = <&sysc 14>;
+			resets = <&cpg 615>;
+		};
+
+		fcpvb0: fcp at fe96f000 {
+			compatible = "renesas,fcpv";
+			reg = <0 0xfe96f000 0 0x200>;
+			clocks = <&cpg CPG_MOD 607>;
+			power-domains = <&sysc 14>;
+			resets = <&cpg 607>;
+		};
+
+		fcpvd0: fcp at fea27000 {
+			compatible = "renesas,fcpv";
+			reg = <0 0xfea27000 0 0x200>;
+			clocks = <&cpg CPG_MOD 603>;
+			power-domains = <&sysc 32>;
+			resets = <&cpg 603>;
+			iommus = <&ipmmu_vi0 8>;
+		};
+
+		fcpvd1: fcp at fea2f000 {
+			compatible = "renesas,fcpv";
+			reg = <0 0xfea2f000 0 0x200>;
+			clocks = <&cpg CPG_MOD 602>;
+			power-domains = <&sysc 32>;
+			resets = <&cpg 602>;
+			iommus = <&ipmmu_vi0 9>;
+		};
+
+		fcpvd2: fcp at fea37000 {
+			compatible = "renesas,fcpv";
+			reg = <0 0xfea37000 0 0x200>;
+			clocks = <&cpg CPG_MOD 601>;
+			power-domains = <&sysc 32>;
+			resets = <&cpg 601>;
+			iommus = <&ipmmu_vi0 10>;
+		};
+
+		fcpvi0: fcp at fe9af000 {
+			compatible = "renesas,fcpv";
+			reg = <0 0xfe9af000 0 0x200>;
+			clocks = <&cpg CPG_MOD 611>;
+			power-domains = <&sysc 14>;
+			resets = <&cpg 611>;
+			iommus = <&ipmmu_vc0 19>;
+		};
+
 		prr: chipid at fff00044 {
 			compatible = "renesas,prr";
 			reg = <0 0xfff00044 0 4>;
-- 
2.7.4

[cip-dev] [PATCH 4.19.y-cip v2 46/57] arm64: dts: renesas: r8a774a1: Add USB2.0 phy and host(EHCI/OHCI) device nodes

[Fabrizio Castro]

From: Biju Das <biju.das@bp.renesas.com>

commit 4c2c2fb9987601b5dd7de3ccd70dc2270434b351 upstream.

Add USB2.0 phy and host (EHCI/OHCI) device nodes on RZ/G2M SoC dtsi.

Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
---
 arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 73 +++++++++++++++++++++++++++++++
 1 file changed, 73 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
index 5d0109a..1111386 100644
--- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
@@ -1320,6 +1320,79 @@
 			dma-channels = <16>;
 		};
 
+		ohci0: usb at ee080000 {
+			compatible = "generic-ohci";
+			reg = <0 0xee080000 0 0x100>;
+			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 703>;
+			phys = <&usb2_phy0>;
+			phy-names = "usb";
+			power-domains = <&sysc 32>;
+			resets = <&cpg 703>;
+			status = "disabled";
+		};
+
+		ohci1: usb at ee0a0000 {
+			compatible = "generic-ohci";
+			reg = <0 0xee0a0000 0 0x100>;
+			interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 702>;
+			phys = <&usb2_phy1>;
+			phy-names = "usb";
+			power-domains = <&sysc 32>;
+			resets = <&cpg 702>;
+			status = "disabled";
+		};
+
+		ehci0: usb at ee080100 {
+			compatible = "generic-ehci";
+			reg = <0 0xee080100 0 0x100>;
+			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 703>;
+			phys = <&usb2_phy0>;
+			phy-names = "usb";
+			companion= <&ohci0>;
+			power-domains = <&sysc 32>;
+			resets = <&cpg 703>;
+			status = "disabled";
+		};
+
+		ehci1: usb at ee0a0100 {
+			compatible = "generic-ehci";
+			reg = <0 0xee0a0100 0 0x100>;
+			interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 702>;
+			phys = <&usb2_phy1>;
+			phy-names = "usb";
+			companion= <&ohci1>;
+			power-domains = <&sysc 32>;
+			resets = <&cpg 702>;
+			status = "disabled";
+		};
+
+		usb2_phy0: usb-phy at ee080200 {
+			compatible = "renesas,usb2-phy-r8a774a1",
+				     "renesas,rcar-gen3-usb2-phy";
+			reg = <0 0xee080200 0 0x700>;
+			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 703>;
+			power-domains = <&sysc 32>;
+			resets = <&cpg 703>;
+			#phy-cells = <0>;
+			status = "disabled";
+		};
+
+		usb2_phy1: usb-phy at ee0a0200 {
+			compatible = "renesas,usb2-phy-r8a774a1",
+				     "renesas,rcar-gen3-usb2-phy";
+			reg = <0 0xee0a0200 0 0x700>;
+			clocks = <&cpg CPG_MOD 702>;
+			power-domains = <&sysc 32>;
+			resets = <&cpg 702>;
+			#phy-cells = <0>;
+			status = "disabled";
+		};
+
 		sdhi0: sd at ee100000 {
 			compatible = "renesas,sdhi-r8a774a1",
 				     "renesas,rcar-gen3-sdhi";
-- 
2.7.4

[cip-dev] [PATCH 4.19.y-cip v2 47/57] arm64: dts: renesas: r8a774a1: Add USB-DMAC and HSUSB device nodes

[Fabrizio Castro]

From: Biju Das <biju.das@bp.renesas.com>

commit ed898d4fc19d279e508440c6156fe31755865af1 upstream.

Add usb dmac and hsusb device nodes on RZ/G2M SoC dtsi.

Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
---
 arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 45 +++++++++++++++++++++++++++++++
 1 file changed, 45 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
index 1111386..b421174 100644
--- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
@@ -596,6 +596,51 @@
 			status = "disabled";
 		};
 
+		hsusb: usb at e6590000 {
+			compatible = "renesas,usbhs-r8a774a1",
+				     "renesas,rcar-gen3-usbhs";
+			reg = <0 0xe6590000 0 0x100>;
+			interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 704>;
+			dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
+			       <&usb_dmac1 0>, <&usb_dmac1 1>;
+			dma-names = "ch0", "ch1", "ch2", "ch3";
+			renesas,buswait = <11>;
+			phys = <&usb2_phy0>;
+			phy-names = "usb";
+			power-domains = <&sysc 32>;
+			resets = <&cpg 704>;
+			status = "disabled";
+		};
+
+		usb_dmac0: dma-controller at e65a0000 {
+			compatible = "renesas,r8a774a1-usb-dmac",
+				     "renesas,usb-dmac";
+			reg = <0 0xe65a0000 0 0x100>;
+			interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH
+				      GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "ch0", "ch1";
+			clocks = <&cpg CPG_MOD 330>;
+			power-domains = <&sysc 32>;
+			resets = <&cpg 330>;
+			#dma-cells = <1>;
+			dma-channels = <2>;
+		};
+
+		usb_dmac1: dma-controller at e65b0000 {
+			compatible = "renesas,r8a774a1-usb-dmac",
+				     "renesas,usb-dmac";
+			reg = <0 0xe65b0000 0 0x100>;
+			interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH
+				      GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "ch0", "ch1";
+			clocks = <&cpg CPG_MOD 331>;
+			power-domains = <&sysc 32>;
+			resets = <&cpg 331>;
+			#dma-cells = <1>;
+			dma-channels = <2>;
+		};
+
 		dmac0: dma-controller at e6700000 {
 			compatible = "renesas,dmac-r8a774a1",
 				     "renesas,rcar-dmac";
-- 
2.7.4

[cip-dev] [PATCH 4.19.y-cip v2 48/57] arm64: dts: renesas: r8a774a1: Add USB3.0 device nodes

[Fabrizio Castro]

From: Biju Das <biju.das@bp.renesas.com>

commit 453240f6657a6f87dd59e39c1f0d2655d40f112c upstream.

Add usb3.0 phy, host and function device nodes on RZ/G2M SoC dtsi.

Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
---
 arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 35 +++++++++++++++++++++++++++++++
 1 file changed, 35 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
index b421174..d2c67f3 100644
--- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
@@ -641,6 +641,19 @@
 			dma-channels = <2>;
 		};
 
+		usb3_phy0: usb-phy at e65ee000 {
+			compatible = "renesas,r8a774a1-usb3-phy",
+				     "renesas,rcar-gen3-usb3-phy";
+			reg = <0 0xe65ee000 0 0x90>;
+			clocks = <&cpg CPG_MOD 328>, <&usb3s0_clk>,
+				 <&usb_extal_clk>;
+			clock-names = "usb3-if", "usb3s_clk", "usb_extal";
+			power-domains = <&sysc 32>;
+			resets = <&cpg 328>;
+			#phy-cells = <0>;
+			status = "disabled";
+		};
+
 		dmac0: dma-controller at e6700000 {
 			compatible = "renesas,dmac-r8a774a1",
 				     "renesas,rcar-dmac";
@@ -1365,6 +1378,28 @@
 			dma-channels = <16>;
 		};
 
+		xhci0: usb at ee000000 {
+			compatible = "renesas,xhci-r8a774a1",
+				     "renesas,rcar-gen3-xhci";
+			reg = <0 0xee000000 0 0xc00>;
+			interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 328>;
+			power-domains = <&sysc 32>;
+			resets = <&cpg 328>;
+			status = "disabled";
+		};
+
+		usb3_peri0: usb at ee020000 {
+			compatible = "renesas,r8a774a1-usb3-peri",
+				     "renesas,rcar-gen3-usb3-peri";
+			reg = <0 0xee020000 0 0x400>;
+			interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 328>;
+			power-domains = <&sysc 32>;
+			resets = <&cpg 328>;
+			status = "disabled";
+		};
+
 		ohci0: usb at ee080000 {
 			compatible = "generic-ohci";
 			reg = <0 0xee080000 0 0x100>;
-- 
2.7.4

[cip-dev] [PATCH 4.19.y-cip v2 49/57] arm64: dts: renesas: Fix whitespace around assignments

[Fabrizio Castro]

From: Geert Uytterhoeven <geert+renesas@glider.be>

commit fced3a97f80955e5950b76d164a4124cb1303853 upstream.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
[simon: updated for a few new cases]
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
[fab: dropped changes not related to r8a774a1.dtsi]
Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
---
 arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
index d2c67f3..046fc93 100644
--- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
@@ -66,7 +66,7 @@
 			power-domains = <&sysc 0>;
 			next-level-cache = <&L2_CA57>;
 			enable-method = "psci";
-			clocks =<&cpg CPG_CORE 0>;
+			clocks = <&cpg CPG_CORE 0>;
 		};
 
 		a57_1: cpu at 1 {
@@ -76,7 +76,7 @@
 			power-domains = <&sysc 1>;
 			next-level-cache = <&L2_CA57>;
 			enable-method = "psci";
-			clocks =<&cpg CPG_CORE 0>;
+			clocks = <&cpg CPG_CORE 0>;
 		};
 
 		a53_0: cpu at 100 {
@@ -1431,7 +1431,7 @@
 			clocks = <&cpg CPG_MOD 703>;
 			phys = <&usb2_phy0>;
 			phy-names = "usb";
-			companion= <&ohci0>;
+			companion = <&ohci0>;
 			power-domains = <&sysc 32>;
 			resets = <&cpg 703>;
 			status = "disabled";
@@ -1444,7 +1444,7 @@
 			clocks = <&cpg CPG_MOD 702>;
 			phys = <&usb2_phy1>;
 			phy-names = "usb";
-			companion= <&ohci1>;
+			companion = <&ohci1>;
 			power-domains = <&sysc 32>;
 			resets = <&cpg 702>;
 			status = "disabled";
-- 
2.7.4

[cip-dev] [PATCH 4.19.y-cip v2 50/57] arm64: dts: renesas: Remove unneeded status from thermal nodes

[Fabrizio Castro]

From: Geert Uytterhoeven <geert+renesas@glider.be>

commit c79661eb5060e2bf18875d86caf3324b4ab4c03f upstream.

The thermal device is supposed to be always enabled.  As the default
value of the status property is "okay", there is no need to make this
explicit in SoC-specific .dtsi files where no override is involved.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
[fab: dropped changes not related to r8a774a1.dtsi]
Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
---
 arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 1 -
 1 file changed, 1 deletion(-)

diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
index 046fc93..012cbb6 100644
--- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
@@ -358,7 +358,6 @@
 			power-domains = <&sysc 32>;
 			resets = <&cpg 522>;
 			#thermal-sensor-cells = <1>;
-			status = "okay";
 		};
 
 		intc_ex: interrupt-controller at e61c0000 {
-- 
2.7.4

[cip-dev] [PATCH 4.19.y-cip v2 51/57] arm64: dts: renesas: r8a774a1: Add CAN nodes

[Fabrizio Castro]

From: Chris Paterson <chris.paterson2@renesas.com>

commit b823d65f3380e9d7dd19c8e015dd7f22a0a09957 upstream.

Add the device nodes for both RZ/G2M CAN channels.

Signed-off-by: Chris Paterson <chris.paterson2@renesas.com>
Reviewed-by: Biju Das <biju.das@bp.renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
---
 arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 24 ++++++++++++++++++++++++
 1 file changed, 24 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
index 012cbb6..a4817a0 100644
--- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
@@ -873,6 +873,30 @@
 			status = "disabled";
 		};
 
+		can0: can at e6c30000 {
+			compatible = "renesas,can-r8a774a1",
+				     "renesas,rcar-gen3-can";
+			reg = <0 0xe6c30000 0 0x1000>;
+			interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 916>, <&can_clk>;
+			clock-names = "clkp1", "can_clk";
+			power-domains = <&sysc 32>;
+			resets = <&cpg 916>;
+			status = "disabled";
+		};
+
+		can1: can at e6c38000 {
+			compatible = "renesas,can-r8a774a1",
+				     "renesas,rcar-gen3-can";
+			reg = <0 0xe6c38000 0 0x1000>;
+			interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 915>, <&can_clk>;
+			clock-names = "clkp1", "can_clk";
+			power-domains = <&sysc 32>;
+			resets = <&cpg 915>;
+			status = "disabled";
+		};
+
 		pwm0: pwm at e6e30000 {
 			compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar";
 			reg = <0 0xe6e30000 0 0x8>;
-- 
2.7.4

[cip-dev] [PATCH 4.19.y-cip v2 52/57] arm64: dts: renesas: r8a774a1: Replace power magic numbers

[Fabrizio Castro]

commit aeee3d9cb776542f5700425f703fa78c70a1dcd0 upstream.

Now that include/dt-bindings/power/r8a774a1-sysc.h is in Linus'
master branch we can replace power related magic numbers with
the corresponding labels.

Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 181 +++++++++++++++---------------
 1 file changed, 91 insertions(+), 90 deletions(-)

diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
index a4817a0..000b280 100644
--- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
@@ -8,6 +8,7 @@
 #include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/clock/renesas-cpg-mssr.h>
+#include <dt-bindings/power/r8a774a1-sysc.h>
 
 / {
 	compatible = "renesas,r8a774a1";
@@ -63,7 +64,7 @@
 			compatible = "arm,cortex-a57", "arm,armv8";
 			reg = <0x0>;
 			device_type = "cpu";
-			power-domains = <&sysc 0>;
+			power-domains = <&sysc R8A774A1_PD_CA57_CPU0>;
 			next-level-cache = <&L2_CA57>;
 			enable-method = "psci";
 			clocks = <&cpg CPG_CORE 0>;
@@ -73,7 +74,7 @@
 			compatible = "arm,cortex-a57", "arm,armv8";
 			reg = <0x1>;
 			device_type = "cpu";
-			power-domains = <&sysc 1>;
+			power-domains = <&sysc R8A774A1_PD_CA57_CPU1>;
 			next-level-cache = <&L2_CA57>;
 			enable-method = "psci";
 			clocks = <&cpg CPG_CORE 0>;
@@ -83,7 +84,7 @@
 			compatible = "arm,cortex-a53", "arm,armv8";
 			reg = <0x100>;
 			device_type = "cpu";
-			power-domains = <&sysc 5>;
+			power-domains = <&sysc R8A774A1_PD_CA53_CPU0>;
 			next-level-cache = <&L2_CA53>;
 			enable-method = "psci";
 			clocks =<&cpg CPG_CORE 1>;
@@ -93,7 +94,7 @@
 			compatible = "arm,cortex-a53", "arm,armv8";
 			reg = <0x101>;
 			device_type = "cpu";
-			power-domains = <&sysc 6>;
+			power-domains = <&sysc R8A774A1_PD_CA53_CPU1>;
 			next-level-cache = <&L2_CA53>;
 			enable-method = "psci";
 			clocks =<&cpg CPG_CORE 1>;
@@ -103,7 +104,7 @@
 			compatible = "arm,cortex-a53", "arm,armv8";
 			reg = <0x102>;
 			device_type = "cpu";
-			power-domains = <&sysc 7>;
+			power-domains = <&sysc R8A774A1_PD_CA53_CPU2>;
 			next-level-cache = <&L2_CA53>;
 			enable-method = "psci";
 			clocks =<&cpg CPG_CORE 1>;
@@ -113,7 +114,7 @@
 			compatible = "arm,cortex-a53", "arm,armv8";
 			reg = <0x103>;
 			device_type = "cpu";
-			power-domains = <&sysc 8>;
+			power-domains = <&sysc R8A774A1_PD_CA53_CPU3>;
 			next-level-cache = <&L2_CA53>;
 			enable-method = "psci";
 			clocks =<&cpg CPG_CORE 1>;
@@ -121,14 +122,14 @@
 
 		L2_CA57: cache-controller-0 {
 			compatible = "cache";
-			power-domains = <&sysc 12>;
+			power-domains = <&sysc R8A774A1_PD_CA57_SCU>;
 			cache-unified;
 			cache-level = <2>;
 		};
 
 		L2_CA53: cache-controller-1 {
 			compatible = "cache";
-			power-domains = <&sysc 21>;
+			power-domains = <&sysc R8A774A1_PD_CA53_SCU>;
 			cache-unified;
 			cache-level = <2>;
 		};
@@ -195,7 +196,7 @@
 				     "renesas,rcar-gen3-wdt";
 			reg = <0 0xe6020000 0 0x0c>;
 			clocks = <&cpg CPG_MOD 402>;
-			power-domains = <&sysc 32>;
+			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
 			resets = <&cpg 402>;
 			status = "disabled";
 		};
@@ -211,7 +212,7 @@
 			#interrupt-cells = <2>;
 			interrupt-controller;
 			clocks = <&cpg CPG_MOD 912>;
-			power-domains = <&sysc 32>;
+			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
 			resets = <&cpg 912>;
 		};
 
@@ -226,7 +227,7 @@
 			#interrupt-cells = <2>;
 			interrupt-controller;
 			clocks = <&cpg CPG_MOD 911>;
-			power-domains = <&sysc 32>;
+			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
 			resets = <&cpg 911>;
 		};
 
@@ -241,7 +242,7 @@
 			#interrupt-cells = <2>;
 			interrupt-controller;
 			clocks = <&cpg CPG_MOD 910>;
-			power-domains = <&sysc 32>;
+			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
 			resets = <&cpg 910>;
 		};
 
@@ -256,7 +257,7 @@
 			#interrupt-cells = <2>;
 			interrupt-controller;
 			clocks = <&cpg CPG_MOD 909>;
-			power-domains = <&sysc 32>;
+			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
 			resets = <&cpg 909>;
 		};
 
@@ -271,7 +272,7 @@
 			#interrupt-cells = <2>;
 			interrupt-controller;
 			clocks = <&cpg CPG_MOD 908>;
-			power-domains = <&sysc 32>;
+			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
 			resets = <&cpg 908>;
 		};
 
@@ -286,7 +287,7 @@
 			#interrupt-cells = <2>;
 			interrupt-controller;
 			clocks = <&cpg CPG_MOD 907>;
-			power-domains = <&sysc 32>;
+			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
 			resets = <&cpg 907>;
 		};
 
@@ -301,7 +302,7 @@
 			#interrupt-cells = <2>;
 			interrupt-controller;
 			clocks = <&cpg CPG_MOD 906>;
-			power-domains = <&sysc 32>;
+			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
 			resets = <&cpg 906>;
 		};
 
@@ -316,7 +317,7 @@
 			#interrupt-cells = <2>;
 			interrupt-controller;
 			clocks = <&cpg CPG_MOD 905>;
-			power-domains = <&sysc 32>;
+			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
 			resets = <&cpg 905>;
 		};
 
@@ -355,7 +356,7 @@
 				     <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&cpg CPG_MOD 522>;
-			power-domains = <&sysc 32>;
+			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
 			resets = <&cpg 522>;
 			#thermal-sensor-cells = <1>;
 		};
@@ -372,7 +373,7 @@
 				      GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH
 				      GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&cpg CPG_MOD 407>;
-			power-domains = <&sysc 32>;
+			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
 			resets = <&cpg 407>;
 		};
 
@@ -384,7 +385,7 @@
 			reg = <0 0xe6500000 0 0x40>;
 			interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&cpg CPG_MOD 931>;
-			power-domains = <&sysc 32>;
+			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
 			resets = <&cpg 931>;
 			dmas = <&dmac1 0x91>, <&dmac1 0x90>,
 			       <&dmac2 0x91>, <&dmac2 0x90>;
@@ -401,7 +402,7 @@
 			reg = <0 0xe6508000 0 0x40>;
 			interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&cpg CPG_MOD 930>;
-			power-domains = <&sysc 32>;
+			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
 			resets = <&cpg 930>;
 			dmas = <&dmac1 0x93>, <&dmac1 0x92>,
 			       <&dmac2 0x93>, <&dmac2 0x92>;
@@ -418,7 +419,7 @@
 			reg = <0 0xe6510000 0 0x40>;
 			interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&cpg CPG_MOD 929>;
-			power-domains = <&sysc 32>;
+			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
 			resets = <&cpg 929>;
 			dmas = <&dmac1 0x95>, <&dmac1 0x94>,
 			       <&dmac2 0x95>, <&dmac2 0x94>;
@@ -435,7 +436,7 @@
 			reg = <0 0xe66d0000 0 0x40>;
 			interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&cpg CPG_MOD 928>;
-			power-domains = <&sysc 32>;
+			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
 			resets = <&cpg 928>;
 			dmas = <&dmac0 0x97>, <&dmac0 0x96>;
 			dma-names = "tx", "rx";
@@ -451,7 +452,7 @@
 			reg = <0 0xe66d8000 0 0x40>;
 			interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&cpg CPG_MOD 927>;
-			power-domains = <&sysc 32>;
+			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
 			resets = <&cpg 927>;
 			dmas = <&dmac0 0x99>, <&dmac0 0x98>;
 			dma-names = "tx", "rx";
@@ -467,7 +468,7 @@
 			reg = <0 0xe66e0000 0 0x40>;
 			interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&cpg CPG_MOD 919>;
-			power-domains = <&sysc 32>;
+			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
 			resets = <&cpg 919>;
 			dmas = <&dmac0 0x9b>, <&dmac0 0x9a>;
 			dma-names = "tx", "rx";
@@ -483,7 +484,7 @@
 			reg = <0 0xe66e8000 0 0x40>;
 			interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&cpg CPG_MOD 918>;
-			power-domains = <&sysc 32>;
+			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
 			resets = <&cpg 918>;
 			dmas = <&dmac0 0x9d>, <&dmac0 0x9c>;
 			dma-names = "tx", "rx";
@@ -500,7 +501,7 @@
 			reg = <0 0xe60b0000 0 0x425>;
 			interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&cpg CPG_MOD 926>;
-			power-domains = <&sysc 32>;
+			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
 			resets = <&cpg 926>;
 			dmas = <&dmac0 0x11>, <&dmac0 0x10>;
 			dma-names = "tx", "rx";
@@ -520,7 +521,7 @@
 			dmas = <&dmac1 0x31>, <&dmac1 0x30>,
 			       <&dmac2 0x31>, <&dmac2 0x30>;
 			dma-names = "tx", "rx", "tx", "rx";
-			power-domains = <&sysc 32>;
+			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
 			resets = <&cpg 520>;
 			status = "disabled";
 		};
@@ -538,7 +539,7 @@
 			dmas = <&dmac1 0x33>, <&dmac1 0x32>,
 			       <&dmac2 0x33>, <&dmac2 0x32>;
 			dma-names = "tx", "rx", "tx", "rx";
-			power-domains = <&sysc 32>;
+			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
 			resets = <&cpg 519>;
 			status = "disabled";
 		};
@@ -556,7 +557,7 @@
 			dmas = <&dmac1 0x35>, <&dmac1 0x34>,
 			       <&dmac2 0x35>, <&dmac2 0x34>;
 			dma-names = "tx", "rx", "tx", "rx";
-			power-domains = <&sysc 32>;
+			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
 			resets = <&cpg 518>;
 			status = "disabled";
 		};
@@ -573,7 +574,7 @@
 			clock-names = "fck", "brg_int", "scif_clk";
 			dmas = <&dmac0 0x37>, <&dmac0 0x36>;
 			dma-names = "tx", "rx";
-			power-domains = <&sysc 32>;
+			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
 			resets = <&cpg 517>;
 			status = "disabled";
 		};
@@ -590,7 +591,7 @@
 			clock-names = "fck", "brg_int", "scif_clk";
 			dmas = <&dmac0 0x39>, <&dmac0 0x38>;
 			dma-names = "tx", "rx";
-			power-domains = <&sysc 32>;
+			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
 			resets = <&cpg 516>;
 			status = "disabled";
 		};
@@ -607,7 +608,7 @@
 			renesas,buswait = <11>;
 			phys = <&usb2_phy0>;
 			phy-names = "usb";
-			power-domains = <&sysc 32>;
+			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
 			resets = <&cpg 704>;
 			status = "disabled";
 		};
@@ -620,7 +621,7 @@
 				      GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "ch0", "ch1";
 			clocks = <&cpg CPG_MOD 330>;
-			power-domains = <&sysc 32>;
+			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
 			resets = <&cpg 330>;
 			#dma-cells = <1>;
 			dma-channels = <2>;
@@ -634,7 +635,7 @@
 				      GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "ch0", "ch1";
 			clocks = <&cpg CPG_MOD 331>;
-			power-domains = <&sysc 32>;
+			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
 			resets = <&cpg 331>;
 			#dma-cells = <1>;
 			dma-channels = <2>;
@@ -647,7 +648,7 @@
 			clocks = <&cpg CPG_MOD 328>, <&usb3s0_clk>,
 				 <&usb_extal_clk>;
 			clock-names = "usb3-if", "usb3s_clk", "usb_extal";
-			power-domains = <&sysc 32>;
+			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
 			resets = <&cpg 328>;
 			#phy-cells = <0>;
 			status = "disabled";
@@ -681,7 +682,7 @@
 					"ch12", "ch13", "ch14", "ch15";
 			clocks = <&cpg CPG_MOD 219>;
 			clock-names = "fck";
-			power-domains = <&sysc 32>;
+			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
 			resets = <&cpg 219>;
 			#dma-cells = <1>;
 			dma-channels = <16>;
@@ -715,7 +716,7 @@
 					"ch12", "ch13", "ch14", "ch15";
 			clocks = <&cpg CPG_MOD 218>;
 			clock-names = "fck";
-			power-domains = <&sysc 32>;
+			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
 			resets = <&cpg 218>;
 			#dma-cells = <1>;
 			dma-channels = <16>;
@@ -749,7 +750,7 @@
 					"ch12", "ch13", "ch14", "ch15";
 			clocks = <&cpg CPG_MOD 217>;
 			clock-names = "fck";
-			power-domains = <&sysc 32>;
+			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
 			resets = <&cpg 217>;
 			#dma-cells = <1>;
 			dma-channels = <16>;
@@ -759,7 +760,7 @@
 			compatible = "renesas,ipmmu-r8a774a1";
 			reg = <0 0xe6740000 0 0x1000>;
 			renesas,ipmmu-main = <&ipmmu_mm 0>;
-			power-domains = <&sysc 32>;
+			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
 			#iommu-cells = <1>;
 		};
 
@@ -767,7 +768,7 @@
 			compatible = "renesas,ipmmu-r8a774a1";
 			reg = <0 0xe7740000 0 0x1000>;
 			renesas,ipmmu-main = <&ipmmu_mm 1>;
-			power-domains = <&sysc 32>;
+			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
 			#iommu-cells = <1>;
 		};
 
@@ -775,7 +776,7 @@
 			compatible = "renesas,ipmmu-r8a774a1";
 			reg = <0 0xe6570000 0 0x1000>;
 			renesas,ipmmu-main = <&ipmmu_mm 2>;
-			power-domains = <&sysc 32>;
+			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
 			#iommu-cells = <1>;
 		};
 
@@ -784,7 +785,7 @@
 			reg = <0 0xe67b0000 0 0x1000>;
 			interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
-			power-domains = <&sysc 32>;
+			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
 			#iommu-cells = <1>;
 		};
 
@@ -792,7 +793,7 @@
 			compatible = "renesas,ipmmu-r8a774a1";
 			reg = <0 0xec670000 0 0x1000>;
 			renesas,ipmmu-main = <&ipmmu_mm 4>;
-			power-domains = <&sysc 32>;
+			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
 			#iommu-cells = <1>;
 		};
 
@@ -800,7 +801,7 @@
 			compatible = "renesas,ipmmu-r8a774a1";
 			reg = <0 0xfd800000 0 0x1000>;
 			renesas,ipmmu-main = <&ipmmu_mm 5>;
-			power-domains = <&sysc 32>;
+			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
 			#iommu-cells = <1>;
 		};
 
@@ -808,7 +809,7 @@
 			compatible = "renesas,ipmmu-r8a774a1";
 			reg = <0 0xfd950000 0 0x1000>;
 			renesas,ipmmu-main = <&ipmmu_mm 6>;
-			power-domains = <&sysc 32>;
+			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
 			#iommu-cells = <1>;
 		};
 
@@ -816,7 +817,7 @@
 			compatible = "renesas,ipmmu-r8a774a1";
 			reg = <0 0xfe6b0000 0 0x1000>;
 			renesas,ipmmu-main = <&ipmmu_mm 8>;
-			power-domains = <&sysc 14>;
+			power-domains = <&sysc R8A774A1_PD_A3VC>;
 			#iommu-cells = <1>;
 		};
 
@@ -824,7 +825,7 @@
 			compatible = "renesas,ipmmu-r8a774a1";
 			reg = <0 0xfebd0000 0 0x1000>;
 			renesas,ipmmu-main = <&ipmmu_mm 9>;
-			power-domains = <&sysc 32>;
+			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
 			#iommu-cells = <1>;
 		};
 
@@ -865,7 +866,7 @@
 					  "ch20", "ch21", "ch22", "ch23",
 					  "ch24";
 			clocks = <&cpg CPG_MOD 812>;
-			power-domains = <&sysc 32>;
+			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
 			resets = <&cpg 812>;
 			phy-mode = "rgmii";
 			#address-cells = <1>;
@@ -880,7 +881,7 @@
 			interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&cpg CPG_MOD 916>, <&can_clk>;
 			clock-names = "clkp1", "can_clk";
-			power-domains = <&sysc 32>;
+			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
 			resets = <&cpg 916>;
 			status = "disabled";
 		};
@@ -892,7 +893,7 @@
 			interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&cpg CPG_MOD 915>, <&can_clk>;
 			clock-names = "clkp1", "can_clk";
-			power-domains = <&sysc 32>;
+			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
 			resets = <&cpg 915>;
 			status = "disabled";
 		};
@@ -903,7 +904,7 @@
 			#pwm-cells = <2>;
 			clocks = <&cpg CPG_MOD 523>;
 			resets = <&cpg 523>;
-			power-domains = <&sysc 32>;
+			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
 			status = "disabled";
 		};
 
@@ -913,7 +914,7 @@
 			#pwm-cells = <2>;
 			clocks = <&cpg CPG_MOD 523>;
 			resets = <&cpg 523>;
-			power-domains = <&sysc 32>;
+			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
 			status = "disabled";
 		};
 
@@ -923,7 +924,7 @@
 			#pwm-cells = <2>;
 			clocks = <&cpg CPG_MOD 523>;
 			resets = <&cpg 523>;
-			power-domains = <&sysc 32>;
+			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
 			status = "disabled";
 		};
 
@@ -933,7 +934,7 @@
 			#pwm-cells = <2>;
 			clocks = <&cpg CPG_MOD 523>;
 			resets = <&cpg 523>;
-			power-domains = <&sysc 32>;
+			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
 			status = "disabled";
 		};
 
@@ -943,7 +944,7 @@
 			#pwm-cells = <2>;
 			clocks = <&cpg CPG_MOD 523>;
 			resets = <&cpg 523>;
-			power-domains = <&sysc 32>;
+			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
 			status = "disabled";
 		};
 
@@ -953,7 +954,7 @@
 			#pwm-cells = <2>;
 			clocks = <&cpg CPG_MOD 523>;
 			resets = <&cpg 523>;
-			power-domains = <&sysc 32>;
+			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
 			status = "disabled";
 		};
 
@@ -963,7 +964,7 @@
 			#pwm-cells = <2>;
 			clocks = <&cpg CPG_MOD 523>;
 			resets = <&cpg 523>;
-			power-domains = <&sysc 32>;
+			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
 			status = "disabled";
 		};
 
@@ -979,7 +980,7 @@
 			dmas = <&dmac1 0x51>, <&dmac1 0x50>,
 			       <&dmac2 0x51>, <&dmac2 0x50>;
 			dma-names = "tx", "rx", "tx", "rx";
-			power-domains = <&sysc 32>;
+			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
 			resets = <&cpg 207>;
 			status = "disabled";
 		};
@@ -996,7 +997,7 @@
 			dmas = <&dmac1 0x53>, <&dmac1 0x52>,
 			       <&dmac2 0x53>, <&dmac2 0x52>;
 			dma-names = "tx", "rx", "tx", "rx";
-			power-domains = <&sysc 32>;
+			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
 			resets = <&cpg 206>;
 			status = "disabled";
 		};
@@ -1010,7 +1011,7 @@
 				 <&cpg CPG_CORE 19>,
 				 <&scif_clk>;
 			clock-names = "fck", "brg_int", "scif_clk";
-			power-domains = <&sysc 32>;
+			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
 			resets = <&cpg 310>;
 			status = "disabled";
 		};
@@ -1026,7 +1027,7 @@
 			clock-names = "fck", "brg_int", "scif_clk";
 			dmas = <&dmac0 0x57>, <&dmac0 0x56>;
 			dma-names = "tx", "rx";
-			power-domains = <&sysc 32>;
+			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
 			resets = <&cpg 204>;
 			status = "disabled";
 		};
@@ -1042,7 +1043,7 @@
 			clock-names = "fck", "brg_int", "scif_clk";
 			dmas = <&dmac0 0x59>, <&dmac0 0x58>;
 			dma-names = "tx", "rx";
-			power-domains = <&sysc 32>;
+			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
 			resets = <&cpg 203>;
 			status = "disabled";
 		};
@@ -1059,7 +1060,7 @@
 			dmas = <&dmac1 0x5b>, <&dmac1 0x5a>,
 			       <&dmac2 0x5b>, <&dmac2 0x5a>;
 			dma-names = "tx", "rx", "tx", "rx";
-			power-domains = <&sysc 32>;
+			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
 			resets = <&cpg 202>;
 			status = "disabled";
 		};
@@ -1073,7 +1074,7 @@
 			dmas = <&dmac1 0x41>, <&dmac1 0x40>,
 			       <&dmac2 0x41>, <&dmac2 0x40>;
 			dma-names = "tx", "rx", "tx", "rx";
-			power-domains = <&sysc 32>;
+			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
 			resets = <&cpg 211>;
 			#address-cells = <1>;
 			#size-cells = <0>;
@@ -1089,7 +1090,7 @@
 			dmas = <&dmac1 0x43>, <&dmac1 0x42>,
 			       <&dmac2 0x43>, <&dmac2 0x42>;
 			dma-names = "tx", "rx", "tx", "rx";
-			power-domains = <&sysc 32>;
+			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
 			resets = <&cpg 210>;
 			#address-cells = <1>;
 			#size-cells = <0>;
@@ -1104,7 +1105,7 @@
 			clocks = <&cpg CPG_MOD 209>;
 			dmas = <&dmac0 0x45>, <&dmac0 0x44>;
 			dma-names = "tx", "rx";
-			power-domains = <&sysc 32>;
+			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
 			resets = <&cpg 209>;
 			#address-cells = <1>;
 			#size-cells = <0>;
@@ -1119,7 +1120,7 @@
 			clocks = <&cpg CPG_MOD 208>;
 			dmas = <&dmac0 0x47>, <&dmac0 0x46>;
 			dma-names = "tx", "rx";
-			power-domains = <&sysc 32>;
+			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
 			resets = <&cpg 208>;
 			#address-cells = <1>;
 			#size-cells = <0>;
@@ -1175,7 +1176,7 @@
 				      "ctu.1", "ctu.0",
 				      "dvc.0", "dvc.1",
 				      "clk_a", "clk_b", "clk_c", "clk_i";
-			power-domains = <&sysc 32>;
+			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
 			resets = <&cpg 1005>,
 				 <&cpg 1006>, <&cpg 1007>,
 				 <&cpg 1008>, <&cpg 1009>,
@@ -1361,7 +1362,7 @@
 					"ch12", "ch13", "ch14", "ch15";
 			clocks = <&cpg CPG_MOD 502>;
 			clock-names = "fck";
-			power-domains = <&sysc 32>;
+			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
 			resets = <&cpg 502>;
 			#dma-cells = <1>;
 			dma-channels = <16>;
@@ -1395,7 +1396,7 @@
 					"ch12", "ch13", "ch14", "ch15";
 			clocks = <&cpg CPG_MOD 501>;
 			clock-names = "fck";
-			power-domains = <&sysc 32>;
+			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
 			resets = <&cpg 501>;
 			#dma-cells = <1>;
 			dma-channels = <16>;
@@ -1407,7 +1408,7 @@
 			reg = <0 0xee000000 0 0xc00>;
 			interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&cpg CPG_MOD 328>;
-			power-domains = <&sysc 32>;
+			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
 			resets = <&cpg 328>;
 			status = "disabled";
 		};
@@ -1418,7 +1419,7 @@
 			reg = <0 0xee020000 0 0x400>;
 			interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&cpg CPG_MOD 328>;
-			power-domains = <&sysc 32>;
+			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
 			resets = <&cpg 328>;
 			status = "disabled";
 		};
@@ -1430,7 +1431,7 @@
 			clocks = <&cpg CPG_MOD 703>;
 			phys = <&usb2_phy0>;
 			phy-names = "usb";
-			power-domains = <&sysc 32>;
+			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
 			resets = <&cpg 703>;
 			status = "disabled";
 		};
@@ -1442,7 +1443,7 @@
 			clocks = <&cpg CPG_MOD 702>;
 			phys = <&usb2_phy1>;
 			phy-names = "usb";
-			power-domains = <&sysc 32>;
+			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
 			resets = <&cpg 702>;
 			status = "disabled";
 		};
@@ -1455,7 +1456,7 @@
 			phys = <&usb2_phy0>;
 			phy-names = "usb";
 			companion = <&ohci0>;
-			power-domains = <&sysc 32>;
+			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
 			resets = <&cpg 703>;
 			status = "disabled";
 		};
@@ -1468,7 +1469,7 @@
 			phys = <&usb2_phy1>;
 			phy-names = "usb";
 			companion = <&ohci1>;
-			power-domains = <&sysc 32>;
+			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
 			resets = <&cpg 702>;
 			status = "disabled";
 		};
@@ -1479,7 +1480,7 @@
 			reg = <0 0xee080200 0 0x700>;
 			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&cpg CPG_MOD 703>;
-			power-domains = <&sysc 32>;
+			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
 			resets = <&cpg 703>;
 			#phy-cells = <0>;
 			status = "disabled";
@@ -1490,7 +1491,7 @@
 				     "renesas,rcar-gen3-usb2-phy";
 			reg = <0 0xee0a0200 0 0x700>;
 			clocks = <&cpg CPG_MOD 702>;
-			power-domains = <&sysc 32>;
+			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
 			resets = <&cpg 702>;
 			#phy-cells = <0>;
 			status = "disabled";
@@ -1503,7 +1504,7 @@
 			interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&cpg CPG_MOD 314>;
 			max-frequency = <200000000>;
-			power-domains = <&sysc 32>;
+			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
 			resets = <&cpg 314>;
 			status = "disabled";
 		};
@@ -1515,7 +1516,7 @@
 			interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&cpg CPG_MOD 313>;
 			max-frequency = <200000000>;
-			power-domains = <&sysc 32>;
+			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
 			resets = <&cpg 313>;
 			status = "disabled";
 		};
@@ -1527,7 +1528,7 @@
 			interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&cpg CPG_MOD 312>;
 			max-frequency = <200000000>;
-			power-domains = <&sysc 32>;
+			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
 			resets = <&cpg 312>;
 			status = "disabled";
 		};
@@ -1539,7 +1540,7 @@
 			interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&cpg CPG_MOD 311>;
 			max-frequency = <200000000>;
-			power-domains = <&sysc 32>;
+			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
 			resets = <&cpg 311>;
 			status = "disabled";
 		};
@@ -1557,7 +1558,7 @@
 					(GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>;
 			clocks = <&cpg CPG_MOD 408>;
 			clock-names = "clk";
-			power-domains = <&sysc 32>;
+			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
 			resets = <&cpg 408>;
 		};
 
@@ -1565,7 +1566,7 @@
 			compatible = "renesas,fcpf";
 			reg = <0 0xfe950000 0 0x200>;
 			clocks = <&cpg CPG_MOD 615>;
-			power-domains = <&sysc 14>;
+			power-domains = <&sysc R8A774A1_PD_A3VC>;
 			resets = <&cpg 615>;
 		};
 
@@ -1573,7 +1574,7 @@
 			compatible = "renesas,fcpv";
 			reg = <0 0xfe96f000 0 0x200>;
 			clocks = <&cpg CPG_MOD 607>;
-			power-domains = <&sysc 14>;
+			power-domains = <&sysc R8A774A1_PD_A3VC>;
 			resets = <&cpg 607>;
 		};
 
@@ -1581,7 +1582,7 @@
 			compatible = "renesas,fcpv";
 			reg = <0 0xfea27000 0 0x200>;
 			clocks = <&cpg CPG_MOD 603>;
-			power-domains = <&sysc 32>;
+			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
 			resets = <&cpg 603>;
 			iommus = <&ipmmu_vi0 8>;
 		};
@@ -1590,7 +1591,7 @@
 			compatible = "renesas,fcpv";
 			reg = <0 0xfea2f000 0 0x200>;
 			clocks = <&cpg CPG_MOD 602>;
-			power-domains = <&sysc 32>;
+			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
 			resets = <&cpg 602>;
 			iommus = <&ipmmu_vi0 9>;
 		};
@@ -1599,7 +1600,7 @@
 			compatible = "renesas,fcpv";
 			reg = <0 0xfea37000 0 0x200>;
 			clocks = <&cpg CPG_MOD 601>;
-			power-domains = <&sysc 32>;
+			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
 			resets = <&cpg 601>;
 			iommus = <&ipmmu_vi0 10>;
 		};
@@ -1608,7 +1609,7 @@
 			compatible = "renesas,fcpv";
 			reg = <0 0xfe9af000 0 0x200>;
 			clocks = <&cpg CPG_MOD 611>;
-			power-domains = <&sysc 14>;
+			power-domains = <&sysc R8A774A1_PD_A3VC>;
 			resets = <&cpg 611>;
 			iommus = <&ipmmu_vc0 19>;
 		};
-- 
2.7.4

[cip-dev] [PATCH 4.19.y-cip v2 53/57] arm64: dts: renesas: r8a774a1: Replace clock magic numbers

[Fabrizio Castro]

commit 8ebb50389eed04b989a0d5532f9208c338bf66b8 upstream.

Now that include/dt-bindings/clock/r8a774a1-cpg-mssr.h is in Linus'
master branch we can replace clock related magic numbers with the
corresponding labels.

Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
[simon: corrected whitespace]
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 38 +++++++++++++++----------------
 1 file changed, 19 insertions(+), 19 deletions(-)

diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
index 000b280..ed31054 100644
--- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
@@ -7,7 +7,7 @@
 
 #include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/clock/renesas-cpg-mssr.h>
+#include <dt-bindings/clock/r8a774a1-cpg-mssr.h>
 #include <dt-bindings/power/r8a774a1-sysc.h>
 
 / {
@@ -67,7 +67,7 @@
 			power-domains = <&sysc R8A774A1_PD_CA57_CPU0>;
 			next-level-cache = <&L2_CA57>;
 			enable-method = "psci";
-			clocks = <&cpg CPG_CORE 0>;
+			clocks = <&cpg CPG_CORE R8A774A1_CLK_Z>;
 		};
 
 		a57_1: cpu at 1 {
@@ -77,7 +77,7 @@
 			power-domains = <&sysc R8A774A1_PD_CA57_CPU1>;
 			next-level-cache = <&L2_CA57>;
 			enable-method = "psci";
-			clocks = <&cpg CPG_CORE 0>;
+			clocks = <&cpg CPG_CORE R8A774A1_CLK_Z>;
 		};
 
 		a53_0: cpu at 100 {
@@ -87,7 +87,7 @@
 			power-domains = <&sysc R8A774A1_PD_CA53_CPU0>;
 			next-level-cache = <&L2_CA53>;
 			enable-method = "psci";
-			clocks =<&cpg CPG_CORE 1>;
+			clocks = <&cpg CPG_CORE R8A774A1_CLK_Z2>;
 		};
 
 		a53_1: cpu at 101 {
@@ -97,7 +97,7 @@
 			power-domains = <&sysc R8A774A1_PD_CA53_CPU1>;
 			next-level-cache = <&L2_CA53>;
 			enable-method = "psci";
-			clocks =<&cpg CPG_CORE 1>;
+			clocks = <&cpg CPG_CORE R8A774A1_CLK_Z2>;
 		};
 
 		a53_2: cpu at 102 {
@@ -107,7 +107,7 @@
 			power-domains = <&sysc R8A774A1_PD_CA53_CPU2>;
 			next-level-cache = <&L2_CA53>;
 			enable-method = "psci";
-			clocks =<&cpg CPG_CORE 1>;
+			clocks = <&cpg CPG_CORE R8A774A1_CLK_Z2>;
 		};
 
 		a53_3: cpu at 103 {
@@ -117,7 +117,7 @@
 			power-domains = <&sysc R8A774A1_PD_CA53_CPU3>;
 			next-level-cache = <&L2_CA53>;
 			enable-method = "psci";
-			clocks =<&cpg CPG_CORE 1>;
+			clocks = <&cpg CPG_CORE R8A774A1_CLK_Z2>;
 		};
 
 		L2_CA57: cache-controller-0 {
@@ -515,7 +515,7 @@
 			reg = <0 0xe6540000 0 0x60>;
 			interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&cpg CPG_MOD 520>,
-				 <&cpg CPG_CORE 19>,
+				 <&cpg CPG_CORE R8A774A1_CLK_S3D1>,
 				 <&scif_clk>;
 			clock-names = "fck", "brg_int", "scif_clk";
 			dmas = <&dmac1 0x31>, <&dmac1 0x30>,
@@ -533,7 +533,7 @@
 			reg = <0 0xe6550000 0 0x60>;
 			interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&cpg CPG_MOD 519>,
-				 <&cpg CPG_CORE 19>,
+				 <&cpg CPG_CORE R8A774A1_CLK_S3D1>,
 				 <&scif_clk>;
 			clock-names = "fck", "brg_int", "scif_clk";
 			dmas = <&dmac1 0x33>, <&dmac1 0x32>,
@@ -551,7 +551,7 @@
 			reg = <0 0xe6560000 0 0x60>;
 			interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&cpg CPG_MOD 518>,
-				 <&cpg CPG_CORE 19>,
+				 <&cpg CPG_CORE R8A774A1_CLK_S3D1>,
 				 <&scif_clk>;
 			clock-names = "fck", "brg_int", "scif_clk";
 			dmas = <&dmac1 0x35>, <&dmac1 0x34>,
@@ -569,7 +569,7 @@
 			reg = <0 0xe66a0000 0 0x60>;
 			interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&cpg CPG_MOD 517>,
-				 <&cpg CPG_CORE 19>,
+				 <&cpg CPG_CORE R8A774A1_CLK_S3D1>,
 				 <&scif_clk>;
 			clock-names = "fck", "brg_int", "scif_clk";
 			dmas = <&dmac0 0x37>, <&dmac0 0x36>;
@@ -586,7 +586,7 @@
 			reg = <0 0xe66b0000 0 0x60>;
 			interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&cpg CPG_MOD 516>,
-				 <&cpg CPG_CORE 19>,
+				 <&cpg CPG_CORE R8A774A1_CLK_S3D1>,
 				 <&scif_clk>;
 			clock-names = "fck", "brg_int", "scif_clk";
 			dmas = <&dmac0 0x39>, <&dmac0 0x38>;
@@ -974,7 +974,7 @@
 			reg = <0 0xe6e60000 0 0x40>;
 			interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&cpg CPG_MOD 207>,
-				 <&cpg CPG_CORE 19>,
+				 <&cpg CPG_CORE R8A774A1_CLK_S3D1>,
 				 <&scif_clk>;
 			clock-names = "fck", "brg_int", "scif_clk";
 			dmas = <&dmac1 0x51>, <&dmac1 0x50>,
@@ -991,7 +991,7 @@
 			reg = <0 0xe6e68000 0 0x40>;
 			interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&cpg CPG_MOD 206>,
-				 <&cpg CPG_CORE 19>,
+				 <&cpg CPG_CORE R8A774A1_CLK_S3D1>,
 				 <&scif_clk>;
 			clock-names = "fck", "brg_int", "scif_clk";
 			dmas = <&dmac1 0x53>, <&dmac1 0x52>,
@@ -1008,7 +1008,7 @@
 			reg = <0 0xe6e88000 0 0x40>;
 			interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&cpg CPG_MOD 310>,
-				 <&cpg CPG_CORE 19>,
+				 <&cpg CPG_CORE R8A774A1_CLK_S3D1>,
 				 <&scif_clk>;
 			clock-names = "fck", "brg_int", "scif_clk";
 			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
@@ -1022,7 +1022,7 @@
 			reg = <0 0xe6c50000 0 0x40>;
 			interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&cpg CPG_MOD 204>,
-				 <&cpg CPG_CORE 19>,
+				 <&cpg CPG_CORE R8A774A1_CLK_S3D1>,
 				 <&scif_clk>;
 			clock-names = "fck", "brg_int", "scif_clk";
 			dmas = <&dmac0 0x57>, <&dmac0 0x56>;
@@ -1038,7 +1038,7 @@
 			reg = <0 0xe6c40000 0 0x40>;
 			interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&cpg CPG_MOD 203>,
-				 <&cpg CPG_CORE 19>,
+				 <&cpg CPG_CORE R8A774A1_CLK_S3D1>,
 				 <&scif_clk>;
 			clock-names = "fck", "brg_int", "scif_clk";
 			dmas = <&dmac0 0x59>, <&dmac0 0x58>;
@@ -1054,7 +1054,7 @@
 			reg = <0 0xe6f30000 0 0x40>;
 			interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&cpg CPG_MOD 202>,
-				 <&cpg CPG_CORE 19>,
+				 <&cpg CPG_CORE R8A774A1_CLK_S3D1>,
 				 <&scif_clk>;
 			clock-names = "fck", "brg_int", "scif_clk";
 			dmas = <&dmac1 0x5b>, <&dmac1 0x5a>,
@@ -1164,7 +1164,7 @@
 				 <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
 				 <&audio_clk_a>, <&audio_clk_b>,
 				 <&audio_clk_c>,
-				 <&cpg CPG_CORE 10>;
+				 <&cpg CPG_CORE R8A774A1_CLK_S0D4>;
 			clock-names = "ssi-all",
 				      "ssi.9", "ssi.8", "ssi.7", "ssi.6",
 				      "ssi.5", "ssi.4", "ssi.3", "ssi.2",
-- 
2.7.4

[cip-dev] [PATCH 4.19.y-cip v2 54/57] arm64: dts: renesas: r8a774a1: Enable DMA for SCIF2

[Fabrizio Castro]

From: Geert Uytterhoeven <geert+renesas@glider.be>

commit 2bb7b675248c3ad11ada0ce3d0f6d480ec8cc87b upstream.

SCIF2 on RZ/G2M can be used with both DMAC1 and DMAC2.

Fixes: 3a3933a4fa36430a ("arm64: dts: renesas: r8a774a1: Add SCIF and HSCIF nodes")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
---
 arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
index ed31054..61258ab 100644
--- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
@@ -1011,6 +1011,9 @@
 				 <&cpg CPG_CORE R8A774A1_CLK_S3D1>,
 				 <&scif_clk>;
 			clock-names = "fck", "brg_int", "scif_clk";
+			dmas = <&dmac1 0x13>, <&dmac1 0x12>,
+			       <&dmac2 0x13>, <&dmac2 0x12>;
+			dma-names = "tx", "rx", "tx", "rx";
 			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
 			resets = <&cpg 310>;
 			status = "disabled";
-- 
2.7.4

[cip-dev] [PATCH 4.19.y-cip v2 55/57] arm64: dts: renesas: r8a774a1: Fix hsusb reg size

[Fabrizio Castro]

commit 173c3b3ca2130af4d69b1b25d95c52709fbd4a2f upstream.

HS-USB has registers outside the currently specified memory area,
therefore change the definition accordingly.

Fixes: ed898d4fc19d ("arm64: dts: renesas: r8a774a1: Add USB-DMAC and HSUSB device nodes")
Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Chris Paterson <Chris.Paterson2@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
index 61258ab..1969649 100644
--- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
@@ -599,7 +599,7 @@
 		hsusb: usb at e6590000 {
 			compatible = "renesas,usbhs-r8a774a1",
 				     "renesas,rcar-gen3-usbhs";
-			reg = <0 0xe6590000 0 0x100>;
+			reg = <0 0xe6590000 0 0x200>;
 			interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&cpg CPG_MOD 704>;
 			dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
-- 
2.7.4

[cip-dev] [PATCH 4.19.y-cip v2 56/57] arm64: dts: Remove inconsistent use of 'arm, armv8' compatible string

[Fabrizio Castro]

From: Rob Herring <robh@kernel.org>

commit 31af04cd60d3162a58213363fd740a2b0cf0a08e upstream.

The 'arm,armv8' compatible string is only for software models. It adds
little value otherwise and is inconsistently used as a fallback on some
platforms. Remove it from those platforms.

This fixes warnings generated by the DT schema.

Reported-by: Michal Simek <michal.simek@xilinx.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Acked-by: Antoine Tenart <antoine.tenart@bootlin.com>
Acked-by: Nishanth Menon <nm@ti.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Acked-by: Chanho Min <chanho.min@lge.com>
Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Acked-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Simon Horman <horms+renesas@verge.net.au>
Acked-by: Tero Kristo <t-kristo@ti.com>
Acked-by: Wei Xu <xuwei5@hisilicon.com>
Acked-by: Liviu Dudau <liviu.dudau@arm.com>
Acked-by: Matthias Brugger <matthias.bgg@gmail.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Scott Branden <scott.branden@broadcom.com>
Acked-by: Kevin Hilman <khilman@baylibre.com>
Acked-by: Chunyan Zhang <zhang.lyra@gmail.com>
Acked-by: Robert Richter <rrichter@cavium.com>
Acked-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com>
Acked-by: Dinh Nguyen <dinguyen@kernel.org>
Signed-off-by: Rob Herring <robh@kernel.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
[fab: dropped changes not related to r8a774a1.dtsi]
Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
---
 arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
index 1969649..a77de9e 100644
--- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
@@ -61,7 +61,7 @@
 		#size-cells = <0>;
 
 		a57_0: cpu at 0 {
-			compatible = "arm,cortex-a57", "arm,armv8";
+			compatible = "arm,cortex-a57";
 			reg = <0x0>;
 			device_type = "cpu";
 			power-domains = <&sysc R8A774A1_PD_CA57_CPU0>;
@@ -71,7 +71,7 @@
 		};
 
 		a57_1: cpu at 1 {
-			compatible = "arm,cortex-a57", "arm,armv8";
+			compatible = "arm,cortex-a57";
 			reg = <0x1>;
 			device_type = "cpu";
 			power-domains = <&sysc R8A774A1_PD_CA57_CPU1>;
@@ -81,7 +81,7 @@
 		};
 
 		a53_0: cpu at 100 {
-			compatible = "arm,cortex-a53", "arm,armv8";
+			compatible = "arm,cortex-a53";
 			reg = <0x100>;
 			device_type = "cpu";
 			power-domains = <&sysc R8A774A1_PD_CA53_CPU0>;
@@ -91,7 +91,7 @@
 		};
 
 		a53_1: cpu at 101 {
-			compatible = "arm,cortex-a53", "arm,armv8";
+			compatible = "arm,cortex-a53";
 			reg = <0x101>;
 			device_type = "cpu";
 			power-domains = <&sysc R8A774A1_PD_CA53_CPU1>;
@@ -101,7 +101,7 @@
 		};
 
 		a53_2: cpu at 102 {
-			compatible = "arm,cortex-a53", "arm,armv8";
+			compatible = "arm,cortex-a53";
 			reg = <0x102>;
 			device_type = "cpu";
 			power-domains = <&sysc R8A774A1_PD_CA53_CPU2>;
@@ -111,7 +111,7 @@
 		};
 
 		a53_3: cpu at 103 {
-			compatible = "arm,cortex-a53", "arm,armv8";
+			compatible = "arm,cortex-a53";
 			reg = <0x103>;
 			device_type = "cpu";
 			power-domains = <&sysc R8A774A1_PD_CA53_CPU3>;
-- 
2.7.4

[cip-dev] [PATCH 4.19.y-cip v2 57/57] arm64: dts: renesas: r8a774a1: Add clkp2 clock to CAN nodes

[Fabrizio Castro]

commit eccc40002972c4248652befa4513c76cdb350a5c upstream.

According to the latest information, clkp2 is available on RZ/G2.
Modify CAN0 and CAN1 nodes accordingly.

Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Chris Paterson <Chris.Paterson2@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 12 ++++++++----
 1 file changed, 8 insertions(+), 4 deletions(-)

diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
index a77de9e..12f28aa 100644
--- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
@@ -879,8 +879,10 @@
 				     "renesas,rcar-gen3-can";
 			reg = <0 0xe6c30000 0 0x1000>;
 			interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&cpg CPG_MOD 916>, <&can_clk>;
-			clock-names = "clkp1", "can_clk";
+			clocks = <&cpg CPG_MOD 916>,
+				 <&cpg CPG_CORE R8A774A1_CLK_CANFD>,
+				 <&can_clk>;
+			clock-names = "clkp1", "clkp2", "can_clk";
 			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
 			resets = <&cpg 916>;
 			status = "disabled";
@@ -891,8 +893,10 @@
 				     "renesas,rcar-gen3-can";
 			reg = <0 0xe6c38000 0 0x1000>;
 			interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&cpg CPG_MOD 915>, <&can_clk>;
-			clock-names = "clkp1", "can_clk";
+			clocks = <&cpg CPG_MOD 915>,
+				 <&cpg CPG_CORE R8A774A1_CLK_CANFD>,
+				 <&can_clk>;
+			clock-names = "clkp1", "clkp2", "can_clk";
 			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
 			resets = <&cpg 915>;
 			status = "disabled";
-- 
2.7.4

[cip-dev] [PATCH 4.19.y-cip v2 00/57] Add basic RZ/G2M SoC support

[nobuhiro1.iwamatsu at toshiba.co.jp]

Hi Fabrizio,

Thanks for your patch.
I will check these.

Best regards,
  Nobuhiro

> -----Original Message-----
> From: cip-dev-bounces at lists.cip-project.org
> [mailto:cip-dev-bounces at lists.cip-project.org] On Behalf Of Fabrizio
> Castro
> Sent: Wednesday, August 28, 2019 10:32 PM
> To: cip-dev at lists.cip-project.org
> Cc: Biju Das <biju.das@bp.renesas.com>
> Subject: [cip-dev] [PATCH 4.19.y-cip v2 00/57] Add basic RZ/G2M SoC
> support
> 
> Dear All,
> 
> this series aims at providing basic RZ/G2M SoC dtsi support.
> 
> v1->v2:
> * dropped "serial: sh-sci: Fix TX DMA buffer flushing and workqueue races"
> * dropped "serial: sh-sci: Terminate TX DMA during buffer flushing"
> * dropped "dmaengine: rcar-dmac: Reject zero-length slave DMA requests"
> 
> Thanks,
> Fab
> 
> Biju Das (13):
>   dt-bindings: dmaengine: usb-dmac: Add binding for r8a774a1
>   arm64: dts: renesas: Initial r8a774a1 SoC device tree
>   arm64: dts: renesas: r8a774a1: Add SYS-DMAC controller nodes
>   arm64: dts: renesas: r8a774a1: Add INTC-EX device node
>   arm64: dts: renesas: r8a774a1: Add RWDT node
>   arm64: dts: renesas: r8a774a1: Add I2C and IIC-DVFS support
>   arm64: dts: renesas: r8a774a1: Add RZ/G2M thermal support
>   arm64: dts: renesas: r8a774a1: Add all MSIOF nodes
>   arm64: dts: renesas: r8a774a1: Add Cortex-A53 CPU cores
>   arm64: dts: renesas: r8a774a1: Add audio support
>   arm64: dts: renesas: r8a774a1: Add USB2.0 phy and host(EHCI/OHCI)
>     device nodes
>   arm64: dts: renesas: r8a774a1: Add USB-DMAC and HSUSB device nodes
>   arm64: dts: renesas: r8a774a1: Add USB3.0 device nodes
> 
> Chris Paterson (1):
>   arm64: dts: renesas: r8a774a1: Add CAN nodes
> 
> Enrico Weigelt, metux IT consult (1):
>   gpio: rcar: Pedantic formatting
> 
> Fabrizio Castro (21):
>   dt-bindings: can: rcar_can: Add r8a774a1 support
>   dt-bindings: can: rcar_can: Fix RZ/G2 CAN clocks
>   dt-bindings: can: rcar_can: Add r8a774c0 support
>   dt-bindings: rcar-gen3-phy-usb3: Add r8a774a1 support
>   dt-bindings: usb-xhci: Add r8a774a1 support
>   dt-bindings: usb-xhci: Add r8a774c0 support
>   dt-bindings: usb: renesas_usbhs: Add r8a774a1 support
>   dt-bindings: thermal: rcar-gen3-thermal: Add r8a774a1 support
>   thermal: rcar_gen3_thermal: Add r8a774a1 support
>   arm64: dts: renesas: r8a774a1: Add SCIF and HSCIF nodes
>   arm64: dts: renesas: r8a774a1: Add Ethernet AVB node
>   arm64: dts: renesas: r8a774a1: Add pinctrl device node
>   arm64: dts: renesas: r8a774a1: Add GPIO device nodes
>   arm64: dts: renesas: r8a774a1: Add SDHI nodes
>   arm64: dts: renesas: r8a774a1: Add IPMMU device nodes
>   arm64: dts: renesas: r8a774a1: Add PWM device nodes
>   arm64: dts: renesas: r8a774a1: Add FCPF and FCPV instances
>   arm64: dts: renesas: r8a774a1: Replace power magic numbers
>   arm64: dts: renesas: r8a774a1: Replace clock magic numbers
>   arm64: dts: renesas: r8a774a1: Fix hsusb reg size
>   arm64: dts: renesas: r8a774a1: Add clkp2 clock to CAN nodes
> 
> Geert Uytterhoeven (12):
>   clk: renesas: cpg-mssr: Use genpd of_node instead of local copy
>   clk: renesas: cpg-mssr: Remove error messages on out-of-memory
>     conditions
>   soc: renesas: rcar-sysc: Remove rcar_sysc_power_{down,up}() helpers
>   soc: renesas: rcar-sysc: Merge PM Domain registration and linking
>   soc: renesas: rcar-sysc: Fix power domain control after system resume
>   serial: sh-sci: Fix crash in rx_timer_fn() on PIO fallback
>   serial: sh-sci: Extract sci_dma_rx_chan_invalidate()
>   serial: sh-sci: Extract sci_dma_rx_reenable_irq()
>   serial: sh-sci: Fix fallback to PIO in sci_dma_rx_complete()
>   arm64: dts: renesas: Fix whitespace around assignments
>   arm64: dts: renesas: Remove unneeded status from thermal nodes
>   arm64: dts: renesas: r8a774a1: Enable DMA for SCIF2
> 
> Hiroyuki Yokoyama (1):
>   dmaengine: rcar-dmac: Update copyright information
> 
> Kazuya Mizuguchi (1):
>   ravb: remove tx buffer addr 4byte alilgnment restriction for R-Car
>     Gen3
> 
> Niklas S?derlund (1):
>   mmc: renesas_sdhi_internal_dmac: set scatter/gather max segment size
> 
> Rob Herring (1):
>   arm64: dts: Remove inconsistent use of 'arm,armv8' compatible string
> 
> Sergei Shtylyov (1):
>   spi: sh-msiof: fix deferred probing
> 
> Simon Horman (1):
>   ravb: Avoid unsupported internal delay mode for R-Car E3/D3
> 
> Vladimir Zapolskiy (2):
>   gpio: rcar: reference device instead of platform device
>   gpio: rcar: select General Output Register to set output states
> 
> Wolfram Sang (1):
>   dmaengine: rcar-dmac: set scatter/gather max segment size
> 
>  .../devicetree/bindings/dma/renesas,usb-dmac.txt   |    1 +
>  .../devicetree/bindings/net/can/rcar_can.txt       |    9 +-
>  .../devicetree/bindings/phy/rcar-gen3-phy-usb3.txt |   10 +-
>  .../bindings/thermal/rcar-gen3-thermal.txt         |    1 +
>  .../devicetree/bindings/usb/renesas_usbhs.txt      |    3 +-
>  Documentation/devicetree/bindings/usb/usb-xhci.txt |    5 +-
>  arch/arm64/boot/dts/renesas/r8a774a1.dtsi          | 1695
> ++++++++++++++++++++
>  drivers/clk/renesas/renesas-cpg-mssr.c             |   12 +-
>  drivers/dma/sh/rcar-dmac.c                         |    7 +-
>  drivers/gpio/gpio-rcar.c                           |   38 +-
>  drivers/mmc/host/renesas_sdhi_internal_dmac.c      |    8 +
>  drivers/net/ethernet/renesas/ravb.h                |    6 +-
>  drivers/net/ethernet/renesas/ravb_main.c           |  158 +-
>  drivers/soc/renesas/rcar-sysc.c                    |   65 +-
>  drivers/spi/spi-sh-msiof.c                         |    4 +-
>  drivers/thermal/rcar_gen3_thermal.c                |    1 +
>  drivers/tty/serial/sh-sci.c                        |   47 +-
>  17 files changed, 1911 insertions(+), 159 deletions(-)  create mode
> 100644 arch/arm64/boot/dts/renesas/r8a774a1.dtsi
> 
> --
> 2.7.4
> 
> _______________________________________________
> cip-dev mailing list
> cip-dev at lists.cip-project.org
> https://lists.cip-project.org/mailman/listinfo/cip-dev

[cip-dev] [PATCH 4.19.y-cip v2 52/57] arm64: dts: renesas: r8a774a1: Replace power magic numbers

[nobuhiro1.iwamatsu at toshiba.co.jp]

Hi,

Fix for VIN (and others?) has been removed from original commit.
Please add this to the commit message.

https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=aeee3d9cb776542f5700425f703fa78c70a1dcd0

Best regards,
  Nobuhiro

> -----Original Message-----
> From: cip-dev-bounces at lists.cip-project.org
> [mailto:cip-dev-bounces at lists.cip-project.org] On Behalf Of Fabrizio
> Castro
> Sent: Wednesday, August 28, 2019 10:33 PM
> To: cip-dev at lists.cip-project.org
> Cc: Biju Das <biju.das@bp.renesas.com>
> Subject: [cip-dev] [PATCH 4.19.y-cip v2 52/57] arm64: dts: renesas:
> r8a774a1: Replace power magic numbers
> 
> commit aeee3d9cb776542f5700425f703fa78c70a1dcd0 upstream.
> 
> Now that include/dt-bindings/power/r8a774a1-sysc.h is in Linus'
> master branch we can replace power related magic numbers with the
> corresponding labels.
> 
> Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
> ---
>  arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 181
> +++++++++++++++---------------
>  1 file changed, 91 insertions(+), 90 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
> b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
> index a4817a0..000b280 100644
> --- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
> @@ -8,6 +8,7 @@
>  #include <dt-bindings/interrupt-controller/irq.h>
>  #include <dt-bindings/interrupt-controller/arm-gic.h>
>  #include <dt-bindings/clock/renesas-cpg-mssr.h>
> +#include <dt-bindings/power/r8a774a1-sysc.h>
> 
>  / {
>  	compatible = "renesas,r8a774a1";
> @@ -63,7 +64,7 @@
>  			compatible = "arm,cortex-a57", "arm,armv8";
>  			reg = <0x0>;
>  			device_type = "cpu";
> -			power-domains = <&sysc 0>;
> +			power-domains = <&sysc R8A774A1_PD_CA57_CPU0>;
>  			next-level-cache = <&L2_CA57>;
>  			enable-method = "psci";
>  			clocks = <&cpg CPG_CORE 0>;
> @@ -73,7 +74,7 @@
>  			compatible = "arm,cortex-a57", "arm,armv8";
>  			reg = <0x1>;
>  			device_type = "cpu";
> -			power-domains = <&sysc 1>;
> +			power-domains = <&sysc R8A774A1_PD_CA57_CPU1>;
>  			next-level-cache = <&L2_CA57>;
>  			enable-method = "psci";
>  			clocks = <&cpg CPG_CORE 0>;
> @@ -83,7 +84,7 @@
>  			compatible = "arm,cortex-a53", "arm,armv8";
>  			reg = <0x100>;
>  			device_type = "cpu";
> -			power-domains = <&sysc 5>;
> +			power-domains = <&sysc R8A774A1_PD_CA53_CPU0>;
>  			next-level-cache = <&L2_CA53>;
>  			enable-method = "psci";
>  			clocks =<&cpg CPG_CORE 1>;
> @@ -93,7 +94,7 @@
>  			compatible = "arm,cortex-a53", "arm,armv8";
>  			reg = <0x101>;
>  			device_type = "cpu";
> -			power-domains = <&sysc 6>;
> +			power-domains = <&sysc R8A774A1_PD_CA53_CPU1>;
>  			next-level-cache = <&L2_CA53>;
>  			enable-method = "psci";
>  			clocks =<&cpg CPG_CORE 1>;
> @@ -103,7 +104,7 @@
>  			compatible = "arm,cortex-a53", "arm,armv8";
>  			reg = <0x102>;
>  			device_type = "cpu";
> -			power-domains = <&sysc 7>;
> +			power-domains = <&sysc R8A774A1_PD_CA53_CPU2>;
>  			next-level-cache = <&L2_CA53>;
>  			enable-method = "psci";
>  			clocks =<&cpg CPG_CORE 1>;
> @@ -113,7 +114,7 @@
>  			compatible = "arm,cortex-a53", "arm,armv8";
>  			reg = <0x103>;
>  			device_type = "cpu";
> -			power-domains = <&sysc 8>;
> +			power-domains = <&sysc R8A774A1_PD_CA53_CPU3>;
>  			next-level-cache = <&L2_CA53>;
>  			enable-method = "psci";
>  			clocks =<&cpg CPG_CORE 1>;
> @@ -121,14 +122,14 @@
> 
>  		L2_CA57: cache-controller-0 {
>  			compatible = "cache";
> -			power-domains = <&sysc 12>;
> +			power-domains = <&sysc R8A774A1_PD_CA57_SCU>;
>  			cache-unified;
>  			cache-level = <2>;
>  		};
> 
>  		L2_CA53: cache-controller-1 {
>  			compatible = "cache";
> -			power-domains = <&sysc 21>;
> +			power-domains = <&sysc R8A774A1_PD_CA53_SCU>;
>  			cache-unified;
>  			cache-level = <2>;
>  		};
> @@ -195,7 +196,7 @@
>  				     "renesas,rcar-gen3-wdt";
>  			reg = <0 0xe6020000 0 0x0c>;
>  			clocks = <&cpg CPG_MOD 402>;
> -			power-domains = <&sysc 32>;
> +			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
>  			resets = <&cpg 402>;
>  			status = "disabled";
>  		};
> @@ -211,7 +212,7 @@
>  			#interrupt-cells = <2>;
>  			interrupt-controller;
>  			clocks = <&cpg CPG_MOD 912>;
> -			power-domains = <&sysc 32>;
> +			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
>  			resets = <&cpg 912>;
>  		};
> 
> @@ -226,7 +227,7 @@
>  			#interrupt-cells = <2>;
>  			interrupt-controller;
>  			clocks = <&cpg CPG_MOD 911>;
> -			power-domains = <&sysc 32>;
> +			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
>  			resets = <&cpg 911>;
>  		};
> 
> @@ -241,7 +242,7 @@
>  			#interrupt-cells = <2>;
>  			interrupt-controller;
>  			clocks = <&cpg CPG_MOD 910>;
> -			power-domains = <&sysc 32>;
> +			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
>  			resets = <&cpg 910>;
>  		};
> 
> @@ -256,7 +257,7 @@
>  			#interrupt-cells = <2>;
>  			interrupt-controller;
>  			clocks = <&cpg CPG_MOD 909>;
> -			power-domains = <&sysc 32>;
> +			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
>  			resets = <&cpg 909>;
>  		};
> 
> @@ -271,7 +272,7 @@
>  			#interrupt-cells = <2>;
>  			interrupt-controller;
>  			clocks = <&cpg CPG_MOD 908>;
> -			power-domains = <&sysc 32>;
> +			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
>  			resets = <&cpg 908>;
>  		};
> 
> @@ -286,7 +287,7 @@
>  			#interrupt-cells = <2>;
>  			interrupt-controller;
>  			clocks = <&cpg CPG_MOD 907>;
> -			power-domains = <&sysc 32>;
> +			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
>  			resets = <&cpg 907>;
>  		};
> 
> @@ -301,7 +302,7 @@
>  			#interrupt-cells = <2>;
>  			interrupt-controller;
>  			clocks = <&cpg CPG_MOD 906>;
> -			power-domains = <&sysc 32>;
> +			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
>  			resets = <&cpg 906>;
>  		};
> 
> @@ -316,7 +317,7 @@
>  			#interrupt-cells = <2>;
>  			interrupt-controller;
>  			clocks = <&cpg CPG_MOD 905>;
> -			power-domains = <&sysc 32>;
> +			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
>  			resets = <&cpg 905>;
>  		};
> 
> @@ -355,7 +356,7 @@
>  				     <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
>  				     <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
>  			clocks = <&cpg CPG_MOD 522>;
> -			power-domains = <&sysc 32>;
> +			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
>  			resets = <&cpg 522>;
>  			#thermal-sensor-cells = <1>;
>  		};
> @@ -372,7 +373,7 @@
>  				      GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH
>  				      GIC_SPI 161
> IRQ_TYPE_LEVEL_HIGH>;
>  			clocks = <&cpg CPG_MOD 407>;
> -			power-domains = <&sysc 32>;
> +			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
>  			resets = <&cpg 407>;
>  		};
> 
> @@ -384,7 +385,7 @@
>  			reg = <0 0xe6500000 0 0x40>;
>  			interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
>  			clocks = <&cpg CPG_MOD 931>;
> -			power-domains = <&sysc 32>;
> +			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
>  			resets = <&cpg 931>;
>  			dmas = <&dmac1 0x91>, <&dmac1 0x90>,
>  			       <&dmac2 0x91>, <&dmac2 0x90>; @@ -401,7
> +402,7 @@
>  			reg = <0 0xe6508000 0 0x40>;
>  			interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
>  			clocks = <&cpg CPG_MOD 930>;
> -			power-domains = <&sysc 32>;
> +			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
>  			resets = <&cpg 930>;
>  			dmas = <&dmac1 0x93>, <&dmac1 0x92>,
>  			       <&dmac2 0x93>, <&dmac2 0x92>; @@ -418,7
> +419,7 @@
>  			reg = <0 0xe6510000 0 0x40>;
>  			interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
>  			clocks = <&cpg CPG_MOD 929>;
> -			power-domains = <&sysc 32>;
> +			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
>  			resets = <&cpg 929>;
>  			dmas = <&dmac1 0x95>, <&dmac1 0x94>,
>  			       <&dmac2 0x95>, <&dmac2 0x94>; @@ -435,7
> +436,7 @@
>  			reg = <0 0xe66d0000 0 0x40>;
>  			interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
>  			clocks = <&cpg CPG_MOD 928>;
> -			power-domains = <&sysc 32>;
> +			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
>  			resets = <&cpg 928>;
>  			dmas = <&dmac0 0x97>, <&dmac0 0x96>;
>  			dma-names = "tx", "rx";
> @@ -451,7 +452,7 @@
>  			reg = <0 0xe66d8000 0 0x40>;
>  			interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
>  			clocks = <&cpg CPG_MOD 927>;
> -			power-domains = <&sysc 32>;
> +			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
>  			resets = <&cpg 927>;
>  			dmas = <&dmac0 0x99>, <&dmac0 0x98>;
>  			dma-names = "tx", "rx";
> @@ -467,7 +468,7 @@
>  			reg = <0 0xe66e0000 0 0x40>;
>  			interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
>  			clocks = <&cpg CPG_MOD 919>;
> -			power-domains = <&sysc 32>;
> +			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
>  			resets = <&cpg 919>;
>  			dmas = <&dmac0 0x9b>, <&dmac0 0x9a>;
>  			dma-names = "tx", "rx";
> @@ -483,7 +484,7 @@
>  			reg = <0 0xe66e8000 0 0x40>;
>  			interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
>  			clocks = <&cpg CPG_MOD 918>;
> -			power-domains = <&sysc 32>;
> +			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
>  			resets = <&cpg 918>;
>  			dmas = <&dmac0 0x9d>, <&dmac0 0x9c>;
>  			dma-names = "tx", "rx";
> @@ -500,7 +501,7 @@
>  			reg = <0 0xe60b0000 0 0x425>;
>  			interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
>  			clocks = <&cpg CPG_MOD 926>;
> -			power-domains = <&sysc 32>;
> +			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
>  			resets = <&cpg 926>;
>  			dmas = <&dmac0 0x11>, <&dmac0 0x10>;
>  			dma-names = "tx", "rx";
> @@ -520,7 +521,7 @@
>  			dmas = <&dmac1 0x31>, <&dmac1 0x30>,
>  			       <&dmac2 0x31>, <&dmac2 0x30>;
>  			dma-names = "tx", "rx", "tx", "rx";
> -			power-domains = <&sysc 32>;
> +			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
>  			resets = <&cpg 520>;
>  			status = "disabled";
>  		};
> @@ -538,7 +539,7 @@
>  			dmas = <&dmac1 0x33>, <&dmac1 0x32>,
>  			       <&dmac2 0x33>, <&dmac2 0x32>;
>  			dma-names = "tx", "rx", "tx", "rx";
> -			power-domains = <&sysc 32>;
> +			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
>  			resets = <&cpg 519>;
>  			status = "disabled";
>  		};
> @@ -556,7 +557,7 @@
>  			dmas = <&dmac1 0x35>, <&dmac1 0x34>,
>  			       <&dmac2 0x35>, <&dmac2 0x34>;
>  			dma-names = "tx", "rx", "tx", "rx";
> -			power-domains = <&sysc 32>;
> +			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
>  			resets = <&cpg 518>;
>  			status = "disabled";
>  		};
> @@ -573,7 +574,7 @@
>  			clock-names = "fck", "brg_int", "scif_clk";
>  			dmas = <&dmac0 0x37>, <&dmac0 0x36>;
>  			dma-names = "tx", "rx";
> -			power-domains = <&sysc 32>;
> +			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
>  			resets = <&cpg 517>;
>  			status = "disabled";
>  		};
> @@ -590,7 +591,7 @@
>  			clock-names = "fck", "brg_int", "scif_clk";
>  			dmas = <&dmac0 0x39>, <&dmac0 0x38>;
>  			dma-names = "tx", "rx";
> -			power-domains = <&sysc 32>;
> +			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
>  			resets = <&cpg 516>;
>  			status = "disabled";
>  		};
> @@ -607,7 +608,7 @@
>  			renesas,buswait = <11>;
>  			phys = <&usb2_phy0>;
>  			phy-names = "usb";
> -			power-domains = <&sysc 32>;
> +			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
>  			resets = <&cpg 704>;
>  			status = "disabled";
>  		};
> @@ -620,7 +621,7 @@
>  				      GIC_SPI 109
> IRQ_TYPE_LEVEL_HIGH>;
>  			interrupt-names = "ch0", "ch1";
>  			clocks = <&cpg CPG_MOD 330>;
> -			power-domains = <&sysc 32>;
> +			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
>  			resets = <&cpg 330>;
>  			#dma-cells = <1>;
>  			dma-channels = <2>;
> @@ -634,7 +635,7 @@
>  				      GIC_SPI 110
> IRQ_TYPE_LEVEL_HIGH>;
>  			interrupt-names = "ch0", "ch1";
>  			clocks = <&cpg CPG_MOD 331>;
> -			power-domains = <&sysc 32>;
> +			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
>  			resets = <&cpg 331>;
>  			#dma-cells = <1>;
>  			dma-channels = <2>;
> @@ -647,7 +648,7 @@
>  			clocks = <&cpg CPG_MOD 328>, <&usb3s0_clk>,
>  				 <&usb_extal_clk>;
>  			clock-names = "usb3-if", "usb3s_clk",
> "usb_extal";
> -			power-domains = <&sysc 32>;
> +			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
>  			resets = <&cpg 328>;
>  			#phy-cells = <0>;
>  			status = "disabled";
> @@ -681,7 +682,7 @@
>  					"ch12", "ch13", "ch14", "ch15";
>  			clocks = <&cpg CPG_MOD 219>;
>  			clock-names = "fck";
> -			power-domains = <&sysc 32>;
> +			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
>  			resets = <&cpg 219>;
>  			#dma-cells = <1>;
>  			dma-channels = <16>;
> @@ -715,7 +716,7 @@
>  					"ch12", "ch13", "ch14", "ch15";
>  			clocks = <&cpg CPG_MOD 218>;
>  			clock-names = "fck";
> -			power-domains = <&sysc 32>;
> +			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
>  			resets = <&cpg 218>;
>  			#dma-cells = <1>;
>  			dma-channels = <16>;
> @@ -749,7 +750,7 @@
>  					"ch12", "ch13", "ch14", "ch15";
>  			clocks = <&cpg CPG_MOD 217>;
>  			clock-names = "fck";
> -			power-domains = <&sysc 32>;
> +			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
>  			resets = <&cpg 217>;
>  			#dma-cells = <1>;
>  			dma-channels = <16>;
> @@ -759,7 +760,7 @@
>  			compatible = "renesas,ipmmu-r8a774a1";
>  			reg = <0 0xe6740000 0 0x1000>;
>  			renesas,ipmmu-main = <&ipmmu_mm 0>;
> -			power-domains = <&sysc 32>;
> +			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
>  			#iommu-cells = <1>;
>  		};
> 
> @@ -767,7 +768,7 @@
>  			compatible = "renesas,ipmmu-r8a774a1";
>  			reg = <0 0xe7740000 0 0x1000>;
>  			renesas,ipmmu-main = <&ipmmu_mm 1>;
> -			power-domains = <&sysc 32>;
> +			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
>  			#iommu-cells = <1>;
>  		};
> 
> @@ -775,7 +776,7 @@
>  			compatible = "renesas,ipmmu-r8a774a1";
>  			reg = <0 0xe6570000 0 0x1000>;
>  			renesas,ipmmu-main = <&ipmmu_mm 2>;
> -			power-domains = <&sysc 32>;
> +			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
>  			#iommu-cells = <1>;
>  		};
> 
> @@ -784,7 +785,7 @@
>  			reg = <0 0xe67b0000 0 0x1000>;
>  			interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
>  				     <GIC_SPI 197
> IRQ_TYPE_LEVEL_HIGH>;
> -			power-domains = <&sysc 32>;
> +			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
>  			#iommu-cells = <1>;
>  		};
> 
> @@ -792,7 +793,7 @@
>  			compatible = "renesas,ipmmu-r8a774a1";
>  			reg = <0 0xec670000 0 0x1000>;
>  			renesas,ipmmu-main = <&ipmmu_mm 4>;
> -			power-domains = <&sysc 32>;
> +			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
>  			#iommu-cells = <1>;
>  		};
> 
> @@ -800,7 +801,7 @@
>  			compatible = "renesas,ipmmu-r8a774a1";
>  			reg = <0 0xfd800000 0 0x1000>;
>  			renesas,ipmmu-main = <&ipmmu_mm 5>;
> -			power-domains = <&sysc 32>;
> +			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
>  			#iommu-cells = <1>;
>  		};
> 
> @@ -808,7 +809,7 @@
>  			compatible = "renesas,ipmmu-r8a774a1";
>  			reg = <0 0xfd950000 0 0x1000>;
>  			renesas,ipmmu-main = <&ipmmu_mm 6>;
> -			power-domains = <&sysc 32>;
> +			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
>  			#iommu-cells = <1>;
>  		};
> 
> @@ -816,7 +817,7 @@
>  			compatible = "renesas,ipmmu-r8a774a1";
>  			reg = <0 0xfe6b0000 0 0x1000>;
>  			renesas,ipmmu-main = <&ipmmu_mm 8>;
> -			power-domains = <&sysc 14>;
> +			power-domains = <&sysc R8A774A1_PD_A3VC>;
>  			#iommu-cells = <1>;
>  		};
> 
> @@ -824,7 +825,7 @@
>  			compatible = "renesas,ipmmu-r8a774a1";
>  			reg = <0 0xfebd0000 0 0x1000>;
>  			renesas,ipmmu-main = <&ipmmu_mm 9>;
> -			power-domains = <&sysc 32>;
> +			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
>  			#iommu-cells = <1>;
>  		};
> 
> @@ -865,7 +866,7 @@
>  					  "ch20", "ch21", "ch22",
> "ch23",
>  					  "ch24";
>  			clocks = <&cpg CPG_MOD 812>;
> -			power-domains = <&sysc 32>;
> +			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
>  			resets = <&cpg 812>;
>  			phy-mode = "rgmii";
>  			#address-cells = <1>;
> @@ -880,7 +881,7 @@
>  			interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
>  			clocks = <&cpg CPG_MOD 916>, <&can_clk>;
>  			clock-names = "clkp1", "can_clk";
> -			power-domains = <&sysc 32>;
> +			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
>  			resets = <&cpg 916>;
>  			status = "disabled";
>  		};
> @@ -892,7 +893,7 @@
>  			interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
>  			clocks = <&cpg CPG_MOD 915>, <&can_clk>;
>  			clock-names = "clkp1", "can_clk";
> -			power-domains = <&sysc 32>;
> +			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
>  			resets = <&cpg 915>;
>  			status = "disabled";
>  		};
> @@ -903,7 +904,7 @@
>  			#pwm-cells = <2>;
>  			clocks = <&cpg CPG_MOD 523>;
>  			resets = <&cpg 523>;
> -			power-domains = <&sysc 32>;
> +			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
>  			status = "disabled";
>  		};
> 
> @@ -913,7 +914,7 @@
>  			#pwm-cells = <2>;
>  			clocks = <&cpg CPG_MOD 523>;
>  			resets = <&cpg 523>;
> -			power-domains = <&sysc 32>;
> +			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
>  			status = "disabled";
>  		};
> 
> @@ -923,7 +924,7 @@
>  			#pwm-cells = <2>;
>  			clocks = <&cpg CPG_MOD 523>;
>  			resets = <&cpg 523>;
> -			power-domains = <&sysc 32>;
> +			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
>  			status = "disabled";
>  		};
> 
> @@ -933,7 +934,7 @@
>  			#pwm-cells = <2>;
>  			clocks = <&cpg CPG_MOD 523>;
>  			resets = <&cpg 523>;
> -			power-domains = <&sysc 32>;
> +			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
>  			status = "disabled";
>  		};
> 
> @@ -943,7 +944,7 @@
>  			#pwm-cells = <2>;
>  			clocks = <&cpg CPG_MOD 523>;
>  			resets = <&cpg 523>;
> -			power-domains = <&sysc 32>;
> +			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
>  			status = "disabled";
>  		};
> 
> @@ -953,7 +954,7 @@
>  			#pwm-cells = <2>;
>  			clocks = <&cpg CPG_MOD 523>;
>  			resets = <&cpg 523>;
> -			power-domains = <&sysc 32>;
> +			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
>  			status = "disabled";
>  		};
> 
> @@ -963,7 +964,7 @@
>  			#pwm-cells = <2>;
>  			clocks = <&cpg CPG_MOD 523>;
>  			resets = <&cpg 523>;
> -			power-domains = <&sysc 32>;
> +			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
>  			status = "disabled";
>  		};
> 
> @@ -979,7 +980,7 @@
>  			dmas = <&dmac1 0x51>, <&dmac1 0x50>,
>  			       <&dmac2 0x51>, <&dmac2 0x50>;
>  			dma-names = "tx", "rx", "tx", "rx";
> -			power-domains = <&sysc 32>;
> +			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
>  			resets = <&cpg 207>;
>  			status = "disabled";
>  		};
> @@ -996,7 +997,7 @@
>  			dmas = <&dmac1 0x53>, <&dmac1 0x52>,
>  			       <&dmac2 0x53>, <&dmac2 0x52>;
>  			dma-names = "tx", "rx", "tx", "rx";
> -			power-domains = <&sysc 32>;
> +			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
>  			resets = <&cpg 206>;
>  			status = "disabled";
>  		};
> @@ -1010,7 +1011,7 @@
>  				 <&cpg CPG_CORE 19>,
>  				 <&scif_clk>;
>  			clock-names = "fck", "brg_int", "scif_clk";
> -			power-domains = <&sysc 32>;
> +			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
>  			resets = <&cpg 310>;
>  			status = "disabled";
>  		};
> @@ -1026,7 +1027,7 @@
>  			clock-names = "fck", "brg_int", "scif_clk";
>  			dmas = <&dmac0 0x57>, <&dmac0 0x56>;
>  			dma-names = "tx", "rx";
> -			power-domains = <&sysc 32>;
> +			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
>  			resets = <&cpg 204>;
>  			status = "disabled";
>  		};
> @@ -1042,7 +1043,7 @@
>  			clock-names = "fck", "brg_int", "scif_clk";
>  			dmas = <&dmac0 0x59>, <&dmac0 0x58>;
>  			dma-names = "tx", "rx";
> -			power-domains = <&sysc 32>;
> +			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
>  			resets = <&cpg 203>;
>  			status = "disabled";
>  		};
> @@ -1059,7 +1060,7 @@
>  			dmas = <&dmac1 0x5b>, <&dmac1 0x5a>,
>  			       <&dmac2 0x5b>, <&dmac2 0x5a>;
>  			dma-names = "tx", "rx", "tx", "rx";
> -			power-domains = <&sysc 32>;
> +			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
>  			resets = <&cpg 202>;
>  			status = "disabled";
>  		};
> @@ -1073,7 +1074,7 @@
>  			dmas = <&dmac1 0x41>, <&dmac1 0x40>,
>  			       <&dmac2 0x41>, <&dmac2 0x40>;
>  			dma-names = "tx", "rx", "tx", "rx";
> -			power-domains = <&sysc 32>;
> +			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
>  			resets = <&cpg 211>;
>  			#address-cells = <1>;
>  			#size-cells = <0>;
> @@ -1089,7 +1090,7 @@
>  			dmas = <&dmac1 0x43>, <&dmac1 0x42>,
>  			       <&dmac2 0x43>, <&dmac2 0x42>;
>  			dma-names = "tx", "rx", "tx", "rx";
> -			power-domains = <&sysc 32>;
> +			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
>  			resets = <&cpg 210>;
>  			#address-cells = <1>;
>  			#size-cells = <0>;
> @@ -1104,7 +1105,7 @@
>  			clocks = <&cpg CPG_MOD 209>;
>  			dmas = <&dmac0 0x45>, <&dmac0 0x44>;
>  			dma-names = "tx", "rx";
> -			power-domains = <&sysc 32>;
> +			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
>  			resets = <&cpg 209>;
>  			#address-cells = <1>;
>  			#size-cells = <0>;
> @@ -1119,7 +1120,7 @@
>  			clocks = <&cpg CPG_MOD 208>;
>  			dmas = <&dmac0 0x47>, <&dmac0 0x46>;
>  			dma-names = "tx", "rx";
> -			power-domains = <&sysc 32>;
> +			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
>  			resets = <&cpg 208>;
>  			#address-cells = <1>;
>  			#size-cells = <0>;
> @@ -1175,7 +1176,7 @@
>  				      "ctu.1", "ctu.0",
>  				      "dvc.0", "dvc.1",
>  				      "clk_a", "clk_b", "clk_c",
> "clk_i";
> -			power-domains = <&sysc 32>;
> +			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
>  			resets = <&cpg 1005>,
>  				 <&cpg 1006>, <&cpg 1007>,
>  				 <&cpg 1008>, <&cpg 1009>,
> @@ -1361,7 +1362,7 @@
>  					"ch12", "ch13", "ch14", "ch15";
>  			clocks = <&cpg CPG_MOD 502>;
>  			clock-names = "fck";
> -			power-domains = <&sysc 32>;
> +			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
>  			resets = <&cpg 502>;
>  			#dma-cells = <1>;
>  			dma-channels = <16>;
> @@ -1395,7 +1396,7 @@
>  					"ch12", "ch13", "ch14", "ch15";
>  			clocks = <&cpg CPG_MOD 501>;
>  			clock-names = "fck";
> -			power-domains = <&sysc 32>;
> +			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
>  			resets = <&cpg 501>;
>  			#dma-cells = <1>;
>  			dma-channels = <16>;
> @@ -1407,7 +1408,7 @@
>  			reg = <0 0xee000000 0 0xc00>;
>  			interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
>  			clocks = <&cpg CPG_MOD 328>;
> -			power-domains = <&sysc 32>;
> +			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
>  			resets = <&cpg 328>;
>  			status = "disabled";
>  		};
> @@ -1418,7 +1419,7 @@
>  			reg = <0 0xee020000 0 0x400>;
>  			interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
>  			clocks = <&cpg CPG_MOD 328>;
> -			power-domains = <&sysc 32>;
> +			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
>  			resets = <&cpg 328>;
>  			status = "disabled";
>  		};
> @@ -1430,7 +1431,7 @@
>  			clocks = <&cpg CPG_MOD 703>;
>  			phys = <&usb2_phy0>;
>  			phy-names = "usb";
> -			power-domains = <&sysc 32>;
> +			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
>  			resets = <&cpg 703>;
>  			status = "disabled";
>  		};
> @@ -1442,7 +1443,7 @@
>  			clocks = <&cpg CPG_MOD 702>;
>  			phys = <&usb2_phy1>;
>  			phy-names = "usb";
> -			power-domains = <&sysc 32>;
> +			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
>  			resets = <&cpg 702>;
>  			status = "disabled";
>  		};
> @@ -1455,7 +1456,7 @@
>  			phys = <&usb2_phy0>;
>  			phy-names = "usb";
>  			companion = <&ohci0>;
> -			power-domains = <&sysc 32>;
> +			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
>  			resets = <&cpg 703>;
>  			status = "disabled";
>  		};
> @@ -1468,7 +1469,7 @@
>  			phys = <&usb2_phy1>;
>  			phy-names = "usb";
>  			companion = <&ohci1>;
> -			power-domains = <&sysc 32>;
> +			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
>  			resets = <&cpg 702>;
>  			status = "disabled";
>  		};
> @@ -1479,7 +1480,7 @@
>  			reg = <0 0xee080200 0 0x700>;
>  			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
>  			clocks = <&cpg CPG_MOD 703>;
> -			power-domains = <&sysc 32>;
> +			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
>  			resets = <&cpg 703>;
>  			#phy-cells = <0>;
>  			status = "disabled";
> @@ -1490,7 +1491,7 @@
>  				     "renesas,rcar-gen3-usb2-phy";
>  			reg = <0 0xee0a0200 0 0x700>;
>  			clocks = <&cpg CPG_MOD 702>;
> -			power-domains = <&sysc 32>;
> +			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
>  			resets = <&cpg 702>;
>  			#phy-cells = <0>;
>  			status = "disabled";
> @@ -1503,7 +1504,7 @@
>  			interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
>  			clocks = <&cpg CPG_MOD 314>;
>  			max-frequency = <200000000>;
> -			power-domains = <&sysc 32>;
> +			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
>  			resets = <&cpg 314>;
>  			status = "disabled";
>  		};
> @@ -1515,7 +1516,7 @@
>  			interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
>  			clocks = <&cpg CPG_MOD 313>;
>  			max-frequency = <200000000>;
> -			power-domains = <&sysc 32>;
> +			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
>  			resets = <&cpg 313>;
>  			status = "disabled";
>  		};
> @@ -1527,7 +1528,7 @@
>  			interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
>  			clocks = <&cpg CPG_MOD 312>;
>  			max-frequency = <200000000>;
> -			power-domains = <&sysc 32>;
> +			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
>  			resets = <&cpg 312>;
>  			status = "disabled";
>  		};
> @@ -1539,7 +1540,7 @@
>  			interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
>  			clocks = <&cpg CPG_MOD 311>;
>  			max-frequency = <200000000>;
> -			power-domains = <&sysc 32>;
> +			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
>  			resets = <&cpg 311>;
>  			status = "disabled";
>  		};
> @@ -1557,7 +1558,7 @@
>  					(GIC_CPU_MASK_SIMPLE(6) |
> IRQ_TYPE_LEVEL_HIGH)>;
>  			clocks = <&cpg CPG_MOD 408>;
>  			clock-names = "clk";
> -			power-domains = <&sysc 32>;
> +			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
>  			resets = <&cpg 408>;
>  		};
> 
> @@ -1565,7 +1566,7 @@
>  			compatible = "renesas,fcpf";
>  			reg = <0 0xfe950000 0 0x200>;
>  			clocks = <&cpg CPG_MOD 615>;
> -			power-domains = <&sysc 14>;
> +			power-domains = <&sysc R8A774A1_PD_A3VC>;
>  			resets = <&cpg 615>;
>  		};
> 
> @@ -1573,7 +1574,7 @@
>  			compatible = "renesas,fcpv";
>  			reg = <0 0xfe96f000 0 0x200>;
>  			clocks = <&cpg CPG_MOD 607>;
> -			power-domains = <&sysc 14>;
> +			power-domains = <&sysc R8A774A1_PD_A3VC>;
>  			resets = <&cpg 607>;
>  		};
> 
> @@ -1581,7 +1582,7 @@
>  			compatible = "renesas,fcpv";
>  			reg = <0 0xfea27000 0 0x200>;
>  			clocks = <&cpg CPG_MOD 603>;
> -			power-domains = <&sysc 32>;
> +			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
>  			resets = <&cpg 603>;
>  			iommus = <&ipmmu_vi0 8>;
>  		};
> @@ -1590,7 +1591,7 @@
>  			compatible = "renesas,fcpv";
>  			reg = <0 0xfea2f000 0 0x200>;
>  			clocks = <&cpg CPG_MOD 602>;
> -			power-domains = <&sysc 32>;
> +			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
>  			resets = <&cpg 602>;
>  			iommus = <&ipmmu_vi0 9>;
>  		};
> @@ -1599,7 +1600,7 @@
>  			compatible = "renesas,fcpv";
>  			reg = <0 0xfea37000 0 0x200>;
>  			clocks = <&cpg CPG_MOD 601>;
> -			power-domains = <&sysc 32>;
> +			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
>  			resets = <&cpg 601>;
>  			iommus = <&ipmmu_vi0 10>;
>  		};
> @@ -1608,7 +1609,7 @@
>  			compatible = "renesas,fcpv";
>  			reg = <0 0xfe9af000 0 0x200>;
>  			clocks = <&cpg CPG_MOD 611>;
> -			power-domains = <&sysc 14>;
> +			power-domains = <&sysc R8A774A1_PD_A3VC>;
>  			resets = <&cpg 611>;
>  			iommus = <&ipmmu_vc0 19>;
>  		};
> --
> 2.7.4
> 
> _______________________________________________
> cip-dev mailing list
> cip-dev at lists.cip-project.org
> https://lists.cip-project.org/mailman/listinfo/cip-dev

[cip-dev] [PATCH 4.19.y-cip v2 56/57] arm64: dts: Remove inconsistent use of 'arm, armv8' compatible string

[nobuhiro1.iwamatsu at toshiba.co.jp]

Hi,

> arm64: dts: Remove inconsistent use of 'arm, armv8' compatible string

It's not that important, but why is there a space between 'arm,' and 'armv8'
in subject?

Original subject does not have space.
  https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=31af04cd60d3162a58213363fd740a2b0cf0a08e

The following patch have similar problem.

soc: renesas: rcar-sysc: Remove rcar_sysc_power_{down, up}() helpers

Best regards,
  Nobuhiro

> -----Original Message-----
> From: cip-dev-bounces at lists.cip-project.org
> [mailto:cip-dev-bounces at lists.cip-project.org] On Behalf Of Fabrizio
> Castro
> Sent: Wednesday, August 28, 2019 10:33 PM
> To: cip-dev at lists.cip-project.org
> Cc: Biju Das <biju.das@bp.renesas.com>
> Subject: [cip-dev] [PATCH 4.19.y-cip v2 56/57] arm64: dts: Remove
> inconsistent use of 'arm, armv8' compatible string
> 
> From: Rob Herring <robh@kernel.org>
> 
> commit 31af04cd60d3162a58213363fd740a2b0cf0a08e upstream.
> 
> The 'arm,armv8' compatible string is only for software models. It adds
> little value otherwise and is inconsistently used as a fallback on some
> platforms. Remove it from those platforms.
> 
> This fixes warnings generated by the DT schema.
> 
> Reported-by: Michal Simek <michal.simek@xilinx.com>
> Cc: Mark Rutland <mark.rutland@arm.com>
> Cc: Will Deacon <will.deacon@arm.com>
> Acked-by: Antoine Tenart <antoine.tenart@bootlin.com>
> Acked-by: Nishanth Menon <nm@ti.com>
> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
> Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> Acked-by: Chanho Min <chanho.min@lge.com>
> Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
> Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com>
> Acked-by: Gregory CLEMENT <gregory.clement@bootlin.com>
> Acked-by: Thierry Reding <treding@nvidia.com>
> Acked-by: Heiko Stuebner <heiko@sntech.de>
> Acked-by: Simon Horman <horms+renesas@verge.net.au>
> Acked-by: Tero Kristo <t-kristo@ti.com>
> Acked-by: Wei Xu <xuwei5@hisilicon.com>
> Acked-by: Liviu Dudau <liviu.dudau@arm.com>
> Acked-by: Matthias Brugger <matthias.bgg@gmail.com>
> Acked-by: Michal Simek <michal.simek@xilinx.com>
> Acked-by: Scott Branden <scott.branden@broadcom.com>
> Acked-by: Kevin Hilman <khilman@baylibre.com>
> Acked-by: Chunyan Zhang <zhang.lyra@gmail.com>
> Acked-by: Robert Richter <rrichter@cavium.com>
> Acked-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com>
> Acked-by: Dinh Nguyen <dinguyen@kernel.org>
> Signed-off-by: Rob Herring <robh@kernel.org>
> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
> [fab: dropped changes not related to r8a774a1.dtsi]
> Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> ---
>  arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 12 ++++++------
>  1 file changed, 6 insertions(+), 6 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
> b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
> index 1969649..a77de9e 100644
> --- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
> @@ -61,7 +61,7 @@
>  		#size-cells = <0>;
> 
>  		a57_0: cpu at 0 {
> -			compatible = "arm,cortex-a57", "arm,armv8";
> +			compatible = "arm,cortex-a57";
>  			reg = <0x0>;
>  			device_type = "cpu";
>  			power-domains = <&sysc R8A774A1_PD_CA57_CPU0>;
> @@ -71,7 +71,7 @@
>  		};
> 
>  		a57_1: cpu at 1 {
> -			compatible = "arm,cortex-a57", "arm,armv8";
> +			compatible = "arm,cortex-a57";
>  			reg = <0x1>;
>  			device_type = "cpu";
>  			power-domains = <&sysc R8A774A1_PD_CA57_CPU1>;
> @@ -81,7 +81,7 @@
>  		};
> 
>  		a53_0: cpu at 100 {
> -			compatible = "arm,cortex-a53", "arm,armv8";
> +			compatible = "arm,cortex-a53";
>  			reg = <0x100>;
>  			device_type = "cpu";
>  			power-domains = <&sysc R8A774A1_PD_CA53_CPU0>;
> @@ -91,7 +91,7 @@
>  		};
> 
>  		a53_1: cpu at 101 {
> -			compatible = "arm,cortex-a53", "arm,armv8";
> +			compatible = "arm,cortex-a53";
>  			reg = <0x101>;
>  			device_type = "cpu";
>  			power-domains = <&sysc R8A774A1_PD_CA53_CPU1>;
> @@ -101,7 +101,7 @@
>  		};
> 
>  		a53_2: cpu at 102 {
> -			compatible = "arm,cortex-a53", "arm,armv8";
> +			compatible = "arm,cortex-a53";
>  			reg = <0x102>;
>  			device_type = "cpu";
>  			power-domains = <&sysc R8A774A1_PD_CA53_CPU2>;
> @@ -111,7 +111,7 @@
>  		};
> 
>  		a53_3: cpu at 103 {
> -			compatible = "arm,cortex-a53", "arm,armv8";
> +			compatible = "arm,cortex-a53";
>  			reg = <0x103>;
>  			device_type = "cpu";
>  			power-domains = <&sysc R8A774A1_PD_CA53_CPU3>;
> --
> 2.7.4
> 
> _______________________________________________
> cip-dev mailing list
> cip-dev at lists.cip-project.org
> https://lists.cip-project.org/mailman/listinfo/cip-dev

[cip-dev] [PATCH 4.19.y-cip v2 56/57] arm64: dts: Remove inconsistent use of 'arm, armv8' compatible string

[Fabrizio Castro]

Hi,

>It's not that important, but why is there a space between 'arm,' and 'armv8'
>in subject?
>Original subject does not have space.

It is actually VERY, VERY, important, as the email I have sent out doesn't contain the space.
I have even run hexdump on the patch file on my disk, it confirms there is no space.
I am replying to my own email, and as you can see, there is no space.

>The following patch have similar problem.
>soc: renesas: rcar-sysc: Remove rcar_sysc_power_{down, up}() helpers

Same thing here, there is no space in the email I have sent out, which means it's
probably down to patchwork? Somehow a space gets automatically added, I wonder if
this is happening with the code too?

How do we find out if the problem is with patchwork?

Thanks,
Fab

> From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> Sent: 28 August 2019 14:33
> Subject: [cip-dev][PATCH 4.19.y-cip v2 56/57] arm64: dts: Remove inconsistent use of 'arm,armv8' compatible string
> 
> From: Rob Herring <robh@kernel.org>
> 
> commit 31af04cd60d3162a58213363fd740a2b0cf0a08e upstream.
> 
> The 'arm,armv8' compatible string is only for software models. It adds
> little value otherwise and is inconsistently used as a fallback on some
> platforms. Remove it from those platforms.
> 
> This fixes warnings generated by the DT schema.
> 
> Reported-by: Michal Simek <michal.simek@xilinx.com>
> Cc: Mark Rutland <mark.rutland@arm.com>
> Cc: Will Deacon <will.deacon@arm.com>
> Acked-by: Antoine Tenart <antoine.tenart@bootlin.com>
> Acked-by: Nishanth Menon <nm@ti.com>
> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
> Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> Acked-by: Chanho Min <chanho.min@lge.com>
> Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
> Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com>
> Acked-by: Gregory CLEMENT <gregory.clement@bootlin.com>
> Acked-by: Thierry Reding <treding@nvidia.com>
> Acked-by: Heiko Stuebner <heiko@sntech.de>
> Acked-by: Simon Horman <horms+renesas@verge.net.au>
> Acked-by: Tero Kristo <t-kristo@ti.com>
> Acked-by: Wei Xu <xuwei5@hisilicon.com>
> Acked-by: Liviu Dudau <liviu.dudau@arm.com>
> Acked-by: Matthias Brugger <matthias.bgg@gmail.com>
> Acked-by: Michal Simek <michal.simek@xilinx.com>
> Acked-by: Scott Branden <scott.branden@broadcom.com>
> Acked-by: Kevin Hilman <khilman@baylibre.com>
> Acked-by: Chunyan Zhang <zhang.lyra@gmail.com>
> Acked-by: Robert Richter <rrichter@cavium.com>
> Acked-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com>
> Acked-by: Dinh Nguyen <dinguyen@kernel.org>
> Signed-off-by: Rob Herring <robh@kernel.org>
> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
> [fab: dropped changes not related to r8a774a1.dtsi]
> Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> ---
>  arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 12 ++++++------
>  1 file changed, 6 insertions(+), 6 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
> index 1969649..a77de9e 100644
> --- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
> @@ -61,7 +61,7 @@
>  		#size-cells = <0>;
> 
>  		a57_0: cpu at 0 {
> -			compatible = "arm,cortex-a57", "arm,armv8";
> +			compatible = "arm,cortex-a57";
>  			reg = <0x0>;
>  			device_type = "cpu";
>  			power-domains = <&sysc R8A774A1_PD_CA57_CPU0>;
> @@ -71,7 +71,7 @@
>  		};
> 
>  		a57_1: cpu at 1 {
> -			compatible = "arm,cortex-a57", "arm,armv8";
> +			compatible = "arm,cortex-a57";
>  			reg = <0x1>;
>  			device_type = "cpu";
>  			power-domains = <&sysc R8A774A1_PD_CA57_CPU1>;
> @@ -81,7 +81,7 @@
>  		};
> 
>  		a53_0: cpu at 100 {
> -			compatible = "arm,cortex-a53", "arm,armv8";
> +			compatible = "arm,cortex-a53";
>  			reg = <0x100>;
>  			device_type = "cpu";
>  			power-domains = <&sysc R8A774A1_PD_CA53_CPU0>;
> @@ -91,7 +91,7 @@
>  		};
> 
>  		a53_1: cpu at 101 {
> -			compatible = "arm,cortex-a53", "arm,armv8";
> +			compatible = "arm,cortex-a53";
>  			reg = <0x101>;
>  			device_type = "cpu";
>  			power-domains = <&sysc R8A774A1_PD_CA53_CPU1>;
> @@ -101,7 +101,7 @@
>  		};
> 
>  		a53_2: cpu at 102 {
> -			compatible = "arm,cortex-a53", "arm,armv8";
> +			compatible = "arm,cortex-a53";
>  			reg = <0x102>;
>  			device_type = "cpu";
>  			power-domains = <&sysc R8A774A1_PD_CA53_CPU2>;
> @@ -111,7 +111,7 @@
>  		};
> 
>  		a53_3: cpu at 103 {
> -			compatible = "arm,cortex-a53", "arm,armv8";
> +			compatible = "arm,cortex-a53";
>  			reg = <0x103>;
>  			device_type = "cpu";
>  			power-domains = <&sysc R8A774A1_PD_CA53_CPU3>;
> --
> 2.7.4

[cip-dev] [PATCH 4.19.y-cip v2 56/57] arm64: dts: Remove inconsistent use of 'arm, armv8' compatible string

[Pavel Machek]

Hi!

> >It's not that important, but why is there a space between 'arm,' and 'armv8'
> >in subject?
> >Original subject does not have space.
> 
> It is actually VERY, VERY, important, as the email I have sent out doesn't contain the space.
> I have even run hexdump on the patch file on my disk, it confirms there is no space.
> I am replying to my own email, and as you can see, there is no
>space.

Can you take a look at the email, as received from the mailinglist? I
see a space in subject, between 'arm,' and 'armv8'.

Can you send the original email, as a binary attachment?

> >The following patch have similar problem.
> >soc: renesas: rcar-sysc: Remove rcar_sysc_power_{down, up}() helpers
> 
> Same thing here, there is no space in the email I have sent out, which means it's
> probably down to patchwork? Somehow a space gets automatically added, I wonder if
> this is happening with the code too?
> 
> How do we find out if the problem is with patchwork?

I don't think patchwork is responsible. It would have to be something
in the mailing list.

Best regards,
								Pavel

-- 
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
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[cip-dev] [PATCH 4.19.y-cip v2 56/57] arm64: dts: Remove inconsistent use of 'arm, armv8' compatible string

[Fabrizio Castro]

Hi Pavel,

> From: Pavel Machek <pavel@denx.de>
> Sent: 30 August 2019 10:10
> Subject: Re: [cip-dev][PATCH 4.19.y-cip v2 56/57] arm64: dts: Remove inconsistent use of 'arm,armv8' compatible string
> 
> Hi!
> 
> > >It's not that important, but why is there a space between 'arm,' and 'armv8'
> > >in subject?
> > >Original subject does not have space.
> >
> > It is actually VERY, VERY, important, as the email I have sent out doesn't contain the space.
> > I have even run hexdump on the patch file on my disk, it confirms there is no space.
> > I am replying to my own email, and as you can see, there is no
> >space.
> 
> Can you take a look at the email, as received from the mailinglist? I
> see a space in subject, between 'arm,' and 'armv8'.

Interesting...

> 
> Can you send the original email, as a binary attachment?

I use git send-email, therefore unfortunately I don't have the original email.
I have attached the email msg as received from my email client, and the patch file.
It doesn't look like there is a space there...

In both cases:
* "arm64: dts: Remove inconsistent use of 'arm,armv8' compatible string", and
* "soc: renesas: rcar-sysc: Remove rcar_sysc_power_{down,up}() helpers"
it seems like a space was added after the comma, like autocorrect programs would
do...

Has anybody seen this before?

Thanks,
Fab

> 
> > >The following patch have similar problem.
> > >soc: renesas: rcar-sysc: Remove rcar_sysc_power_{down, up}() helpers
> >
> > Same thing here, there is no space in the email I have sent out, which means it's
> > probably down to patchwork? Somehow a space gets automatically added, I wonder if
> > this is happening with the code too?
> >
> > How do we find out if the problem is with patchwork?
> 
> I don't think patchwork is responsible. It would have to be something
> in the mailing list.
> 
> Best regards,
> 								Pavel
> 
> --
> DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
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[cip-dev] [PATCH 4.19.y-cip v2 52/57] arm64: dts: renesas: r8a774a1: Replace power magic numbers

[Fabrizio Castro]

Hi!,

Thank you for your feedback!

> From: nobuhiro1.iwamatsu at toshiba.co.jp <nobuhiro1.iwamatsu@toshiba.co.jp>
> Sent: 30 August 2019 06:32
> Subject: RE: [cip-dev] [PATCH 4.19.y-cip v2 52/57] arm64: dts: renesas: r8a774a1: Replace power magic numbers
> 
> Hi,
> 
> Fix for VIN (and others?) has been removed from original commit.
> Please add this to the commit message.

You are right, I forgot to add a comment in the commit message for this.
What's missing from the backported commit is vin (vin[0-7]), csi20, and csi40.

Will send a v2 for this patch.

Thanks!

Fab

> 
> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=aeee3d9cb776542f5700425f703fa78c70a1dcd0
> 
> Best regards,
>   Nobuhiro
> 
> > -----Original Message-----
> > From: cip-dev-bounces at lists.cip-project.org
> > [mailto:cip-dev-bounces at lists.cip-project.org] On Behalf Of Fabrizio
> > Castro
> > Sent: Wednesday, August 28, 2019 10:33 PM
> > To: cip-dev at lists.cip-project.org
> > Cc: Biju Das <biju.das@bp.renesas.com>
> > Subject: [cip-dev] [PATCH 4.19.y-cip v2 52/57] arm64: dts: renesas:
> > r8a774a1: Replace power magic numbers
> >
> > commit aeee3d9cb776542f5700425f703fa78c70a1dcd0 upstream.
> >
> > Now that include/dt-bindings/power/r8a774a1-sysc.h is in Linus'
> > master branch we can replace power related magic numbers with the
> > corresponding labels.
> >
> > Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> > Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
> > ---
> >  arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 181
> > +++++++++++++++---------------
> >  1 file changed, 91 insertions(+), 90 deletions(-)
> >
> > diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
> > b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
> > index a4817a0..000b280 100644
> > --- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
> > +++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
> > @@ -8,6 +8,7 @@
> >  #include <dt-bindings/interrupt-controller/irq.h>
> >  #include <dt-bindings/interrupt-controller/arm-gic.h>
> >  #include <dt-bindings/clock/renesas-cpg-mssr.h>
> > +#include <dt-bindings/power/r8a774a1-sysc.h>
> >
> >  / {
> >  	compatible = "renesas,r8a774a1";
> > @@ -63,7 +64,7 @@
> >  			compatible = "arm,cortex-a57", "arm,armv8";
> >  			reg = <0x0>;
> >  			device_type = "cpu";
> > -			power-domains = <&sysc 0>;
> > +			power-domains = <&sysc R8A774A1_PD_CA57_CPU0>;
> >  			next-level-cache = <&L2_CA57>;
> >  			enable-method = "psci";
> >  			clocks = <&cpg CPG_CORE 0>;
> > @@ -73,7 +74,7 @@
> >  			compatible = "arm,cortex-a57", "arm,armv8";
> >  			reg = <0x1>;
> >  			device_type = "cpu";
> > -			power-domains = <&sysc 1>;
> > +			power-domains = <&sysc R8A774A1_PD_CA57_CPU1>;
> >  			next-level-cache = <&L2_CA57>;
> >  			enable-method = "psci";
> >  			clocks = <&cpg CPG_CORE 0>;
> > @@ -83,7 +84,7 @@
> >  			compatible = "arm,cortex-a53", "arm,armv8";
> >  			reg = <0x100>;
> >  			device_type = "cpu";
> > -			power-domains = <&sysc 5>;
> > +			power-domains = <&sysc R8A774A1_PD_CA53_CPU0>;
> >  			next-level-cache = <&L2_CA53>;
> >  			enable-method = "psci";
> >  			clocks =<&cpg CPG_CORE 1>;
> > @@ -93,7 +94,7 @@
> >  			compatible = "arm,cortex-a53", "arm,armv8";
> >  			reg = <0x101>;
> >  			device_type = "cpu";
> > -			power-domains = <&sysc 6>;
> > +			power-domains = <&sysc R8A774A1_PD_CA53_CPU1>;
> >  			next-level-cache = <&L2_CA53>;
> >  			enable-method = "psci";
> >  			clocks =<&cpg CPG_CORE 1>;
> > @@ -103,7 +104,7 @@
> >  			compatible = "arm,cortex-a53", "arm,armv8";
> >  			reg = <0x102>;
> >  			device_type = "cpu";
> > -			power-domains = <&sysc 7>;
> > +			power-domains = <&sysc R8A774A1_PD_CA53_CPU2>;
> >  			next-level-cache = <&L2_CA53>;
> >  			enable-method = "psci";
> >  			clocks =<&cpg CPG_CORE 1>;
> > @@ -113,7 +114,7 @@
> >  			compatible = "arm,cortex-a53", "arm,armv8";
> >  			reg = <0x103>;
> >  			device_type = "cpu";
> > -			power-domains = <&sysc 8>;
> > +			power-domains = <&sysc R8A774A1_PD_CA53_CPU3>;
> >  			next-level-cache = <&L2_CA53>;
> >  			enable-method = "psci";
> >  			clocks =<&cpg CPG_CORE 1>;
> > @@ -121,14 +122,14 @@
> >
> >  		L2_CA57: cache-controller-0 {
> >  			compatible = "cache";
> > -			power-domains = <&sysc 12>;
> > +			power-domains = <&sysc R8A774A1_PD_CA57_SCU>;
> >  			cache-unified;
> >  			cache-level = <2>;
> >  		};
> >
> >  		L2_CA53: cache-controller-1 {
> >  			compatible = "cache";
> > -			power-domains = <&sysc 21>;
> > +			power-domains = <&sysc R8A774A1_PD_CA53_SCU>;
> >  			cache-unified;
> >  			cache-level = <2>;
> >  		};
> > @@ -195,7 +196,7 @@
> >  				     "renesas,rcar-gen3-wdt";
> >  			reg = <0 0xe6020000 0 0x0c>;
> >  			clocks = <&cpg CPG_MOD 402>;
> > -			power-domains = <&sysc 32>;
> > +			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
> >  			resets = <&cpg 402>;
> >  			status = "disabled";
> >  		};
> > @@ -211,7 +212,7 @@
> >  			#interrupt-cells = <2>;
> >  			interrupt-controller;
> >  			clocks = <&cpg CPG_MOD 912>;
> > -			power-domains = <&sysc 32>;
> > +			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
> >  			resets = <&cpg 912>;
> >  		};
> >
> > @@ -226,7 +227,7 @@
> >  			#interrupt-cells = <2>;
> >  			interrupt-controller;
> >  			clocks = <&cpg CPG_MOD 911>;
> > -			power-domains = <&sysc 32>;
> > +			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
> >  			resets = <&cpg 911>;
> >  		};
> >
> > @@ -241,7 +242,7 @@
> >  			#interrupt-cells = <2>;
> >  			interrupt-controller;
> >  			clocks = <&cpg CPG_MOD 910>;
> > -			power-domains = <&sysc 32>;
> > +			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
> >  			resets = <&cpg 910>;
> >  		};
> >
> > @@ -256,7 +257,7 @@
> >  			#interrupt-cells = <2>;
> >  			interrupt-controller;
> >  			clocks = <&cpg CPG_MOD 909>;
> > -			power-domains = <&sysc 32>;
> > +			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
> >  			resets = <&cpg 909>;
> >  		};
> >
> > @@ -271,7 +272,7 @@
> >  			#interrupt-cells = <2>;
> >  			interrupt-controller;
> >  			clocks = <&cpg CPG_MOD 908>;
> > -			power-domains = <&sysc 32>;
> > +			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
> >  			resets = <&cpg 908>;
> >  		};
> >
> > @@ -286,7 +287,7 @@
> >  			#interrupt-cells = <2>;
> >  			interrupt-controller;
> >  			clocks = <&cpg CPG_MOD 907>;
> > -			power-domains = <&sysc 32>;
> > +			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
> >  			resets = <&cpg 907>;
> >  		};
> >
> > @@ -301,7 +302,7 @@
> >  			#interrupt-cells = <2>;
> >  			interrupt-controller;
> >  			clocks = <&cpg CPG_MOD 906>;
> > -			power-domains = <&sysc 32>;
> > +			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
> >  			resets = <&cpg 906>;
> >  		};
> >
> > @@ -316,7 +317,7 @@
> >  			#interrupt-cells = <2>;
> >  			interrupt-controller;
> >  			clocks = <&cpg CPG_MOD 905>;
> > -			power-domains = <&sysc 32>;
> > +			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
> >  			resets = <&cpg 905>;
> >  		};
> >
> > @@ -355,7 +356,7 @@
> >  				     <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
> >  				     <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
> >  			clocks = <&cpg CPG_MOD 522>;
> > -			power-domains = <&sysc 32>;
> > +			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
> >  			resets = <&cpg 522>;
> >  			#thermal-sensor-cells = <1>;
> >  		};
> > @@ -372,7 +373,7 @@
> >  				      GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH
> >  				      GIC_SPI 161
> > IRQ_TYPE_LEVEL_HIGH>;
> >  			clocks = <&cpg CPG_MOD 407>;
> > -			power-domains = <&sysc 32>;
> > +			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
> >  			resets = <&cpg 407>;
> >  		};
> >
> > @@ -384,7 +385,7 @@
> >  			reg = <0 0xe6500000 0 0x40>;
> >  			interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
> >  			clocks = <&cpg CPG_MOD 931>;
> > -			power-domains = <&sysc 32>;
> > +			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
> >  			resets = <&cpg 931>;
> >  			dmas = <&dmac1 0x91>, <&dmac1 0x90>,
> >  			       <&dmac2 0x91>, <&dmac2 0x90>; @@ -401,7
> > +402,7 @@
> >  			reg = <0 0xe6508000 0 0x40>;
> >  			interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
> >  			clocks = <&cpg CPG_MOD 930>;
> > -			power-domains = <&sysc 32>;
> > +			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
> >  			resets = <&cpg 930>;
> >  			dmas = <&dmac1 0x93>, <&dmac1 0x92>,
> >  			       <&dmac2 0x93>, <&dmac2 0x92>; @@ -418,7
> > +419,7 @@
> >  			reg = <0 0xe6510000 0 0x40>;
> >  			interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
> >  			clocks = <&cpg CPG_MOD 929>;
> > -			power-domains = <&sysc 32>;
> > +			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
> >  			resets = <&cpg 929>;
> >  			dmas = <&dmac1 0x95>, <&dmac1 0x94>,
> >  			       <&dmac2 0x95>, <&dmac2 0x94>; @@ -435,7
> > +436,7 @@
> >  			reg = <0 0xe66d0000 0 0x40>;
> >  			interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
> >  			clocks = <&cpg CPG_MOD 928>;
> > -			power-domains = <&sysc 32>;
> > +			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
> >  			resets = <&cpg 928>;
> >  			dmas = <&dmac0 0x97>, <&dmac0 0x96>;
> >  			dma-names = "tx", "rx";
> > @@ -451,7 +452,7 @@
> >  			reg = <0 0xe66d8000 0 0x40>;
> >  			interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
> >  			clocks = <&cpg CPG_MOD 927>;
> > -			power-domains = <&sysc 32>;
> > +			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
> >  			resets = <&cpg 927>;
> >  			dmas = <&dmac0 0x99>, <&dmac0 0x98>;
> >  			dma-names = "tx", "rx";
> > @@ -467,7 +468,7 @@
> >  			reg = <0 0xe66e0000 0 0x40>;
> >  			interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
> >  			clocks = <&cpg CPG_MOD 919>;
> > -			power-domains = <&sysc 32>;
> > +			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
> >  			resets = <&cpg 919>;
> >  			dmas = <&dmac0 0x9b>, <&dmac0 0x9a>;
> >  			dma-names = "tx", "rx";
> > @@ -483,7 +484,7 @@
> >  			reg = <0 0xe66e8000 0 0x40>;
> >  			interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
> >  			clocks = <&cpg CPG_MOD 918>;
> > -			power-domains = <&sysc 32>;
> > +			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
> >  			resets = <&cpg 918>;
> >  			dmas = <&dmac0 0x9d>, <&dmac0 0x9c>;
> >  			dma-names = "tx", "rx";
> > @@ -500,7 +501,7 @@
> >  			reg = <0 0xe60b0000 0 0x425>;
> >  			interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
> >  			clocks = <&cpg CPG_MOD 926>;
> > -			power-domains = <&sysc 32>;
> > +			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
> >  			resets = <&cpg 926>;
> >  			dmas = <&dmac0 0x11>, <&dmac0 0x10>;
> >  			dma-names = "tx", "rx";
> > @@ -520,7 +521,7 @@
> >  			dmas = <&dmac1 0x31>, <&dmac1 0x30>,
> >  			       <&dmac2 0x31>, <&dmac2 0x30>;
> >  			dma-names = "tx", "rx", "tx", "rx";
> > -			power-domains = <&sysc 32>;
> > +			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
> >  			resets = <&cpg 520>;
> >  			status = "disabled";
> >  		};
> > @@ -538,7 +539,7 @@
> >  			dmas = <&dmac1 0x33>, <&dmac1 0x32>,
> >  			       <&dmac2 0x33>, <&dmac2 0x32>;
> >  			dma-names = "tx", "rx", "tx", "rx";
> > -			power-domains = <&sysc 32>;
> > +			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
> >  			resets = <&cpg 519>;
> >  			status = "disabled";
> >  		};
> > @@ -556,7 +557,7 @@
> >  			dmas = <&dmac1 0x35>, <&dmac1 0x34>,
> >  			       <&dmac2 0x35>, <&dmac2 0x34>;
> >  			dma-names = "tx", "rx", "tx", "rx";
> > -			power-domains = <&sysc 32>;
> > +			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
> >  			resets = <&cpg 518>;
> >  			status = "disabled";
> >  		};
> > @@ -573,7 +574,7 @@
> >  			clock-names = "fck", "brg_int", "scif_clk";
> >  			dmas = <&dmac0 0x37>, <&dmac0 0x36>;
> >  			dma-names = "tx", "rx";
> > -			power-domains = <&sysc 32>;
> > +			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
> >  			resets = <&cpg 517>;
> >  			status = "disabled";
> >  		};
> > @@ -590,7 +591,7 @@
> >  			clock-names = "fck", "brg_int", "scif_clk";
> >  			dmas = <&dmac0 0x39>, <&dmac0 0x38>;
> >  			dma-names = "tx", "rx";
> > -			power-domains = <&sysc 32>;
> > +			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
> >  			resets = <&cpg 516>;
> >  			status = "disabled";
> >  		};
> > @@ -607,7 +608,7 @@
> >  			renesas,buswait = <11>;
> >  			phys = <&usb2_phy0>;
> >  			phy-names = "usb";
> > -			power-domains = <&sysc 32>;
> > +			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
> >  			resets = <&cpg 704>;
> >  			status = "disabled";
> >  		};
> > @@ -620,7 +621,7 @@
> >  				      GIC_SPI 109
> > IRQ_TYPE_LEVEL_HIGH>;
> >  			interrupt-names = "ch0", "ch1";
> >  			clocks = <&cpg CPG_MOD 330>;
> > -			power-domains = <&sysc 32>;
> > +			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
> >  			resets = <&cpg 330>;
> >  			#dma-cells = <1>;
> >  			dma-channels = <2>;
> > @@ -634,7 +635,7 @@
> >  				      GIC_SPI 110
> > IRQ_TYPE_LEVEL_HIGH>;
> >  			interrupt-names = "ch0", "ch1";
> >  			clocks = <&cpg CPG_MOD 331>;
> > -			power-domains = <&sysc 32>;
> > +			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
> >  			resets = <&cpg 331>;
> >  			#dma-cells = <1>;
> >  			dma-channels = <2>;
> > @@ -647,7 +648,7 @@
> >  			clocks = <&cpg CPG_MOD 328>, <&usb3s0_clk>,
> >  				 <&usb_extal_clk>;
> >  			clock-names = "usb3-if", "usb3s_clk",
> > "usb_extal";
> > -			power-domains = <&sysc 32>;
> > +			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
> >  			resets = <&cpg 328>;
> >  			#phy-cells = <0>;
> >  			status = "disabled";
> > @@ -681,7 +682,7 @@
> >  					"ch12", "ch13", "ch14", "ch15";
> >  			clocks = <&cpg CPG_MOD 219>;
> >  			clock-names = "fck";
> > -			power-domains = <&sysc 32>;
> > +			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
> >  			resets = <&cpg 219>;
> >  			#dma-cells = <1>;
> >  			dma-channels = <16>;
> > @@ -715,7 +716,7 @@
> >  					"ch12", "ch13", "ch14", "ch15";
> >  			clocks = <&cpg CPG_MOD 218>;
> >  			clock-names = "fck";
> > -			power-domains = <&sysc 32>;
> > +			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
> >  			resets = <&cpg 218>;
> >  			#dma-cells = <1>;
> >  			dma-channels = <16>;
> > @@ -749,7 +750,7 @@
> >  					"ch12", "ch13", "ch14", "ch15";
> >  			clocks = <&cpg CPG_MOD 217>;
> >  			clock-names = "fck";
> > -			power-domains = <&sysc 32>;
> > +			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
> >  			resets = <&cpg 217>;
> >  			#dma-cells = <1>;
> >  			dma-channels = <16>;
> > @@ -759,7 +760,7 @@
> >  			compatible = "renesas,ipmmu-r8a774a1";
> >  			reg = <0 0xe6740000 0 0x1000>;
> >  			renesas,ipmmu-main = <&ipmmu_mm 0>;
> > -			power-domains = <&sysc 32>;
> > +			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
> >  			#iommu-cells = <1>;
> >  		};
> >
> > @@ -767,7 +768,7 @@
> >  			compatible = "renesas,ipmmu-r8a774a1";
> >  			reg = <0 0xe7740000 0 0x1000>;
> >  			renesas,ipmmu-main = <&ipmmu_mm 1>;
> > -			power-domains = <&sysc 32>;
> > +			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
> >  			#iommu-cells = <1>;
> >  		};
> >
> > @@ -775,7 +776,7 @@
> >  			compatible = "renesas,ipmmu-r8a774a1";
> >  			reg = <0 0xe6570000 0 0x1000>;
> >  			renesas,ipmmu-main = <&ipmmu_mm 2>;
> > -			power-domains = <&sysc 32>;
> > +			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
> >  			#iommu-cells = <1>;
> >  		};
> >
> > @@ -784,7 +785,7 @@
> >  			reg = <0 0xe67b0000 0 0x1000>;
> >  			interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
> >  				     <GIC_SPI 197
> > IRQ_TYPE_LEVEL_HIGH>;
> > -			power-domains = <&sysc 32>;
> > +			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
> >  			#iommu-cells = <1>;
> >  		};
> >
> > @@ -792,7 +793,7 @@
> >  			compatible = "renesas,ipmmu-r8a774a1";
> >  			reg = <0 0xec670000 0 0x1000>;
> >  			renesas,ipmmu-main = <&ipmmu_mm 4>;
> > -			power-domains = <&sysc 32>;
> > +			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
> >  			#iommu-cells = <1>;
> >  		};
> >
> > @@ -800,7 +801,7 @@
> >  			compatible = "renesas,ipmmu-r8a774a1";
> >  			reg = <0 0xfd800000 0 0x1000>;
> >  			renesas,ipmmu-main = <&ipmmu_mm 5>;
> > -			power-domains = <&sysc 32>;
> > +			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
> >  			#iommu-cells = <1>;
> >  		};
> >
> > @@ -808,7 +809,7 @@
> >  			compatible = "renesas,ipmmu-r8a774a1";
> >  			reg = <0 0xfd950000 0 0x1000>;
> >  			renesas,ipmmu-main = <&ipmmu_mm 6>;
> > -			power-domains = <&sysc 32>;
> > +			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
> >  			#iommu-cells = <1>;
> >  		};
> >
> > @@ -816,7 +817,7 @@
> >  			compatible = "renesas,ipmmu-r8a774a1";
> >  			reg = <0 0xfe6b0000 0 0x1000>;
> >  			renesas,ipmmu-main = <&ipmmu_mm 8>;
> > -			power-domains = <&sysc 14>;
> > +			power-domains = <&sysc R8A774A1_PD_A3VC>;
> >  			#iommu-cells = <1>;
> >  		};
> >
> > @@ -824,7 +825,7 @@
> >  			compatible = "renesas,ipmmu-r8a774a1";
> >  			reg = <0 0xfebd0000 0 0x1000>;
> >  			renesas,ipmmu-main = <&ipmmu_mm 9>;
> > -			power-domains = <&sysc 32>;
> > +			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
> >  			#iommu-cells = <1>;
> >  		};
> >
> > @@ -865,7 +866,7 @@
> >  					  "ch20", "ch21", "ch22",
> > "ch23",
> >  					  "ch24";
> >  			clocks = <&cpg CPG_MOD 812>;
> > -			power-domains = <&sysc 32>;
> > +			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
> >  			resets = <&cpg 812>;
> >  			phy-mode = "rgmii";
> >  			#address-cells = <1>;
> > @@ -880,7 +881,7 @@
> >  			interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
> >  			clocks = <&cpg CPG_MOD 916>, <&can_clk>;
> >  			clock-names = "clkp1", "can_clk";
> > -			power-domains = <&sysc 32>;
> > +			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
> >  			resets = <&cpg 916>;
> >  			status = "disabled";
> >  		};
> > @@ -892,7 +893,7 @@
> >  			interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
> >  			clocks = <&cpg CPG_MOD 915>, <&can_clk>;
> >  			clock-names = "clkp1", "can_clk";
> > -			power-domains = <&sysc 32>;
> > +			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
> >  			resets = <&cpg 915>;
> >  			status = "disabled";
> >  		};
> > @@ -903,7 +904,7 @@
> >  			#pwm-cells = <2>;
> >  			clocks = <&cpg CPG_MOD 523>;
> >  			resets = <&cpg 523>;
> > -			power-domains = <&sysc 32>;
> > +			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
> >  			status = "disabled";
> >  		};
> >
> > @@ -913,7 +914,7 @@
> >  			#pwm-cells = <2>;
> >  			clocks = <&cpg CPG_MOD 523>;
> >  			resets = <&cpg 523>;
> > -			power-domains = <&sysc 32>;
> > +			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
> >  			status = "disabled";
> >  		};
> >
> > @@ -923,7 +924,7 @@
> >  			#pwm-cells = <2>;
> >  			clocks = <&cpg CPG_MOD 523>;
> >  			resets = <&cpg 523>;
> > -			power-domains = <&sysc 32>;
> > +			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
> >  			status = "disabled";
> >  		};
> >
> > @@ -933,7 +934,7 @@
> >  			#pwm-cells = <2>;
> >  			clocks = <&cpg CPG_MOD 523>;
> >  			resets = <&cpg 523>;
> > -			power-domains = <&sysc 32>;
> > +			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
> >  			status = "disabled";
> >  		};
> >
> > @@ -943,7 +944,7 @@
> >  			#pwm-cells = <2>;
> >  			clocks = <&cpg CPG_MOD 523>;
> >  			resets = <&cpg 523>;
> > -			power-domains = <&sysc 32>;
> > +			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
> >  			status = "disabled";
> >  		};
> >
> > @@ -953,7 +954,7 @@
> >  			#pwm-cells = <2>;
> >  			clocks = <&cpg CPG_MOD 523>;
> >  			resets = <&cpg 523>;
> > -			power-domains = <&sysc 32>;
> > +			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
> >  			status = "disabled";
> >  		};
> >
> > @@ -963,7 +964,7 @@
> >  			#pwm-cells = <2>;
> >  			clocks = <&cpg CPG_MOD 523>;
> >  			resets = <&cpg 523>;
> > -			power-domains = <&sysc 32>;
> > +			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
> >  			status = "disabled";
> >  		};
> >
> > @@ -979,7 +980,7 @@
> >  			dmas = <&dmac1 0x51>, <&dmac1 0x50>,
> >  			       <&dmac2 0x51>, <&dmac2 0x50>;
> >  			dma-names = "tx", "rx", "tx", "rx";
> > -			power-domains = <&sysc 32>;
> > +			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
> >  			resets = <&cpg 207>;
> >  			status = "disabled";
> >  		};
> > @@ -996,7 +997,7 @@
> >  			dmas = <&dmac1 0x53>, <&dmac1 0x52>,
> >  			       <&dmac2 0x53>, <&dmac2 0x52>;
> >  			dma-names = "tx", "rx", "tx", "rx";
> > -			power-domains = <&sysc 32>;
> > +			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
> >  			resets = <&cpg 206>;
> >  			status = "disabled";
> >  		};
> > @@ -1010,7 +1011,7 @@
> >  				 <&cpg CPG_CORE 19>,
> >  				 <&scif_clk>;
> >  			clock-names = "fck", "brg_int", "scif_clk";
> > -			power-domains = <&sysc 32>;
> > +			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
> >  			resets = <&cpg 310>;
> >  			status = "disabled";
> >  		};
> > @@ -1026,7 +1027,7 @@
> >  			clock-names = "fck", "brg_int", "scif_clk";
> >  			dmas = <&dmac0 0x57>, <&dmac0 0x56>;
> >  			dma-names = "tx", "rx";
> > -			power-domains = <&sysc 32>;
> > +			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
> >  			resets = <&cpg 204>;
> >  			status = "disabled";
> >  		};
> > @@ -1042,7 +1043,7 @@
> >  			clock-names = "fck", "brg_int", "scif_clk";
> >  			dmas = <&dmac0 0x59>, <&dmac0 0x58>;
> >  			dma-names = "tx", "rx";
> > -			power-domains = <&sysc 32>;
> > +			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
> >  			resets = <&cpg 203>;
> >  			status = "disabled";
> >  		};
> > @@ -1059,7 +1060,7 @@
> >  			dmas = <&dmac1 0x5b>, <&dmac1 0x5a>,
> >  			       <&dmac2 0x5b>, <&dmac2 0x5a>;
> >  			dma-names = "tx", "rx", "tx", "rx";
> > -			power-domains = <&sysc 32>;
> > +			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
> >  			resets = <&cpg 202>;
> >  			status = "disabled";
> >  		};
> > @@ -1073,7 +1074,7 @@
> >  			dmas = <&dmac1 0x41>, <&dmac1 0x40>,
> >  			       <&dmac2 0x41>, <&dmac2 0x40>;
> >  			dma-names = "tx", "rx", "tx", "rx";
> > -			power-domains = <&sysc 32>;
> > +			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
> >  			resets = <&cpg 211>;
> >  			#address-cells = <1>;
> >  			#size-cells = <0>;
> > @@ -1089,7 +1090,7 @@
> >  			dmas = <&dmac1 0x43>, <&dmac1 0x42>,
> >  			       <&dmac2 0x43>, <&dmac2 0x42>;
> >  			dma-names = "tx", "rx", "tx", "rx";
> > -			power-domains = <&sysc 32>;
> > +			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
> >  			resets = <&cpg 210>;
> >  			#address-cells = <1>;
> >  			#size-cells = <0>;
> > @@ -1104,7 +1105,7 @@
> >  			clocks = <&cpg CPG_MOD 209>;
> >  			dmas = <&dmac0 0x45>, <&dmac0 0x44>;
> >  			dma-names = "tx", "rx";
> > -			power-domains = <&sysc 32>;
> > +			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
> >  			resets = <&cpg 209>;
> >  			#address-cells = <1>;
> >  			#size-cells = <0>;
> > @@ -1119,7 +1120,7 @@
> >  			clocks = <&cpg CPG_MOD 208>;
> >  			dmas = <&dmac0 0x47>, <&dmac0 0x46>;
> >  			dma-names = "tx", "rx";
> > -			power-domains = <&sysc 32>;
> > +			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
> >  			resets = <&cpg 208>;
> >  			#address-cells = <1>;
> >  			#size-cells = <0>;
> > @@ -1175,7 +1176,7 @@
> >  				      "ctu.1", "ctu.0",
> >  				      "dvc.0", "dvc.1",
> >  				      "clk_a", "clk_b", "clk_c",
> > "clk_i";
> > -			power-domains = <&sysc 32>;
> > +			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
> >  			resets = <&cpg 1005>,
> >  				 <&cpg 1006>, <&cpg 1007>,
> >  				 <&cpg 1008>, <&cpg 1009>,
> > @@ -1361,7 +1362,7 @@
> >  					"ch12", "ch13", "ch14", "ch15";
> >  			clocks = <&cpg CPG_MOD 502>;
> >  			clock-names = "fck";
> > -			power-domains = <&sysc 32>;
> > +			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
> >  			resets = <&cpg 502>;
> >  			#dma-cells = <1>;
> >  			dma-channels = <16>;
> > @@ -1395,7 +1396,7 @@
> >  					"ch12", "ch13", "ch14", "ch15";
> >  			clocks = <&cpg CPG_MOD 501>;
> >  			clock-names = "fck";
> > -			power-domains = <&sysc 32>;
> > +			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
> >  			resets = <&cpg 501>;
> >  			#dma-cells = <1>;
> >  			dma-channels = <16>;
> > @@ -1407,7 +1408,7 @@
> >  			reg = <0 0xee000000 0 0xc00>;
> >  			interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
> >  			clocks = <&cpg CPG_MOD 328>;
> > -			power-domains = <&sysc 32>;
> > +			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
> >  			resets = <&cpg 328>;
> >  			status = "disabled";
> >  		};
> > @@ -1418,7 +1419,7 @@
> >  			reg = <0 0xee020000 0 0x400>;
> >  			interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
> >  			clocks = <&cpg CPG_MOD 328>;
> > -			power-domains = <&sysc 32>;
> > +			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
> >  			resets = <&cpg 328>;
> >  			status = "disabled";
> >  		};
> > @@ -1430,7 +1431,7 @@
> >  			clocks = <&cpg CPG_MOD 703>;
> >  			phys = <&usb2_phy0>;
> >  			phy-names = "usb";
> > -			power-domains = <&sysc 32>;
> > +			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
> >  			resets = <&cpg 703>;
> >  			status = "disabled";
> >  		};
> > @@ -1442,7 +1443,7 @@
> >  			clocks = <&cpg CPG_MOD 702>;
> >  			phys = <&usb2_phy1>;
> >  			phy-names = "usb";
> > -			power-domains = <&sysc 32>;
> > +			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
> >  			resets = <&cpg 702>;
> >  			status = "disabled";
> >  		};
> > @@ -1455,7 +1456,7 @@
> >  			phys = <&usb2_phy0>;
> >  			phy-names = "usb";
> >  			companion = <&ohci0>;
> > -			power-domains = <&sysc 32>;
> > +			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
> >  			resets = <&cpg 703>;
> >  			status = "disabled";
> >  		};
> > @@ -1468,7 +1469,7 @@
> >  			phys = <&usb2_phy1>;
> >  			phy-names = "usb";
> >  			companion = <&ohci1>;
> > -			power-domains = <&sysc 32>;
> > +			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
> >  			resets = <&cpg 702>;
> >  			status = "disabled";
> >  		};
> > @@ -1479,7 +1480,7 @@
> >  			reg = <0 0xee080200 0 0x700>;
> >  			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
> >  			clocks = <&cpg CPG_MOD 703>;
> > -			power-domains = <&sysc 32>;
> > +			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
> >  			resets = <&cpg 703>;
> >  			#phy-cells = <0>;
> >  			status = "disabled";
> > @@ -1490,7 +1491,7 @@
> >  				     "renesas,rcar-gen3-usb2-phy";
> >  			reg = <0 0xee0a0200 0 0x700>;
> >  			clocks = <&cpg CPG_MOD 702>;
> > -			power-domains = <&sysc 32>;
> > +			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
> >  			resets = <&cpg 702>;
> >  			#phy-cells = <0>;
> >  			status = "disabled";
> > @@ -1503,7 +1504,7 @@
> >  			interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
> >  			clocks = <&cpg CPG_MOD 314>;
> >  			max-frequency = <200000000>;
> > -			power-domains = <&sysc 32>;
> > +			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
> >  			resets = <&cpg 314>;
> >  			status = "disabled";
> >  		};
> > @@ -1515,7 +1516,7 @@
> >  			interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
> >  			clocks = <&cpg CPG_MOD 313>;
> >  			max-frequency = <200000000>;
> > -			power-domains = <&sysc 32>;
> > +			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
> >  			resets = <&cpg 313>;
> >  			status = "disabled";
> >  		};
> > @@ -1527,7 +1528,7 @@
> >  			interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
> >  			clocks = <&cpg CPG_MOD 312>;
> >  			max-frequency = <200000000>;
> > -			power-domains = <&sysc 32>;
> > +			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
> >  			resets = <&cpg 312>;
> >  			status = "disabled";
> >  		};
> > @@ -1539,7 +1540,7 @@
> >  			interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
> >  			clocks = <&cpg CPG_MOD 311>;
> >  			max-frequency = <200000000>;
> > -			power-domains = <&sysc 32>;
> > +			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
> >  			resets = <&cpg 311>;
> >  			status = "disabled";
> >  		};
> > @@ -1557,7 +1558,7 @@
> >  					(GIC_CPU_MASK_SIMPLE(6) |
> > IRQ_TYPE_LEVEL_HIGH)>;
> >  			clocks = <&cpg CPG_MOD 408>;
> >  			clock-names = "clk";
> > -			power-domains = <&sysc 32>;
> > +			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
> >  			resets = <&cpg 408>;
> >  		};
> >
> > @@ -1565,7 +1566,7 @@
> >  			compatible = "renesas,fcpf";
> >  			reg = <0 0xfe950000 0 0x200>;
> >  			clocks = <&cpg CPG_MOD 615>;
> > -			power-domains = <&sysc 14>;
> > +			power-domains = <&sysc R8A774A1_PD_A3VC>;
> >  			resets = <&cpg 615>;
> >  		};
> >
> > @@ -1573,7 +1574,7 @@
> >  			compatible = "renesas,fcpv";
> >  			reg = <0 0xfe96f000 0 0x200>;
> >  			clocks = <&cpg CPG_MOD 607>;
> > -			power-domains = <&sysc 14>;
> > +			power-domains = <&sysc R8A774A1_PD_A3VC>;
> >  			resets = <&cpg 607>;
> >  		};
> >
> > @@ -1581,7 +1582,7 @@
> >  			compatible = "renesas,fcpv";
> >  			reg = <0 0xfea27000 0 0x200>;
> >  			clocks = <&cpg CPG_MOD 603>;
> > -			power-domains = <&sysc 32>;
> > +			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
> >  			resets = <&cpg 603>;
> >  			iommus = <&ipmmu_vi0 8>;
> >  		};
> > @@ -1590,7 +1591,7 @@
> >  			compatible = "renesas,fcpv";
> >  			reg = <0 0xfea2f000 0 0x200>;
> >  			clocks = <&cpg CPG_MOD 602>;
> > -			power-domains = <&sysc 32>;
> > +			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
> >  			resets = <&cpg 602>;
> >  			iommus = <&ipmmu_vi0 9>;
> >  		};
> > @@ -1599,7 +1600,7 @@
> >  			compatible = "renesas,fcpv";
> >  			reg = <0 0xfea37000 0 0x200>;
> >  			clocks = <&cpg CPG_MOD 601>;
> > -			power-domains = <&sysc 32>;
> > +			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
> >  			resets = <&cpg 601>;
> >  			iommus = <&ipmmu_vi0 10>;
> >  		};
> > @@ -1608,7 +1609,7 @@
> >  			compatible = "renesas,fcpv";
> >  			reg = <0 0xfe9af000 0 0x200>;
> >  			clocks = <&cpg CPG_MOD 611>;
> > -			power-domains = <&sysc 14>;
> > +			power-domains = <&sysc R8A774A1_PD_A3VC>;
> >  			resets = <&cpg 611>;
> >  			iommus = <&ipmmu_vc0 19>;
> >  		};
> > --
> > 2.7.4
> >
> > _______________________________________________
> > cip-dev mailing list
> > cip-dev at lists.cip-project.org
> > https://lists.cip-project.org/mailman/listinfo/cip-dev

[cip-dev] [PATCH 4.19.y-cip v2 56/57] arm64: dts: Remove inconsistent use of 'arm, armv8' compatible string

[nobuhiro1.iwamatsu at toshiba.co.jp]

Hi Fabrizio,

> -----Original Message-----
> From: Fabrizio Castro [mailto:fabrizio.castro at bp.renesas.com]
> Sent: Friday, August 30, 2019 6:34 PM
> To: Pavel Machek <pavel@denx.de>
> Cc: iwamatsu nobuhiro(?? ?? ????????)
> <nobuhiro1.iwamatsu@toshiba.co.jp>; Chris Paterson
> <Chris.Paterson2@renesas.com>; Biju Das <biju.das@bp.renesas.com>;
> cip-dev at lists.cip-project.org
> Subject: RE: [cip-dev][PATCH 4.19.y-cip v2 56/57] arm64: dts: Remove
> inconsistent use of 'arm,armv8' compatible string
> 
> Hi Pavel,
> 
> > From: Pavel Machek <pavel@denx.de>
> > Sent: 30 August 2019 10:10
> > Subject: Re: [cip-dev][PATCH 4.19.y-cip v2 56/57] arm64: dts: Remove
> > inconsistent use of 'arm,armv8' compatible string
> >
> > Hi!
> >
> > > >It's not that important, but why is there a space between 'arm,'
> and 'armv8'
> > > >in subject?
> > > >Original subject does not have space.
> > >
> > > It is actually VERY, VERY, important, as the email I have sent out
> doesn't contain the space.
> > > I have even run hexdump on the patch file on my disk, it confirms
> there is no space.
> > > I am replying to my own email, and as you can see, there is no
> > >space.
> >
> > Can you take a look at the email, as received from the mailinglist?
> I
> > see a space in subject, between 'arm,' and 'armv8'.
> 
> Interesting...
> 
> >
> > Can you send the original email, as a binary attachment?
> 
> I use git send-email, therefore unfortunately I don't have the original
> email.
> I have attached the email msg as received from my email client, and the
> patch file.
> It doesn't look like there is a space there...
> 

Hmm, what do you use smtp server? There may be a problem with the SMTP server.

> In both cases:
> * "arm64: dts: Remove inconsistent use of 'arm,armv8' compatible string",
> and
> * "soc: renesas: rcar-sysc: Remove rcar_sysc_power_{down,up}() helpers"
> it seems like a space was added after the comma, like autocorrect programs
> would do...
> 
> Has anybody seen this before?
> 

I've easily checked.
The pinctrl patch sent last week seems to have the same problem.
e.g. https://lists.cip-project.org/pipermail/cip-dev/2019-August/002988.html

bd3eb391f0fc pinctrl: sh-pfc: r8a77995: Remove unused PINMUX_IPSR_{MSEL2, PHYS}()
f2be905d124b pinctrl: sh-pfc: rcar-gen3: Rename RTS{0, 1, 3, 4}# pin function definitions
db4bd73cbd2c pinctrl: sh-pfc: rcar-gen3: Rename SEL_ADG_{A, B, C} to SEL_ADG{A, B, C}
c50668864e27 pinctrl: sh-pfc: r8a7796: Add I2C{0, 3, 5} pins, groups and functions

> Thanks,
> Fab


Best regards,
  Nobuhiro

> 
> >
> > > >The following patch have similar problem.
> > > >soc: renesas: rcar-sysc: Remove rcar_sysc_power_{down, up}()
> > > >helpers
> > >
> > > Same thing here, there is no space in the email I have sent out,
> > > which means it's probably down to patchwork? Somehow a space gets
> > > automatically added, I wonder if this is happening with the code too?
> > >
> > > How do we find out if the problem is with patchwork?
> >
> > I don't think patchwork is responsible. It would have to be something
> > in the mailing list.
> >
> > Best regards,
> > 								Pavel
> >
> > --
> > DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
> > HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany

[cip-dev] [PATCH 4.19.y-cip v2 56/57] arm64: dts: Remove inconsistent use of 'arm, armv8' compatible string

[Fabrizio Castro]

Hello Iwamatsu-san,

> From: nobuhiro1.iwamatsu at toshiba.co.jp <nobuhiro1.iwamatsu@toshiba.co.jp>
> Sent: 02 September 2019 02:46
> Subject: RE: [cip-dev][PATCH 4.19.y-cip v2 56/57] arm64: dts: Remove inconsistent use of 'arm,armv8' compatible string
> 
> Hi Fabrizio,
> 
> > -----Original Message-----
> > From: Fabrizio Castro [mailto:fabrizio.castro at bp.renesas.com]
> > Sent: Friday, August 30, 2019 6:34 PM
> > To: Pavel Machek <pavel@denx.de>
> > Cc: iwamatsu nobuhiro(?? ?? ????????)
> > <nobuhiro1.iwamatsu@toshiba.co.jp>; Chris Paterson
> > <Chris.Paterson2@renesas.com>; Biju Das <biju.das@bp.renesas.com>;
> > cip-dev at lists.cip-project.org
> > Subject: RE: [cip-dev][PATCH 4.19.y-cip v2 56/57] arm64: dts: Remove
> > inconsistent use of 'arm,armv8' compatible string
> >
> > Hi Pavel,
> >
> > > From: Pavel Machek <pavel@denx.de>
> > > Sent: 30 August 2019 10:10
> > > Subject: Re: [cip-dev][PATCH 4.19.y-cip v2 56/57] arm64: dts: Remove
> > > inconsistent use of 'arm,armv8' compatible string
> > >
> > > Hi!
> > >
> > > > >It's not that important, but why is there a space between 'arm,'
> > and 'armv8'
> > > > >in subject?
> > > > >Original subject does not have space.
> > > >
> > > > It is actually VERY, VERY, important, as the email I have sent out
> > doesn't contain the space.
> > > > I have even run hexdump on the patch file on my disk, it confirms
> > there is no space.
> > > > I am replying to my own email, and as you can see, there is no
> > > >space.
> > >
> > > Can you take a look at the email, as received from the mailinglist?
> > I
> > > see a space in subject, between 'arm,' and 'armv8'.
> >
> > Interesting...
> >
> > >
> > > Can you send the original email, as a binary attachment?
> >
> > I use git send-email, therefore unfortunately I don't have the original
> > email.
> > I have attached the email msg as received from my email client, and the
> > patch file.
> > It doesn't look like there is a space there...
> >
> 
> Hmm, what do you use smtp server? There may be a problem with the SMTP server.

I am using Renesas' SMTP server, I have been using the same server for the past two
years, and this is the first time I have seen this problem.

> 
> > In both cases:
> > * "arm64: dts: Remove inconsistent use of 'arm,armv8' compatible string",
> > and
> > * "soc: renesas: rcar-sysc: Remove rcar_sysc_power_{down,up}() helpers"
> > it seems like a space was added after the comma, like autocorrect programs
> > would do...
> >
> > Has anybody seen this before?
> >
> 
> I've easily checked.
> The pinctrl patch sent last week seems to have the same problem.
> e.g. https://lists.cip-project.org/pipermail/cip-dev/2019-August/002988.html
> 
> bd3eb391f0fc pinctrl: sh-pfc: r8a77995: Remove unused PINMUX_IPSR_{MSEL2, PHYS}()
> f2be905d124b pinctrl: sh-pfc: rcar-gen3: Rename RTS{0, 1, 3, 4}# pin function definitions
> db4bd73cbd2c pinctrl: sh-pfc: rcar-gen3: Rename SEL_ADG_{A, B, C} to SEL_ADG{A, B, C}
> c50668864e27 pinctrl: sh-pfc: r8a7796: Add I2C{0, 3, 5} pins, groups and functions

All those patches look ok in my inbox. I put myself in CC when sending out emails with
git send-email, therefore whatever I send out with git send-email reaches my inbox
before the mailing list daemon has the chance to forward the emails to my account, I
wonder if the problem is with the mailing list?

Thanks,
Fab

> 
> > Thanks,
> > Fab
> 
> 
> Best regards,
>   Nobuhiro
> 
> >
> > >
> > > > >The following patch have similar problem.
> > > > >soc: renesas: rcar-sysc: Remove rcar_sysc_power_{down, up}()
> > > > >helpers
> > > >
> > > > Same thing here, there is no space in the email I have sent out,
> > > > which means it's probably down to patchwork? Somehow a space gets
> > > > automatically added, I wonder if this is happening with the code too?
> > > >
> > > > How do we find out if the problem is with patchwork?
> > >
> > > I don't think patchwork is responsible. It would have to be something
> > > in the mailing list.
> > >
> > > Best regards,
> > > 								Pavel
> > >
> > > --
> > > DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
> > > HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany

[cip-dev] [PATCH 4.19.y-cip v2 56/57] arm64: dts: Remove inconsistent use of 'arm, armv8' compatible string

[Pavel Machek]

Hi!


> > Hmm, what do you use smtp server? There may be a problem with the SMTP server.
> 
> I am using Renesas' SMTP server, I have been using the same server for the past two
> years, and this is the first time I have seen this problem.
> 
> > 
> > > In both cases:
> > > * "arm64: dts: Remove inconsistent use of 'arm,armv8' compatible string",
> > > and
> > > * "soc: renesas: rcar-sysc: Remove rcar_sysc_power_{down,up}() helpers"
> > > it seems like a space was added after the comma, like autocorrect programs
> > > would do...
> > >
> > > Has anybody seen this before?
> > >
> > 
> > I've easily checked.
> > The pinctrl patch sent last week seems to have the same problem.
> > e.g. https://lists.cip-project.org/pipermail/cip-dev/2019-August/002988.html
> > 
> > bd3eb391f0fc pinctrl: sh-pfc: r8a77995: Remove unused PINMUX_IPSR_{MSEL2, PHYS}()
> > f2be905d124b pinctrl: sh-pfc: rcar-gen3: Rename RTS{0, 1, 3, 4}# pin function definitions
> > db4bd73cbd2c pinctrl: sh-pfc: rcar-gen3: Rename SEL_ADG_{A, B, C} to SEL_ADG{A, B, C}
> > c50668864e27 pinctrl: sh-pfc: r8a7796: Add I2C{0, 3, 5} pins, groups and functions
> 
> All those patches look ok in my inbox. I put myself in CC when sending out emails with
> git send-email, therefore whatever I send out with git send-email reaches my inbox
> before the mailing list daemon has the chance to forward the emails to my account, I
> wonder if the problem is with the mailing list?

That should be easy to test. Feel free to send a test patch to a
mailing list, ccing us directly....

Best regards,
								Pavel
-- 
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
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