* [cip-dev] [PATCH 4.19.y-cip 0/6] Renesas RZ/G2H add PCIe{EP}/SATA support
@ 2020-11-02 9:24 Lad Prabhakar
2020-11-02 9:24 ` [cip-dev] [PATCH 4.19.y-cip 1/6] arm64: dts: renesas: r8a774e1: Add PCIe device nodes Lad Prabhakar
` (6 more replies)
0 siblings, 7 replies; 10+ messages in thread
From: Lad Prabhakar @ 2020-11-02 9:24 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das
[-- Attachment #1: Type: text/plain, Size: 828 bytes --]
Hi All,
This patch series adds PCIe{EP}/SATA support to Renesas RZ/G2H.
All the patches have been cherry-picked from mainline kernel
v5.10-rc2.
Cheers,
Prabhakar
Lad Prabhakar (6):
arm64: dts: renesas: r8a774e1: Add PCIe device nodes
arm64: dts: renesas: r8a774e1: Add SATA controller node
dt-bindings: pci: rcar-pci-ep: Document r8a774e1
arm64: dts: renesas: r8a774e1: Add PCIe EP nodes
misc: pci_endpoint_test: Add Device ID for RZ/G2H PCIe controller
arm64: dts: renesas: r8a774e1-hihope-rzg2h-ex: Enable sata
.../devicetree/bindings/pci/rcar-pci-ep.yaml | 1 +
.../dts/renesas/r8a774e1-hihope-rzg2h-ex.dts | 5 +
arch/arm64/boot/dts/renesas/r8a774e1.dtsi | 97 ++++++++++++++++++-
drivers/misc/pci_endpoint_test.c | 2 +
4 files changed, 104 insertions(+), 1 deletion(-)
--
2.17.1
[-- Attachment #2: Type: text/plain, Size: 420 bytes --]
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* [cip-dev] [PATCH 4.19.y-cip 1/6] arm64: dts: renesas: r8a774e1: Add PCIe device nodes
2020-11-02 9:24 [cip-dev] [PATCH 4.19.y-cip 0/6] Renesas RZ/G2H add PCIe{EP}/SATA support Lad Prabhakar
@ 2020-11-02 9:24 ` Lad Prabhakar
2020-11-02 9:24 ` [cip-dev] [PATCH 4.19.y-cip 2/6] arm64: dts: renesas: r8a774e1: Add SATA controller node Lad Prabhakar
` (5 subsequent siblings)
6 siblings, 0 replies; 10+ messages in thread
From: Lad Prabhakar @ 2020-11-02 9:24 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das
[-- Attachment #1: Type: text/plain, Size: 3100 bytes --]
commit cbb2f09abcd635888508338d4436771fe07688d1 upstream.
Add PCIe{0,1} device nodes for R8A774E1 SoC.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
Link: https://lore.kernel.org/r/1594919915-5225-3-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
arch/arm64/boot/dts/renesas/r8a774e1.dtsi | 47 ++++++++++++++++++++++-
1 file changed, 46 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi
index 0f86cfd52425..aaa55f9449f5 100644
--- a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi
@@ -1517,12 +1517,57 @@
};
pciec0: pcie@fe000000 {
+ compatible = "renesas,pcie-r8a774e1",
+ "renesas,pcie-rcar-gen3";
reg = <0 0xfe000000 0 0x80000>;
#address-cells = <3>;
#size-cells = <2>;
+ bus-range = <0x00 0xff>;
+ device_type = "pci";
+ ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>,
+ <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,
+ <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,
+ <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
+ /* Map all possible DDR as inbound ranges */
+ dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
+ interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>;
+ clock-names = "pcie", "pcie_bus";
+ power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+ resets = <&cpg 319>;
status = "disabled";
+ };
- /* placeholder */
+ pciec1: pcie@ee800000 {
+ compatible = "renesas,pcie-r8a774e1",
+ "renesas,pcie-rcar-gen3";
+ reg = <0 0xee800000 0 0x80000>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ bus-range = <0x00 0xff>;
+ device_type = "pci";
+ ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000>,
+ <0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>,
+ <0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>,
+ <0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>;
+ /* Map all possible DDR as inbound ranges */
+ dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
+ interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 318>, <&pcie_bus_clk>;
+ clock-names = "pcie", "pcie_bus";
+ power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+ resets = <&cpg 318>;
+ status = "disabled";
};
hdmi0: hdmi@fead0000 {
--
2.17.1
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* [cip-dev] [PATCH 4.19.y-cip 2/6] arm64: dts: renesas: r8a774e1: Add SATA controller node
2020-11-02 9:24 [cip-dev] [PATCH 4.19.y-cip 0/6] Renesas RZ/G2H add PCIe{EP}/SATA support Lad Prabhakar
2020-11-02 9:24 ` [cip-dev] [PATCH 4.19.y-cip 1/6] arm64: dts: renesas: r8a774e1: Add PCIe device nodes Lad Prabhakar
@ 2020-11-02 9:24 ` Lad Prabhakar
2020-11-02 9:24 ` [cip-dev] [PATCH 4.19.y-cip 3/6] dt-bindings: pci: rcar-pci-ep: Document r8a774e1 Lad Prabhakar
` (4 subsequent siblings)
6 siblings, 0 replies; 10+ messages in thread
From: Lad Prabhakar @ 2020-11-02 9:24 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das
[-- Attachment #1: Type: text/plain, Size: 1375 bytes --]
commit 2f3c7323aba207b5cf1e769b8f48ce726531de4a upstream.
Add the SATA controller node to the RZ/G2H SoC specific dtsi.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
Link: https://lore.kernel.org/r/1594919915-5225-5-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
arch/arm64/boot/dts/renesas/r8a774e1.dtsi | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi
index aaa55f9449f5..832abe712e6c 100644
--- a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi
@@ -1499,6 +1499,18 @@
status = "disabled";
};
+ sata: sata@ee300000 {
+ compatible = "renesas,sata-r8a774e1",
+ "renesas,rcar-gen3-sata";
+ reg = <0 0xee300000 0 0x200000>;
+ interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 815>;
+ power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+ resets = <&cpg 815>;
+ iommus = <&ipmmu_hc 2>;
+ status = "disabled";
+ };
+
gic: interrupt-controller@f1010000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
--
2.17.1
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* [cip-dev] [PATCH 4.19.y-cip 3/6] dt-bindings: pci: rcar-pci-ep: Document r8a774e1
2020-11-02 9:24 [cip-dev] [PATCH 4.19.y-cip 0/6] Renesas RZ/G2H add PCIe{EP}/SATA support Lad Prabhakar
2020-11-02 9:24 ` [cip-dev] [PATCH 4.19.y-cip 1/6] arm64: dts: renesas: r8a774e1: Add PCIe device nodes Lad Prabhakar
2020-11-02 9:24 ` [cip-dev] [PATCH 4.19.y-cip 2/6] arm64: dts: renesas: r8a774e1: Add SATA controller node Lad Prabhakar
@ 2020-11-02 9:24 ` Lad Prabhakar
2020-11-02 9:24 ` [cip-dev] [PATCH 4.19.y-cip 4/6] arm64: dts: renesas: r8a774e1: Add PCIe EP nodes Lad Prabhakar
` (3 subsequent siblings)
6 siblings, 0 replies; 10+ messages in thread
From: Lad Prabhakar @ 2020-11-02 9:24 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das
[-- Attachment #1: Type: text/plain, Size: 1236 bytes --]
commit 5e94083c781445b4b5c00689167558dce694da65 upstream.
Document the support for R-Car PCIe EP on R8A774E1 SoC device.
Link: https://lore.kernel.org/r/20200904103851.3946-2-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
Documentation/devicetree/bindings/pci/rcar-pci-ep.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/pci/rcar-pci-ep.yaml b/Documentation/devicetree/bindings/pci/rcar-pci-ep.yaml
index 70c45f72ab20..a059c96c294b 100644
--- a/Documentation/devicetree/bindings/pci/rcar-pci-ep.yaml
+++ b/Documentation/devicetree/bindings/pci/rcar-pci-ep.yaml
@@ -18,6 +18,7 @@ properties:
- renesas,r8a774a1-pcie-ep # RZ/G2M
- renesas,r8a774b1-pcie-ep # RZ/G2N
- renesas,r8a774c0-pcie-ep # RZ/G2E
+ - renesas,r8a774e1-pcie-ep # RZ/G2H
- const: renesas,rcar-gen3-pcie-ep # R-Car Gen3 and RZ/G2
reg:
--
2.17.1
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* [cip-dev] [PATCH 4.19.y-cip 4/6] arm64: dts: renesas: r8a774e1: Add PCIe EP nodes
2020-11-02 9:24 [cip-dev] [PATCH 4.19.y-cip 0/6] Renesas RZ/G2H add PCIe{EP}/SATA support Lad Prabhakar
` (2 preceding siblings ...)
2020-11-02 9:24 ` [cip-dev] [PATCH 4.19.y-cip 3/6] dt-bindings: pci: rcar-pci-ep: Document r8a774e1 Lad Prabhakar
@ 2020-11-02 9:24 ` Lad Prabhakar
2020-11-02 9:24 ` [cip-dev] [PATCH 4.19.y-cip 5/6] misc: pci_endpoint_test: Add Device ID for RZ/G2H PCIe controller Lad Prabhakar
` (2 subsequent siblings)
6 siblings, 0 replies; 10+ messages in thread
From: Lad Prabhakar @ 2020-11-02 9:24 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das
[-- Attachment #1: Type: text/plain, Size: 2374 bytes --]
commit b7ecb51b2d9bd12c80c24d2fd1cadedd35e7cb7e upstream.
Add PCIe EP nodes for R8A774E1 Soc dtsi.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20200904103851.3946-3-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
[PL: manually applied the changes]
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
arch/arm64/boot/dts/renesas/r8a774e1.dtsi | 38 +++++++++++++++++++++++
1 file changed, 38 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi
index 832abe712e6c..8e9292d46cc4 100644
--- a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi
@@ -1582,6 +1582,44 @@
status = "disabled";
};
+ pciec0_ep: pcie-ep@fe000000 {
+ compatible = "renesas,r8a774e1-pcie-ep",
+ "renesas,rcar-gen3-pcie-ep";
+ reg = <0x0 0xfe000000 0 0x80000>,
+ <0x0 0xfe100000 0 0x100000>,
+ <0x0 0xfe200000 0 0x200000>,
+ <0x0 0x30000000 0 0x8000000>,
+ <0x0 0x38000000 0 0x8000000>;
+ reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3";
+ interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 319>;
+ clock-names = "pcie";
+ resets = <&cpg 319>;
+ power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
+
+ pciec1_ep: pcie-ep@ee800000 {
+ compatible = "renesas,r8a774e1-pcie-ep",
+ "renesas,rcar-gen3-pcie-ep";
+ reg = <0x0 0xee800000 0 0x80000>,
+ <0x0 0xee900000 0 0x100000>,
+ <0x0 0xeea00000 0 0x200000>,
+ <0x0 0xc0000000 0 0x8000000>,
+ <0x0 0xc8000000 0 0x8000000>;
+ reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3";
+ interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 318>;
+ clock-names = "pcie";
+ resets = <&cpg 318>;
+ power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
+
hdmi0: hdmi@fead0000 {
reg = <0 0xfead0000 0 0x10000>;
status = "disabled";
--
2.17.1
[-- Attachment #2: Type: text/plain, Size: 420 bytes --]
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* [cip-dev] [PATCH 4.19.y-cip 5/6] misc: pci_endpoint_test: Add Device ID for RZ/G2H PCIe controller
2020-11-02 9:24 [cip-dev] [PATCH 4.19.y-cip 0/6] Renesas RZ/G2H add PCIe{EP}/SATA support Lad Prabhakar
` (3 preceding siblings ...)
2020-11-02 9:24 ` [cip-dev] [PATCH 4.19.y-cip 4/6] arm64: dts: renesas: r8a774e1: Add PCIe EP nodes Lad Prabhakar
@ 2020-11-02 9:24 ` Lad Prabhakar
2020-11-02 9:24 ` [cip-dev] [PATCH 4.19.y-cip 6/6] arm64: dts: renesas: r8a774e1-hihope-rzg2h-ex: Enable sata Lad Prabhakar
2020-11-02 10:31 ` [cip-dev] [PATCH 4.19.y-cip 0/6] Renesas RZ/G2H add PCIe{EP}/SATA support Pavel Machek
6 siblings, 0 replies; 10+ messages in thread
From: Lad Prabhakar @ 2020-11-02 9:24 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das
[-- Attachment #1: Type: text/plain, Size: 1590 bytes --]
commit a63c5f3db07dab2b205ac9a6a6ca96c4f72290de upstream.
Add Renesas R8A774E1 in pci_device_id table so that pci-epf-test
can be used for testing PCIe EP on RZ/G2H.
Link: https://lore.kernel.org/r/20200904103851.3946-4-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
[PL: manually applied the changes]
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
drivers/misc/pci_endpoint_test.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/misc/pci_endpoint_test.c b/drivers/misc/pci_endpoint_test.c
index a1083f568d2c..9413a08ee351 100644
--- a/drivers/misc/pci_endpoint_test.c
+++ b/drivers/misc/pci_endpoint_test.c
@@ -83,6 +83,7 @@
#define PCI_DEVICE_ID_RENESAS_R8A774A1 0x0028
#define PCI_DEVICE_ID_RENESAS_R8A774B1 0x002b
#define PCI_DEVICE_ID_RENESAS_R8A774C0 0x002d
+#define PCI_DEVICE_ID_RENESAS_R8A774E1 0x0025
static DEFINE_IDA(pci_endpoint_test_ida);
@@ -821,6 +822,7 @@ static const struct pci_device_id pci_endpoint_test_tbl[] = {
{ PCI_DEVICE(PCI_VENDOR_ID_RENESAS, PCI_DEVICE_ID_RENESAS_R8A774A1),},
{ PCI_DEVICE(PCI_VENDOR_ID_RENESAS, PCI_DEVICE_ID_RENESAS_R8A774B1),},
{ PCI_DEVICE(PCI_VENDOR_ID_RENESAS, PCI_DEVICE_ID_RENESAS_R8A774C0),},
+ { PCI_DEVICE(PCI_VENDOR_ID_RENESAS, PCI_DEVICE_ID_RENESAS_R8A774E1),},
{ }
};
MODULE_DEVICE_TABLE(pci, pci_endpoint_test_tbl);
--
2.17.1
[-- Attachment #2: Type: text/plain, Size: 420 bytes --]
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* [cip-dev] [PATCH 4.19.y-cip 6/6] arm64: dts: renesas: r8a774e1-hihope-rzg2h-ex: Enable sata
2020-11-02 9:24 [cip-dev] [PATCH 4.19.y-cip 0/6] Renesas RZ/G2H add PCIe{EP}/SATA support Lad Prabhakar
` (4 preceding siblings ...)
2020-11-02 9:24 ` [cip-dev] [PATCH 4.19.y-cip 5/6] misc: pci_endpoint_test: Add Device ID for RZ/G2H PCIe controller Lad Prabhakar
@ 2020-11-02 9:24 ` Lad Prabhakar
2020-11-02 10:31 ` [cip-dev] [PATCH 4.19.y-cip 0/6] Renesas RZ/G2H add PCIe{EP}/SATA support Pavel Machek
6 siblings, 0 replies; 10+ messages in thread
From: Lad Prabhakar @ 2020-11-02 9:24 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das
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commit 7345e5c1853d7173bf06923c29f93c0308ac89e5 upstream.
Enable sata interface on HiHope RZ/G2H board.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20200907073214.13929-1-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
arch/arm64/boot/dts/renesas/r8a774e1-hihope-rzg2h-ex.dts | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a774e1-hihope-rzg2h-ex.dts b/arch/arm64/boot/dts/renesas/r8a774e1-hihope-rzg2h-ex.dts
index 265355e0de5f..812995939841 100644
--- a/arch/arm64/boot/dts/renesas/r8a774e1-hihope-rzg2h-ex.dts
+++ b/arch/arm64/boot/dts/renesas/r8a774e1-hihope-rzg2h-ex.dts
@@ -13,3 +13,8 @@
compatible = "hoperun,hihope-rzg2-ex", "hoperun,hihope-rzg2h",
"renesas,r8a774e1";
};
+
+/* Set SW43 = ON and SW1001[7] = OFF for SATA port to be activated */
+&sata {
+ status = "okay";
+};
--
2.17.1
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* Re: [cip-dev] [PATCH 4.19.y-cip 0/6] Renesas RZ/G2H add PCIe{EP}/SATA support
2020-11-02 9:24 [cip-dev] [PATCH 4.19.y-cip 0/6] Renesas RZ/G2H add PCIe{EP}/SATA support Lad Prabhakar
` (5 preceding siblings ...)
2020-11-02 9:24 ` [cip-dev] [PATCH 4.19.y-cip 6/6] arm64: dts: renesas: r8a774e1-hihope-rzg2h-ex: Enable sata Lad Prabhakar
@ 2020-11-02 10:31 ` Pavel Machek
2020-11-03 9:22 ` Pavel Machek
2020-11-04 0:42 ` Nobuhiro Iwamatsu
6 siblings, 2 replies; 10+ messages in thread
From: Pavel Machek @ 2020-11-02 10:31 UTC (permalink / raw)
To: Lad Prabhakar; +Cc: cip-dev, Nobuhiro Iwamatsu, Pavel Machek, Biju Das
[-- Attachment #1.1: Type: text/plain, Size: 429 bytes --]
Hi!
> This patch series adds PCIe{EP}/SATA support to Renesas RZ/G2H.
>
> All the patches have been cherry-picked from mainline kernel
> v5.10-rc2.
Looks good and passes our tests. I can apply it if there are no other
comments.
Best regards,
Pavel
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
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* Re: [cip-dev] [PATCH 4.19.y-cip 0/6] Renesas RZ/G2H add PCIe{EP}/SATA support
2020-11-02 10:31 ` [cip-dev] [PATCH 4.19.y-cip 0/6] Renesas RZ/G2H add PCIe{EP}/SATA support Pavel Machek
@ 2020-11-03 9:22 ` Pavel Machek
2020-11-04 0:42 ` Nobuhiro Iwamatsu
1 sibling, 0 replies; 10+ messages in thread
From: Pavel Machek @ 2020-11-03 9:22 UTC (permalink / raw)
To: Pavel Machek; +Cc: Lad Prabhakar, cip-dev, Nobuhiro Iwamatsu, Biju Das
[-- Attachment #1.1: Type: text/plain, Size: 486 bytes --]
Hi!
> > This patch series adds PCIe{EP}/SATA support to Renesas RZ/G2H.
> >
> > All the patches have been cherry-picked from mainline kernel
> > v5.10-rc2.
>
> Looks good and passes our tests. I can apply it if there are no other
> comments.
Thanks for the patches, applied and pushed out.
Best regards,
Pavel
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
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* Re: [cip-dev] [PATCH 4.19.y-cip 0/6] Renesas RZ/G2H add PCIe{EP}/SATA support
2020-11-02 10:31 ` [cip-dev] [PATCH 4.19.y-cip 0/6] Renesas RZ/G2H add PCIe{EP}/SATA support Pavel Machek
2020-11-03 9:22 ` Pavel Machek
@ 2020-11-04 0:42 ` Nobuhiro Iwamatsu
1 sibling, 0 replies; 10+ messages in thread
From: Nobuhiro Iwamatsu @ 2020-11-04 0:42 UTC (permalink / raw)
To: pavel, prabhakar.mahadev-lad.rj; +Cc: cip-dev, biju.das.jz
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Hi,
> -----Original Message-----
> From: Pavel Machek [mailto:pavel@denx.de]
> Sent: Monday, November 2, 2020 7:31 PM
> To: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> Cc: cip-dev@lists.cip-project.org; iwamatsu nobuhiro(岩松 信洋 □SWC◯ACT)
> <nobuhiro1.iwamatsu@toshiba.co.jp>; Pavel Machek <pavel@denx.de>; Biju Das <biju.das.jz@bp.renesas.com>
> Subject: Re: [PATCH 4.19.y-cip 0/6] Renesas RZ/G2H add PCIe{EP}/SATA support
>
> Hi!
>
> > This patch series adds PCIe{EP}/SATA support to Renesas RZ/G2H.
> >
> > All the patches have been cherry-picked from mainline kernel
> > v5.10-rc2.
>
> Looks good and passes our tests. I can apply it if there are no other
> comments.
Looks good to me, too.
Best regards,
Nobuhiro
>
> Best regards,
> Pavel
>
> --
> DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
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2020-11-02 9:24 [cip-dev] [PATCH 4.19.y-cip 0/6] Renesas RZ/G2H add PCIe{EP}/SATA support Lad Prabhakar
2020-11-02 9:24 ` [cip-dev] [PATCH 4.19.y-cip 1/6] arm64: dts: renesas: r8a774e1: Add PCIe device nodes Lad Prabhakar
2020-11-02 9:24 ` [cip-dev] [PATCH 4.19.y-cip 2/6] arm64: dts: renesas: r8a774e1: Add SATA controller node Lad Prabhakar
2020-11-02 9:24 ` [cip-dev] [PATCH 4.19.y-cip 3/6] dt-bindings: pci: rcar-pci-ep: Document r8a774e1 Lad Prabhakar
2020-11-02 9:24 ` [cip-dev] [PATCH 4.19.y-cip 4/6] arm64: dts: renesas: r8a774e1: Add PCIe EP nodes Lad Prabhakar
2020-11-02 9:24 ` [cip-dev] [PATCH 4.19.y-cip 5/6] misc: pci_endpoint_test: Add Device ID for RZ/G2H PCIe controller Lad Prabhakar
2020-11-02 9:24 ` [cip-dev] [PATCH 4.19.y-cip 6/6] arm64: dts: renesas: r8a774e1-hihope-rzg2h-ex: Enable sata Lad Prabhakar
2020-11-02 10:31 ` [cip-dev] [PATCH 4.19.y-cip 0/6] Renesas RZ/G2H add PCIe{EP}/SATA support Pavel Machek
2020-11-03 9:22 ` Pavel Machek
2020-11-04 0:42 ` Nobuhiro Iwamatsu
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