From: Biju Das <biju.das.jz@bp.renesas.com>
To: cip-dev@lists.cip-project.org,
Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>,
Pavel Machek <pavel@denx.de>
Cc: Chris Paterson <chris.paterson2@renesas.com>,
Biju Das <biju.das.jz@bp.renesas.com>,
Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Subject: [PATCH 6.1.y-cip 1/8] clk: renesas: r9a07g044: Add MTU3a clock and reset entry
Date: Tue, 6 Jun 2023 08:52:28 +0100 [thread overview]
Message-ID: <20230606075235.183132-2-biju.das.jz@bp.renesas.com> (raw)
In-Reply-To: <20230606075235.183132-1-biju.das.jz@bp.renesas.com>
commit 576d6b40dcceade7d77e88f63e621349c6937bc3 upstream.
Add MTU3a clock and reset entry to CPG driver.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20221005111855.553436-1-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
drivers/clk/renesas/r9a07g044-cpg.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/renesas/r9a07g044-cpg.c b/drivers/clk/renesas/r9a07g044-cpg.c
index 02a4fc41bb6e..12b1a83625cb 100644
--- a/drivers/clk/renesas/r9a07g044-cpg.c
+++ b/drivers/clk/renesas/r9a07g044-cpg.c
@@ -182,7 +182,7 @@ static const struct {
};
static const struct {
- struct rzg2l_mod_clk common[76];
+ struct rzg2l_mod_clk common[77];
#ifdef CONFIG_CLK_R9A07G054
struct rzg2l_mod_clk drp[0];
#endif
@@ -204,6 +204,8 @@ static const struct {
0x534, 1),
DEF_MOD("ostm2_pclk", R9A07G044_OSTM2_PCLK, R9A07G044_CLK_P0,
0x534, 2),
+ DEF_MOD("mtu_x_mck", R9A07G044_MTU_X_MCK_MTU3, R9A07G044_CLK_P0,
+ 0x538, 0),
DEF_MOD("gpt_pclk", R9A07G044_GPT_PCLK, R9A07G044_CLK_P0,
0x540, 0),
DEF_MOD("poeg_a_clkp", R9A07G044_POEG_A_CLKP, R9A07G044_CLK_P0,
@@ -356,6 +358,7 @@ static struct rzg2l_reset r9a07g044_resets[] = {
DEF_RST(R9A07G044_OSTM0_PRESETZ, 0x834, 0),
DEF_RST(R9A07G044_OSTM1_PRESETZ, 0x834, 1),
DEF_RST(R9A07G044_OSTM2_PRESETZ, 0x834, 2),
+ DEF_RST(R9A07G044_MTU_X_PRESET_MTU3, 0x838, 0),
DEF_RST(R9A07G044_GPT_RST_C, 0x840, 0),
DEF_RST(R9A07G044_POEG_A_RST, 0x844, 0),
DEF_RST(R9A07G044_POEG_B_RST, 0x844, 1),
--
2.25.1
next prev parent reply other threads:[~2023-06-06 7:52 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-06-06 7:52 [PATCH 6.1.y-cip 0/8] Add MTU3 core/counter driver support for RZ/G2L alike SoCs Biju Das
2023-06-06 7:52 ` Biju Das [this message]
2023-06-06 7:52 ` [PATCH 6.1.y-cip 2/8] dt-bindings: timer: Document RZ/G2L MTU3a bindings Biju Das
2023-06-06 9:35 ` Pavel Machek
2023-06-06 10:18 ` Biju Das
2023-06-06 7:52 ` [PATCH 6.1.y-cip 3/8] mfd: Add Renesas RZ/G2L MTU3a core driver Biju Das
2023-06-06 9:59 ` Pavel Machek
2023-06-06 10:11 ` Biju Das
2023-06-09 10:31 ` Pavel Machek
2023-06-09 12:19 ` Biju Das
2023-06-09 10:36 ` Pavel Machek
2023-06-12 11:38 ` Biju Das
2023-06-06 7:52 ` [PATCH 6.1.y-cip 4/8] Documentation: ABI: sysfs-bus-counter: add cascade_counts_enable and external_input_phase_clock_select Biju Das
2023-06-06 10:01 ` Pavel Machek
2023-06-06 10:19 ` Biju Das
2023-06-06 7:52 ` [PATCH 6.1.y-cip 5/8] counter: Add Renesas RZ/G2L MTU3a counter driver Biju Das
2023-06-06 10:08 ` Pavel Machek
2023-06-06 10:33 ` Biju Das
2023-06-06 7:52 ` [PATCH 6.1.y-cip 6/8] MAINTAINERS: Add entries for " Biju Das
2023-06-06 7:52 ` [PATCH 6.1.y-cip 7/8] arm64: dts: renesas: r9a07g044: Add MTU3a node Biju Das
2023-06-06 7:52 ` [PATCH 6.1.y-cip 8/8] arm64: dts: renesas: r9a07g054: " Biju Das
2023-06-06 9:15 ` [PATCH 6.1.y-cip 0/8] Add MTU3 core/counter driver support for RZ/G2L alike SoCs Pavel Machek
2023-06-06 9:17 ` Biju Das
2023-06-22 11:13 ` Pavel Machek
2023-06-22 11:42 ` Biju Das
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