From: Biju Das <biju.das.jz@bp.renesas.com>
To: cip-dev@lists.cip-project.org,
Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>,
Pavel Machek <pavel@denx.de>
Cc: Chris Paterson <chris.paterson2@renesas.com>,
Biju Das <biju.das.jz@bp.renesas.com>,
Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Subject: [PATCH 6.1.y-cip 8/8] arm64: dts: renesas: r9a07g054: Add MTU3a node
Date: Tue, 6 Jun 2023 08:52:35 +0100 [thread overview]
Message-ID: <20230606075235.183132-9-biju.das.jz@bp.renesas.com> (raw)
In-Reply-To: <20230606075235.183132-1-biju.das.jz@bp.renesas.com>
commit dd123dd01def6ad917703542cf7263865bed3239 upstream.
Add MTU3a node to R9A07G054 (RZ/V2L) SoC DTSI.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20230417090159.191346-2-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
arch/arm64/boot/dts/renesas/r9a07g054.dtsi | 70 ++++++++++++++++++++++
1 file changed, 70 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi
index df91ed900a4f..9c046d4bd11d 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi
@@ -168,6 +168,76 @@ soc: soc {
#size-cells = <2>;
ranges;
+ mtu3: timer@10001200 {
+ compatible = "renesas,r9a07g054-mtu3",
+ "renesas,rz-mtu3";
+ reg = <0 0x10001200 0 0xb00>;
+ interrupts = <GIC_SPI 170 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 171 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 173 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 174 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 175 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 176 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 177 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 179 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 180 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 181 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 182 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 183 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 184 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 185 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 186 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 187 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 188 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 189 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 190 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 191 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 192 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 194 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 198 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 199 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 200 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 201 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 202 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 203 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 204 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 205 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 206 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 207 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 209 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 210 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 211 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 212 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 213 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "tgia0", "tgib0", "tgic0", "tgid0",
+ "tgiv0", "tgie0", "tgif0",
+ "tgia1", "tgib1", "tgiv1", "tgiu1",
+ "tgia2", "tgib2", "tgiv2", "tgiu2",
+ "tgia3", "tgib3", "tgic3", "tgid3",
+ "tgiv3",
+ "tgia4", "tgib4", "tgic4", "tgid4",
+ "tgiv4",
+ "tgiu5", "tgiv5", "tgiw5",
+ "tgia6", "tgib6", "tgic6", "tgid6",
+ "tgiv6",
+ "tgia7", "tgib7", "tgic7", "tgid7",
+ "tgiv7",
+ "tgia8", "tgib8", "tgic8", "tgid8",
+ "tgiv8", "tgiu8";
+ clocks = <&cpg CPG_MOD R9A07G054_MTU_X_MCK_MTU3>;
+ power-domains = <&cpg>;
+ resets = <&cpg R9A07G054_MTU_X_PRESET_MTU3>;
+ #pwm-cells = <2>;
+ status = "disabled";
+ };
+
ssi0: ssi@10049c00 {
compatible = "renesas,r9a07g054-ssi",
"renesas,rz-ssi";
--
2.25.1
next prev parent reply other threads:[~2023-06-06 7:53 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-06-06 7:52 [PATCH 6.1.y-cip 0/8] Add MTU3 core/counter driver support for RZ/G2L alike SoCs Biju Das
2023-06-06 7:52 ` [PATCH 6.1.y-cip 1/8] clk: renesas: r9a07g044: Add MTU3a clock and reset entry Biju Das
2023-06-06 7:52 ` [PATCH 6.1.y-cip 2/8] dt-bindings: timer: Document RZ/G2L MTU3a bindings Biju Das
2023-06-06 9:35 ` Pavel Machek
2023-06-06 10:18 ` Biju Das
2023-06-06 7:52 ` [PATCH 6.1.y-cip 3/8] mfd: Add Renesas RZ/G2L MTU3a core driver Biju Das
2023-06-06 9:59 ` Pavel Machek
2023-06-06 10:11 ` Biju Das
2023-06-09 10:31 ` Pavel Machek
2023-06-09 12:19 ` Biju Das
2023-06-09 10:36 ` Pavel Machek
2023-06-12 11:38 ` Biju Das
2023-06-06 7:52 ` [PATCH 6.1.y-cip 4/8] Documentation: ABI: sysfs-bus-counter: add cascade_counts_enable and external_input_phase_clock_select Biju Das
2023-06-06 10:01 ` Pavel Machek
2023-06-06 10:19 ` Biju Das
2023-06-06 7:52 ` [PATCH 6.1.y-cip 5/8] counter: Add Renesas RZ/G2L MTU3a counter driver Biju Das
2023-06-06 10:08 ` Pavel Machek
2023-06-06 10:33 ` Biju Das
2023-06-06 7:52 ` [PATCH 6.1.y-cip 6/8] MAINTAINERS: Add entries for " Biju Das
2023-06-06 7:52 ` [PATCH 6.1.y-cip 7/8] arm64: dts: renesas: r9a07g044: Add MTU3a node Biju Das
2023-06-06 7:52 ` Biju Das [this message]
2023-06-06 9:15 ` [PATCH 6.1.y-cip 0/8] Add MTU3 core/counter driver support for RZ/G2L alike SoCs Pavel Machek
2023-06-06 9:17 ` Biju Das
2023-06-22 11:13 ` Pavel Machek
2023-06-22 11:42 ` Biju Das
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