From: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
To: dmaengine@vger.kernel.org
Cc: Michal Simek <michal.simek@xilinx.com>,
Hyun Kwon <hyun.kwon@xilinx.com>,
Tejas Upadhyay <tejasu@xilinx.com>,
Satish Kumar Nagireddy <SATISHNA@xilinx.com>,
devicetree@vger.kernel.org
Subject: [PATCH v3 1/6] dt: bindings: dma: xilinx: dpdma: DT bindings for Xilinx DPDMA
Date: Thu, 23 Jan 2020 04:29:34 +0200 [thread overview]
Message-ID: <20200123022939.9739-2-laurent.pinchart@ideasonboard.com> (raw)
In-Reply-To: <20200123022939.9739-1-laurent.pinchart@ideasonboard.com>
The ZynqMP includes the DisplayPort subsystem with its own DMA engine
called DPDMA. The DPDMA IP comes with 6 individual channels
(4 for display, 2 for audio). This documentation describes DT bindings
of DPDMA.
Signed-off-by: Hyun Kwon <hyun.kwon@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Reviewed-by: Rob Herring <robh@kernel.org>
---
Changes since v2:
- Fix id URL
- Fix path to dma-controller.yaml
- Update license to GPL-2.0-only OR BSD-2-Clause
Changes since v1:
- Convert the DT bindings to YAML
- Drop the DT child nodes
---
.../dma/xilinx/xlnx,zynqmp-dpdma.yaml | 68 +++++++++++++++++++
MAINTAINERS | 8 +++
include/dt-bindings/dma/xlnx-zynqmp-dpdma.h | 16 +++++
3 files changed, 92 insertions(+)
create mode 100644 Documentation/devicetree/bindings/dma/xilinx/xlnx,zynqmp-dpdma.yaml
create mode 100644 include/dt-bindings/dma/xlnx-zynqmp-dpdma.h
diff --git a/Documentation/devicetree/bindings/dma/xilinx/xlnx,zynqmp-dpdma.yaml b/Documentation/devicetree/bindings/dma/xilinx/xlnx,zynqmp-dpdma.yaml
new file mode 100644
index 000000000000..5de510f8c88c
--- /dev/null
+++ b/Documentation/devicetree/bindings/dma/xilinx/xlnx,zynqmp-dpdma.yaml
@@ -0,0 +1,68 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/dma/xilinx/xlnx,zynqmp-dpdma.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Xilinx ZynqMP DisplayPort DMA Controller Device Tree Bindings
+
+description: |
+ These bindings describe the DMA engine included in the Xilinx ZynqMP
+ DisplayPort Subsystem. The DMA engine supports up to 6 DMA channels (3
+ channels for a video stream, 1 channel for a graphics stream, and 2 channels
+ for an audio stream).
+
+maintainers:
+ - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+
+allOf:
+ - $ref: "../dma-controller.yaml#"
+
+properties:
+ "#dma-cells":
+ const: 1
+ description: |
+ The cell is the DMA channel ID (see dt-bindings/dma/xlnx-zynqmp-dpdma.h
+ for a list of channel IDs).
+
+ compatible:
+ const: xlnx,zynqmp-dpdma
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ description: The AXI clock
+ maxItems: 1
+
+ clock-names:
+ const: axi_clk
+
+required:
+ - "#dma-cells"
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ dma: dma-controller@fd4c0000 {
+ compatible = "xlnx,zynqmp-dpdma";
+ reg = <0x0 0xfd4c0000 0x0 0x1000>;
+ interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&gic>;
+ clocks = <&dpdma_clk>;
+ clock-names = "axi_clk";
+ #dma-cells = <1>;
+ };
+
+...
diff --git a/MAINTAINERS b/MAINTAINERS
index cc0a4a8ae06a..c7a011837102 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -18182,6 +18182,14 @@ F: drivers/misc/Kconfig
F: drivers/misc/Makefile
F: include/uapi/misc/xilinx_sdfec.h
+XILINX ZYNQMP DPDMA DRIVER
+M: Hyun Kwon <hyun.kwon@xilinx.com>
+M: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+L: dmaengine@vger.kernel.org
+S: Supported
+F: Documentation/devicetree/bindings/dma/xilinx/xlnx,zynqmp-dpdma.yaml
+F: include/dt-bindings/dma/xlnx-zynqmp-dpdma.h
+
XILLYBUS DRIVER
M: Eli Billauer <eli.billauer@gmail.com>
L: linux-kernel@vger.kernel.org
diff --git a/include/dt-bindings/dma/xlnx-zynqmp-dpdma.h b/include/dt-bindings/dma/xlnx-zynqmp-dpdma.h
new file mode 100644
index 000000000000..3719cda5679d
--- /dev/null
+++ b/include/dt-bindings/dma/xlnx-zynqmp-dpdma.h
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
+/*
+ * Copyright 2019 Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+ */
+
+#ifndef __DT_BINDINGS_DMA_XLNX_ZYNQMP_DPDMA_H__
+#define __DT_BINDINGS_DMA_XLNX_ZYNQMP_DPDMA_H__
+
+#define ZYNQMP_DPDMA_VIDEO0 0
+#define ZYNQMP_DPDMA_VIDEO1 1
+#define ZYNQMP_DPDMA_VIDEO2 2
+#define ZYNQMP_DPDMA_GRAPHICS 3
+#define ZYNQMP_DPDMA_AUDIO0 4
+#define ZYNQMP_DPDMA_AUDIO1 5
+
+#endif /* __DT_BINDINGS_DMA_XLNX_ZYNQMP_DPDMA_H__ */
--
Regards,
Laurent Pinchart
next prev parent reply other threads:[~2020-01-23 2:30 UTC|newest]
Thread overview: 46+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-01-23 2:29 [PATCH v3 0/6] dma: Add Xilinx ZynqMP DPDMA driver Laurent Pinchart
2020-01-23 2:29 ` Laurent Pinchart [this message]
2020-01-23 2:29 ` [PATCH v3 2/6] dmaengine: Add interleaved cyclic transaction type Laurent Pinchart
2020-01-23 8:03 ` Peter Ujfalusi
2020-01-23 8:43 ` Vinod Koul
2020-01-23 8:51 ` Peter Ujfalusi
2020-01-23 12:23 ` Laurent Pinchart
2020-01-24 6:10 ` Vinod Koul
2020-01-24 8:50 ` Laurent Pinchart
2020-02-10 14:06 ` Laurent Pinchart
2020-02-13 13:29 ` Vinod Koul
2020-02-13 13:48 ` Laurent Pinchart
2020-02-13 14:07 ` Vinod Koul
2020-02-13 14:15 ` Peter Ujfalusi
2020-02-13 16:52 ` Laurent Pinchart
2020-02-14 4:23 ` Vinod Koul
2020-02-14 16:22 ` Laurent Pinchart
2020-02-17 10:00 ` Peter Ujfalusi
2020-02-19 9:25 ` Vinod Koul
2020-02-26 16:30 ` Laurent Pinchart
2020-03-02 3:47 ` Vinod Koul
2020-03-02 7:37 ` Laurent Pinchart
2020-03-03 4:32 ` Vinod Koul
2020-03-03 19:22 ` Laurent Pinchart
2020-03-04 5:13 ` Vinod Koul
2020-03-04 8:01 ` Laurent Pinchart
2020-03-04 15:37 ` Vinod Koul
2020-03-04 16:00 ` Laurent Pinchart
2020-03-04 16:24 ` Vinod Koul
[not found] ` <20200311155248.GA4772@pendragon.ideasonboard.com>
2020-03-18 15:14 ` Laurent Pinchart
2020-03-25 16:00 ` Laurent Pinchart
2020-03-26 7:02 ` Vinod Koul
2020-04-08 17:00 ` Laurent Pinchart
2020-04-15 15:12 ` Laurent Pinchart
2020-03-06 14:49 ` Peter Ujfalusi
2020-03-11 23:15 ` Laurent Pinchart
2020-02-26 16:24 ` Laurent Pinchart
2020-03-02 3:42 ` Vinod Koul
2020-01-24 7:20 ` Peter Ujfalusi
2020-01-24 7:38 ` Peter Ujfalusi
2020-01-24 8:58 ` Laurent Pinchart
2020-01-24 8:56 ` Laurent Pinchart
2020-01-23 2:29 ` [PATCH v3 3/6] dmaengine: virt-dma: Use lockdep to check locking requirements Laurent Pinchart
2020-01-23 2:29 ` [PATCH v3 4/6] dmaengine: xilinx: dpdma: Add the Xilinx DisplayPort DMA engine driver Laurent Pinchart
2020-01-23 2:29 ` [PATCH v3 5/6] dmaengine: xilinx: dpdma: Add debugfs support Laurent Pinchart
2020-01-23 2:29 ` [PATCH v3 6/6] arm64: dts: zynqmp: Add DPDMA node Laurent Pinchart
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