* [PATCH v4, 0/3] Add mt8186 dsi compatoble & Convert dsi_dtbinding to .yaml
@ 2022-04-09 9:11 xinlei.lee
2022-04-09 9:11 ` [PATCH v4, 1/3] dt-bindings: display: mediatek: dsi: " xinlei.lee
` (2 more replies)
0 siblings, 3 replies; 9+ messages in thread
From: xinlei.lee @ 2022-04-09 9:11 UTC (permalink / raw)
To: chunkuang.hu, p.zabel, airlied, daniel, robh+dt, matthias.bgg
Cc: devicetree, jitao.shi, Xinlei Lee, linux-kernel, dri-devel,
Project_Global_Chrome_Upstream_Group, linux-mediatek,
rex-bc.chen, linux-arm-kernel
From: Xinlei Lee <xinlei.lee@mediatek.com>
Changes since v3:
1. Add dsi port property.
2. Fix some formatting.
Changes since v2:
1. Added #address-cells, #size-cells two properties.
2. Fix some formatting issues.
Changes since v1:
1. Delete the mediatek,dsi.txt & Add the mediatek,dsi.yaml.
2. Ignore the Move the getting bridge node function patch for V1.
Xinlei Lee (3):
dt-bindings: display: mediatek: dsi: Convert dsi_dtbinding to .yaml
dt-bindings: display: mediatek: dsi: Add compatible for MediaTek
MT8186
drm/mediatek: Add mt8186 dsi compatible to mtk_dsi.c
.../display/mediatek/mediatek,dsi.txt | 62 ---------
.../display/mediatek/mediatek,dsi.yaml | 119 ++++++++++++++++++
drivers/gpu/drm/mediatek/mtk_dsi.c | 8 ++
3 files changed, 127 insertions(+), 62 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt
create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yaml
--
2.18.0
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH v4, 1/3] dt-bindings: display: mediatek: dsi: Convert dsi_dtbinding to .yaml
2022-04-09 9:11 [PATCH v4, 0/3] Add mt8186 dsi compatoble & Convert dsi_dtbinding to .yaml xinlei.lee
@ 2022-04-09 9:11 ` xinlei.lee
2022-04-12 9:17 ` CK Hu
2022-04-13 21:20 ` [PATCH v4,1/3] " Rob Herring
2022-04-09 9:11 ` [PATCH v4, 2/3] dt-bindings: display: mediatek: dsi: Add compatible for MediaTek MT8186 xinlei.lee
2022-04-09 9:11 ` [PATCH v4,3/3] drm/mediatek: Add mt8186 dsi compatible to mtk_dsi.c xinlei.lee
2 siblings, 2 replies; 9+ messages in thread
From: xinlei.lee @ 2022-04-09 9:11 UTC (permalink / raw)
To: chunkuang.hu, p.zabel, airlied, daniel, robh+dt, matthias.bgg
Cc: devicetree, jitao.shi, Xinlei Lee, linux-kernel, dri-devel,
Project_Global_Chrome_Upstream_Group, linux-mediatek,
rex-bc.chen, linux-arm-kernel
From: Xinlei Lee <xinlei.lee@mediatek.com>
Convert mediatek,dsi.txt to mediatek,dsi.yaml format
Signed-off-by: Xinlei Lee <xinlei.lee@mediatek.com>
---
.../display/mediatek/mediatek,dsi.txt | 62 ---------
.../display/mediatek/mediatek,dsi.yaml | 118 ++++++++++++++++++
2 files changed, 118 insertions(+), 62 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt
create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yaml
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt
deleted file mode 100644
index 36b01458f45c..000000000000
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt
+++ /dev/null
@@ -1,62 +0,0 @@
-Mediatek DSI Device
-===================
-
-The Mediatek DSI function block is a sink of the display subsystem and can
-drive up to 4-lane MIPI DSI output. Two DSIs can be synchronized for dual-
-channel output.
-
-Required properties:
-- compatible: "mediatek,<chip>-dsi"
-- the supported chips are mt2701, mt7623, mt8167, mt8173 and mt8183.
-- reg: Physical base address and length of the controller's registers
-- interrupts: The interrupt signal from the function block.
-- clocks: device clocks
- See Documentation/devicetree/bindings/clock/clock-bindings.txt for details.
-- clock-names: must contain "engine", "digital", and "hs"
-- phys: phandle link to the MIPI D-PHY controller.
-- phy-names: must contain "dphy"
-- port: Output port node with endpoint definitions as described in
- Documentation/devicetree/bindings/graph.txt. This port should be connected
- to the input port of an attached DSI panel or DSI-to-eDP encoder chip.
-
-Optional properties:
-- resets: list of phandle + reset specifier pair, as described in [1].
-
-[1] Documentation/devicetree/bindings/reset/reset.txt
-
-MIPI TX Configuration Module
-============================
-
-See phy/mediatek,dsi-phy.yaml
-
-Example:
-
-mipi_tx0: mipi-dphy@10215000 {
- compatible = "mediatek,mt8173-mipi-tx";
- reg = <0 0x10215000 0 0x1000>;
- clocks = <&clk26m>;
- clock-output-names = "mipi_tx0_pll";
- #clock-cells = <0>;
- #phy-cells = <0>;
- drive-strength-microamp = <4600>;
- nvmem-cells= <&mipi_tx_calibration>;
- nvmem-cell-names = "calibration-data";
-};
-
-dsi0: dsi@1401b000 {
- compatible = "mediatek,mt8173-dsi";
- reg = <0 0x1401b000 0 0x1000>;
- interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_LOW>;
- clocks = <&mmsys MM_DSI0_ENGINE>, <&mmsys MM_DSI0_DIGITAL>,
- <&mipi_tx0>;
- clock-names = "engine", "digital", "hs";
- resets = <&mmsys MT8173_MMSYS_SW0_RST_B_DISP_DSI0>;
- phys = <&mipi_tx0>;
- phy-names = "dphy";
-
- port {
- dsi0_out: endpoint {
- remote-endpoint = <&panel_in>;
- };
- };
-};
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yaml
new file mode 100644
index 000000000000..431bb981394f
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yaml
@@ -0,0 +1,118 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/mediatek/mediatek,dsi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek DSI Controller Device Tree Bindings
+
+maintainers:
+ - CK Hu <ck.hu@mediatek.com>
+ - Jitao Shi <jitao.shi@mediatek.com>
+ - Xinlei Lee <xinlei.lee@mediatek.com>
+
+description: |
+ The MediaTek DSI function block is a sink of the display subsystem and can
+ drive up to 4-lane MIPI DSI output. Two DSIs can be synchronized for dual-
+ channel output.
+
+properties:
+ compatible:
+ enum:
+ - mediatek,mt2701-dsi
+ - mediatek,mt7623-dsi
+ - mediatek,mt8167-dsi
+ - mediatek,mt8173-dsi
+ - mediatek,mt8183-dsi
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ power-domains:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: Engine Clock
+ - description: Digital Clock
+ - description: HS Clock
+
+ clock-names:
+ items:
+ - const: engine
+ - const: digital
+ - const: hs
+
+ resets:
+ maxItems: 1
+
+ phys:
+ maxItems: 1
+
+ phy-names:
+ items:
+ - const: dphy
+
+ port:
+ $ref: /schemas/graph.yaml#/properties/port
+ description:
+ Output port node. This port should be connected to the input
+ port of an attached DSI panel or DSI-to-eDP encoder chip.
+
+
+ "#address-cells":
+ const: 2
+
+ "#size-cells":
+ const: 2
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - power-domains
+ - clocks
+ - clock-names
+ - phys
+ - phy-names
+ - port
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/mt8183-clk.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/power/mt8183-power.h>
+ #include <dt-bindings/phy/phy.h>
+ #include <dt-bindings/reset/mt8183-resets.h>
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ dsi0: dsi@14014000 {
+ compatible = "mediatek,mt8183-dsi";
+ reg = <0 0x14014000 0 0x1000>;
+ interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
+ clocks = <&mmsys CLK_MM_DSI0_MM>,
+ <&mmsys CLK_MM_DSI0_IF>,
+ <&mipi_tx0>;
+ clock-names = "engine", "digital", "hs";
+ resets = <&mmsys MT8183_MMSYS_SW0_RST_B_DISP_DSI0>;
+ phys = <&mipi_tx0>;
+ phy-names = "dphy";
+ port {
+ dsi0_out: endpoint {
+ remote-endpoint = <&panel_in>;
+ };
+ };
+ };
+ };
+
+...
--
2.18.0
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH v4, 2/3] dt-bindings: display: mediatek: dsi: Add compatible for MediaTek MT8186
2022-04-09 9:11 [PATCH v4, 0/3] Add mt8186 dsi compatoble & Convert dsi_dtbinding to .yaml xinlei.lee
2022-04-09 9:11 ` [PATCH v4, 1/3] dt-bindings: display: mediatek: dsi: " xinlei.lee
@ 2022-04-09 9:11 ` xinlei.lee
2022-04-13 21:20 ` [PATCH v4,2/3] " Rob Herring
2022-04-09 9:11 ` [PATCH v4,3/3] drm/mediatek: Add mt8186 dsi compatible to mtk_dsi.c xinlei.lee
2 siblings, 1 reply; 9+ messages in thread
From: xinlei.lee @ 2022-04-09 9:11 UTC (permalink / raw)
To: chunkuang.hu, p.zabel, airlied, daniel, robh+dt, matthias.bgg
Cc: devicetree, jitao.shi, Xinlei Lee, linux-kernel, dri-devel,
Project_Global_Chrome_Upstream_Group, linux-mediatek,
rex-bc.chen, linux-arm-kernel
From: Xinlei Lee <xinlei.lee@mediatek.com>
Add dt-binding documentation of dsi for MediaTek MT8186 SoC.
Signed-off-by: Xinlei Lee <xinlei.lee@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
---
.../devicetree/bindings/display/mediatek/mediatek,dsi.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yaml
index 431bb981394f..4ef0d3bf55ca 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yaml
@@ -24,6 +24,7 @@ properties:
- mediatek,mt8167-dsi
- mediatek,mt8173-dsi
- mediatek,mt8183-dsi
+ - mediatek,mt8186-dsi
reg:
maxItems: 1
--
2.18.0
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH v4,3/3] drm/mediatek: Add mt8186 dsi compatible to mtk_dsi.c
2022-04-09 9:11 [PATCH v4, 0/3] Add mt8186 dsi compatoble & Convert dsi_dtbinding to .yaml xinlei.lee
2022-04-09 9:11 ` [PATCH v4, 1/3] dt-bindings: display: mediatek: dsi: " xinlei.lee
2022-04-09 9:11 ` [PATCH v4, 2/3] dt-bindings: display: mediatek: dsi: Add compatible for MediaTek MT8186 xinlei.lee
@ 2022-04-09 9:11 ` xinlei.lee
2 siblings, 0 replies; 9+ messages in thread
From: xinlei.lee @ 2022-04-09 9:11 UTC (permalink / raw)
To: chunkuang.hu, p.zabel, airlied, daniel, robh+dt, matthias.bgg
Cc: devicetree, jitao.shi, Xinlei Lee, linux-kernel, dri-devel,
Project_Global_Chrome_Upstream_Group, linux-mediatek,
rex-bc.chen, linux-arm-kernel
From: Xinlei Lee <xinlei.lee@mediatek.com>
Add the compatible because use different cmdq addresses in mt8186.
Signed-off-by: Xinlei Lee <xinlei.lee@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
---
drivers/gpu/drm/mediatek/mtk_dsi.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/mtk_dsi.c
index ccb0511b9cd5..b13fd0317e96 100644
--- a/drivers/gpu/drm/mediatek/mtk_dsi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
@@ -1155,6 +1155,12 @@ static const struct mtk_dsi_driver_data mt8183_dsi_driver_data = {
.has_size_ctl = true,
};
+static const struct mtk_dsi_driver_data mt8186_dsi_driver_data = {
+ .reg_cmdq_off = 0xd00,
+ .has_shadow_ctl = true,
+ .has_size_ctl = true,
+};
+
static const struct of_device_id mtk_dsi_of_match[] = {
{ .compatible = "mediatek,mt2701-dsi",
.data = &mt2701_dsi_driver_data },
@@ -1162,6 +1168,8 @@ static const struct of_device_id mtk_dsi_of_match[] = {
.data = &mt8173_dsi_driver_data },
{ .compatible = "mediatek,mt8183-dsi",
.data = &mt8183_dsi_driver_data },
+ { .compatible = "mediatek,mt8186-dsi",
+ .data = &mt8186_dsi_driver_data },
{ },
};
MODULE_DEVICE_TABLE(of, mtk_dsi_of_match);
--
2.18.0
^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH v4, 1/3] dt-bindings: display: mediatek: dsi: Convert dsi_dtbinding to .yaml
2022-04-09 9:11 ` [PATCH v4, 1/3] dt-bindings: display: mediatek: dsi: " xinlei.lee
@ 2022-04-12 9:17 ` CK Hu
2022-04-12 13:00 ` xinlei.lee
2022-04-13 21:20 ` [PATCH v4,1/3] " Rob Herring
1 sibling, 1 reply; 9+ messages in thread
From: CK Hu @ 2022-04-12 9:17 UTC (permalink / raw)
To: xinlei.lee, chunkuang.hu, p.zabel, airlied, daniel, robh+dt,
matthias.bgg
Cc: devicetree, jitao.shi, linux-kernel, dri-devel,
Project_Global_Chrome_Upstream_Group, linux-mediatek,
rex-bc.chen, linux-arm-kernel
Hi, Xinlei:
On Sat, 2022-04-09 at 17:11 +0800, xinlei.lee@mediatek.com wrote:
> From: Xinlei Lee <xinlei.lee@mediatek.com>
>
> Convert mediatek,dsi.txt to mediatek,dsi.yaml format
>
> Signed-off-by: Xinlei Lee <xinlei.lee@mediatek.com>
> ---
> .../display/mediatek/mediatek,dsi.txt | 62 ---------
> .../display/mediatek/mediatek,dsi.yaml | 118
> ++++++++++++++++++
> 2 files changed, 118 insertions(+), 62 deletions(-)
> delete mode 100644
> Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt
> create mode 100644
> Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yaml
>
> diff --git
> a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt
> b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt
> deleted file mode 100644
> index 36b01458f45c..000000000000
> ---
> a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt
> +++ /dev/null
> @@ -1,62 +0,0 @@
> -Mediatek DSI Device
> -===================
> -
> -The Mediatek DSI function block is a sink of the display subsystem
> and can
> -drive up to 4-lane MIPI DSI output. Two DSIs can be synchronized for
> dual-
> -channel output.
> -
> -Required properties:
> -- compatible: "mediatek,<chip>-dsi"
> -- the supported chips are mt2701, mt7623, mt8167, mt8173 and mt8183.
> -- reg: Physical base address and length of the controller's
> registers
> -- interrupts: The interrupt signal from the function block.
> -- clocks: device clocks
> - See Documentation/devicetree/bindings/clock/clock-bindings.txt for
> details.
> -- clock-names: must contain "engine", "digital", and "hs"
> -- phys: phandle link to the MIPI D-PHY controller.
> -- phy-names: must contain "dphy"
> -- port: Output port node with endpoint definitions as described in
> - Documentation/devicetree/bindings/graph.txt. This port should be
> connected
> - to the input port of an attached DSI panel or DSI-to-eDP encoder
> chip.
> -
> -Optional properties:
> -- resets: list of phandle + reset specifier pair, as described in
> [1].
> -
> -[1] Documentation/devicetree/bindings/reset/reset.txt
> -
> -MIPI TX Configuration Module
> -============================
> -
> -See phy/mediatek,dsi-phy.yaml
> -
> -Example:
> -
> -mipi_tx0: mipi-dphy@10215000 {
> - compatible = "mediatek,mt8173-mipi-tx";
> - reg = <0 0x10215000 0 0x1000>;
> - clocks = <&clk26m>;
> - clock-output-names = "mipi_tx0_pll";
> - #clock-cells = <0>;
> - #phy-cells = <0>;
> - drive-strength-microamp = <4600>;
> - nvmem-cells= <&mipi_tx_calibration>;
> - nvmem-cell-names = "calibration-data";
> -};
> -
> -dsi0: dsi@1401b000 {
> - compatible = "mediatek,mt8173-dsi";
> - reg = <0 0x1401b000 0 0x1000>;
> - interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_LOW>;
> - clocks = <&mmsys MM_DSI0_ENGINE>, <&mmsys MM_DSI0_DIGITAL>,
> - <&mipi_tx0>;
> - clock-names = "engine", "digital", "hs";
> - resets = <&mmsys MT8173_MMSYS_SW0_RST_B_DISP_DSI0>;
> - phys = <&mipi_tx0>;
> - phy-names = "dphy";
> -
> - port {
> - dsi0_out: endpoint {
> - remote-endpoint = <&panel_in>;
> - };
> - };
> -};
> diff --git
> a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yam
> l
> b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yam
> l
> new file mode 100644
> index 000000000000..431bb981394f
> --- /dev/null
> +++
> b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yam
> l
> @@ -0,0 +1,118 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id:
> https://urldefense.com/v3/__http://devicetree.org/schemas/display/mediatek/mediatek,dsi.yaml*__;Iw!!CTRNKA9wMg0ARbw!1nUf3PGHra5nGo845exNyAn1KxdDMSV2ISukRJ6hQejfVta1JOIVoNEZ5BleoA$
>
> +$schema:
> https://urldefense.com/v3/__http://devicetree.org/meta-schemas/core.yaml*__;Iw!!CTRNKA9wMg0ARbw!1nUf3PGHra5nGo845exNyAn1KxdDMSV2ISukRJ6hQejfVta1JOIVoNHzl2rp1Q$
>
> +
> +title: MediaTek DSI Controller Device Tree Bindings
> +
> +maintainers:
> + - CK Hu <ck.hu@mediatek.com>
Replace 'CK Hu' with MediaTek DRM driver maintainer:
Chun-Kuang Hu <chunkuang.hu@kernel.org>
Philipp Zabel <p.zabel@pengutronix.de>
> + - Jitao Shi <jitao.shi@mediatek.com>
> + - Xinlei Lee <xinlei.lee@mediatek.com>
> +
> +description: |
> + The MediaTek DSI function block is a sink of the display subsystem
> and can
> + drive up to 4-lane MIPI DSI output. Two DSIs can be synchronized
> for dual-
> + channel output.
> +
> +properties:
> + compatible:
> + enum:
> + - mediatek,mt2701-dsi
> + - mediatek,mt7623-dsi
> + - mediatek,mt8167-dsi
> + - mediatek,mt8173-dsi
> + - mediatek,mt8183-dsi
> +
> + reg:
> + maxItems: 1
> +
> + interrupts:
> + maxItems: 1
> +
> + power-domains:
> + maxItems: 1
> +
> + clocks:
> + items:
> + - description: Engine Clock
> + - description: Digital Clock
> + - description: HS Clock
> +
> + clock-names:
> + items:
> + - const: engine
> + - const: digital
> + - const: hs
> +
> + resets:
> + maxItems: 1
> +
> + phys:
> + maxItems: 1
> +
> + phy-names:
> + items:
> + - const: dphy
> +
> + port:
> + $ref: /schemas/graph.yaml#/properties/port
> + description:
> + Output port node. This port should be connected to the input
> + port of an attached DSI panel or DSI-to-eDP encoder chip.
> +
> +
> + "#address-cells":
> + const: 2
> +
> + "#size-cells":
> + const: 2
> +
> +required:
> + - compatible
> + - reg
> + - interrupts
> + - power-domains
> + - clocks
> + - clock-names
> + - phys
> + - phy-names
> + - port
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/mt8183-clk.h>
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> + #include <dt-bindings/interrupt-controller/irq.h>
> + #include <dt-bindings/power/mt8183-power.h>
> + #include <dt-bindings/phy/phy.h>
> + #include <dt-bindings/reset/mt8183-resets.h>
> +
> + soc {
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + dsi0: dsi@14014000 {
> + compatible = "mediatek,mt8183-dsi";
> + reg = <0 0x14014000 0 0x1000>;
> + interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_LOW>;
> + power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
> + clocks = <&mmsys CLK_MM_DSI0_MM>,
> + <&mmsys CLK_MM_DSI0_IF>,
> + <&mipi_tx0>;
> + clock-names = "engine", "digital", "hs";
> + resets = <&mmsys MT8183_MMSYS_SW0_RST_B_DISP_DSI0>;
> + phys = <&mipi_tx0>;
> + phy-names = "dphy";
> + port {
> + dsi0_out: endpoint {
> + remote-endpoint = <&panel_in>;
> + };
> + };
> + };
> + };
> +
> +...
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v4, 1/3] dt-bindings: display: mediatek: dsi: Convert dsi_dtbinding to .yaml
2022-04-12 9:17 ` CK Hu
@ 2022-04-12 13:00 ` xinlei.lee
0 siblings, 0 replies; 9+ messages in thread
From: xinlei.lee @ 2022-04-12 13:00 UTC (permalink / raw)
To: CK Hu, chunkuang.hu, p.zabel, airlied, daniel, robh+dt, matthias.bgg
Cc: devicetree, jitao.shi, linux-kernel, dri-devel,
Project_Global_Chrome_Upstream_Group, linux-mediatek,
rex-bc.chen, linux-arm-kernel
On Tue, 2022-04-12 at 17:17 +0800, CK Hu wrote:
> Hi, Xinlei:
>
> On Sat, 2022-04-09 at 17:11 +0800, xinlei.lee@mediatek.com wrote:
> > From: Xinlei Lee <xinlei.lee@mediatek.com>
> >
> > Convert mediatek,dsi.txt to mediatek,dsi.yaml format
> >
> > Signed-off-by: Xinlei Lee <xinlei.lee@mediatek.com>
> > ---
> > .../display/mediatek/mediatek,dsi.txt | 62 ---------
> > .../display/mediatek/mediatek,dsi.yaml | 118
> > ++++++++++++++++++
> > 2 files changed, 118 insertions(+), 62 deletions(-)
> > delete mode 100644
> > Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt
> > create mode 100644
> > Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yam
> > l
> >
> > diff --git
> > a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.t
> > xt
> > b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.t
> > xt
> > deleted file mode 100644
> > index 36b01458f45c..000000000000
> > ---
> > a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.t
> > xt
> > +++ /dev/null
> > @@ -1,62 +0,0 @@
> > -Mediatek DSI Device
> > -===================
> > -
> > -The Mediatek DSI function block is a sink of the display subsystem
> > and can
> > -drive up to 4-lane MIPI DSI output. Two DSIs can be synchronized
> > for
> > dual-
> > -channel output.
> > -
> > -Required properties:
> > -- compatible: "mediatek,<chip>-dsi"
> > -- the supported chips are mt2701, mt7623, mt8167, mt8173 and
> > mt8183.
> > -- reg: Physical base address and length of the controller's
> > registers
> > -- interrupts: The interrupt signal from the function block.
> > -- clocks: device clocks
> > - See Documentation/devicetree/bindings/clock/clock-bindings.txt
> > for
> > details.
> > -- clock-names: must contain "engine", "digital", and "hs"
> > -- phys: phandle link to the MIPI D-PHY controller.
> > -- phy-names: must contain "dphy"
> > -- port: Output port node with endpoint definitions as described in
> > - Documentation/devicetree/bindings/graph.txt. This port should be
> > connected
> > - to the input port of an attached DSI panel or DSI-to-eDP encoder
> > chip.
> > -
> > -Optional properties:
> > -- resets: list of phandle + reset specifier pair, as described in
> > [1].
> > -
> > -[1] Documentation/devicetree/bindings/reset/reset.txt
> > -
> > -MIPI TX Configuration Module
> > -============================
> > -
> > -See phy/mediatek,dsi-phy.yaml
> > -
> > -Example:
> > -
> > -mipi_tx0: mipi-dphy@10215000 {
> > - compatible = "mediatek,mt8173-mipi-tx";
> > - reg = <0 0x10215000 0 0x1000>;
> > - clocks = <&clk26m>;
> > - clock-output-names = "mipi_tx0_pll";
> > - #clock-cells = <0>;
> > - #phy-cells = <0>;
> > - drive-strength-microamp = <4600>;
> > - nvmem-cells= <&mipi_tx_calibration>;
> > - nvmem-cell-names = "calibration-data";
> > -};
> > -
> > -dsi0: dsi@1401b000 {
> > - compatible = "mediatek,mt8173-dsi";
> > - reg = <0 0x1401b000 0 0x1000>;
> > - interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_LOW>;
> > - clocks = <&mmsys MM_DSI0_ENGINE>, <&mmsys MM_DSI0_DIGITAL>,
> > - <&mipi_tx0>;
> > - clock-names = "engine", "digital", "hs";
> > - resets = <&mmsys MT8173_MMSYS_SW0_RST_B_DISP_DSI0>;
> > - phys = <&mipi_tx0>;
> > - phy-names = "dphy";
> > -
> > - port {
> > - dsi0_out: endpoint {
> > - remote-endpoint = <&panel_in>;
> > - };
> > - };
> > -};
> > diff --git
> > a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.y
> > am
> > l
> > b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.y
> > am
> > l
> > new file mode 100644
> > index 000000000000..431bb981394f
> > --- /dev/null
> > +++
> > b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.y
> > am
> > l
> > @@ -0,0 +1,118 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id:
> >
https://urldefense.com/v3/__http://devicetree.org/schemas/display/mediatek/mediatek,dsi.yaml*__;Iw!!CTRNKA9wMg0ARbw!1nUf3PGHra5nGo845exNyAn1KxdDMSV2ISukRJ6hQejfVta1JOIVoNEZ5BleoA$
> >
> > +$schema:
> >
https://urldefense.com/v3/__http://devicetree.org/meta-schemas/core.yaml*__;Iw!!CTRNKA9wMg0ARbw!1nUf3PGHra5nGo845exNyAn1KxdDMSV2ISukRJ6hQejfVta1JOIVoNHzl2rp1Q$
> >
> > +
> > +title: MediaTek DSI Controller Device Tree Bindings
> > +
> > +maintainers:
> > + - CK Hu <ck.hu@mediatek.com>
>
> Replace 'CK Hu' with MediaTek DRM driver maintainer:
>
> Chun-Kuang Hu <chunkuang.hu@kernel.org>
> Philipp Zabel <p.zabel@pengutronix.de>
>
> > + - Jitao Shi <jitao.shi@mediatek.com>
> > + - Xinlei Lee <xinlei.lee@mediatek.com>
> > +
> > +description: |
> > + The MediaTek DSI function block is a sink of the display
> > subsystem
> > and can
> > + drive up to 4-lane MIPI DSI output. Two DSIs can be synchronized
> > for dual-
> > + channel output.
> > +
> > +properties:
> > + compatible:
> > + enum:
> > + - mediatek,mt2701-dsi
> > + - mediatek,mt7623-dsi
> > + - mediatek,mt8167-dsi
> > + - mediatek,mt8173-dsi
> > + - mediatek,mt8183-dsi
> > +
> > + reg:
> > + maxItems: 1
> > +
> > + interrupts:
> > + maxItems: 1
> > +
> > + power-domains:
> > + maxItems: 1
> > +
> > + clocks:
> > + items:
> > + - description: Engine Clock
> > + - description: Digital Clock
> > + - description: HS Clock
> > +
> > + clock-names:
> > + items:
> > + - const: engine
> > + - const: digital
> > + - const: hs
> > +
> > + resets:
> > + maxItems: 1
> > +
> > + phys:
> > + maxItems: 1
> > +
> > + phy-names:
> > + items:
> > + - const: dphy
> > +
> > + port:
> > + $ref: /schemas/graph.yaml#/properties/port
> > + description:
> > + Output port node. This port should be connected to the input
> > + port of an attached DSI panel or DSI-to-eDP encoder chip.
> > +
> > +
> > + "#address-cells":
> > + const: 2
> > +
> > + "#size-cells":
> > + const: 2
> > +
> > +required:
> > + - compatible
> > + - reg
> > + - interrupts
> > + - power-domains
> > + - clocks
> > + - clock-names
> > + - phys
> > + - phy-names
> > + - port
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > + - |
> > + #include <dt-bindings/clock/mt8183-clk.h>
> > + #include <dt-bindings/interrupt-controller/arm-gic.h>
> > + #include <dt-bindings/interrupt-controller/irq.h>
> > + #include <dt-bindings/power/mt8183-power.h>
> > + #include <dt-bindings/phy/phy.h>
> > + #include <dt-bindings/reset/mt8183-resets.h>
> > +
> > + soc {
> > + #address-cells = <2>;
> > + #size-cells = <2>;
> > +
> > + dsi0: dsi@14014000 {
> > + compatible = "mediatek,mt8183-dsi";
> > + reg = <0 0x14014000 0 0x1000>;
> > + interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_LOW>;
> > + power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
> > + clocks = <&mmsys CLK_MM_DSI0_MM>,
> > + <&mmsys CLK_MM_DSI0_IF>,
> > + <&mipi_tx0>;
> > + clock-names = "engine", "digital", "hs";
> > + resets = <&mmsys MT8183_MMSYS_SW0_RST_B_DISP_DSI0>;
> > + phys = <&mipi_tx0>;
> > + phy-names = "dphy";
> > + port {
> > + dsi0_out: endpoint {
> > + remote-endpoint = <&panel_in>;
> > + };
> > + };
> > + };
> > + };
> > +
> > +...
>
>
Hi CK:
Thanks for your review.
I will replace in the next version.
Best Regards!
xinlei
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v4,1/3] dt-bindings: display: mediatek: dsi: Convert dsi_dtbinding to .yaml
2022-04-09 9:11 ` [PATCH v4, 1/3] dt-bindings: display: mediatek: dsi: " xinlei.lee
2022-04-12 9:17 ` CK Hu
@ 2022-04-13 21:20 ` Rob Herring
2022-04-28 12:49 ` Rex-BC Chen
1 sibling, 1 reply; 9+ messages in thread
From: Rob Herring @ 2022-04-13 21:20 UTC (permalink / raw)
To: xinlei.lee
Cc: chunkuang.hu, jitao.shi, devicetree, airlied, linux-kernel,
dri-devel, Project_Global_Chrome_Upstream_Group, rex-bc.chen,
linux-mediatek, matthias.bgg, linux-arm-kernel
On Sat, Apr 09, 2022 at 05:11:52PM +0800, xinlei.lee@mediatek.com wrote:
> From: Xinlei Lee <xinlei.lee@mediatek.com>
>
> Convert mediatek,dsi.txt to mediatek,dsi.yaml format
>
> Signed-off-by: Xinlei Lee <xinlei.lee@mediatek.com>
> ---
> .../display/mediatek/mediatek,dsi.txt | 62 ---------
> .../display/mediatek/mediatek,dsi.yaml | 118 ++++++++++++++++++
> 2 files changed, 118 insertions(+), 62 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt
> create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yaml
> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yaml
> new file mode 100644
> index 000000000000..431bb981394f
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yaml
> @@ -0,0 +1,118 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/display/mediatek/mediatek,dsi.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: MediaTek DSI Controller Device Tree Bindings
> +
> +maintainers:
> + - CK Hu <ck.hu@mediatek.com>
> + - Jitao Shi <jitao.shi@mediatek.com>
> + - Xinlei Lee <xinlei.lee@mediatek.com>
> +
> +description: |
> + The MediaTek DSI function block is a sink of the display subsystem and can
> + drive up to 4-lane MIPI DSI output. Two DSIs can be synchronized for dual-
> + channel output.
allOf:
- $ref: /schemas/display/dsi-controller.yaml#
> +
> +properties:
> + compatible:
> + enum:
> + - mediatek,mt2701-dsi
> + - mediatek,mt7623-dsi
> + - mediatek,mt8167-dsi
> + - mediatek,mt8173-dsi
> + - mediatek,mt8183-dsi
> +
> + reg:
> + maxItems: 1
> +
> + interrupts:
> + maxItems: 1
> +
> + power-domains:
> + maxItems: 1
> +
> + clocks:
> + items:
> + - description: Engine Clock
> + - description: Digital Clock
> + - description: HS Clock
> +
> + clock-names:
> + items:
> + - const: engine
> + - const: digital
> + - const: hs
> +
> + resets:
> + maxItems: 1
> +
> + phys:
> + maxItems: 1
> +
> + phy-names:
> + items:
> + - const: dphy
> +
> + port:
> + $ref: /schemas/graph.yaml#/properties/port
> + description:
> + Output port node. This port should be connected to the input
> + port of an attached DSI panel or DSI-to-eDP encoder chip.
> +
> +
> + "#address-cells":
> + const: 2
> +
> + "#size-cells":
> + const: 2
> +
> +required:
> + - compatible
> + - reg
> + - interrupts
> + - power-domains
> + - clocks
> + - clock-names
> + - phys
> + - phy-names
> + - port
> +
> +additionalProperties: false
with the above,
unevaluatedProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/mt8183-clk.h>
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> + #include <dt-bindings/interrupt-controller/irq.h>
> + #include <dt-bindings/power/mt8183-power.h>
> + #include <dt-bindings/phy/phy.h>
> + #include <dt-bindings/reset/mt8183-resets.h>
> +
> + soc {
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + dsi0: dsi@14014000 {
> + compatible = "mediatek,mt8183-dsi";
> + reg = <0 0x14014000 0 0x1000>;
> + interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_LOW>;
> + power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
> + clocks = <&mmsys CLK_MM_DSI0_MM>,
> + <&mmsys CLK_MM_DSI0_IF>,
> + <&mipi_tx0>;
> + clock-names = "engine", "digital", "hs";
> + resets = <&mmsys MT8183_MMSYS_SW0_RST_B_DISP_DSI0>;
> + phys = <&mipi_tx0>;
> + phy-names = "dphy";
> + port {
> + dsi0_out: endpoint {
> + remote-endpoint = <&panel_in>;
> + };
> + };
> + };
> + };
> +
> +...
> --
> 2.18.0
>
>
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v4,2/3] dt-bindings: display: mediatek: dsi: Add compatible for MediaTek MT8186
2022-04-09 9:11 ` [PATCH v4, 2/3] dt-bindings: display: mediatek: dsi: Add compatible for MediaTek MT8186 xinlei.lee
@ 2022-04-13 21:20 ` Rob Herring
0 siblings, 0 replies; 9+ messages in thread
From: Rob Herring @ 2022-04-13 21:20 UTC (permalink / raw)
To: xinlei.lee
Cc: chunkuang.hu, jitao.shi, devicetree, airlied, linux-kernel,
dri-devel, Project_Global_Chrome_Upstream_Group, rex-bc.chen,
robh+dt, linux-mediatek, matthias.bgg, linux-arm-kernel
On Sat, 09 Apr 2022 17:11:53 +0800, xinlei.lee@mediatek.com wrote:
> From: Xinlei Lee <xinlei.lee@mediatek.com>
>
> Add dt-binding documentation of dsi for MediaTek MT8186 SoC.
>
> Signed-off-by: Xinlei Lee <xinlei.lee@mediatek.com>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
> ---
> .../devicetree/bindings/display/mediatek/mediatek,dsi.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
Acked-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v4,1/3] dt-bindings: display: mediatek: dsi: Convert dsi_dtbinding to .yaml
2022-04-13 21:20 ` [PATCH v4,1/3] " Rob Herring
@ 2022-04-28 12:49 ` Rex-BC Chen
0 siblings, 0 replies; 9+ messages in thread
From: Rex-BC Chen @ 2022-04-28 12:49 UTC (permalink / raw)
To: Rob Herring, xinlei.lee
Cc: chunkuang.hu, jitao.shi, devicetree, airlied, linux-kernel,
dri-devel, Project_Global_Chrome_Upstream_Group, linux-mediatek,
matthias.bgg, linux-arm-kernel
On Wed, 2022-04-13 at 16:20 -0500, Rob Herring wrote:
> On Sat, Apr 09, 2022 at 05:11:52PM +0800, xinlei.lee@mediatek.com
> wrote:
> > From: Xinlei Lee <xinlei.lee@mediatek.com>
> >
> > Convert mediatek,dsi.txt to mediatek,dsi.yaml format
> >
> > Signed-off-by: Xinlei Lee <xinlei.lee@mediatek.com>
> > ---
> > .../display/mediatek/mediatek,dsi.txt | 62 ---------
> > .../display/mediatek/mediatek,dsi.yaml | 118
> > ++++++++++++++++++
> > 2 files changed, 118 insertions(+), 62 deletions(-)
> > delete mode 100644
> > Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt
> > create mode 100644
> > Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yam
> > l
>
>
> > diff --git
> > a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.y
> > aml
> > b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.y
> > aml
> > new file mode 100644
> > index 000000000000..431bb981394f
> > --- /dev/null
> > +++
> > b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.y
> > aml
> > @@ -0,0 +1,118 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id:
> > http://devicetree.org/schemas/display/mediatek/mediatek,dsi.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: MediaTek DSI Controller Device Tree Bindings
> > +
> > +maintainers:
> > + - CK Hu <ck.hu@mediatek.com>
> > + - Jitao Shi <jitao.shi@mediatek.com>
> > + - Xinlei Lee <xinlei.lee@mediatek.com>
> > +
> > +description: |
> > + The MediaTek DSI function block is a sink of the display
> > subsystem and can
> > + drive up to 4-lane MIPI DSI output. Two DSIs can be synchronized
> > for dual-
> > + channel output.
>
> allOf:
> - $ref: /schemas/display/dsi-controller.yaml#
>
Hello Rob,
Thanks for your review.
I will help Xinlei to push next version.
I will add this in next version.
> > +
> > +properties:
> > + compatible:
> > + enum:
> > + - mediatek,mt2701-dsi
> > + - mediatek,mt7623-dsi
> > + - mediatek,mt8167-dsi
> > + - mediatek,mt8173-dsi
> > + - mediatek,mt8183-dsi
> > +
> > + reg:
> > + maxItems: 1
> > +
> > + interrupts:
> > + maxItems: 1
> > +
> > + power-domains:
> > + maxItems: 1
> > +
> > + clocks:
> > + items:
> > + - description: Engine Clock
> > + - description: Digital Clock
> > + - description: HS Clock
> > +
> > + clock-names:
> > + items:
> > + - const: engine
> > + - const: digital
> > + - const: hs
> > +
> > + resets:
> > + maxItems: 1
> > +
> > + phys:
> > + maxItems: 1
> > +
> > + phy-names:
> > + items:
> > + - const: dphy
> > +
> > + port:
> > + $ref: /schemas/graph.yaml#/properties/port
> > + description:
> > + Output port node. This port should be connected to the input
> > + port of an attached DSI panel or DSI-to-eDP encoder chip.
> > +
> > +
> > + "#address-cells":
> > + const: 2
> > +
> > + "#size-cells":
> > + const: 2
> > +
> > +required:
> > + - compatible
> > + - reg
> > + - interrupts
> > + - power-domains
> > + - clocks
> > + - clock-names
> > + - phys
> > + - phy-names
> > + - port
> > +
> > +additionalProperties: false
>
> with the above,
>
> unevaluatedProperties: false
>
OK, I will modify additionalProperties to unevaluatedProperties in next
version.
BRs,
Rex
> > +
> > +examples:
> > + - |
> > + #include <dt-bindings/clock/mt8183-clk.h>
> > + #include <dt-bindings/interrupt-controller/arm-gic.h>
> > + #include <dt-bindings/interrupt-controller/irq.h>
> > + #include <dt-bindings/power/mt8183-power.h>
> > + #include <dt-bindings/phy/phy.h>
> > + #include <dt-bindings/reset/mt8183-resets.h>
> > +
> > + soc {
> > + #address-cells = <2>;
> > + #size-cells = <2>;
> > +
> > + dsi0: dsi@14014000 {
> > + compatible = "mediatek,mt8183-dsi";
> > + reg = <0 0x14014000 0 0x1000>;
> > + interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_LOW>;
> > + power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
> > + clocks = <&mmsys CLK_MM_DSI0_MM>,
> > + <&mmsys CLK_MM_DSI0_IF>,
> > + <&mipi_tx0>;
> > + clock-names = "engine", "digital", "hs";
> > + resets = <&mmsys MT8183_MMSYS_SW0_RST_B_DISP_DSI0>;
> > + phys = <&mipi_tx0>;
> > + phy-names = "dphy";
> > + port {
> > + dsi0_out: endpoint {
> > + remote-endpoint = <&panel_in>;
> > + };
> > + };
> > + };
> > + };
> > +
> > +...
> > --
> > 2.18.0
> >
> >
^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2022-04-28 12:50 UTC | newest]
Thread overview: 9+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-04-09 9:11 [PATCH v4, 0/3] Add mt8186 dsi compatoble & Convert dsi_dtbinding to .yaml xinlei.lee
2022-04-09 9:11 ` [PATCH v4, 1/3] dt-bindings: display: mediatek: dsi: " xinlei.lee
2022-04-12 9:17 ` CK Hu
2022-04-12 13:00 ` xinlei.lee
2022-04-13 21:20 ` [PATCH v4,1/3] " Rob Herring
2022-04-28 12:49 ` Rex-BC Chen
2022-04-09 9:11 ` [PATCH v4, 2/3] dt-bindings: display: mediatek: dsi: Add compatible for MediaTek MT8186 xinlei.lee
2022-04-13 21:20 ` [PATCH v4,2/3] " Rob Herring
2022-04-09 9:11 ` [PATCH v4,3/3] drm/mediatek: Add mt8186 dsi compatible to mtk_dsi.c xinlei.lee
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).