[PATCHv2 1/2] drm/display/dp: Check for MSTM_CAP before MSTM_CTRL write

[PATCHv2 1/2] drm/display/dp: Check for MSTM_CAP before MSTM_CTRL write

[Arun R Murthy]

With DP2.1, multistream packetization and the underneth MST protocol
will be required for SST. So check for MSTM_CAP to see if MST is really
required and skip the MSTM_CTRL write so that we ensure that only the
underneth protocol and the multistream packetization will be enabled and
sink will not be confused by a corresponding dpcd write.

Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
---
 drivers/gpu/drm/display/drm_dp_mst_topology.c | 38 +++++++++++--------
 1 file changed, 22 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/display/drm_dp_mst_topology.c b/drivers/gpu/drm/display/drm_dp_mst_topology.c
index 8ca01a6bf645..c5b3e51ea0c9 100644
--- a/drivers/gpu/drm/display/drm_dp_mst_topology.c
+++ b/drivers/gpu/drm/display/drm_dp_mst_topology.c
@@ -3666,12 +3666,14 @@ int drm_dp_mst_topology_mgr_set_mst(struct drm_dp_mst_topology_mgr *mgr, bool ms
 		mgr->mst_primary = mstb;
 		drm_dp_mst_topology_get_mstb(mgr->mst_primary);
 
-		ret = drm_dp_dpcd_writeb(mgr->aux, DP_MSTM_CTRL,
-					 DP_MST_EN |
-					 DP_UP_REQ_EN |
-					 DP_UPSTREAM_IS_SRC);
-		if (ret < 0)
-			goto out_unlock;
+		if (drm_dp_read_mst_cap(mgr->aux, mgr->dpcd)) {
+			ret = drm_dp_dpcd_writeb(mgr->aux, DP_MSTM_CTRL,
+						 DP_MST_EN |
+						 DP_UP_REQ_EN |
+						 DP_UPSTREAM_IS_SRC);
+			if (ret < 0)
+				goto out_unlock;
+		}
 
 		/* Write reset payload */
 		drm_dp_dpcd_write_payload(mgr, 0, 0, 0x3f);
@@ -3684,7 +3686,8 @@ int drm_dp_mst_topology_mgr_set_mst(struct drm_dp_mst_topology_mgr *mgr, bool ms
 		mstb = mgr->mst_primary;
 		mgr->mst_primary = NULL;
 		/* this can fail if the device is gone */
-		drm_dp_dpcd_writeb(mgr->aux, DP_MSTM_CTRL, 0);
+		if (drm_dp_read_mst_cap(mgr->aux, mgr->dpcd))
+			drm_dp_dpcd_writeb(mgr->aux, DP_MSTM_CTRL, 0);
 		ret = 0;
 		mgr->payload_id_table_cleared = false;
 
@@ -3724,8 +3727,9 @@ drm_dp_mst_topology_mgr_invalidate_mstb(struct drm_dp_mst_branch *mstb)
 void drm_dp_mst_topology_mgr_suspend(struct drm_dp_mst_topology_mgr *mgr)
 {
 	mutex_lock(&mgr->lock);
-	drm_dp_dpcd_writeb(mgr->aux, DP_MSTM_CTRL,
-			   DP_MST_EN | DP_UPSTREAM_IS_SRC);
+	if (drm_dp_read_mst_cap(mgr->aux, mgr->dpcd))
+		drm_dp_dpcd_writeb(mgr->aux, DP_MSTM_CTRL,
+				   DP_MST_EN | DP_UPSTREAM_IS_SRC);
 	mutex_unlock(&mgr->lock);
 	flush_work(&mgr->up_req_work);
 	flush_work(&mgr->work);
@@ -3773,13 +3777,15 @@ int drm_dp_mst_topology_mgr_resume(struct drm_dp_mst_topology_mgr *mgr,
 		goto out_fail;
 	}
 
-	ret = drm_dp_dpcd_writeb(mgr->aux, DP_MSTM_CTRL,
-				 DP_MST_EN |
-				 DP_UP_REQ_EN |
-				 DP_UPSTREAM_IS_SRC);
-	if (ret < 0) {
-		drm_dbg_kms(mgr->dev, "mst write failed - undocked during suspend?\n");
-		goto out_fail;
+	if (drm_dp_read_mst_cap(mgr->aux, mgr->dpcd)) {
+		ret = drm_dp_dpcd_writeb(mgr->aux, DP_MSTM_CTRL,
+					 DP_MST_EN |
+					 DP_UP_REQ_EN |
+					 DP_UPSTREAM_IS_SRC);
+		if (ret < 0) {
+			drm_dbg_kms(mgr->dev, "mst write failed - undocked during suspend?\n");
+			goto out_fail;
+		}
 	}
 
 	/* Some hubs forget their guids after they resume */
-- 
2.25.1

[PATCHv2 2/2] drm/i915/display/dp: 128/132b DP-capable with SST

[Arun R Murthy]

With a value of '0' read from MSTM_CAP register MST to be enabled.
DP2.1 SCR updates the spec for 128/132b DP capable supporting only one
stream and not supporting single stream sideband MSG.
The underlying protocol will be MST to enable use of MTP.

Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 12 +++++++++---
 1 file changed, 9 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 9ff0cbd9c0df..05722f10cdd7 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -4037,9 +4037,15 @@ intel_dp_configure_mst(struct intel_dp *intel_dp)
 
 	if (!intel_dp_mst_source_support(intel_dp))
 		return;
-
-	intel_dp->is_mst = sink_can_mst &&
-		i915->display.params.enable_dp_mst;
+	/*
+	 * Even if dpcd reg MSTM_CAP is 0, if the sink supports UHBR rates then
+	 * DP2.1 can be enabled with underlying protocol using MST for MTP
+	 * TODO: Need to accommodate MSTM_CAP bit[0]=0, bit[1]=1 condition, i.e
+	 * one stream with single stream sideband msg.
+	 */
+	intel_dp->is_mst = (sink_can_mst || (intel_dp->dpcd[DP_MAIN_LINK_CHANNEL_CODING] &
+					     DP_CAP_ANSI_128B132B)) &&
+			    i915->display.params.enable_dp_mst;
 
 	drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
 					intel_dp->is_mst);
-- 
2.25.1

Re: [PATCHv2 2/2] drm/i915/display/dp: 128/132b DP-capable with SST

[Jani Nikula]

On Wed, 31 Jan 2024, Arun R Murthy <arun.r.murthy@intel.com> wrote:
> With a value of '0' read from MSTM_CAP register MST to be enabled.
> DP2.1 SCR updates the spec for 128/132b DP capable supporting only one
> stream and not supporting single stream sideband MSG.
> The underlying protocol will be MST to enable use of MTP.
>
> Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dp.c | 12 +++++++++---
>  1 file changed, 9 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 9ff0cbd9c0df..05722f10cdd7 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -4037,9 +4037,15 @@ intel_dp_configure_mst(struct intel_dp *intel_dp)
>  
>  	if (!intel_dp_mst_source_support(intel_dp))
>  		return;
> -
> -	intel_dp->is_mst = sink_can_mst &&
> -		i915->display.params.enable_dp_mst;
> +	/*
> +	 * Even if dpcd reg MSTM_CAP is 0, if the sink supports UHBR rates then
> +	 * DP2.1 can be enabled with underlying protocol using MST for MTP
> +	 * TODO: Need to accommodate MSTM_CAP bit[0]=0, bit[1]=1 condition, i.e
> +	 * one stream with single stream sideband msg.
> +	 */
> +	intel_dp->is_mst = (sink_can_mst || (intel_dp->dpcd[DP_MAIN_LINK_CHANNEL_CODING] &
> +					     DP_CAP_ANSI_128B132B)) &&
> +			    i915->display.params.enable_dp_mst;

Based on testing with the specific display in question, it looks like
this works because the display, while having DP_MSTM_CAP == 0, does
actually support sideband messaging. Which is unexpected.

This means a display that has DP_MSTM_CAP == 0 that actually does not
support sideband messaging, which is expected, will get a black screen
with this patch.

This was the conclusion when I discussed this with Ville and Imre.

Related to this, I've posted a series to enable MST mode for 128b/132b
displays that support single-stream with sideband messaging [1]. It
obviously does not directly help here, as that requires DP_MSTM_CAP ==
2. It might be possible to quirk the one display to use that. Maybe. The
alternative is actually implementing 128b/132b single-stream w/o
sideband messaging using our regular SST paths.

BR,
Jani.


[1] https://patchwork.freedesktop.org/series/129468/


>  
>  	drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
>  					intel_dp->is_mst);

-- 
Jani Nikula, Intel