* [PATCH] drm/amd/display: Fix 64-bit division for 32-bit builds
@ 2018-12-19 20:28 sunpeng.li-5C7GfCeVMHo
[not found] ` <1545251294-28136-1-git-send-email-sunpeng.li-5C7GfCeVMHo@public.gmane.org>
0 siblings, 1 reply; 2+ messages in thread
From: sunpeng.li-5C7GfCeVMHo @ 2018-12-19 20:28 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: harry.wentland-5C7GfCeVMHo, Ken Chalmers
From: Ken Chalmers <ken.chalmers@amd.com>
[Why]
32-bit builds break when doing 64-bit division directly.
[How]
Use the div_u64() function instead to perform the division.
Fixes: https://lists.freedesktop.org/archives/dri-devel/2018-December/201008.html
Signed-off-by: Ken Chalmers <ken.chalmers@amd.com>
Reviewed-by: Leo Li <sunpeng.li@amd.com>
---
drivers/gpu/drm/amd/display/dc/dce80/dce80_timing_generator.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_timing_generator.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_timing_generator.c
index 5c629ae..8b5ce55 100644
--- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_timing_generator.c
+++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_timing_generator.c
@@ -94,7 +94,7 @@ static void program_pix_dur(struct timing_generator *tg, uint32_t pix_clk_100hz)
if (pix_clk_100hz == 0)
return;
- pix_dur = 10000000000ull / pix_clk_100hz;
+ pix_dur = div_u64(10000000000ull, pix_clk_100hz);
set_reg_field_value(
value,
--
2.7.4
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 2+ messages in thread
* Re: [PATCH] drm/amd/display: Fix 64-bit division for 32-bit builds
[not found] ` <1545251294-28136-1-git-send-email-sunpeng.li-5C7GfCeVMHo@public.gmane.org>
@ 2018-12-19 21:17 ` Wentland, Harry
0 siblings, 0 replies; 2+ messages in thread
From: Wentland, Harry @ 2018-12-19 21:17 UTC (permalink / raw)
To: Li, Sun peng (Leo),
amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Chalmers, Kenneth
On 2018-12-19 3:28 p.m., sunpeng.li@amd.com wrote:
> From: Ken Chalmers <ken.chalmers@amd.com>
>
> [Why]
> 32-bit builds break when doing 64-bit division directly.
>
> [How]
> Use the div_u64() function instead to perform the division.
>
> Fixes: https://lists.freedesktop.org/archives/dri-devel/2018-December/201008.html
> Signed-off-by: Ken Chalmers <ken.chalmers@amd.com>
> Reviewed-by: Leo Li <sunpeng.li@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Harry
> ---
> drivers/gpu/drm/amd/display/dc/dce80/dce80_timing_generator.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_timing_generator.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_timing_generator.c
> index 5c629ae..8b5ce55 100644
> --- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_timing_generator.c
> +++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_timing_generator.c
> @@ -94,7 +94,7 @@ static void program_pix_dur(struct timing_generator *tg, uint32_t pix_clk_100hz)
> if (pix_clk_100hz == 0)
> return;
>
> - pix_dur = 10000000000ull / pix_clk_100hz;
> + pix_dur = div_u64(10000000000ull, pix_clk_100hz);
>
> set_reg_field_value(
> value,
>
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 2+ messages in thread
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2018-12-19 20:28 [PATCH] drm/amd/display: Fix 64-bit division for 32-bit builds sunpeng.li-5C7GfCeVMHo
[not found] ` <1545251294-28136-1-git-send-email-sunpeng.li-5C7GfCeVMHo@public.gmane.org>
2018-12-19 21:17 ` Wentland, Harry
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