[PATCH 1/4] drm/fourcc: Introduce format modifiers for DG2 render and media compression

[PATCH 1/4] drm/fourcc: Introduce format modifiers for DG2 render and media compression

[Imre Deak]

From: Matt Roper <matthew.d.roper@intel.com>

The render/media engines on DG2 unify render compression and media
compression into a single format for the first time, using the Tile 4
layout for main surfaces. The compression algorithm is different from
any previous platform and the display engine must still be configured to
decompress either a render or media compressed surface; as such, we
need new RC and MC framebuffer modifiers to represent buffers in this
format.

v2: Clarify modifier layout description.

Cc: dri-devel@lists.freedesktop.org
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Acked-by: Nanley Chery <nanley.g.chery@intel.com>
---
 include/uapi/drm/drm_fourcc.h | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
index b73fe6797fc37..4a5117715db3c 100644
--- a/include/uapi/drm/drm_fourcc.h
+++ b/include/uapi/drm/drm_fourcc.h
@@ -583,6 +583,28 @@ extern "C" {
  */
 #define I915_FORMAT_MOD_4_TILED         fourcc_mod_code(INTEL, 9)
 
+/*
+ * Intel color control surfaces (CCS) for DG2 render compression.
+ *
+ * The main surface is Tile 4 and at plane index 0. The CCS data is stored
+ * outside of the GEM object in a reserved memory area dedicated for the
+ * storage of the CCS data for all RC/RC_CC/MC compressible GEM objects. The
+ * main surface pitch is required to be a multiple of four Tile 4 widths.
+ */
+#define I915_FORMAT_MOD_4_TILED_DG2_RC_CCS fourcc_mod_code(INTEL, 10)
+
+/*
+ * Intel color control surfaces (CCS) for DG2 media compression.
+ *
+ * The main surface is Tile 4 and at plane index 0. For semi-planar formats
+ * like NV12, the Y and UV planes are Tile 4 and are located at plane indices
+ * 0 and 1, respectively. The CCS for all planes are stored outside of the
+ * GEM object in a reserved memory area dedicated for the storage of the
+ * CCS data for all RC/RC_CC/MC compressible GEM objects. The main surface
+ * pitch is required to be a multiple of four Tile 4 widths.
+ */
+#define I915_FORMAT_MOD_4_TILED_DG2_MC_CCS fourcc_mod_code(INTEL, 11)
+
 /*
  * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
  *
-- 
2.30.2

[PATCH 3/4] drm/fourcc: Introduce format modifier for DG2 clear color

[Imre Deak]

From: Mika Kahola <mika.kahola@intel.com>

DG2 clear color render compression uses Tile4 layout. Therefore, we need
to define a new format modifier for uAPI to support clear color rendering.

v2:
  Display version is fixed. [Imre]
  KDoc is enhanced for cc modifier. [Nanley & Lionel]
v3:
  Split out the modifier addition to a separate patch.
  Clarify the modifier layout description.

Cc: dri-devel@lists.freedesktop.org
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
cc: Anshuman Gupta <anshuman.gupta@intel.com>
Signed-off-by: Juha-Pekka Heikkilä <juha-pekka.heikkila@intel.com>
Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Acked-by: Nanley Chery <nanley.g.chery@intel.com>
---
 include/uapi/drm/drm_fourcc.h | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
index 4a5117715db3c..e5074162bcdd4 100644
--- a/include/uapi/drm/drm_fourcc.h
+++ b/include/uapi/drm/drm_fourcc.h
@@ -605,6 +605,20 @@ extern "C" {
  */
 #define I915_FORMAT_MOD_4_TILED_DG2_MC_CCS fourcc_mod_code(INTEL, 11)
 
+/*
+ * Intel Color Control Surface with Clear Color (CCS) for DG2 render compression.
+ *
+ * The main surface is Tile 4 and at plane index 0. The CCS data is stored
+ * outside of the GEM object in a reserved memory area dedicated for the
+ * storage of the CCS data for all RC/RC_CC/MC compressible GEM objects. The
+ * main surface pitch is required to be a multiple of four Tile 4 widths. The
+ * clear color is stored at plane index 1 and the pitch should be ignored. The
+ * format of the 256 bits of clear color data matches the one used for the
+ * I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC modifier, see its description
+ * for details.
+ */
+#define I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC fourcc_mod_code(INTEL, 12)
+
 /*
  * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
  *
-- 
2.30.2

Re: [PATCH 1/4] drm/fourcc: Introduce format modifiers for DG2 render and media compression

[Juha-Pekka Heikkila]

Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>

On 4.4.2022 16.38, Imre Deak wrote:
> From: Matt Roper <matthew.d.roper@intel.com>
> 
> The render/media engines on DG2 unify render compression and media
> compression into a single format for the first time, using the Tile 4
> layout for main surfaces. The compression algorithm is different from
> any previous platform and the display engine must still be configured to
> decompress either a render or media compressed surface; as such, we
> need new RC and MC framebuffer modifiers to represent buffers in this
> format.
> 
> v2: Clarify modifier layout description.
> 
> Cc: dri-devel@lists.freedesktop.org
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> Acked-by: Nanley Chery <nanley.g.chery@intel.com>
> ---
>   include/uapi/drm/drm_fourcc.h | 22 ++++++++++++++++++++++
>   1 file changed, 22 insertions(+)
> 
> diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
> index b73fe6797fc37..4a5117715db3c 100644
> --- a/include/uapi/drm/drm_fourcc.h
> +++ b/include/uapi/drm/drm_fourcc.h
> @@ -583,6 +583,28 @@ extern "C" {
>    */
>   #define I915_FORMAT_MOD_4_TILED         fourcc_mod_code(INTEL, 9)
>   
> +/*
> + * Intel color control surfaces (CCS) for DG2 render compression.
> + *
> + * The main surface is Tile 4 and at plane index 0. The CCS data is stored
> + * outside of the GEM object in a reserved memory area dedicated for the
> + * storage of the CCS data for all RC/RC_CC/MC compressible GEM objects. The
> + * main surface pitch is required to be a multiple of four Tile 4 widths.
> + */
> +#define I915_FORMAT_MOD_4_TILED_DG2_RC_CCS fourcc_mod_code(INTEL, 10)
> +
> +/*
> + * Intel color control surfaces (CCS) for DG2 media compression.
> + *
> + * The main surface is Tile 4 and at plane index 0. For semi-planar formats
> + * like NV12, the Y and UV planes are Tile 4 and are located at plane indices
> + * 0 and 1, respectively. The CCS for all planes are stored outside of the
> + * GEM object in a reserved memory area dedicated for the storage of the
> + * CCS data for all RC/RC_CC/MC compressible GEM objects. The main surface
> + * pitch is required to be a multiple of four Tile 4 widths.
> + */
> +#define I915_FORMAT_MOD_4_TILED_DG2_MC_CCS fourcc_mod_code(INTEL, 11)
> +
>   /*
>    * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
>    *

Re: [PATCH 1/4] drm/fourcc: Introduce format modifiers for DG2 render and media compression

[Juha-Pekka Heikkilä]

Seems my first mail didn't come through so here's second time for this patch:

Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>

On Mon, Apr 4, 2022 at 4:39 PM Imre Deak <imre.deak@intel.com> wrote:
>
> From: Matt Roper <matthew.d.roper@intel.com>
>
> The render/media engines on DG2 unify render compression and media
> compression into a single format for the first time, using the Tile 4
> layout for main surfaces. The compression algorithm is different from
> any previous platform and the display engine must still be configured to
> decompress either a render or media compressed surface; as such, we
> need new RC and MC framebuffer modifiers to represent buffers in this
> format.
>
> v2: Clarify modifier layout description.
>
> Cc: dri-devel@lists.freedesktop.org
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> Acked-by: Nanley Chery <nanley.g.chery@intel.com>
> ---
>  include/uapi/drm/drm_fourcc.h | 22 ++++++++++++++++++++++
>  1 file changed, 22 insertions(+)
>
> diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
> index b73fe6797fc37..4a5117715db3c 100644
> --- a/include/uapi/drm/drm_fourcc.h
> +++ b/include/uapi/drm/drm_fourcc.h
> @@ -583,6 +583,28 @@ extern "C" {
>   */
>  #define I915_FORMAT_MOD_4_TILED         fourcc_mod_code(INTEL, 9)
>
> +/*
> + * Intel color control surfaces (CCS) for DG2 render compression.
> + *
> + * The main surface is Tile 4 and at plane index 0. The CCS data is stored
> + * outside of the GEM object in a reserved memory area dedicated for the
> + * storage of the CCS data for all RC/RC_CC/MC compressible GEM objects. The
> + * main surface pitch is required to be a multiple of four Tile 4 widths.
> + */
> +#define I915_FORMAT_MOD_4_TILED_DG2_RC_CCS fourcc_mod_code(INTEL, 10)
> +
> +/*
> + * Intel color control surfaces (CCS) for DG2 media compression.
> + *
> + * The main surface is Tile 4 and at plane index 0. For semi-planar formats
> + * like NV12, the Y and UV planes are Tile 4 and are located at plane indices
> + * 0 and 1, respectively. The CCS for all planes are stored outside of the
> + * GEM object in a reserved memory area dedicated for the storage of the
> + * CCS data for all RC/RC_CC/MC compressible GEM objects. The main surface
> + * pitch is required to be a multiple of four Tile 4 widths.
> + */
> +#define I915_FORMAT_MOD_4_TILED_DG2_MC_CCS fourcc_mod_code(INTEL, 11)
> +
>  /*
>   * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
>   *
> --
> 2.30.2
>

Re: [Intel-gfx] [PATCH 0/4] drm/i915/dg2: Add support for render/media decompression

[Jani Nikula]

On Mon, 04 Apr 2022, Imre Deak <imre.deak@intel.com> wrote:
> This is a rebased version of patches 15-17 of [1], adding DG2 display
> engine support for decompressing render and media compressed
> framebuffers.
>
> The dependency patches from [1] should be merged already to drm-tip.
>
> It addresses the review comments on the modifier layout description from
> Nanley, updates the commit logs vs. flat CCS and Tile4 and splits out
> the changes adding the modifiers to drm_fourcc.h to separate patches.

Cc'd a bunch more people; ack on merging patches 2 & 4 via drm-intel?

BR,
Jani.


>
> [1] https://patchwork.freedesktop.org/series/95686/
>
> Cc: Anshuman Gupta <anshuman.gupta@intel.com>
> Cc: Ramalingam C <ramalingam.c@intel.com>
> Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Cc: Mika Kahola <mika.kahola@intel.com>
> Cc: Juha-Pekka Heikkilä <juha-pekka.heikkila@intel.com>
> Cc: Nanley Chery <nanley.g.chery@intel.com>
>
> Anshuman Gupta (1):
>   drm/i915/dg2: Add support for DG2 clear color compression
>
> Matt Roper (2):
>   drm/fourcc: Introduce format modifiers for DG2 render and media
>     compression
>   drm/i915/dg2: Add support for DG2 render and media compression
>
> Mika Kahola (1):
>   drm/fourcc: Introduce format modifier for DG2 clear color
>
>  drivers/gpu/drm/i915/display/intel_display.c  |  4 +-
>  drivers/gpu/drm/i915/display/intel_fb.c       | 53 +++++++++++++++----
>  .../drm/i915/display/skl_universal_plane.c    | 49 +++++++++++++----
>  include/uapi/drm/drm_fourcc.h                 | 36 +++++++++++++
>  4 files changed, 122 insertions(+), 20 deletions(-)

-- 
Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [PATCH 0/4] drm/i915/dg2: Add support for render/media decompression

[Jani Nikula]

On Fri, 08 Apr 2022, Jani Nikula <jani.nikula@linux.intel.com> wrote:
> On Mon, 04 Apr 2022, Imre Deak <imre.deak@intel.com> wrote:
>> This is a rebased version of patches 15-17 of [1], adding DG2 display
>> engine support for decompressing render and media compressed
>> framebuffers.
>>
>> The dependency patches from [1] should be merged already to drm-tip.
>>
>> It addresses the review comments on the modifier layout description from
>> Nanley, updates the commit logs vs. flat CCS and Tile4 and splits out
>> the changes adding the modifiers to drm_fourcc.h to separate patches.
>
> Cc'd a bunch more people; ack on merging patches 2 & 4 via drm-intel?

Both off by one, I mean 1 & 3.

>
> BR,
> Jani.
>
>
>>
>> [1] https://patchwork.freedesktop.org/series/95686/
>>
>> Cc: Anshuman Gupta <anshuman.gupta@intel.com>
>> Cc: Ramalingam C <ramalingam.c@intel.com>
>> Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
>> Cc: Matt Roper <matthew.d.roper@intel.com>
>> Cc: Mika Kahola <mika.kahola@intel.com>
>> Cc: Juha-Pekka Heikkilä <juha-pekka.heikkila@intel.com>
>> Cc: Nanley Chery <nanley.g.chery@intel.com>
>>
>> Anshuman Gupta (1):
>>   drm/i915/dg2: Add support for DG2 clear color compression
>>
>> Matt Roper (2):
>>   drm/fourcc: Introduce format modifiers for DG2 render and media
>>     compression
>>   drm/i915/dg2: Add support for DG2 render and media compression
>>
>> Mika Kahola (1):
>>   drm/fourcc: Introduce format modifier for DG2 clear color
>>
>>  drivers/gpu/drm/i915/display/intel_display.c  |  4 +-
>>  drivers/gpu/drm/i915/display/intel_fb.c       | 53 +++++++++++++++----
>>  .../drm/i915/display/skl_universal_plane.c    | 49 +++++++++++++----
>>  include/uapi/drm/drm_fourcc.h                 | 36 +++++++++++++
>>  4 files changed, 122 insertions(+), 20 deletions(-)

-- 
Jani Nikula, Intel Open Source Graphics Center