* [PATCH 00/12] drm/msm/adreno: Move away from legacy revision matching
@ 2023-07-06 21:10 Rob Clark
2023-07-06 21:10 ` [PATCH 01/12] drm/msm/adreno: Remove GPU name Rob Clark
` (11 more replies)
0 siblings, 12 replies; 73+ messages in thread
From: Rob Clark @ 2023-07-06 21:10 UTC (permalink / raw)
To: dri-devel; +Cc: Konrad Dybcio, linux-arm-msm, Rob Clark, freedreno
From: Rob Clark <robdclark@chromium.org>
Downstream seems to be moving to using the chip_id as simply an opaque
identifier, and if we want to avoid headaches with userspace mesa
supporting both kgsl and upstream, we should move away from the
assumption that certain bits in the chip_id have a specific meaning.
Patches 6 and 7 were something that I came up with before Konrad
suggesting moving fuse/speedbin mapping to a separate per-SoC table.
Which I guess would also work. But I guess if we did that, we'd want
to move things like whether cached-coherent is supported to that table
as well. I'm not a huge fan of pretending that whether or not you have
cached-coherent is anything to do with GMU itself, rather than just a
happy coincidence.
Rob Clark (12):
drm/msm/adreno: Remove GPU name
drm/msm/adreno: Remove redundant gmem size param
drm/msm/adreno: Remove redundant revn param
drm/msm/adreno: Use quirk identify hw_apriv
drm/msm/adreno: Use quirk to identify cached-coherent support
drm/msm/adreno: Allow SoC specific gpu device table entries
drm/msm/adreno: Move speedbin mapping to device table
drm/msm/adreno: Bring the a630 family together
drm/msm/adreno: Add adreno family
drm/msm/adreno: Add helper for formating chip-id
dt-bindings: drm/msm/gpu: Extend bindings for chip-id
drm/msm/adreno: Switch to chip-id for identifying GPU
.../devicetree/bindings/display/msm/gpu.yaml | 6 +
drivers/gpu/drm/msm/adreno/a2xx_gpu.c | 2 +-
drivers/gpu/drm/msm/adreno/a4xx_gpu.c | 2 +-
drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 13 +-
drivers/gpu/drm/msm/adreno/a5xx_power.c | 2 +-
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 15 +-
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 187 ++----------
drivers/gpu/drm/msm/adreno/adreno_device.c | 282 ++++++++++++------
drivers/gpu/drm/msm/adreno/adreno_gpu.c | 52 ++--
drivers/gpu/drm/msm/adreno/adreno_gpu.h | 150 +++++++---
10 files changed, 362 insertions(+), 349 deletions(-)
--
2.41.0
^ permalink raw reply [flat|nested] 73+ messages in thread
* [PATCH 01/12] drm/msm/adreno: Remove GPU name
2023-07-06 21:10 [PATCH 00/12] drm/msm/adreno: Move away from legacy revision matching Rob Clark
@ 2023-07-06 21:10 ` Rob Clark
2023-07-06 23:21 ` Konrad Dybcio
2023-07-07 0:04 ` [Freedreno] " Dmitry Baryshkov
2023-07-06 21:10 ` [PATCH 02/12] drm/msm/adreno: Remove redundant gmem size param Rob Clark
` (10 subsequent siblings)
11 siblings, 2 replies; 73+ messages in thread
From: Rob Clark @ 2023-07-06 21:10 UTC (permalink / raw)
To: dri-devel; +Cc: Konrad Dybcio, linux-arm-msm, Rob Clark, freedreno
From: Rob Clark <robdclark@chromium.org>
No real need to have marketing names in the kernel.
Signed-off-by: Rob Clark <robdclark@chromium.org>
---
drivers/gpu/drm/msm/adreno/adreno_device.c | 24 ----------------------
drivers/gpu/drm/msm/adreno/adreno_gpu.c | 13 +++++-------
drivers/gpu/drm/msm/adreno/adreno_gpu.h | 1 -
3 files changed, 5 insertions(+), 33 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c
index ce8d0b2475bf..5eba0ae5c9a7 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_device.c
+++ b/drivers/gpu/drm/msm/adreno/adreno_device.c
@@ -24,7 +24,6 @@ static const struct adreno_info gpulist[] = {
{
.rev = ADRENO_REV(2, 0, 0, 0),
.revn = 200,
- .name = "A200",
.fw = {
[ADRENO_FW_PM4] = "yamato_pm4.fw",
[ADRENO_FW_PFP] = "yamato_pfp.fw",
@@ -35,7 +34,6 @@ static const struct adreno_info gpulist[] = {
}, { /* a200 on i.mx51 has only 128kib gmem */
.rev = ADRENO_REV(2, 0, 0, 1),
.revn = 201,
- .name = "A200",
.fw = {
[ADRENO_FW_PM4] = "yamato_pm4.fw",
[ADRENO_FW_PFP] = "yamato_pfp.fw",
@@ -46,7 +44,6 @@ static const struct adreno_info gpulist[] = {
}, {
.rev = ADRENO_REV(2, 2, 0, ANY_ID),
.revn = 220,
- .name = "A220",
.fw = {
[ADRENO_FW_PM4] = "leia_pm4_470.fw",
[ADRENO_FW_PFP] = "leia_pfp_470.fw",
@@ -57,7 +54,6 @@ static const struct adreno_info gpulist[] = {
}, {
.rev = ADRENO_REV(3, 0, 5, ANY_ID),
.revn = 305,
- .name = "A305",
.fw = {
[ADRENO_FW_PM4] = "a300_pm4.fw",
[ADRENO_FW_PFP] = "a300_pfp.fw",
@@ -68,7 +64,6 @@ static const struct adreno_info gpulist[] = {
}, {
.rev = ADRENO_REV(3, 0, 6, 0),
.revn = 307, /* because a305c is revn==306 */
- .name = "A306",
.fw = {
[ADRENO_FW_PM4] = "a300_pm4.fw",
[ADRENO_FW_PFP] = "a300_pfp.fw",
@@ -79,7 +74,6 @@ static const struct adreno_info gpulist[] = {
}, {
.rev = ADRENO_REV(3, 2, ANY_ID, ANY_ID),
.revn = 320,
- .name = "A320",
.fw = {
[ADRENO_FW_PM4] = "a300_pm4.fw",
[ADRENO_FW_PFP] = "a300_pfp.fw",
@@ -90,7 +84,6 @@ static const struct adreno_info gpulist[] = {
}, {
.rev = ADRENO_REV(3, 3, 0, ANY_ID),
.revn = 330,
- .name = "A330",
.fw = {
[ADRENO_FW_PM4] = "a330_pm4.fw",
[ADRENO_FW_PFP] = "a330_pfp.fw",
@@ -101,7 +94,6 @@ static const struct adreno_info gpulist[] = {
}, {
.rev = ADRENO_REV(4, 0, 5, ANY_ID),
.revn = 405,
- .name = "A405",
.fw = {
[ADRENO_FW_PM4] = "a420_pm4.fw",
[ADRENO_FW_PFP] = "a420_pfp.fw",
@@ -112,7 +104,6 @@ static const struct adreno_info gpulist[] = {
}, {
.rev = ADRENO_REV(4, 2, 0, ANY_ID),
.revn = 420,
- .name = "A420",
.fw = {
[ADRENO_FW_PM4] = "a420_pm4.fw",
[ADRENO_FW_PFP] = "a420_pfp.fw",
@@ -123,7 +114,6 @@ static const struct adreno_info gpulist[] = {
}, {
.rev = ADRENO_REV(4, 3, 0, ANY_ID),
.revn = 430,
- .name = "A430",
.fw = {
[ADRENO_FW_PM4] = "a420_pm4.fw",
[ADRENO_FW_PFP] = "a420_pfp.fw",
@@ -134,7 +124,6 @@ static const struct adreno_info gpulist[] = {
}, {
.rev = ADRENO_REV(5, 0, 6, ANY_ID),
.revn = 506,
- .name = "A506",
.fw = {
[ADRENO_FW_PM4] = "a530_pm4.fw",
[ADRENO_FW_PFP] = "a530_pfp.fw",
@@ -152,7 +141,6 @@ static const struct adreno_info gpulist[] = {
}, {
.rev = ADRENO_REV(5, 0, 8, ANY_ID),
.revn = 508,
- .name = "A508",
.fw = {
[ADRENO_FW_PM4] = "a530_pm4.fw",
[ADRENO_FW_PFP] = "a530_pfp.fw",
@@ -169,7 +157,6 @@ static const struct adreno_info gpulist[] = {
}, {
.rev = ADRENO_REV(5, 0, 9, ANY_ID),
.revn = 509,
- .name = "A509",
.fw = {
[ADRENO_FW_PM4] = "a530_pm4.fw",
[ADRENO_FW_PFP] = "a530_pfp.fw",
@@ -187,7 +174,6 @@ static const struct adreno_info gpulist[] = {
}, {
.rev = ADRENO_REV(5, 1, 0, ANY_ID),
.revn = 510,
- .name = "A510",
.fw = {
[ADRENO_FW_PM4] = "a530_pm4.fw",
[ADRENO_FW_PFP] = "a530_pfp.fw",
@@ -202,7 +188,6 @@ static const struct adreno_info gpulist[] = {
}, {
.rev = ADRENO_REV(5, 1, 2, ANY_ID),
.revn = 512,
- .name = "A512",
.fw = {
[ADRENO_FW_PM4] = "a530_pm4.fw",
[ADRENO_FW_PFP] = "a530_pfp.fw",
@@ -219,7 +204,6 @@ static const struct adreno_info gpulist[] = {
}, {
.rev = ADRENO_REV(5, 3, 0, 2),
.revn = 530,
- .name = "A530",
.fw = {
[ADRENO_FW_PM4] = "a530_pm4.fw",
[ADRENO_FW_PFP] = "a530_pfp.fw",
@@ -238,7 +222,6 @@ static const struct adreno_info gpulist[] = {
}, {
.rev = ADRENO_REV(5, 4, 0, ANY_ID),
.revn = 540,
- .name = "A540",
.fw = {
[ADRENO_FW_PM4] = "a530_pm4.fw",
[ADRENO_FW_PFP] = "a530_pfp.fw",
@@ -268,7 +251,6 @@ static const struct adreno_info gpulist[] = {
}, {
.rev = ADRENO_REV(6, 1, 8, ANY_ID),
.revn = 618,
- .name = "A618",
.fw = {
[ADRENO_FW_SQE] = "a630_sqe.fw",
[ADRENO_FW_GMU] = "a630_gmu.bin",
@@ -279,7 +261,6 @@ static const struct adreno_info gpulist[] = {
}, {
.rev = ADRENO_REV(6, 1, 9, ANY_ID),
.revn = 619,
- .name = "A619",
.fw = {
[ADRENO_FW_SQE] = "a630_sqe.fw",
[ADRENO_FW_GMU] = "a619_gmu.bin",
@@ -292,7 +273,6 @@ static const struct adreno_info gpulist[] = {
}, {
.rev = ADRENO_REV(6, 3, 0, ANY_ID),
.revn = 630,
- .name = "A630",
.fw = {
[ADRENO_FW_SQE] = "a630_sqe.fw",
[ADRENO_FW_GMU] = "a630_gmu.bin",
@@ -305,7 +285,6 @@ static const struct adreno_info gpulist[] = {
}, {
.rev = ADRENO_REV(6, 4, 0, ANY_ID),
.revn = 640,
- .name = "A640",
.fw = {
[ADRENO_FW_SQE] = "a630_sqe.fw",
[ADRENO_FW_GMU] = "a640_gmu.bin",
@@ -318,7 +297,6 @@ static const struct adreno_info gpulist[] = {
}, {
.rev = ADRENO_REV(6, 5, 0, ANY_ID),
.revn = 650,
- .name = "A650",
.fw = {
[ADRENO_FW_SQE] = "a650_sqe.fw",
[ADRENO_FW_GMU] = "a650_gmu.bin",
@@ -332,7 +310,6 @@ static const struct adreno_info gpulist[] = {
}, {
.rev = ADRENO_REV(6, 6, 0, ANY_ID),
.revn = 660,
- .name = "A660",
.fw = {
[ADRENO_FW_SQE] = "a660_sqe.fw",
[ADRENO_FW_GMU] = "a660_gmu.bin",
@@ -357,7 +334,6 @@ static const struct adreno_info gpulist[] = {
}, {
.rev = ADRENO_REV(6, 8, 0, ANY_ID),
.revn = 680,
- .name = "A680",
.fw = {
[ADRENO_FW_SQE] = "a630_sqe.fw",
[ADRENO_FW_GMU] = "a640_gmu.bin",
diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
index 5c5901d65950..e3cd9ff6ff1d 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
@@ -1105,14 +1105,11 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev,
speedbin = 0xffff;
adreno_gpu->speedbin = (uint16_t) (0xffff & speedbin);
- gpu_name = adreno_gpu->info->name;
- if (!gpu_name) {
- gpu_name = devm_kasprintf(dev, GFP_KERNEL, "%d.%d.%d.%d",
- rev->core, rev->major, rev->minor,
- rev->patchid);
- if (!gpu_name)
- return -ENOMEM;
- }
+ gpu_name = devm_kasprintf(dev, GFP_KERNEL, "%d.%d.%d.%d",
+ rev->core, rev->major, rev->minor,
+ rev->patchid);
+ if (!gpu_name)
+ return -ENOMEM;
adreno_gpu_config.ioname = "kgsl_3d0_reg_memory";
diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
index cf45007400c8..6830c3776c2d 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
+++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
@@ -61,7 +61,6 @@ extern const struct adreno_reglist a660_hwcg[], a690_hwcg[];
struct adreno_info {
struct adreno_rev rev;
uint32_t revn;
- const char *name;
const char *fw[ADRENO_FW_MAX];
uint32_t gmem;
u64 quirks;
--
2.41.0
^ permalink raw reply related [flat|nested] 73+ messages in thread
* [PATCH 02/12] drm/msm/adreno: Remove redundant gmem size param
2023-07-06 21:10 [PATCH 00/12] drm/msm/adreno: Move away from legacy revision matching Rob Clark
2023-07-06 21:10 ` [PATCH 01/12] drm/msm/adreno: Remove GPU name Rob Clark
@ 2023-07-06 21:10 ` Rob Clark
2023-07-06 23:22 ` Konrad Dybcio
2023-07-07 2:23 ` [Freedreno] " Dmitry Baryshkov
2023-07-06 21:10 ` [PATCH 03/12] drm/msm/adreno: Remove redundant revn param Rob Clark
` (9 subsequent siblings)
11 siblings, 2 replies; 73+ messages in thread
From: Rob Clark @ 2023-07-06 21:10 UTC (permalink / raw)
To: dri-devel; +Cc: Konrad Dybcio, linux-arm-msm, Rob Clark, freedreno
From: Rob Clark <robdclark@chromium.org>
Even in the ocmem case, the allocated ocmem buffer size should match the
requested size.
Signed-off-by: Rob Clark <robdclark@chromium.org>
---
drivers/gpu/drm/msm/adreno/a2xx_gpu.c | 2 +-
drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 2 +-
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 2 +-
drivers/gpu/drm/msm/adreno/adreno_device.c | 1 -
drivers/gpu/drm/msm/adreno/adreno_gpu.c | 8 ++++----
drivers/gpu/drm/msm/adreno/adreno_gpu.h | 1 -
6 files changed, 7 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno/a2xx_gpu.c b/drivers/gpu/drm/msm/adreno/a2xx_gpu.c
index c67089a7ebc1..50ee03bc94b4 100644
--- a/drivers/gpu/drm/msm/adreno/a2xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a2xx_gpu.c
@@ -205,7 +205,7 @@ static int a2xx_hw_init(struct msm_gpu *gpu)
A2XX_MH_INTERRUPT_MASK_MMU_PAGE_FAULT);
for (i = 3; i <= 5; i++)
- if ((SZ_16K << i) == adreno_gpu->gmem)
+ if ((SZ_16K << i) == adreno_gpu->info->gmem)
break;
gpu_write(gpu, REG_A2XX_RB_EDRAM_INFO, i);
diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
index a99310b68793..f0803e94ebe5 100644
--- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
@@ -749,7 +749,7 @@ static int a5xx_hw_init(struct msm_gpu *gpu)
gpu_write(gpu, REG_A5XX_UCHE_GMEM_RANGE_MIN_LO, 0x00100000);
gpu_write(gpu, REG_A5XX_UCHE_GMEM_RANGE_MIN_HI, 0x00000000);
gpu_write(gpu, REG_A5XX_UCHE_GMEM_RANGE_MAX_LO,
- 0x00100000 + adreno_gpu->gmem - 1);
+ 0x00100000 + adreno_gpu->info->gmem - 1);
gpu_write(gpu, REG_A5XX_UCHE_GMEM_RANGE_MAX_HI, 0x00000000);
if (adreno_is_a506(adreno_gpu) || adreno_is_a508(adreno_gpu) ||
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index b3ada1e7b598..edbade75020f 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
@@ -1270,7 +1270,7 @@ static int hw_init(struct msm_gpu *gpu)
gpu_write64(gpu, REG_A6XX_UCHE_GMEM_RANGE_MIN, 0x00100000);
gpu_write64(gpu, REG_A6XX_UCHE_GMEM_RANGE_MAX,
- 0x00100000 + adreno_gpu->gmem - 1);
+ 0x00100000 + adreno_gpu->info->gmem - 1);
}
gpu_write(gpu, REG_A6XX_UCHE_FILTER_CNTL, 0x804);
diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c
index 5eba0ae5c9a7..326912284a95 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_device.c
+++ b/drivers/gpu/drm/msm/adreno/adreno_device.c
@@ -239,7 +239,6 @@ static const struct adreno_info gpulist[] = {
}, {
.rev = ADRENO_REV(6, 1, 0, ANY_ID),
.revn = 610,
- .name = "A610",
.fw = {
[ADRENO_FW_SQE] = "a630_sqe.fw",
},
diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
index e3cd9ff6ff1d..4f59682f585e 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
@@ -320,7 +320,7 @@ int adreno_get_param(struct msm_gpu *gpu, struct msm_file_private *ctx,
*value = adreno_gpu->info->revn;
return 0;
case MSM_PARAM_GMEM_SIZE:
- *value = adreno_gpu->gmem;
+ *value = adreno_gpu->info->gmem;
return 0;
case MSM_PARAM_GMEM_BASE:
*value = !adreno_is_a650_family(adreno_gpu) ? 0x100000 : 0;
@@ -1041,14 +1041,15 @@ int adreno_gpu_ocmem_init(struct device *dev, struct adreno_gpu *adreno_gpu,
return PTR_ERR(ocmem);
}
- ocmem_hdl = ocmem_allocate(ocmem, OCMEM_GRAPHICS, adreno_gpu->gmem);
+ ocmem_hdl = ocmem_allocate(ocmem, OCMEM_GRAPHICS, adreno_gpu->info->gmem);
if (IS_ERR(ocmem_hdl))
return PTR_ERR(ocmem_hdl);
adreno_ocmem->ocmem = ocmem;
adreno_ocmem->base = ocmem_hdl->addr;
adreno_ocmem->hdl = ocmem_hdl;
- adreno_gpu->gmem = ocmem_hdl->len;
+
+ WARN_ON(ocmem_hdl->len != adreno_gpu->info->gmem);
return 0;
}
@@ -1097,7 +1098,6 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev,
adreno_gpu->funcs = funcs;
adreno_gpu->info = adreno_info(config->rev);
- adreno_gpu->gmem = adreno_gpu->info->gmem;
adreno_gpu->revn = adreno_gpu->info->revn;
adreno_gpu->rev = *rev;
diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
index 6830c3776c2d..aaf09c642dc6 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
+++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
@@ -77,7 +77,6 @@ struct adreno_gpu {
struct msm_gpu base;
struct adreno_rev rev;
const struct adreno_info *info;
- uint32_t gmem; /* actual gmem size */
uint32_t revn; /* numeric revision name */
uint16_t speedbin;
const struct adreno_gpu_funcs *funcs;
--
2.41.0
^ permalink raw reply related [flat|nested] 73+ messages in thread
* [PATCH 03/12] drm/msm/adreno: Remove redundant revn param
2023-07-06 21:10 [PATCH 00/12] drm/msm/adreno: Move away from legacy revision matching Rob Clark
2023-07-06 21:10 ` [PATCH 01/12] drm/msm/adreno: Remove GPU name Rob Clark
2023-07-06 21:10 ` [PATCH 02/12] drm/msm/adreno: Remove redundant gmem size param Rob Clark
@ 2023-07-06 21:10 ` Rob Clark
2023-07-06 23:26 ` Konrad Dybcio
2023-07-07 2:24 ` [Freedreno] " Dmitry Baryshkov
2023-07-06 21:10 ` [PATCH 04/12] drm/msm/adreno: Use quirk identify hw_apriv Rob Clark
` (8 subsequent siblings)
11 siblings, 2 replies; 73+ messages in thread
From: Rob Clark @ 2023-07-06 21:10 UTC (permalink / raw)
To: dri-devel; +Cc: Konrad Dybcio, linux-arm-msm, Rob Clark, freedreno
From: Rob Clark <robdclark@chromium.org>
This just duplicates what is in adreno_info, and can cause confusion if
used before it is set.
Signed-off-by: Rob Clark <robdclark@chromium.org>
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 2 --
drivers/gpu/drm/msm/adreno/adreno_gpu.c | 1 -
drivers/gpu/drm/msm/adreno/adreno_gpu.h | 22 +++++++++-------------
3 files changed, 9 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index edbade75020f..5ba8b5aca502 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
@@ -2484,8 +2484,6 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev)
return ERR_PTR(-EINVAL);
/* Assign these early so that we can use the is_aXYZ helpers */
- /* Numeric revision IDs (e.g. 630) */
- adreno_gpu->revn = info->revn;
/* New-style ADRENO_REV()-only */
adreno_gpu->rev = info->rev;
/* Quirk data */
diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
index 4f59682f585e..2e62a7ce9f13 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
@@ -1098,7 +1098,6 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev,
adreno_gpu->funcs = funcs;
adreno_gpu->info = adreno_info(config->rev);
- adreno_gpu->revn = adreno_gpu->info->revn;
adreno_gpu->rev = *rev;
if (adreno_read_speedbin(dev, &speedbin) || !speedbin)
diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
index aaf09c642dc6..d31e2d37c61b 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
+++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
@@ -77,7 +77,6 @@ struct adreno_gpu {
struct msm_gpu base;
struct adreno_rev rev;
const struct adreno_info *info;
- uint32_t revn; /* numeric revision name */
uint16_t speedbin;
const struct adreno_gpu_funcs *funcs;
@@ -147,10 +146,9 @@ bool adreno_cmp_rev(struct adreno_rev rev1, struct adreno_rev rev2);
static inline bool adreno_is_revn(const struct adreno_gpu *gpu, uint32_t revn)
{
- /* revn can be zero, but if not is set at same time as info */
- WARN_ON_ONCE(!gpu->info);
-
- return gpu->revn == revn;
+ if (WARN_ON_ONCE(!gpu->info))
+ return false;
+ return gpu->info->revn == revn;
}
static inline bool adreno_has_gmu_wrapper(const struct adreno_gpu *gpu)
@@ -160,18 +158,16 @@ static inline bool adreno_has_gmu_wrapper(const struct adreno_gpu *gpu)
static inline bool adreno_is_a2xx(const struct adreno_gpu *gpu)
{
- /* revn can be zero, but if not is set at same time as info */
- WARN_ON_ONCE(!gpu->info);
-
- return (gpu->revn < 300);
+ if (WARN_ON_ONCE(!gpu->info))
+ return false;
+ return (gpu->info->revn < 300);
}
static inline bool adreno_is_a20x(const struct adreno_gpu *gpu)
{
- /* revn can be zero, but if not is set at same time as info */
- WARN_ON_ONCE(!gpu->info);
-
- return (gpu->revn < 210);
+ if (WARN_ON_ONCE(!gpu->info))
+ return false;
+ return (gpu->info->revn < 210);
}
static inline bool adreno_is_a225(const struct adreno_gpu *gpu)
--
2.41.0
^ permalink raw reply related [flat|nested] 73+ messages in thread
* [PATCH 04/12] drm/msm/adreno: Use quirk identify hw_apriv
2023-07-06 21:10 [PATCH 00/12] drm/msm/adreno: Move away from legacy revision matching Rob Clark
` (2 preceding siblings ...)
2023-07-06 21:10 ` [PATCH 03/12] drm/msm/adreno: Remove redundant revn param Rob Clark
@ 2023-07-06 21:10 ` Rob Clark
2023-07-06 23:27 ` Konrad Dybcio
2023-07-07 2:25 ` [Freedreno] " Dmitry Baryshkov
2023-07-06 21:10 ` [PATCH 05/12] drm/msm/adreno: Use quirk to identify cached-coherent support Rob Clark
` (7 subsequent siblings)
11 siblings, 2 replies; 73+ messages in thread
From: Rob Clark @ 2023-07-06 21:10 UTC (permalink / raw)
To: dri-devel; +Cc: Konrad Dybcio, linux-arm-msm, Rob Clark, freedreno
From: Rob Clark <robdclark@chromium.org>
Rather than just open coding a list of gpu-id matches.
Signed-off-by: Rob Clark <robdclark@chromium.org>
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 3 +--
drivers/gpu/drm/msm/adreno/adreno_device.c | 4 ++++
drivers/gpu/drm/msm/adreno/adreno_gpu.h | 1 +
3 files changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index 5ba8b5aca502..6f8c4381fa4a 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
@@ -2489,8 +2489,7 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev)
/* Quirk data */
adreno_gpu->info = info;
- if (adreno_is_a650(adreno_gpu) || adreno_is_a660_family(adreno_gpu))
- adreno_gpu->base.hw_apriv = true;
+ adreno_gpu->base.hw_apriv = !!(info->quirks & ADRENO_QUIRK_HAS_HW_APRIV);
a6xx_llc_slices_init(pdev, a6xx_gpu);
diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c
index 326912284a95..f469f951a907 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_device.c
+++ b/drivers/gpu/drm/msm/adreno/adreno_device.c
@@ -302,6 +302,7 @@ static const struct adreno_info gpulist[] = {
},
.gmem = SZ_1M + SZ_128K,
.inactive_period = DRM_MSM_INACTIVE_PERIOD,
+ .quirks = ADRENO_QUIRK_HAS_HW_APRIV,
.init = a6xx_gpu_init,
.zapfw = "a650_zap.mdt",
.hwcg = a650_hwcg,
@@ -315,6 +316,7 @@ static const struct adreno_info gpulist[] = {
},
.gmem = SZ_1M + SZ_512K,
.inactive_period = DRM_MSM_INACTIVE_PERIOD,
+ .quirks = ADRENO_QUIRK_HAS_HW_APRIV,
.init = a6xx_gpu_init,
.zapfw = "a660_zap.mdt",
.hwcg = a660_hwcg,
@@ -327,6 +329,7 @@ static const struct adreno_info gpulist[] = {
},
.gmem = SZ_512K,
.inactive_period = DRM_MSM_INACTIVE_PERIOD,
+ .quirks = ADRENO_QUIRK_HAS_HW_APRIV,
.init = a6xx_gpu_init,
.hwcg = a660_hwcg,
.address_space_size = SZ_16G,
@@ -350,6 +353,7 @@ static const struct adreno_info gpulist[] = {
},
.gmem = SZ_4M,
.inactive_period = DRM_MSM_INACTIVE_PERIOD,
+ .quirks = ADRENO_QUIRK_HAS_HW_APRIV,
.init = a6xx_gpu_init,
.zapfw = "a690_zap.mdt",
.hwcg = a690_hwcg,
diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
index d31e2d37c61b..a7c4a2c536e3 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
+++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
@@ -32,6 +32,7 @@ enum {
#define ADRENO_QUIRK_TWO_PASS_USE_WFI BIT(0)
#define ADRENO_QUIRK_FAULT_DETECT_MASK BIT(1)
#define ADRENO_QUIRK_LMLOADKILL_DISABLE BIT(2)
+#define ADRENO_QUIRK_HAS_HW_APRIV BIT(3)
struct adreno_rev {
uint8_t core;
--
2.41.0
^ permalink raw reply related [flat|nested] 73+ messages in thread
* [PATCH 05/12] drm/msm/adreno: Use quirk to identify cached-coherent support
2023-07-06 21:10 [PATCH 00/12] drm/msm/adreno: Move away from legacy revision matching Rob Clark
` (3 preceding siblings ...)
2023-07-06 21:10 ` [PATCH 04/12] drm/msm/adreno: Use quirk identify hw_apriv Rob Clark
@ 2023-07-06 21:10 ` Rob Clark
2023-07-06 23:29 ` Konrad Dybcio
` (2 more replies)
2023-07-06 21:10 ` [PATCH 06/12] drm/msm/adreno: Allow SoC specific gpu device table entries Rob Clark
` (6 subsequent siblings)
11 siblings, 3 replies; 73+ messages in thread
From: Rob Clark @ 2023-07-06 21:10 UTC (permalink / raw)
To: dri-devel; +Cc: Konrad Dybcio, linux-arm-msm, Rob Clark, freedreno
From: Rob Clark <robdclark@chromium.org>
It is better to explicitly list it. With the move to opaque chip-id's
for future devices, we should avoid trying to infer things like
generation from the numerical value.
Signed-off-by: Rob Clark <robdclark@chromium.org>
---
drivers/gpu/drm/msm/adreno/adreno_device.c | 23 +++++++++++++++-------
drivers/gpu/drm/msm/adreno/adreno_gpu.h | 1 +
2 files changed, 17 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c
index f469f951a907..3c531da417b9 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_device.c
+++ b/drivers/gpu/drm/msm/adreno/adreno_device.c
@@ -256,6 +256,7 @@ static const struct adreno_info gpulist[] = {
},
.gmem = SZ_512K,
.inactive_period = DRM_MSM_INACTIVE_PERIOD,
+ .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT,
.init = a6xx_gpu_init,
}, {
.rev = ADRENO_REV(6, 1, 9, ANY_ID),
@@ -266,6 +267,7 @@ static const struct adreno_info gpulist[] = {
},
.gmem = SZ_512K,
.inactive_period = DRM_MSM_INACTIVE_PERIOD,
+ .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT,
.init = a6xx_gpu_init,
.zapfw = "a615_zap.mdt",
.hwcg = a615_hwcg,
@@ -278,6 +280,7 @@ static const struct adreno_info gpulist[] = {
},
.gmem = SZ_1M,
.inactive_period = DRM_MSM_INACTIVE_PERIOD,
+ .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT,
.init = a6xx_gpu_init,
.zapfw = "a630_zap.mdt",
.hwcg = a630_hwcg,
@@ -290,6 +293,7 @@ static const struct adreno_info gpulist[] = {
},
.gmem = SZ_1M,
.inactive_period = DRM_MSM_INACTIVE_PERIOD,
+ .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT,
.init = a6xx_gpu_init,
.zapfw = "a640_zap.mdt",
.hwcg = a640_hwcg,
@@ -302,7 +306,8 @@ static const struct adreno_info gpulist[] = {
},
.gmem = SZ_1M + SZ_128K,
.inactive_period = DRM_MSM_INACTIVE_PERIOD,
- .quirks = ADRENO_QUIRK_HAS_HW_APRIV,
+ .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |
+ ADRENO_QUIRK_HAS_HW_APRIV,
.init = a6xx_gpu_init,
.zapfw = "a650_zap.mdt",
.hwcg = a650_hwcg,
@@ -316,7 +321,8 @@ static const struct adreno_info gpulist[] = {
},
.gmem = SZ_1M + SZ_512K,
.inactive_period = DRM_MSM_INACTIVE_PERIOD,
- .quirks = ADRENO_QUIRK_HAS_HW_APRIV,
+ .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |
+ ADRENO_QUIRK_HAS_HW_APRIV,
.init = a6xx_gpu_init,
.zapfw = "a660_zap.mdt",
.hwcg = a660_hwcg,
@@ -329,7 +335,8 @@ static const struct adreno_info gpulist[] = {
},
.gmem = SZ_512K,
.inactive_period = DRM_MSM_INACTIVE_PERIOD,
- .quirks = ADRENO_QUIRK_HAS_HW_APRIV,
+ .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |
+ ADRENO_QUIRK_HAS_HW_APRIV,
.init = a6xx_gpu_init,
.hwcg = a660_hwcg,
.address_space_size = SZ_16G,
@@ -342,6 +349,7 @@ static const struct adreno_info gpulist[] = {
},
.gmem = SZ_2M,
.inactive_period = DRM_MSM_INACTIVE_PERIOD,
+ .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT,
.init = a6xx_gpu_init,
.zapfw = "a640_zap.mdt",
.hwcg = a640_hwcg,
@@ -353,7 +361,8 @@ static const struct adreno_info gpulist[] = {
},
.gmem = SZ_4M,
.inactive_period = DRM_MSM_INACTIVE_PERIOD,
- .quirks = ADRENO_QUIRK_HAS_HW_APRIV,
+ .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |
+ ADRENO_QUIRK_HAS_HW_APRIV,
.init = a6xx_gpu_init,
.zapfw = "a690_zap.mdt",
.hwcg = a690_hwcg,
@@ -565,9 +574,9 @@ static int adreno_bind(struct device *dev, struct device *master, void *data)
if (ret)
return ret;
- if (config.rev.core >= 6)
- if (!adreno_has_gmu_wrapper(to_adreno_gpu(gpu)))
- priv->has_cached_coherent = true;
+ priv->has_cached_coherent =
+ !!(info->quirks & ADRENO_QUIRK_HAS_CACHED_COHERENT) &&
+ !adreno_has_gmu_wrapper(to_adreno_gpu(gpu));
return 0;
}
diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
index a7c4a2c536e3..e08d41337169 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
+++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
@@ -33,6 +33,7 @@ enum {
#define ADRENO_QUIRK_FAULT_DETECT_MASK BIT(1)
#define ADRENO_QUIRK_LMLOADKILL_DISABLE BIT(2)
#define ADRENO_QUIRK_HAS_HW_APRIV BIT(3)
+#define ADRENO_QUIRK_HAS_CACHED_COHERENT BIT(4)
struct adreno_rev {
uint8_t core;
--
2.41.0
^ permalink raw reply related [flat|nested] 73+ messages in thread
* [PATCH 06/12] drm/msm/adreno: Allow SoC specific gpu device table entries
2023-07-06 21:10 [PATCH 00/12] drm/msm/adreno: Move away from legacy revision matching Rob Clark
` (4 preceding siblings ...)
2023-07-06 21:10 ` [PATCH 05/12] drm/msm/adreno: Use quirk to identify cached-coherent support Rob Clark
@ 2023-07-06 21:10 ` Rob Clark
2023-07-07 0:40 ` Konrad Dybcio
2023-07-07 2:34 ` Dmitry Baryshkov
2023-07-06 21:10 ` [PATCH 07/12] drm/msm/adreno: Move speedbin mapping to device table Rob Clark
` (5 subsequent siblings)
11 siblings, 2 replies; 73+ messages in thread
From: Rob Clark @ 2023-07-06 21:10 UTC (permalink / raw)
To: dri-devel; +Cc: Konrad Dybcio, linux-arm-msm, Rob Clark, freedreno
From: Rob Clark <robdclark@chromium.org>
There are cases where there are differences due to SoC integration.
Such as cache-coherency support, and (in the next patch) e-fuse to
speedbin mappings.
Signed-off-by: Rob Clark <robdclark@chromium.org>
---
drivers/gpu/drm/msm/adreno/adreno_device.c | 34 +++++++++++++++++++---
drivers/gpu/drm/msm/adreno/adreno_gpu.h | 1 +
2 files changed, 31 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c
index 3c531da417b9..e62bc895a31f 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_device.c
+++ b/drivers/gpu/drm/msm/adreno/adreno_device.c
@@ -258,6 +258,32 @@ static const struct adreno_info gpulist[] = {
.inactive_period = DRM_MSM_INACTIVE_PERIOD,
.quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT,
.init = a6xx_gpu_init,
+ }, {
+ .machine = "qcom,sm4350",
+ .rev = ADRENO_REV(6, 1, 9, ANY_ID),
+ .revn = 619,
+ .fw = {
+ [ADRENO_FW_SQE] = "a630_sqe.fw",
+ [ADRENO_FW_GMU] = "a619_gmu.bin",
+ },
+ .gmem = SZ_512K,
+ .inactive_period = DRM_MSM_INACTIVE_PERIOD,
+ .init = a6xx_gpu_init,
+ .zapfw = "a615_zap.mdt",
+ .hwcg = a615_hwcg,
+ }, {
+ .machine = "qcom,sm6375",
+ .rev = ADRENO_REV(6, 1, 9, ANY_ID),
+ .revn = 619,
+ .fw = {
+ [ADRENO_FW_SQE] = "a630_sqe.fw",
+ [ADRENO_FW_GMU] = "a619_gmu.bin",
+ },
+ .gmem = SZ_512K,
+ .inactive_period = DRM_MSM_INACTIVE_PERIOD,
+ .init = a6xx_gpu_init,
+ .zapfw = "a615_zap.mdt",
+ .hwcg = a615_hwcg,
}, {
.rev = ADRENO_REV(6, 1, 9, ANY_ID),
.revn = 619,
@@ -409,6 +435,8 @@ const struct adreno_info *adreno_info(struct adreno_rev rev)
/* identify gpu: */
for (i = 0; i < ARRAY_SIZE(gpulist); i++) {
const struct adreno_info *info = &gpulist[i];
+ if (info->machine && !of_machine_is_compatible(info->machine))
+ continue;
if (adreno_cmp_rev(info->rev, rev))
return info;
}
@@ -563,6 +591,8 @@ static int adreno_bind(struct device *dev, struct device *master, void *data)
config.rev.minor, config.rev.patchid);
priv->is_a2xx = config.rev.core == 2;
+ priv->has_cached_coherent =
+ !!(info->quirks & ADRENO_QUIRK_HAS_CACHED_COHERENT);
gpu = info->init(drm);
if (IS_ERR(gpu)) {
@@ -574,10 +604,6 @@ static int adreno_bind(struct device *dev, struct device *master, void *data)
if (ret)
return ret;
- priv->has_cached_coherent =
- !!(info->quirks & ADRENO_QUIRK_HAS_CACHED_COHERENT) &&
- !adreno_has_gmu_wrapper(to_adreno_gpu(gpu));
-
return 0;
}
diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
index e08d41337169..d5335b99c64c 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
+++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
@@ -61,6 +61,7 @@ extern const struct adreno_reglist a612_hwcg[], a615_hwcg[], a630_hwcg[], a640_h
extern const struct adreno_reglist a660_hwcg[], a690_hwcg[];
struct adreno_info {
+ const char *machine;
struct adreno_rev rev;
uint32_t revn;
const char *fw[ADRENO_FW_MAX];
--
2.41.0
^ permalink raw reply related [flat|nested] 73+ messages in thread
* [PATCH 07/12] drm/msm/adreno: Move speedbin mapping to device table
2023-07-06 21:10 [PATCH 00/12] drm/msm/adreno: Move away from legacy revision matching Rob Clark
` (5 preceding siblings ...)
2023-07-06 21:10 ` [PATCH 06/12] drm/msm/adreno: Allow SoC specific gpu device table entries Rob Clark
@ 2023-07-06 21:10 ` Rob Clark
2023-07-07 2:54 ` [Freedreno] " Dmitry Baryshkov
2023-07-06 21:10 ` [PATCH 08/12] drm/msm/adreno: Bring the a630 family together Rob Clark
` (4 subsequent siblings)
11 siblings, 1 reply; 73+ messages in thread
From: Rob Clark @ 2023-07-06 21:10 UTC (permalink / raw)
To: dri-devel; +Cc: Konrad Dybcio, linux-arm-msm, Rob Clark, freedreno
From: Rob Clark <robdclark@chromium.org>
This simplifies the code.
Signed-off-by: Rob Clark <robdclark@chromium.org>
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 171 ++-------------------
drivers/gpu/drm/msm/adreno/adreno_device.c | 51 ++++++
drivers/gpu/drm/msm/adreno/adreno_gpu.h | 25 +++
3 files changed, 92 insertions(+), 155 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index 6f8c4381fa4a..77b23c004b94 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
@@ -2204,159 +2204,19 @@ static bool a6xx_progress(struct msm_gpu *gpu, struct msm_ringbuffer *ring)
return progress;
}
-static u32 a610_get_speed_bin(u32 fuse)
+static u32 fuse_to_supp_hw(const struct adreno_info *info, u32 fuse)
{
- /*
- * There are (at least) three SoCs implementing A610: SM6125 (trinket),
- * SM6115 (bengal) and SM6225 (khaje). Trinket does not have speedbinning,
- * as only a single SKU exists and we don't support khaje upstream yet.
- * Hence, this matching table is only valid for bengal and can be easily
- * expanded if need be.
- */
-
- if (fuse == 0)
- return 0;
- else if (fuse == 206)
- return 1;
- else if (fuse == 200)
- return 2;
- else if (fuse == 157)
- return 3;
- else if (fuse == 127)
- return 4;
-
- return UINT_MAX;
-}
-
-static u32 a618_get_speed_bin(u32 fuse)
-{
- if (fuse == 0)
- return 0;
- else if (fuse == 169)
- return 1;
- else if (fuse == 174)
- return 2;
-
- return UINT_MAX;
-}
-
-static u32 a619_holi_get_speed_bin(u32 fuse)
-{
- /*
- * There are (at least) two SoCs implementing A619_holi: SM4350 (holi)
- * and SM6375 (blair). Limit the fuse matching to the corresponding
- * SoC to prevent bogus frequency setting (as improbable as it may be,
- * given unexpected fuse values are.. unexpected! But still possible.)
- */
-
- if (fuse == 0)
- return 0;
-
- if (of_machine_is_compatible("qcom,sm4350")) {
- if (fuse == 138)
- return 1;
- else if (fuse == 92)
- return 2;
- } else if (of_machine_is_compatible("qcom,sm6375")) {
- if (fuse == 190)
- return 1;
- else if (fuse == 177)
- return 2;
- } else
- pr_warn("Unknown SoC implementing A619_holi!\n");
-
- return UINT_MAX;
-}
-
-static u32 a619_get_speed_bin(u32 fuse)
-{
- if (fuse == 0)
- return 0;
- else if (fuse == 120)
- return 4;
- else if (fuse == 138)
- return 3;
- else if (fuse == 169)
- return 2;
- else if (fuse == 180)
- return 1;
-
- return UINT_MAX;
-}
-
-static u32 a640_get_speed_bin(u32 fuse)
-{
- if (fuse == 0)
- return 0;
- else if (fuse == 1)
- return 1;
-
- return UINT_MAX;
-}
-
-static u32 a650_get_speed_bin(u32 fuse)
-{
- if (fuse == 0)
- return 0;
- else if (fuse == 1)
- return 1;
- /* Yep, 2 and 3 are swapped! :/ */
- else if (fuse == 2)
- return 3;
- else if (fuse == 3)
- return 2;
-
- return UINT_MAX;
-}
+ if (!info->speedbins)
+ return UINT_MAX;
-static u32 adreno_7c3_get_speed_bin(u32 fuse)
-{
- if (fuse == 0)
- return 0;
- else if (fuse == 117)
- return 0;
- else if (fuse == 190)
- return 1;
+ for (int i = 0; info->speedbins[i] != UINT_MAX; i += 2)
+ if (info->speedbins[i] == fuse)
+ return (1 << info->speedbins[i + 1]);
return UINT_MAX;
}
-static u32 fuse_to_supp_hw(struct device *dev, struct adreno_gpu *adreno_gpu, u32 fuse)
-{
- u32 val = UINT_MAX;
-
- if (adreno_is_a610(adreno_gpu))
- val = a610_get_speed_bin(fuse);
-
- if (adreno_is_a618(adreno_gpu))
- val = a618_get_speed_bin(fuse);
-
- else if (adreno_is_a619_holi(adreno_gpu))
- val = a619_holi_get_speed_bin(fuse);
-
- else if (adreno_is_a619(adreno_gpu))
- val = a619_get_speed_bin(fuse);
-
- else if (adreno_is_7c3(adreno_gpu))
- val = adreno_7c3_get_speed_bin(fuse);
-
- else if (adreno_is_a640(adreno_gpu))
- val = a640_get_speed_bin(fuse);
-
- else if (adreno_is_a650(adreno_gpu))
- val = a650_get_speed_bin(fuse);
-
- if (val == UINT_MAX) {
- DRM_DEV_ERROR(dev,
- "missing support for speed-bin: %u. Some OPPs may not be supported by hardware\n",
- fuse);
- return UINT_MAX;
- }
-
- return (1 << val);
-}
-
-static int a6xx_set_supported_hw(struct device *dev, struct adreno_gpu *adreno_gpu)
+static int a6xx_set_supported_hw(struct device *dev, const struct adreno_info *info)
{
u32 supp_hw;
u32 speedbin;
@@ -2375,7 +2235,14 @@ static int a6xx_set_supported_hw(struct device *dev, struct adreno_gpu *adreno_g
return ret;
}
- supp_hw = fuse_to_supp_hw(dev, adreno_gpu, speedbin);
+ supp_hw = fuse_to_supp_hw(info, speedbin);
+
+ if (supp_hw == UINT_MAX) {
+ DRM_DEV_ERROR(dev,
+ "missing support for speed-bin: %u. Some OPPs may not be supported by hardware\n",
+ speedbin);
+ return UINT_MAX;
+ }
ret = devm_pm_opp_set_supported_hw(dev, &supp_hw, 1);
if (ret)
@@ -2483,17 +2350,11 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev)
if (!info)
return ERR_PTR(-EINVAL);
- /* Assign these early so that we can use the is_aXYZ helpers */
- /* New-style ADRENO_REV()-only */
- adreno_gpu->rev = info->rev;
- /* Quirk data */
- adreno_gpu->info = info;
-
adreno_gpu->base.hw_apriv = !!(info->quirks & ADRENO_QUIRK_HAS_HW_APRIV);
a6xx_llc_slices_init(pdev, a6xx_gpu);
- ret = a6xx_set_supported_hw(&pdev->dev, adreno_gpu);
+ ret = a6xx_set_supported_hw(&pdev->dev, info);
if (ret) {
a6xx_destroy(&(a6xx_gpu->base.base));
return ERR_PTR(ret);
diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c
index e62bc895a31f..b7f70cfe6081 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_device.c
+++ b/drivers/gpu/drm/msm/adreno/adreno_device.c
@@ -247,6 +247,20 @@ static const struct adreno_info gpulist[] = {
.init = a6xx_gpu_init,
.zapfw = "a610_zap.mdt",
.hwcg = a612_hwcg,
+ /*
+ * There are (at least) three SoCs implementing A610: SM6125
+ * (trinket), SM6115 (bengal) and SM6225 (khaje). Trinket does
+ * not have speedbinning, as only a single SKU exists and we
+ * don't support khaje upstream yet. Hence, this matching
+ * table is only valid for bengal.
+ */
+ .speedbins = ADRENO_SPEEDBINS(
+ 0, 0,
+ 206, 1,
+ 200, 2,
+ 157, 3,
+ 127, 4
+ ),
}, {
.rev = ADRENO_REV(6, 1, 8, ANY_ID),
.revn = 618,
@@ -258,6 +272,11 @@ static const struct adreno_info gpulist[] = {
.inactive_period = DRM_MSM_INACTIVE_PERIOD,
.quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT,
.init = a6xx_gpu_init,
+ .speedbins = ADRENO_SPEEDBINS(
+ 0, 0,
+ 169, 1,
+ 174, 2
+ ),
}, {
.machine = "qcom,sm4350",
.rev = ADRENO_REV(6, 1, 9, ANY_ID),
@@ -271,6 +290,11 @@ static const struct adreno_info gpulist[] = {
.init = a6xx_gpu_init,
.zapfw = "a615_zap.mdt",
.hwcg = a615_hwcg,
+ .speedbins = ADRENO_SPEEDBINS(
+ 0, 0,
+ 138, 1,
+ 92, 2
+ ),
}, {
.machine = "qcom,sm6375",
.rev = ADRENO_REV(6, 1, 9, ANY_ID),
@@ -284,6 +308,11 @@ static const struct adreno_info gpulist[] = {
.init = a6xx_gpu_init,
.zapfw = "a615_zap.mdt",
.hwcg = a615_hwcg,
+ .speedbins = ADRENO_SPEEDBINS(
+ 0, 0,
+ 190, 1,
+ 177, 2
+ ),
}, {
.rev = ADRENO_REV(6, 1, 9, ANY_ID),
.revn = 619,
@@ -297,6 +326,13 @@ static const struct adreno_info gpulist[] = {
.init = a6xx_gpu_init,
.zapfw = "a615_zap.mdt",
.hwcg = a615_hwcg,
+ .speedbins = ADRENO_SPEEDBINS(
+ 0, 0,
+ 120, 4,
+ 138, 3,
+ 169, 2,
+ 180, 1
+ ),
}, {
.rev = ADRENO_REV(6, 3, 0, ANY_ID),
.revn = 630,
@@ -323,6 +359,10 @@ static const struct adreno_info gpulist[] = {
.init = a6xx_gpu_init,
.zapfw = "a640_zap.mdt",
.hwcg = a640_hwcg,
+ .speedbins = ADRENO_SPEEDBINS(
+ 0, 0,
+ 1, 1
+ ),
}, {
.rev = ADRENO_REV(6, 5, 0, ANY_ID),
.revn = 650,
@@ -338,6 +378,12 @@ static const struct adreno_info gpulist[] = {
.zapfw = "a650_zap.mdt",
.hwcg = a650_hwcg,
.address_space_size = SZ_16G,
+ .speedbins = ADRENO_SPEEDBINS(
+ 0, 0,
+ 1, 1,
+ 2, 3, /* Yep, 2 and 3 are swapped! :/ */
+ 3, 2
+ ),
}, {
.rev = ADRENO_REV(6, 6, 0, ANY_ID),
.revn = 660,
@@ -366,6 +412,11 @@ static const struct adreno_info gpulist[] = {
.init = a6xx_gpu_init,
.hwcg = a660_hwcg,
.address_space_size = SZ_16G,
+ .speedbins = ADRENO_SPEEDBINS(
+ 0, 0,
+ 117, 0,
+ 190, 1
+ ),
}, {
.rev = ADRENO_REV(6, 8, 0, ANY_ID),
.revn = 680,
diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
index d5335b99c64c..994ac26ce731 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
+++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
@@ -72,8 +72,33 @@ struct adreno_info {
u32 inactive_period;
const struct adreno_reglist *hwcg;
u64 address_space_size;
+ /**
+ * @speedbins: Optional table of fuse to speedbin mappings
+ *
+ * Consists of pairs of fuse, index mappings, terminated with
+ * UINT_MAX sentinal.
+ */
+ uint32_t *speedbins;
};
+/*
+ * Helper to build a speedbin table, ie. the table:
+ * fuse | speedbin
+ * -----+---------
+ * 0 | 0
+ * 169 | 1
+ * 174 | 2
+ *
+ * would be declared as:
+ *
+ * .speedbins = ADRENO_SPEEDBINS(
+ * 0, 0,
+ * 169, 1,
+ * 174, 2
+ * ),
+ */
+#define ADRENO_SPEEDBINS(tbl...) (uint32_t[]) { tbl, UINT_MAX }
+
const struct adreno_info *adreno_info(struct adreno_rev rev);
struct adreno_gpu {
--
2.41.0
^ permalink raw reply related [flat|nested] 73+ messages in thread
* [PATCH 08/12] drm/msm/adreno: Bring the a630 family together
2023-07-06 21:10 [PATCH 00/12] drm/msm/adreno: Move away from legacy revision matching Rob Clark
` (6 preceding siblings ...)
2023-07-06 21:10 ` [PATCH 07/12] drm/msm/adreno: Move speedbin mapping to device table Rob Clark
@ 2023-07-06 21:10 ` Rob Clark
2023-07-06 23:32 ` Konrad Dybcio
2023-07-06 21:10 ` [PATCH 09/12] drm/msm/adreno: Add adreno family Rob Clark
` (3 subsequent siblings)
11 siblings, 1 reply; 73+ messages in thread
From: Rob Clark @ 2023-07-06 21:10 UTC (permalink / raw)
To: dri-devel; +Cc: Konrad Dybcio, linux-arm-msm, Rob Clark, freedreno
From: Rob Clark <robdclark@chromium.org>
All of these are derivatives of a630.
Signed-off-by: Rob Clark <robdclark@chromium.org>
---
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 2 +-
drivers/gpu/drm/msm/adreno/adreno_gpu.h | 7 ++++---
2 files changed, 5 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
index 5deb79924897..f1bb20574018 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
@@ -1617,7 +1617,7 @@ int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node)
SZ_256K - SZ_16K, 0x44000, "dcache");
if (ret)
goto err_memory;
- } else if (adreno_is_a630(adreno_gpu) || adreno_is_a615_family(adreno_gpu)) {
+ } else if (adreno_is_a630_family(adreno_gpu)) {
/* HFI v1, has sptprac */
gmu->legacy = true;
diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
index 994ac26ce731..6066cfaaea52 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
+++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
@@ -335,10 +335,11 @@ static inline int adreno_is_a690(const struct adreno_gpu *gpu)
/* The order of args is important here to handle ANY_ID correctly */
return adreno_cmp_rev(ADRENO_REV(6, 9, 0, ANY_ID), gpu->rev);
};
-/* check for a615, a616, a618, a619 or any derivatives */
-static inline int adreno_is_a615_family(const struct adreno_gpu *gpu)
+/* check for a615, a616, a618, a619 or any a630 derivatives */
+static inline int adreno_is_a630_family(const struct adreno_gpu *gpu)
{
- return adreno_is_revn(gpu, 615) ||
+ return adreno_is_revn(gpu, 630) ||
+ adreno_is_revn(gpu, 615) ||
adreno_is_revn(gpu, 616) ||
adreno_is_revn(gpu, 618) ||
adreno_is_revn(gpu, 619);
--
2.41.0
^ permalink raw reply related [flat|nested] 73+ messages in thread
* [PATCH 09/12] drm/msm/adreno: Add adreno family
2023-07-06 21:10 [PATCH 00/12] drm/msm/adreno: Move away from legacy revision matching Rob Clark
` (7 preceding siblings ...)
2023-07-06 21:10 ` [PATCH 08/12] drm/msm/adreno: Bring the a630 family together Rob Clark
@ 2023-07-06 21:10 ` Rob Clark
2023-07-06 23:35 ` Konrad Dybcio
2023-07-07 2:49 ` [Freedreno] " Dmitry Baryshkov
2023-07-06 21:10 ` [PATCH 10/12] drm/msm/adreno: Add helper for formating chip-id Rob Clark
` (2 subsequent siblings)
11 siblings, 2 replies; 73+ messages in thread
From: Rob Clark @ 2023-07-06 21:10 UTC (permalink / raw)
To: dri-devel; +Cc: Konrad Dybcio, linux-arm-msm, Rob Clark, freedreno
From: Rob Clark <robdclark@chromium.org>
Sometimes it is useful to know the sub-generation (or "family"). And in
any case, this helps us get away from infering the generation from the
numerical chip-id.
Signed-off-by: Rob Clark <robdclark@chromium.org>
---
drivers/gpu/drm/msm/adreno/adreno_device.c | 31 ++++++++++++++-
drivers/gpu/drm/msm/adreno/adreno_gpu.c | 11 +++---
drivers/gpu/drm/msm/adreno/adreno_gpu.h | 46 ++++++++++++++++------
3 files changed, 70 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c
index b7f70cfe6081..dcd6363ac7b0 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_device.c
+++ b/drivers/gpu/drm/msm/adreno/adreno_device.c
@@ -23,6 +23,7 @@ module_param_named(allow_vram_carveout, allow_vram_carveout, bool, 0600);
static const struct adreno_info gpulist[] = {
{
.rev = ADRENO_REV(2, 0, 0, 0),
+ .family = ADRENO_2XX_GEN1,
.revn = 200,
.fw = {
[ADRENO_FW_PM4] = "yamato_pm4.fw",
@@ -33,6 +34,7 @@ static const struct adreno_info gpulist[] = {
.init = a2xx_gpu_init,
}, { /* a200 on i.mx51 has only 128kib gmem */
.rev = ADRENO_REV(2, 0, 0, 1),
+ .family = ADRENO_2XX_GEN1,
.revn = 201,
.fw = {
[ADRENO_FW_PM4] = "yamato_pm4.fw",
@@ -43,6 +45,7 @@ static const struct adreno_info gpulist[] = {
.init = a2xx_gpu_init,
}, {
.rev = ADRENO_REV(2, 2, 0, ANY_ID),
+ .family = ADRENO_2XX_GEN2,
.revn = 220,
.fw = {
[ADRENO_FW_PM4] = "leia_pm4_470.fw",
@@ -53,6 +56,7 @@ static const struct adreno_info gpulist[] = {
.init = a2xx_gpu_init,
}, {
.rev = ADRENO_REV(3, 0, 5, ANY_ID),
+ .family = ADRENO_3XX,
.revn = 305,
.fw = {
[ADRENO_FW_PM4] = "a300_pm4.fw",
@@ -63,6 +67,7 @@ static const struct adreno_info gpulist[] = {
.init = a3xx_gpu_init,
}, {
.rev = ADRENO_REV(3, 0, 6, 0),
+ .family = ADRENO_3XX,
.revn = 307, /* because a305c is revn==306 */
.fw = {
[ADRENO_FW_PM4] = "a300_pm4.fw",
@@ -73,6 +78,7 @@ static const struct adreno_info gpulist[] = {
.init = a3xx_gpu_init,
}, {
.rev = ADRENO_REV(3, 2, ANY_ID, ANY_ID),
+ .family = ADRENO_3XX,
.revn = 320,
.fw = {
[ADRENO_FW_PM4] = "a300_pm4.fw",
@@ -83,6 +89,7 @@ static const struct adreno_info gpulist[] = {
.init = a3xx_gpu_init,
}, {
.rev = ADRENO_REV(3, 3, 0, ANY_ID),
+ .family = ADRENO_3XX,
.revn = 330,
.fw = {
[ADRENO_FW_PM4] = "a330_pm4.fw",
@@ -93,6 +100,7 @@ static const struct adreno_info gpulist[] = {
.init = a3xx_gpu_init,
}, {
.rev = ADRENO_REV(4, 0, 5, ANY_ID),
+ .family = ADRENO_4XX,
.revn = 405,
.fw = {
[ADRENO_FW_PM4] = "a420_pm4.fw",
@@ -103,6 +111,7 @@ static const struct adreno_info gpulist[] = {
.init = a4xx_gpu_init,
}, {
.rev = ADRENO_REV(4, 2, 0, ANY_ID),
+ .family = ADRENO_4XX,
.revn = 420,
.fw = {
[ADRENO_FW_PM4] = "a420_pm4.fw",
@@ -113,6 +122,7 @@ static const struct adreno_info gpulist[] = {
.init = a4xx_gpu_init,
}, {
.rev = ADRENO_REV(4, 3, 0, ANY_ID),
+ .family = ADRENO_4XX,
.revn = 430,
.fw = {
[ADRENO_FW_PM4] = "a420_pm4.fw",
@@ -123,6 +133,7 @@ static const struct adreno_info gpulist[] = {
.init = a4xx_gpu_init,
}, {
.rev = ADRENO_REV(5, 0, 6, ANY_ID),
+ .family = ADRENO_5XX,
.revn = 506,
.fw = {
[ADRENO_FW_PM4] = "a530_pm4.fw",
@@ -140,6 +151,7 @@ static const struct adreno_info gpulist[] = {
.zapfw = "a506_zap.mdt",
}, {
.rev = ADRENO_REV(5, 0, 8, ANY_ID),
+ .family = ADRENO_5XX,
.revn = 508,
.fw = {
[ADRENO_FW_PM4] = "a530_pm4.fw",
@@ -156,6 +168,7 @@ static const struct adreno_info gpulist[] = {
.zapfw = "a508_zap.mdt",
}, {
.rev = ADRENO_REV(5, 0, 9, ANY_ID),
+ .family = ADRENO_5XX,
.revn = 509,
.fw = {
[ADRENO_FW_PM4] = "a530_pm4.fw",
@@ -173,6 +186,7 @@ static const struct adreno_info gpulist[] = {
.zapfw = "a512_zap.mdt",
}, {
.rev = ADRENO_REV(5, 1, 0, ANY_ID),
+ .family = ADRENO_5XX,
.revn = 510,
.fw = {
[ADRENO_FW_PM4] = "a530_pm4.fw",
@@ -187,6 +201,7 @@ static const struct adreno_info gpulist[] = {
.init = a5xx_gpu_init,
}, {
.rev = ADRENO_REV(5, 1, 2, ANY_ID),
+ .family = ADRENO_5XX,
.revn = 512,
.fw = {
[ADRENO_FW_PM4] = "a530_pm4.fw",
@@ -203,6 +218,7 @@ static const struct adreno_info gpulist[] = {
.zapfw = "a512_zap.mdt",
}, {
.rev = ADRENO_REV(5, 3, 0, 2),
+ .family = ADRENO_5XX,
.revn = 530,
.fw = {
[ADRENO_FW_PM4] = "a530_pm4.fw",
@@ -221,6 +237,7 @@ static const struct adreno_info gpulist[] = {
.zapfw = "a530_zap.mdt",
}, {
.rev = ADRENO_REV(5, 4, 0, ANY_ID),
+ .family = ADRENO_5XX,
.revn = 540,
.fw = {
[ADRENO_FW_PM4] = "a530_pm4.fw",
@@ -238,6 +255,7 @@ static const struct adreno_info gpulist[] = {
.zapfw = "a540_zap.mdt",
}, {
.rev = ADRENO_REV(6, 1, 0, ANY_ID),
+ .family = ADRENO_6XX_GEN1,
.revn = 610,
.fw = {
[ADRENO_FW_SQE] = "a630_sqe.fw",
@@ -263,6 +281,7 @@ static const struct adreno_info gpulist[] = {
),
}, {
.rev = ADRENO_REV(6, 1, 8, ANY_ID),
+ .family = ADRENO_6XX_GEN1,
.revn = 618,
.fw = {
[ADRENO_FW_SQE] = "a630_sqe.fw",
@@ -280,6 +299,7 @@ static const struct adreno_info gpulist[] = {
}, {
.machine = "qcom,sm4350",
.rev = ADRENO_REV(6, 1, 9, ANY_ID),
+ .family = ADRENO_6XX_GEN1,
.revn = 619,
.fw = {
[ADRENO_FW_SQE] = "a630_sqe.fw",
@@ -298,6 +318,7 @@ static const struct adreno_info gpulist[] = {
}, {
.machine = "qcom,sm6375",
.rev = ADRENO_REV(6, 1, 9, ANY_ID),
+ .family = ADRENO_6XX_GEN1,
.revn = 619,
.fw = {
[ADRENO_FW_SQE] = "a630_sqe.fw",
@@ -315,6 +336,7 @@ static const struct adreno_info gpulist[] = {
),
}, {
.rev = ADRENO_REV(6, 1, 9, ANY_ID),
+ .family = ADRENO_6XX_GEN1,
.revn = 619,
.fw = {
[ADRENO_FW_SQE] = "a630_sqe.fw",
@@ -335,6 +357,7 @@ static const struct adreno_info gpulist[] = {
),
}, {
.rev = ADRENO_REV(6, 3, 0, ANY_ID),
+ .family = ADRENO_6XX_GEN1,
.revn = 630,
.fw = {
[ADRENO_FW_SQE] = "a630_sqe.fw",
@@ -348,6 +371,7 @@ static const struct adreno_info gpulist[] = {
.hwcg = a630_hwcg,
}, {
.rev = ADRENO_REV(6, 4, 0, ANY_ID),
+ .family = ADRENO_6XX_GEN2,
.revn = 640,
.fw = {
[ADRENO_FW_SQE] = "a630_sqe.fw",
@@ -365,6 +389,7 @@ static const struct adreno_info gpulist[] = {
),
}, {
.rev = ADRENO_REV(6, 5, 0, ANY_ID),
+ .family = ADRENO_6XX_GEN3,
.revn = 650,
.fw = {
[ADRENO_FW_SQE] = "a650_sqe.fw",
@@ -386,6 +411,7 @@ static const struct adreno_info gpulist[] = {
),
}, {
.rev = ADRENO_REV(6, 6, 0, ANY_ID),
+ .family = ADRENO_6XX_GEN4,
.revn = 660,
.fw = {
[ADRENO_FW_SQE] = "a660_sqe.fw",
@@ -401,6 +427,7 @@ static const struct adreno_info gpulist[] = {
.address_space_size = SZ_16G,
}, {
.rev = ADRENO_REV(6, 3, 5, ANY_ID),
+ .family = ADRENO_6XX_GEN4,
.fw = {
[ADRENO_FW_SQE] = "a660_sqe.fw",
[ADRENO_FW_GMU] = "a660_gmu.bin",
@@ -419,6 +446,7 @@ static const struct adreno_info gpulist[] = {
),
}, {
.rev = ADRENO_REV(6, 8, 0, ANY_ID),
+ .family = ADRENO_6XX_GEN2,
.revn = 680,
.fw = {
[ADRENO_FW_SQE] = "a630_sqe.fw",
@@ -432,6 +460,7 @@ static const struct adreno_info gpulist[] = {
.hwcg = a640_hwcg,
}, {
.rev = ADRENO_REV(6, 9, 0, ANY_ID),
+ .family = ADRENO_6XX_GEN4,
.fw = {
[ADRENO_FW_SQE] = "a660_sqe.fw",
[ADRENO_FW_GMU] = "a690_gmu.bin",
@@ -641,7 +670,7 @@ static int adreno_bind(struct device *dev, struct device *master, void *data)
DBG("Found GPU: %u.%u.%u.%u", config.rev.core, config.rev.major,
config.rev.minor, config.rev.patchid);
- priv->is_a2xx = config.rev.core == 2;
+ priv->is_a2xx = info->family < ADRENO_3XX;
priv->has_cached_coherent =
!!(info->quirks & ADRENO_QUIRK_HAS_CACHED_COHERENT);
diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
index 2e62a7ce9f13..75ff7fb46099 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
@@ -1079,8 +1079,13 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev,
u32 speedbin;
int ret;
+ adreno_gpu->funcs = funcs;
+ adreno_gpu->info = adreno_info(config->rev);
+ adreno_gpu->rev = *rev;
+
/* Only handle the core clock when GMU is not in use (or is absent). */
- if (adreno_has_gmu_wrapper(adreno_gpu) || config->rev.core < 6) {
+ if (adreno_has_gmu_wrapper(adreno_gpu) ||
+ adreno_gpu->info->family < ADRENO_6XX_GEN1) {
/*
* This can only be done before devm_pm_opp_of_add_table(), or
* dev_pm_opp_set_config() will WARN_ON()
@@ -1096,10 +1101,6 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev,
devm_pm_opp_set_clkname(dev, "core");
}
- adreno_gpu->funcs = funcs;
- adreno_gpu->info = adreno_info(config->rev);
- adreno_gpu->rev = *rev;
-
if (adreno_read_speedbin(dev, &speedbin) || !speedbin)
speedbin = 0xffff;
adreno_gpu->speedbin = (uint16_t) (0xffff & speedbin);
diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
index 6066cfaaea52..2fa14dcd4e40 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
+++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
@@ -29,6 +29,25 @@ enum {
ADRENO_FW_MAX,
};
+/**
+ * @enum adreno_family: identify generation and possibly sub-generation
+ *
+ * In some cases there are distinct sub-generations within a major revision
+ * so it helps to be able to group the GPU devices by generation and if
+ * necessary sub-generation.
+ */
+enum adreno_family {
+ ADRENO_2XX_GEN1, /* a20x */
+ ADRENO_2XX_GEN2, /* a22x */
+ ADRENO_3XX,
+ ADRENO_4XX,
+ ADRENO_5XX,
+ ADRENO_6XX_GEN1, /* a630 family */
+ ADRENO_6XX_GEN2, /* a640 family */
+ ADRENO_6XX_GEN3, /* a650 family */
+ ADRENO_6XX_GEN4, /* a660 family */
+};
+
#define ADRENO_QUIRK_TWO_PASS_USE_WFI BIT(0)
#define ADRENO_QUIRK_FAULT_DETECT_MASK BIT(1)
#define ADRENO_QUIRK_LMLOADKILL_DISABLE BIT(2)
@@ -63,6 +82,7 @@ extern const struct adreno_reglist a660_hwcg[], a690_hwcg[];
struct adreno_info {
const char *machine;
struct adreno_rev rev;
+ enum adreno_family family;
uint32_t revn;
const char *fw[ADRENO_FW_MAX];
uint32_t gmem;
@@ -188,14 +208,14 @@ static inline bool adreno_is_a2xx(const struct adreno_gpu *gpu)
{
if (WARN_ON_ONCE(!gpu->info))
return false;
- return (gpu->info->revn < 300);
+ return gpu->info->family < ADRENO_2XX_GEN2;
}
static inline bool adreno_is_a20x(const struct adreno_gpu *gpu)
{
if (WARN_ON_ONCE(!gpu->info))
return false;
- return (gpu->info->revn < 210);
+ return gpu->info->family == ADRENO_2XX_GEN1;
}
static inline bool adreno_is_a225(const struct adreno_gpu *gpu)
@@ -338,29 +358,31 @@ static inline int adreno_is_a690(const struct adreno_gpu *gpu)
/* check for a615, a616, a618, a619 or any a630 derivatives */
static inline int adreno_is_a630_family(const struct adreno_gpu *gpu)
{
- return adreno_is_revn(gpu, 630) ||
- adreno_is_revn(gpu, 615) ||
- adreno_is_revn(gpu, 616) ||
- adreno_is_revn(gpu, 618) ||
- adreno_is_revn(gpu, 619);
+ if (WARN_ON_ONCE(!gpu->info))
+ return false;
+ return gpu->info->family == ADRENO_6XX_GEN1;
}
static inline int adreno_is_a660_family(const struct adreno_gpu *gpu)
{
- return adreno_is_a660(gpu) || adreno_is_a690(gpu) || adreno_is_7c3(gpu);
+ if (WARN_ON_ONCE(!gpu->info))
+ return false;
+ return gpu->info->family == ADRENO_6XX_GEN4;
}
/* check for a650, a660, or any derivatives */
static inline int adreno_is_a650_family(const struct adreno_gpu *gpu)
{
- return adreno_is_revn(gpu, 650) ||
- adreno_is_revn(gpu, 620) ||
- adreno_is_a660_family(gpu);
+ if (WARN_ON_ONCE(!gpu->info))
+ return false;
+ return gpu->info->family >= ADRENO_6XX_GEN3;
}
static inline int adreno_is_a640_family(const struct adreno_gpu *gpu)
{
- return adreno_is_a640(gpu) || adreno_is_a680(gpu);
+ if (WARN_ON_ONCE(!gpu->info))
+ return false;
+ return gpu->info->family == ADRENO_6XX_GEN2;
}
u64 adreno_private_address_space_size(struct msm_gpu *gpu);
--
2.41.0
^ permalink raw reply related [flat|nested] 73+ messages in thread
* [PATCH 10/12] drm/msm/adreno: Add helper for formating chip-id
2023-07-06 21:10 [PATCH 00/12] drm/msm/adreno: Move away from legacy revision matching Rob Clark
` (8 preceding siblings ...)
2023-07-06 21:10 ` [PATCH 09/12] drm/msm/adreno: Add adreno family Rob Clark
@ 2023-07-06 21:10 ` Rob Clark
2023-07-06 23:36 ` Konrad Dybcio
2023-07-07 2:50 ` [Freedreno] " Dmitry Baryshkov
2023-07-06 21:10 ` [PATCH 11/12] dt-bindings: drm/msm/gpu: Extend bindings for chip-id Rob Clark
2023-07-06 21:10 ` [PATCH 12/12] drm/msm/adreno: Switch to chip-id for identifying GPU Rob Clark
11 siblings, 2 replies; 73+ messages in thread
From: Rob Clark @ 2023-07-06 21:10 UTC (permalink / raw)
To: dri-devel; +Cc: Konrad Dybcio, linux-arm-msm, Rob Clark, freedreno
From: Rob Clark <robdclark@chromium.org>
This is used in a few places, including one that is parsed by userspace
tools. So let's standardize it a bit better.
Signed-off-by: Rob Clark <robdclark@chromium.org>
---
drivers/gpu/drm/msm/adreno/adreno_device.c | 8 +++-----
drivers/gpu/drm/msm/adreno/adreno_gpu.c | 19 ++++++++-----------
drivers/gpu/drm/msm/adreno/adreno_gpu.h | 6 ++++++
3 files changed, 17 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c
index dcd6363ac7b0..fd2e183bce60 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_device.c
+++ b/drivers/gpu/drm/msm/adreno/adreno_device.c
@@ -661,14 +661,12 @@ static int adreno_bind(struct device *dev, struct device *master, void *data)
info = adreno_info(config.rev);
if (!info) {
- dev_warn(drm->dev, "Unknown GPU revision: %u.%u.%u.%u\n",
- config.rev.core, config.rev.major,
- config.rev.minor, config.rev.patchid);
+ dev_warn(drm->dev, "Unknown GPU revision: %"ADRENO_CHIPID_FMT"\n",
+ ADRENO_CHIPID_ARGS(config.rev));
return -ENXIO;
}
- DBG("Found GPU: %u.%u.%u.%u", config.rev.core, config.rev.major,
- config.rev.minor, config.rev.patchid);
+ DBG("Found GPU: %"ADRENO_CHIPID_FMT, ADRENO_CHIPID_ARGS(config.rev));
priv->is_a2xx = info->family < ADRENO_3XX;
priv->has_cached_coherent =
diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
index 75ff7fb46099..1a982a926f21 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
@@ -847,10 +847,9 @@ void adreno_show(struct msm_gpu *gpu, struct msm_gpu_state *state,
if (IS_ERR_OR_NULL(state))
return;
- drm_printf(p, "revision: %d (%d.%d.%d.%d)\n",
- adreno_gpu->info->revn, adreno_gpu->rev.core,
- adreno_gpu->rev.major, adreno_gpu->rev.minor,
- adreno_gpu->rev.patchid);
+ drm_printf(p, "revision: %u (%"ADRENO_CHIPID_FMT")\n",
+ adreno_gpu->info->revn,
+ ADRENO_CHIPID_ARGS(adreno_gpu->rev));
/*
* If this is state collected due to iova fault, so fault related info
*
@@ -921,10 +920,9 @@ void adreno_dump_info(struct msm_gpu *gpu)
struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
int i;
- printk("revision: %d (%d.%d.%d.%d)\n",
- adreno_gpu->info->revn, adreno_gpu->rev.core,
- adreno_gpu->rev.major, adreno_gpu->rev.minor,
- adreno_gpu->rev.patchid);
+ printk("revision: %u (%"ADRENO_CHIPID_FMT")\n",
+ adreno_gpu->info->revn,
+ ADRENO_CHIPID_ARGS(adreno_gpu->rev));
for (i = 0; i < gpu->nr_rings; i++) {
struct msm_ringbuffer *ring = gpu->rb[i];
@@ -1105,9 +1103,8 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev,
speedbin = 0xffff;
adreno_gpu->speedbin = (uint16_t) (0xffff & speedbin);
- gpu_name = devm_kasprintf(dev, GFP_KERNEL, "%d.%d.%d.%d",
- rev->core, rev->major, rev->minor,
- rev->patchid);
+ gpu_name = devm_kasprintf(dev, GFP_KERNEL, "%"ADRENO_CHIPID_FMT,
+ ADRENO_CHIPID_ARGS(config->rev));
if (!gpu_name)
return -ENOMEM;
diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
index 2fa14dcd4e40..73e7155f164c 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
+++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
@@ -66,6 +66,12 @@ struct adreno_rev {
#define ADRENO_REV(core, major, minor, patchid) \
((struct adreno_rev){ core, major, minor, patchid })
+/* Helper for formating the chip_id in the way that userspace tools like
+ * crashdec expect.
+ */
+#define ADRENO_CHIPID_FMT "u.%u.%u.%u"
+#define ADRENO_CHIPID_ARGS(_r) (_r).core, (_r).major, (_r).minor, (_r).patchid
+
struct adreno_gpu_funcs {
struct msm_gpu_funcs base;
int (*get_timestamp)(struct msm_gpu *gpu, uint64_t *value);
--
2.41.0
^ permalink raw reply related [flat|nested] 73+ messages in thread
* [PATCH 11/12] dt-bindings: drm/msm/gpu: Extend bindings for chip-id
2023-07-06 21:10 [PATCH 00/12] drm/msm/adreno: Move away from legacy revision matching Rob Clark
` (9 preceding siblings ...)
2023-07-06 21:10 ` [PATCH 10/12] drm/msm/adreno: Add helper for formating chip-id Rob Clark
@ 2023-07-06 21:10 ` Rob Clark
2023-07-07 7:26 ` Krzysztof Kozlowski
2023-07-06 21:10 ` [PATCH 12/12] drm/msm/adreno: Switch to chip-id for identifying GPU Rob Clark
11 siblings, 1 reply; 73+ messages in thread
From: Rob Clark @ 2023-07-06 21:10 UTC (permalink / raw)
To: dri-devel; +Cc: Konrad Dybcio, linux-arm-msm, Rob Clark, freedreno
From: Rob Clark <robdclark@chromium.org>
Upcoming GPUs use an opaque chip-id for identifying the GPU.
Signed-off-by: Rob Clark <robdclark@chromium.org>
---
Documentation/devicetree/bindings/display/msm/gpu.yaml | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/msm/gpu.yaml b/Documentation/devicetree/bindings/display/msm/gpu.yaml
index 58ca8912a8c3..56b9b247e8c2 100644
--- a/Documentation/devicetree/bindings/display/msm/gpu.yaml
+++ b/Documentation/devicetree/bindings/display/msm/gpu.yaml
@@ -13,6 +13,12 @@ maintainers:
properties:
compatible:
oneOf:
+ - description: |
+ The driver is parsing the compat string for Adreno to
+ figure out the chip-id.
+ items:
+ - pattern: '^qcom,adreno-[0-9a-f][0-9a-f][0-9a-f][0-9a-f][0-9a-f][0-9a-f][0-9a-f][0-9a-f]$'
+ - const: qcom,adreno
- description: |
The driver is parsing the compat string for Adreno to
figure out the gpu-id and patch level.
--
2.41.0
^ permalink raw reply related [flat|nested] 73+ messages in thread
* [PATCH 12/12] drm/msm/adreno: Switch to chip-id for identifying GPU
2023-07-06 21:10 [PATCH 00/12] drm/msm/adreno: Move away from legacy revision matching Rob Clark
` (10 preceding siblings ...)
2023-07-06 21:10 ` [PATCH 11/12] dt-bindings: drm/msm/gpu: Extend bindings for chip-id Rob Clark
@ 2023-07-06 21:10 ` Rob Clark
2023-07-07 0:25 ` Konrad Dybcio
2023-07-07 3:45 ` [Freedreno] " Dmitry Baryshkov
11 siblings, 2 replies; 73+ messages in thread
From: Rob Clark @ 2023-07-06 21:10 UTC (permalink / raw)
To: dri-devel; +Cc: Konrad Dybcio, linux-arm-msm, Rob Clark, freedreno
From: Rob Clark <robdclark@chromium.org>
Since the revision becomes an opaque identifier with future GPUs, move
away from treating different ranges of bits as having a given meaning.
This means that we need to explicitly list different patch revisions in
the device table.
Signed-off-by: Rob Clark <robdclark@chromium.org>
---
drivers/gpu/drm/msm/adreno/a4xx_gpu.c | 2 +-
drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 11 +-
drivers/gpu/drm/msm/adreno/a5xx_power.c | 2 +-
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 13 ++-
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 9 +-
drivers/gpu/drm/msm/adreno/adreno_device.c | 128 ++++++++++-----------
drivers/gpu/drm/msm/adreno/adreno_gpu.c | 16 +--
drivers/gpu/drm/msm/adreno/adreno_gpu.h | 51 ++++----
8 files changed, 122 insertions(+), 110 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno/a4xx_gpu.c b/drivers/gpu/drm/msm/adreno/a4xx_gpu.c
index 715436cb3996..8b4cdf95f445 100644
--- a/drivers/gpu/drm/msm/adreno/a4xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a4xx_gpu.c
@@ -145,7 +145,7 @@ static void a4xx_enable_hwcg(struct msm_gpu *gpu)
gpu_write(gpu, REG_A4XX_RBBM_CLOCK_DELAY_HLSQ, 0x00220000);
/* Early A430's have a timing issue with SP/TP power collapse;
disabling HW clock gating prevents it. */
- if (adreno_is_a430(adreno_gpu) && adreno_gpu->rev.patchid < 2)
+ if (adreno_is_a430(adreno_gpu) && adreno_patchid(adreno_gpu) < 2)
gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL, 0);
else
gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL, 0xAAAAAAAA);
diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
index f0803e94ebe5..70d2b5342cd9 100644
--- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
@@ -1744,6 +1744,7 @@ struct msm_gpu *a5xx_gpu_init(struct drm_device *dev)
struct msm_drm_private *priv = dev->dev_private;
struct platform_device *pdev = priv->gpu_pdev;
struct adreno_platform_config *config = pdev->dev.platform_data;
+ const struct adreno_info *info;
struct a5xx_gpu *a5xx_gpu = NULL;
struct adreno_gpu *adreno_gpu;
struct msm_gpu *gpu;
@@ -1770,7 +1771,15 @@ struct msm_gpu *a5xx_gpu_init(struct drm_device *dev)
nr_rings = 4;
- if (adreno_cmp_rev(ADRENO_REV(5, 1, 0, ANY_ID), config->rev))
+ /*
+ * Note that we wouldn't have been able to get this far if there is not
+ * a device table entry for this chip_id
+ */
+ info = adreno_find_info(config->chip_id);
+ if (WARN_ON(!info))
+ return ERR_PTR(-EINVAL);
+
+ if (info->revn == 510)
nr_rings = 1;
ret = adreno_gpu_init(dev, pdev, adreno_gpu, &funcs, nr_rings);
diff --git a/drivers/gpu/drm/msm/adreno/a5xx_power.c b/drivers/gpu/drm/msm/adreno/a5xx_power.c
index 0e63a1429189..7705f8010484 100644
--- a/drivers/gpu/drm/msm/adreno/a5xx_power.c
+++ b/drivers/gpu/drm/msm/adreno/a5xx_power.c
@@ -179,7 +179,7 @@ static void a540_lm_setup(struct msm_gpu *gpu)
/* The battery current limiter isn't enabled for A540 */
config = AGC_LM_CONFIG_BCL_DISABLED;
- config |= adreno_gpu->rev.patchid << AGC_LM_CONFIG_GPU_VERSION_SHIFT;
+ config |= adreno_patchid(adreno_gpu) << AGC_LM_CONFIG_GPU_VERSION_SHIFT;
/* For now disable GPMU side throttling */
config |= AGC_LM_CONFIG_THROTTLE_DISABLE;
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
index f1bb20574018..a9ba547a120c 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
@@ -790,10 +790,15 @@ static int a6xx_gmu_fw_start(struct a6xx_gmu *gmu, unsigned int state)
gmu_write(gmu, REG_A6XX_GMU_AHB_FENCE_RANGE_0,
(1 << 31) | (0xa << 18) | (0xa0));
- chipid = adreno_gpu->rev.core << 24;
- chipid |= adreno_gpu->rev.major << 16;
- chipid |= adreno_gpu->rev.minor << 12;
- chipid |= adreno_gpu->rev.patchid << 8;
+ /* Note that the GMU has a slightly different layout for
+ * chip_id, for whatever reason, so a bit of massaging
+ * is needed. The upper 16b are the same, but minor and
+ * patchid are packed in four bits each with the lower
+ * 8b unused:
+ */
+ chipid = adreno_gpu->chip_id & 0xffff0000;
+ chipid |= (adreno_gpu->chip_id << 4) & 0xf000; /* minor */
+ chipid |= (adreno_gpu->chip_id << 8) & 0x0f00; /* patchid */
gmu_write(gmu, REG_A6XX_GMU_HFI_SFR_ADDR, chipid);
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index 77b23c004b94..ed075729ca09 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
@@ -2344,10 +2344,13 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev)
/*
* We need to know the platform type before calling into adreno_gpu_init
* so that the hw_apriv flag can be correctly set. Snoop into the info
- * and grab the revision number
+ * and grab the revision number.
+ *
+ * Note that we wouldn't have been able to get this far if there is not
+ * a device table entry for this chip_id
*/
- info = adreno_info(config->rev);
- if (!info)
+ info = adreno_find_info(config->chip_id);
+ if (WARN_ON(!info))
return ERR_PTR(-EINVAL);
adreno_gpu->base.hw_apriv = !!(info->quirks & ADRENO_QUIRK_HAS_HW_APRIV);
diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c
index fd2e183bce60..4a718ff33635 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_device.c
+++ b/drivers/gpu/drm/msm/adreno/adreno_device.c
@@ -22,7 +22,7 @@ module_param_named(allow_vram_carveout, allow_vram_carveout, bool, 0600);
static const struct adreno_info gpulist[] = {
{
- .rev = ADRENO_REV(2, 0, 0, 0),
+ .chip_ids = ADRENO_CHIP_IDS(0x02000000),
.family = ADRENO_2XX_GEN1,
.revn = 200,
.fw = {
@@ -33,7 +33,7 @@ static const struct adreno_info gpulist[] = {
.inactive_period = DRM_MSM_INACTIVE_PERIOD,
.init = a2xx_gpu_init,
}, { /* a200 on i.mx51 has only 128kib gmem */
- .rev = ADRENO_REV(2, 0, 0, 1),
+ .chip_ids = ADRENO_CHIP_IDS(0x02000001),
.family = ADRENO_2XX_GEN1,
.revn = 201,
.fw = {
@@ -44,7 +44,7 @@ static const struct adreno_info gpulist[] = {
.inactive_period = DRM_MSM_INACTIVE_PERIOD,
.init = a2xx_gpu_init,
}, {
- .rev = ADRENO_REV(2, 2, 0, ANY_ID),
+ .chip_ids = ADRENO_CHIP_IDS(0x02020000),
.family = ADRENO_2XX_GEN2,
.revn = 220,
.fw = {
@@ -55,7 +55,7 @@ static const struct adreno_info gpulist[] = {
.inactive_period = DRM_MSM_INACTIVE_PERIOD,
.init = a2xx_gpu_init,
}, {
- .rev = ADRENO_REV(3, 0, 5, ANY_ID),
+ .chip_ids = ADRENO_CHIP_IDS(0x03000500),
.family = ADRENO_3XX,
.revn = 305,
.fw = {
@@ -66,7 +66,7 @@ static const struct adreno_info gpulist[] = {
.inactive_period = DRM_MSM_INACTIVE_PERIOD,
.init = a3xx_gpu_init,
}, {
- .rev = ADRENO_REV(3, 0, 6, 0),
+ .chip_ids = ADRENO_CHIP_IDS(0x03000600),
.family = ADRENO_3XX,
.revn = 307, /* because a305c is revn==306 */
.fw = {
@@ -77,7 +77,11 @@ static const struct adreno_info gpulist[] = {
.inactive_period = DRM_MSM_INACTIVE_PERIOD,
.init = a3xx_gpu_init,
}, {
- .rev = ADRENO_REV(3, 2, ANY_ID, ANY_ID),
+ .chip_ids = ADRENO_CHIP_IDS(
+ 0x03020000,
+ 0x03020001,
+ 0x03020002
+ ),
.family = ADRENO_3XX,
.revn = 320,
.fw = {
@@ -88,7 +92,11 @@ static const struct adreno_info gpulist[] = {
.inactive_period = DRM_MSM_INACTIVE_PERIOD,
.init = a3xx_gpu_init,
}, {
- .rev = ADRENO_REV(3, 3, 0, ANY_ID),
+ .chip_ids = ADRENO_CHIP_IDS(
+ 0x03030000,
+ 0x03030001,
+ 0x03030002
+ ),
.family = ADRENO_3XX,
.revn = 330,
.fw = {
@@ -99,7 +107,7 @@ static const struct adreno_info gpulist[] = {
.inactive_period = DRM_MSM_INACTIVE_PERIOD,
.init = a3xx_gpu_init,
}, {
- .rev = ADRENO_REV(4, 0, 5, ANY_ID),
+ .chip_ids = ADRENO_CHIP_IDS(0x04000500),
.family = ADRENO_4XX,
.revn = 405,
.fw = {
@@ -110,7 +118,7 @@ static const struct adreno_info gpulist[] = {
.inactive_period = DRM_MSM_INACTIVE_PERIOD,
.init = a4xx_gpu_init,
}, {
- .rev = ADRENO_REV(4, 2, 0, ANY_ID),
+ .chip_ids = ADRENO_CHIP_IDS(0x04020000),
.family = ADRENO_4XX,
.revn = 420,
.fw = {
@@ -121,7 +129,7 @@ static const struct adreno_info gpulist[] = {
.inactive_period = DRM_MSM_INACTIVE_PERIOD,
.init = a4xx_gpu_init,
}, {
- .rev = ADRENO_REV(4, 3, 0, ANY_ID),
+ .chip_ids = ADRENO_CHIP_IDS(0x04030000),
.family = ADRENO_4XX,
.revn = 430,
.fw = {
@@ -132,7 +140,7 @@ static const struct adreno_info gpulist[] = {
.inactive_period = DRM_MSM_INACTIVE_PERIOD,
.init = a4xx_gpu_init,
}, {
- .rev = ADRENO_REV(5, 0, 6, ANY_ID),
+ .chip_ids = ADRENO_CHIP_IDS(0x05000600),
.family = ADRENO_5XX,
.revn = 506,
.fw = {
@@ -150,7 +158,7 @@ static const struct adreno_info gpulist[] = {
.init = a5xx_gpu_init,
.zapfw = "a506_zap.mdt",
}, {
- .rev = ADRENO_REV(5, 0, 8, ANY_ID),
+ .chip_ids = ADRENO_CHIP_IDS(0x05000800),
.family = ADRENO_5XX,
.revn = 508,
.fw = {
@@ -167,7 +175,7 @@ static const struct adreno_info gpulist[] = {
.init = a5xx_gpu_init,
.zapfw = "a508_zap.mdt",
}, {
- .rev = ADRENO_REV(5, 0, 9, ANY_ID),
+ .chip_ids = ADRENO_CHIP_IDS(0x05000900),
.family = ADRENO_5XX,
.revn = 509,
.fw = {
@@ -185,7 +193,7 @@ static const struct adreno_info gpulist[] = {
/* Adreno 509 uses the same ZAP as 512 */
.zapfw = "a512_zap.mdt",
}, {
- .rev = ADRENO_REV(5, 1, 0, ANY_ID),
+ .chip_ids = ADRENO_CHIP_IDS(0x05010000),
.family = ADRENO_5XX,
.revn = 510,
.fw = {
@@ -200,7 +208,7 @@ static const struct adreno_info gpulist[] = {
.inactive_period = 250,
.init = a5xx_gpu_init,
}, {
- .rev = ADRENO_REV(5, 1, 2, ANY_ID),
+ .chip_ids = ADRENO_CHIP_IDS(0x05010200),
.family = ADRENO_5XX,
.revn = 512,
.fw = {
@@ -217,7 +225,7 @@ static const struct adreno_info gpulist[] = {
.init = a5xx_gpu_init,
.zapfw = "a512_zap.mdt",
}, {
- .rev = ADRENO_REV(5, 3, 0, 2),
+ .chip_ids = ADRENO_CHIP_IDS(0x05030002),
.family = ADRENO_5XX,
.revn = 530,
.fw = {
@@ -236,7 +244,7 @@ static const struct adreno_info gpulist[] = {
.init = a5xx_gpu_init,
.zapfw = "a530_zap.mdt",
}, {
- .rev = ADRENO_REV(5, 4, 0, ANY_ID),
+ .chip_ids = ADRENO_CHIP_IDS(0x05040001),
.family = ADRENO_5XX,
.revn = 540,
.fw = {
@@ -254,7 +262,7 @@ static const struct adreno_info gpulist[] = {
.init = a5xx_gpu_init,
.zapfw = "a540_zap.mdt",
}, {
- .rev = ADRENO_REV(6, 1, 0, ANY_ID),
+ .chip_ids = ADRENO_CHIP_IDS(0x06010000),
.family = ADRENO_6XX_GEN1,
.revn = 610,
.fw = {
@@ -280,7 +288,7 @@ static const struct adreno_info gpulist[] = {
127, 4
),
}, {
- .rev = ADRENO_REV(6, 1, 8, ANY_ID),
+ .chip_ids = ADRENO_CHIP_IDS(0x06010800),
.family = ADRENO_6XX_GEN1,
.revn = 618,
.fw = {
@@ -298,7 +306,7 @@ static const struct adreno_info gpulist[] = {
),
}, {
.machine = "qcom,sm4350",
- .rev = ADRENO_REV(6, 1, 9, ANY_ID),
+ .chip_ids = ADRENO_CHIP_IDS(0x06010900),
.family = ADRENO_6XX_GEN1,
.revn = 619,
.fw = {
@@ -317,7 +325,7 @@ static const struct adreno_info gpulist[] = {
),
}, {
.machine = "qcom,sm6375",
- .rev = ADRENO_REV(6, 1, 9, ANY_ID),
+ .chip_ids = ADRENO_CHIP_IDS(0x06010900),
.family = ADRENO_6XX_GEN1,
.revn = 619,
.fw = {
@@ -335,7 +343,7 @@ static const struct adreno_info gpulist[] = {
177, 2
),
}, {
- .rev = ADRENO_REV(6, 1, 9, ANY_ID),
+ .chip_ids = ADRENO_CHIP_IDS(0x06010900),
.family = ADRENO_6XX_GEN1,
.revn = 619,
.fw = {
@@ -356,7 +364,7 @@ static const struct adreno_info gpulist[] = {
180, 1
),
}, {
- .rev = ADRENO_REV(6, 3, 0, ANY_ID),
+ .chip_ids = ADRENO_CHIP_IDS(0x06030002),
.family = ADRENO_6XX_GEN1,
.revn = 630,
.fw = {
@@ -370,7 +378,7 @@ static const struct adreno_info gpulist[] = {
.zapfw = "a630_zap.mdt",
.hwcg = a630_hwcg,
}, {
- .rev = ADRENO_REV(6, 4, 0, ANY_ID),
+ .chip_ids = ADRENO_CHIP_IDS(0x06040001),
.family = ADRENO_6XX_GEN2,
.revn = 640,
.fw = {
@@ -388,7 +396,7 @@ static const struct adreno_info gpulist[] = {
1, 1
),
}, {
- .rev = ADRENO_REV(6, 5, 0, ANY_ID),
+ .chip_ids = ADRENO_CHIP_IDS(0x06050002),
.family = ADRENO_6XX_GEN3,
.revn = 650,
.fw = {
@@ -410,7 +418,7 @@ static const struct adreno_info gpulist[] = {
3, 2
),
}, {
- .rev = ADRENO_REV(6, 6, 0, ANY_ID),
+ .chip_ids = ADRENO_CHIP_IDS(0x06060001),
.family = ADRENO_6XX_GEN4,
.revn = 660,
.fw = {
@@ -426,7 +434,7 @@ static const struct adreno_info gpulist[] = {
.hwcg = a660_hwcg,
.address_space_size = SZ_16G,
}, {
- .rev = ADRENO_REV(6, 3, 5, ANY_ID),
+ .chip_ids = ADRENO_CHIP_IDS(0x06030500),
.family = ADRENO_6XX_GEN4,
.fw = {
[ADRENO_FW_SQE] = "a660_sqe.fw",
@@ -445,7 +453,7 @@ static const struct adreno_info gpulist[] = {
190, 1
),
}, {
- .rev = ADRENO_REV(6, 8, 0, ANY_ID),
+ .chip_ids = ADRENO_CHIP_IDS(0x06080000),
.family = ADRENO_6XX_GEN2,
.revn = 680,
.fw = {
@@ -459,7 +467,7 @@ static const struct adreno_info gpulist[] = {
.zapfw = "a640_zap.mdt",
.hwcg = a640_hwcg,
}, {
- .rev = ADRENO_REV(6, 9, 0, ANY_ID),
+ .chip_ids = ADRENO_CHIP_IDS(0x06090000),
.family = ADRENO_6XX_GEN4,
.fw = {
[ADRENO_FW_SQE] = "a660_sqe.fw",
@@ -494,31 +502,16 @@ MODULE_FIRMWARE("qcom/a630_sqe.fw");
MODULE_FIRMWARE("qcom/a630_gmu.bin");
MODULE_FIRMWARE("qcom/a630_zap.mbn");
-static inline bool _rev_match(uint8_t entry, uint8_t id)
-{
- return (entry == ANY_ID) || (entry == id);
-}
-
-bool adreno_cmp_rev(struct adreno_rev rev1, struct adreno_rev rev2)
-{
-
- return _rev_match(rev1.core, rev2.core) &&
- _rev_match(rev1.major, rev2.major) &&
- _rev_match(rev1.minor, rev2.minor) &&
- _rev_match(rev1.patchid, rev2.patchid);
-}
-
-const struct adreno_info *adreno_info(struct adreno_rev rev)
+const struct adreno_info *adreno_find_info(uint32_t chip_id)
{
- int i;
-
/* identify gpu: */
- for (i = 0; i < ARRAY_SIZE(gpulist); i++) {
+ for (int i = 0; i < ARRAY_SIZE(gpulist); i++) {
const struct adreno_info *info = &gpulist[i];
if (info->machine && !of_machine_is_compatible(info->machine))
continue;
- if (adreno_cmp_rev(info->rev, rev))
- return info;
+ for (int j = 0; info->chip_ids[j]; j++)
+ if (info->chip_ids[j] == chip_id)
+ return info;
}
return NULL;
@@ -598,12 +591,11 @@ struct msm_gpu *adreno_load_gpu(struct drm_device *dev)
return NULL;
}
-static int find_chipid(struct device *dev, struct adreno_rev *rev)
+static int find_chipid(struct device *dev, uint32_t *chipid)
{
struct device_node *node = dev->of_node;
const char *compat;
int ret;
- u32 chipid;
/* first search the compat strings for qcom,adreno-XYZ.W: */
ret = of_property_read_string_index(node, "compatible", 0, &compat);
@@ -612,32 +604,34 @@ static int find_chipid(struct device *dev, struct adreno_rev *rev)
if (sscanf(compat, "qcom,adreno-%u.%u", &r, &patch) == 2 ||
sscanf(compat, "amd,imageon-%u.%u", &r, &patch) == 2) {
- rev->core = r / 100;
+ uint32_t core, major, minor;
+
+ core = r / 100;
r %= 100;
- rev->major = r / 10;
+ major = r / 10;
r %= 10;
- rev->minor = r;
- rev->patchid = patch;
+ minor = r;
+
+ *chipid = (core << 24) |
+ (major << 16) |
+ (minor << 8) |
+ patch;
return 0;
}
+
+ if (sscanf(compat, "qcom,adreno-%08x", chipid) == 1)
+ return 0;
}
/* and if that fails, fall back to legacy "qcom,chipid" property: */
- ret = of_property_read_u32(node, "qcom,chipid", &chipid);
+ ret = of_property_read_u32(node, "qcom,chipid", chipid);
if (ret) {
DRM_DEV_ERROR(dev, "could not parse qcom,chipid: %d\n", ret);
return ret;
}
- rev->core = (chipid >> 24) & 0xff;
- rev->major = (chipid >> 16) & 0xff;
- rev->minor = (chipid >> 8) & 0xff;
- rev->patchid = (chipid & 0xff);
-
dev_warn(dev, "Using legacy qcom,chipid binding!\n");
- dev_warn(dev, "Use compatible qcom,adreno-%u%u%u.%u instead.\n",
- rev->core, rev->major, rev->minor, rev->patchid);
return 0;
}
@@ -651,22 +645,22 @@ static int adreno_bind(struct device *dev, struct device *master, void *data)
struct msm_gpu *gpu;
int ret;
- ret = find_chipid(dev, &config.rev);
+ ret = find_chipid(dev, &config.chip_id);
if (ret)
return ret;
dev->platform_data = &config;
priv->gpu_pdev = to_platform_device(dev);
- info = adreno_info(config.rev);
+ info = adreno_find_info(config.chip_id);
if (!info) {
dev_warn(drm->dev, "Unknown GPU revision: %"ADRENO_CHIPID_FMT"\n",
- ADRENO_CHIPID_ARGS(config.rev));
+ ADRENO_CHIPID_ARGS(config.chip_id));
return -ENXIO;
}
- DBG("Found GPU: %"ADRENO_CHIPID_FMT, ADRENO_CHIPID_ARGS(config.rev));
+ DBG("Found GPU: %"ADRENO_CHIPID_FMT, ADRENO_CHIPID_ARGS(config.chip_id));
priv->is_a2xx = info->family < ADRENO_3XX;
priv->has_cached_coherent =
diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
index 1a982a926f21..1274609a74b1 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
@@ -326,10 +326,7 @@ int adreno_get_param(struct msm_gpu *gpu, struct msm_file_private *ctx,
*value = !adreno_is_a650_family(adreno_gpu) ? 0x100000 : 0;
return 0;
case MSM_PARAM_CHIP_ID:
- *value = (uint64_t)adreno_gpu->rev.patchid |
- ((uint64_t)adreno_gpu->rev.minor << 8) |
- ((uint64_t)adreno_gpu->rev.major << 16) |
- ((uint64_t)adreno_gpu->rev.core << 24);
+ *value = adreno_gpu->chip_id;
if (!adreno_gpu->info->revn)
*value |= ((uint64_t) adreno_gpu->speedbin) << 32;
return 0;
@@ -849,7 +846,7 @@ void adreno_show(struct msm_gpu *gpu, struct msm_gpu_state *state,
drm_printf(p, "revision: %u (%"ADRENO_CHIPID_FMT")\n",
adreno_gpu->info->revn,
- ADRENO_CHIPID_ARGS(adreno_gpu->rev));
+ ADRENO_CHIPID_ARGS(adreno_gpu->chip_id));
/*
* If this is state collected due to iova fault, so fault related info
*
@@ -922,7 +919,7 @@ void adreno_dump_info(struct msm_gpu *gpu)
printk("revision: %u (%"ADRENO_CHIPID_FMT")\n",
adreno_gpu->info->revn,
- ADRENO_CHIPID_ARGS(adreno_gpu->rev));
+ ADRENO_CHIPID_ARGS(adreno_gpu->chip_id));
for (i = 0; i < gpu->nr_rings; i++) {
struct msm_ringbuffer *ring = gpu->rb[i];
@@ -1072,14 +1069,13 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev,
struct adreno_platform_config *config = dev->platform_data;
struct msm_gpu_config adreno_gpu_config = { 0 };
struct msm_gpu *gpu = &adreno_gpu->base;
- struct adreno_rev *rev = &config->rev;
const char *gpu_name;
u32 speedbin;
int ret;
adreno_gpu->funcs = funcs;
- adreno_gpu->info = adreno_info(config->rev);
- adreno_gpu->rev = *rev;
+ adreno_gpu->info = adreno_find_info(config->chip_id);
+ adreno_gpu->chip_id = config->chip_id;
/* Only handle the core clock when GMU is not in use (or is absent). */
if (adreno_has_gmu_wrapper(adreno_gpu) ||
@@ -1104,7 +1100,7 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev,
adreno_gpu->speedbin = (uint16_t) (0xffff & speedbin);
gpu_name = devm_kasprintf(dev, GFP_KERNEL, "%"ADRENO_CHIPID_FMT,
- ADRENO_CHIPID_ARGS(config->rev));
+ ADRENO_CHIPID_ARGS(config->chip_id));
if (!gpu_name)
return -ENOMEM;
diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
index 73e7155f164c..18f53c7ab589 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
+++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
@@ -54,23 +54,15 @@ enum adreno_family {
#define ADRENO_QUIRK_HAS_HW_APRIV BIT(3)
#define ADRENO_QUIRK_HAS_CACHED_COHERENT BIT(4)
-struct adreno_rev {
- uint8_t core;
- uint8_t major;
- uint8_t minor;
- uint8_t patchid;
-};
-
-#define ANY_ID 0xff
-
-#define ADRENO_REV(core, major, minor, patchid) \
- ((struct adreno_rev){ core, major, minor, patchid })
-
/* Helper for formating the chip_id in the way that userspace tools like
* crashdec expect.
*/
#define ADRENO_CHIPID_FMT "u.%u.%u.%u"
-#define ADRENO_CHIPID_ARGS(_r) (_r).core, (_r).major, (_r).minor, (_r).patchid
+#define ADRENO_CHIPID_ARGS(_c) \
+ (((_c) >> 24) & 0xff), \
+ (((_c) >> 16) & 0xff), \
+ (((_c) >> 8) & 0xff), \
+ ((_c) & 0xff)
struct adreno_gpu_funcs {
struct msm_gpu_funcs base;
@@ -87,7 +79,12 @@ extern const struct adreno_reglist a660_hwcg[], a690_hwcg[];
struct adreno_info {
const char *machine;
- struct adreno_rev rev;
+ /**
+ * @chipids: Table of matching chip-ids
+ *
+ * Terminated with 0 sentinal
+ */
+ uint32_t *chip_ids;
enum adreno_family family;
uint32_t revn;
const char *fw[ADRENO_FW_MAX];
@@ -107,6 +104,8 @@ struct adreno_info {
uint32_t *speedbins;
};
+#define ADRENO_CHIP_IDS(tbl...) (uint32_t[]) { tbl, 0 }
+
/*
* Helper to build a speedbin table, ie. the table:
* fuse | speedbin
@@ -125,12 +124,12 @@ struct adreno_info {
*/
#define ADRENO_SPEEDBINS(tbl...) (uint32_t[]) { tbl, UINT_MAX }
-const struct adreno_info *adreno_info(struct adreno_rev rev);
+const struct adreno_info *adreno_find_info(uint32_t chip_id);
struct adreno_gpu {
struct msm_gpu base;
- struct adreno_rev rev;
const struct adreno_info *info;
+ uint32_t chip_id;
uint16_t speedbin;
const struct adreno_gpu_funcs *funcs;
@@ -179,7 +178,7 @@ struct adreno_ocmem {
/* platform config data (ie. from DT, or pdata) */
struct adreno_platform_config {
- struct adreno_rev rev;
+ uint32_t chip_id;
};
#define ADRENO_IDLE_TIMEOUT msecs_to_jiffies(1000)
@@ -196,7 +195,15 @@ struct adreno_platform_config {
__ret; \
})
-bool adreno_cmp_rev(struct adreno_rev rev1, struct adreno_rev rev2);
+static inline uint8_t adreno_patchid(const struct adreno_gpu *gpu)
+{
+ /* It is probably ok to assume legacy "adreno_rev" format
+ * for all a6xx devices, but probably best to limit this
+ * to older things.
+ */
+ WARN_ON_ONCE(gpu->info->family >= ADRENO_6XX_GEN1);
+ return gpu->chip_id & 0xff;
+}
static inline bool adreno_is_revn(const struct adreno_gpu *gpu, uint32_t revn)
{
@@ -252,7 +259,7 @@ static inline bool adreno_is_a330(const struct adreno_gpu *gpu)
static inline bool adreno_is_a330v2(const struct adreno_gpu *gpu)
{
- return adreno_is_a330(gpu) && (gpu->rev.patchid > 0);
+ return adreno_is_a330(gpu) && (adreno_patchid(gpu) > 0);
}
static inline int adreno_is_a405(const struct adreno_gpu *gpu)
@@ -342,8 +349,7 @@ static inline int adreno_is_a650(const struct adreno_gpu *gpu)
static inline int adreno_is_7c3(const struct adreno_gpu *gpu)
{
- /* The order of args is important here to handle ANY_ID correctly */
- return adreno_cmp_rev(ADRENO_REV(6, 3, 5, ANY_ID), gpu->rev);
+ return gpu->info->chip_ids[0] == 0x06030500;
}
static inline int adreno_is_a660(const struct adreno_gpu *gpu)
@@ -358,8 +364,7 @@ static inline int adreno_is_a680(const struct adreno_gpu *gpu)
static inline int adreno_is_a690(const struct adreno_gpu *gpu)
{
- /* The order of args is important here to handle ANY_ID correctly */
- return adreno_cmp_rev(ADRENO_REV(6, 9, 0, ANY_ID), gpu->rev);
+ return gpu->info->chip_ids[0] == 0x06090000;
};
/* check for a615, a616, a618, a619 or any a630 derivatives */
static inline int adreno_is_a630_family(const struct adreno_gpu *gpu)
--
2.41.0
^ permalink raw reply related [flat|nested] 73+ messages in thread
* Re: [PATCH 01/12] drm/msm/adreno: Remove GPU name
2023-07-06 21:10 ` [PATCH 01/12] drm/msm/adreno: Remove GPU name Rob Clark
@ 2023-07-06 23:21 ` Konrad Dybcio
2023-07-07 0:04 ` [Freedreno] " Dmitry Baryshkov
1 sibling, 0 replies; 73+ messages in thread
From: Konrad Dybcio @ 2023-07-06 23:21 UTC (permalink / raw)
To: Rob Clark, dri-devel; +Cc: Rob Clark, linux-arm-msm, freedreno
On 6.07.2023 23:10, Rob Clark wrote:
> From: Rob Clark <robdclark@chromium.org>
>
> No real need to have marketing names in the kernel.
>
> Signed-off-by: Rob Clark <robdclark@chromium.org>
> ---
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
[...]
> - gpu_name = adreno_gpu->info->name;
> - if (!gpu_name) {
> - gpu_name = devm_kasprintf(dev, GFP_KERNEL, "%d.%d.%d.%d",
> - rev->core, rev->major, rev->minor,
> - rev->patchid);
> - if (!gpu_name)
> - return -ENOMEM;
> - }
> + gpu_name = devm_kasprintf(dev, GFP_KERNEL, "%d.%d.%d.%d",
> + rev->core, rev->major, rev->minor,
> + rev->patchid);
nit: great opportunity to align indentation with the opening brace
Konrad
> + if (!gpu_name)
> + return -ENOMEM;
>
> adreno_gpu_config.ioname = "kgsl_3d0_reg_memory";
>
> diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> index cf45007400c8..6830c3776c2d 100644
> --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> @@ -61,7 +61,6 @@ extern const struct adreno_reglist a660_hwcg[], a690_hwcg[];
> struct adreno_info {
> struct adreno_rev rev;
> uint32_t revn;
> - const char *name;
> const char *fw[ADRENO_FW_MAX];
> uint32_t gmem;
> u64 quirks;
^ permalink raw reply [flat|nested] 73+ messages in thread
* Re: [PATCH 02/12] drm/msm/adreno: Remove redundant gmem size param
2023-07-06 21:10 ` [PATCH 02/12] drm/msm/adreno: Remove redundant gmem size param Rob Clark
@ 2023-07-06 23:22 ` Konrad Dybcio
2023-07-13 19:46 ` Akhil P Oommen
2023-07-07 2:23 ` [Freedreno] " Dmitry Baryshkov
1 sibling, 1 reply; 73+ messages in thread
From: Konrad Dybcio @ 2023-07-06 23:22 UTC (permalink / raw)
To: Rob Clark, dri-devel; +Cc: Rob Clark, linux-arm-msm, freedreno
On 6.07.2023 23:10, Rob Clark wrote:
> From: Rob Clark <robdclark@chromium.org>
>
> Even in the ocmem case, the allocated ocmem buffer size should match the
> requested size.
>
> Signed-off-by: Rob Clark <robdclark@chromium.org>
> ---
[...]
> +
> + WARN_ON(ocmem_hdl->len != adreno_gpu->info->gmem);
I believe this should be an error condition. If the sizes are mismatched,
best case scenario you get suboptimal perf and worst case scenario your
system explodes.
Very nice cleanup though!
Konrad
>
> return 0;
> }
> @@ -1097,7 +1098,6 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev,
>
> adreno_gpu->funcs = funcs;
> adreno_gpu->info = adreno_info(config->rev);
> - adreno_gpu->gmem = adreno_gpu->info->gmem;
> adreno_gpu->revn = adreno_gpu->info->revn;
> adreno_gpu->rev = *rev;
>
> diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> index 6830c3776c2d..aaf09c642dc6 100644
> --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> @@ -77,7 +77,6 @@ struct adreno_gpu {
> struct msm_gpu base;
> struct adreno_rev rev;
> const struct adreno_info *info;
> - uint32_t gmem; /* actual gmem size */
> uint32_t revn; /* numeric revision name */
> uint16_t speedbin;
> const struct adreno_gpu_funcs *funcs;
^ permalink raw reply [flat|nested] 73+ messages in thread
* Re: [PATCH 03/12] drm/msm/adreno: Remove redundant revn param
2023-07-06 21:10 ` [PATCH 03/12] drm/msm/adreno: Remove redundant revn param Rob Clark
@ 2023-07-06 23:26 ` Konrad Dybcio
2023-07-07 2:24 ` [Freedreno] " Dmitry Baryshkov
1 sibling, 0 replies; 73+ messages in thread
From: Konrad Dybcio @ 2023-07-06 23:26 UTC (permalink / raw)
To: Rob Clark, dri-devel; +Cc: Rob Clark, linux-arm-msm, freedreno
On 6.07.2023 23:10, Rob Clark wrote:
> From: Rob Clark <robdclark@chromium.org>
>
> This just duplicates what is in adreno_info, and can cause confusion if
> used before it is set.
>
> Signed-off-by: Rob Clark <robdclark@chromium.org>
> ---
[...]
> - return gpu->revn == revn;
> + if (WARN_ON_ONCE(!gpu->info))
> + return false;
I'm unsure about changing this behavior. Especially in a6xx code,
where these calls may guard things like SMMU behavior (the LLCC-SMMU
programming dance is unconditional if adreno_is_a7xx)
Though if gpu->info is missing, it's a lost cause anwyways..
So I guess this is really the least bad thing to do
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Konrad
> + return gpu->info->revn == revn;
> }
>
> static inline bool adreno_has_gmu_wrapper(const struct adreno_gpu *gpu)
> @@ -160,18 +158,16 @@ static inline bool adreno_has_gmu_wrapper(const struct adreno_gpu *gpu)
>
> static inline bool adreno_is_a2xx(const struct adreno_gpu *gpu)
> {
> - /* revn can be zero, but if not is set at same time as info */
> - WARN_ON_ONCE(!gpu->info);
> -
> - return (gpu->revn < 300);
> + if (WARN_ON_ONCE(!gpu->info))
> + return false;
> + return (gpu->info->revn < 300);
> }
>
> static inline bool adreno_is_a20x(const struct adreno_gpu *gpu)
> {
> - /* revn can be zero, but if not is set at same time as info */
> - WARN_ON_ONCE(!gpu->info);
> -
> - return (gpu->revn < 210);
> + if (WARN_ON_ONCE(!gpu->info))
> + return false;
> + return (gpu->info->revn < 210);
> }
>
> static inline bool adreno_is_a225(const struct adreno_gpu *gpu)
^ permalink raw reply [flat|nested] 73+ messages in thread
* Re: [PATCH 04/12] drm/msm/adreno: Use quirk identify hw_apriv
2023-07-06 21:10 ` [PATCH 04/12] drm/msm/adreno: Use quirk identify hw_apriv Rob Clark
@ 2023-07-06 23:27 ` Konrad Dybcio
2023-07-07 2:25 ` [Freedreno] " Dmitry Baryshkov
1 sibling, 0 replies; 73+ messages in thread
From: Konrad Dybcio @ 2023-07-06 23:27 UTC (permalink / raw)
To: Rob Clark, dri-devel; +Cc: Rob Clark, linux-arm-msm, freedreno
On 6.07.2023 23:10, Rob Clark wrote:
> From: Rob Clark <robdclark@chromium.org>
>
> Rather than just open coding a list of gpu-id matches.
>
> Signed-off-by: Rob Clark <robdclark@chromium.org>
> ---
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Konrad
> drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 3 +--
> drivers/gpu/drm/msm/adreno/adreno_device.c | 4 ++++
> drivers/gpu/drm/msm/adreno/adreno_gpu.h | 1 +
> 3 files changed, 6 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> index 5ba8b5aca502..6f8c4381fa4a 100644
> --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> @@ -2489,8 +2489,7 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev)
> /* Quirk data */
> adreno_gpu->info = info;
>
> - if (adreno_is_a650(adreno_gpu) || adreno_is_a660_family(adreno_gpu))
> - adreno_gpu->base.hw_apriv = true;
> + adreno_gpu->base.hw_apriv = !!(info->quirks & ADRENO_QUIRK_HAS_HW_APRIV);
>
> a6xx_llc_slices_init(pdev, a6xx_gpu);
>
> diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c
> index 326912284a95..f469f951a907 100644
> --- a/drivers/gpu/drm/msm/adreno/adreno_device.c
> +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c
> @@ -302,6 +302,7 @@ static const struct adreno_info gpulist[] = {
> },
> .gmem = SZ_1M + SZ_128K,
> .inactive_period = DRM_MSM_INACTIVE_PERIOD,
> + .quirks = ADRENO_QUIRK_HAS_HW_APRIV,
> .init = a6xx_gpu_init,
> .zapfw = "a650_zap.mdt",
> .hwcg = a650_hwcg,
> @@ -315,6 +316,7 @@ static const struct adreno_info gpulist[] = {
> },
> .gmem = SZ_1M + SZ_512K,
> .inactive_period = DRM_MSM_INACTIVE_PERIOD,
> + .quirks = ADRENO_QUIRK_HAS_HW_APRIV,
> .init = a6xx_gpu_init,
> .zapfw = "a660_zap.mdt",
> .hwcg = a660_hwcg,
> @@ -327,6 +329,7 @@ static const struct adreno_info gpulist[] = {
> },
> .gmem = SZ_512K,
> .inactive_period = DRM_MSM_INACTIVE_PERIOD,
> + .quirks = ADRENO_QUIRK_HAS_HW_APRIV,
> .init = a6xx_gpu_init,
> .hwcg = a660_hwcg,
> .address_space_size = SZ_16G,
> @@ -350,6 +353,7 @@ static const struct adreno_info gpulist[] = {
> },
> .gmem = SZ_4M,
> .inactive_period = DRM_MSM_INACTIVE_PERIOD,
> + .quirks = ADRENO_QUIRK_HAS_HW_APRIV,
> .init = a6xx_gpu_init,
> .zapfw = "a690_zap.mdt",
> .hwcg = a690_hwcg,
> diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> index d31e2d37c61b..a7c4a2c536e3 100644
> --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> @@ -32,6 +32,7 @@ enum {
> #define ADRENO_QUIRK_TWO_PASS_USE_WFI BIT(0)
> #define ADRENO_QUIRK_FAULT_DETECT_MASK BIT(1)
> #define ADRENO_QUIRK_LMLOADKILL_DISABLE BIT(2)
> +#define ADRENO_QUIRK_HAS_HW_APRIV BIT(3)
>
> struct adreno_rev {
> uint8_t core;
^ permalink raw reply [flat|nested] 73+ messages in thread
* Re: [PATCH 05/12] drm/msm/adreno: Use quirk to identify cached-coherent support
2023-07-06 21:10 ` [PATCH 05/12] drm/msm/adreno: Use quirk to identify cached-coherent support Rob Clark
@ 2023-07-06 23:29 ` Konrad Dybcio
2023-07-07 2:29 ` [Freedreno] " Dmitry Baryshkov
2023-07-13 20:05 ` Akhil P Oommen
2 siblings, 0 replies; 73+ messages in thread
From: Konrad Dybcio @ 2023-07-06 23:29 UTC (permalink / raw)
To: Rob Clark, dri-devel; +Cc: Rob Clark, linux-arm-msm, freedreno
On 6.07.2023 23:10, Rob Clark wrote:
> From: Rob Clark <robdclark@chromium.org>
>
> It is better to explicitly list it. With the move to opaque chip-id's
> for future devices, we should avoid trying to infer things like
> generation from the numerical value.
>
> Signed-off-by: Rob Clark <robdclark@chromium.org>
> ---
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Konrad
> drivers/gpu/drm/msm/adreno/adreno_device.c | 23 +++++++++++++++-------
> drivers/gpu/drm/msm/adreno/adreno_gpu.h | 1 +
> 2 files changed, 17 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c
> index f469f951a907..3c531da417b9 100644
> --- a/drivers/gpu/drm/msm/adreno/adreno_device.c
> +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c
> @@ -256,6 +256,7 @@ static const struct adreno_info gpulist[] = {
> },
> .gmem = SZ_512K,
> .inactive_period = DRM_MSM_INACTIVE_PERIOD,
> + .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT,
> .init = a6xx_gpu_init,
> }, {
> .rev = ADRENO_REV(6, 1, 9, ANY_ID),
> @@ -266,6 +267,7 @@ static const struct adreno_info gpulist[] = {
> },
> .gmem = SZ_512K,
> .inactive_period = DRM_MSM_INACTIVE_PERIOD,
> + .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT,
> .init = a6xx_gpu_init,
> .zapfw = "a615_zap.mdt",
> .hwcg = a615_hwcg,
> @@ -278,6 +280,7 @@ static const struct adreno_info gpulist[] = {
> },
> .gmem = SZ_1M,
> .inactive_period = DRM_MSM_INACTIVE_PERIOD,
> + .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT,
> .init = a6xx_gpu_init,
> .zapfw = "a630_zap.mdt",
> .hwcg = a630_hwcg,
> @@ -290,6 +293,7 @@ static const struct adreno_info gpulist[] = {
> },
> .gmem = SZ_1M,
> .inactive_period = DRM_MSM_INACTIVE_PERIOD,
> + .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT,
> .init = a6xx_gpu_init,
> .zapfw = "a640_zap.mdt",
> .hwcg = a640_hwcg,
> @@ -302,7 +306,8 @@ static const struct adreno_info gpulist[] = {
> },
> .gmem = SZ_1M + SZ_128K,
> .inactive_period = DRM_MSM_INACTIVE_PERIOD,
> - .quirks = ADRENO_QUIRK_HAS_HW_APRIV,
> + .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |
> + ADRENO_QUIRK_HAS_HW_APRIV,
> .init = a6xx_gpu_init,
> .zapfw = "a650_zap.mdt",
> .hwcg = a650_hwcg,
> @@ -316,7 +321,8 @@ static const struct adreno_info gpulist[] = {
> },
> .gmem = SZ_1M + SZ_512K,
> .inactive_period = DRM_MSM_INACTIVE_PERIOD,
> - .quirks = ADRENO_QUIRK_HAS_HW_APRIV,
> + .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |
> + ADRENO_QUIRK_HAS_HW_APRIV,
> .init = a6xx_gpu_init,
> .zapfw = "a660_zap.mdt",
> .hwcg = a660_hwcg,
> @@ -329,7 +335,8 @@ static const struct adreno_info gpulist[] = {
> },
> .gmem = SZ_512K,
> .inactive_period = DRM_MSM_INACTIVE_PERIOD,
> - .quirks = ADRENO_QUIRK_HAS_HW_APRIV,
> + .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |
> + ADRENO_QUIRK_HAS_HW_APRIV,
> .init = a6xx_gpu_init,
> .hwcg = a660_hwcg,
> .address_space_size = SZ_16G,
> @@ -342,6 +349,7 @@ static const struct adreno_info gpulist[] = {
> },
> .gmem = SZ_2M,
> .inactive_period = DRM_MSM_INACTIVE_PERIOD,
> + .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT,
> .init = a6xx_gpu_init,
> .zapfw = "a640_zap.mdt",
> .hwcg = a640_hwcg,
> @@ -353,7 +361,8 @@ static const struct adreno_info gpulist[] = {
> },
> .gmem = SZ_4M,
> .inactive_period = DRM_MSM_INACTIVE_PERIOD,
> - .quirks = ADRENO_QUIRK_HAS_HW_APRIV,
> + .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |
> + ADRENO_QUIRK_HAS_HW_APRIV,
> .init = a6xx_gpu_init,
> .zapfw = "a690_zap.mdt",
> .hwcg = a690_hwcg,
> @@ -565,9 +574,9 @@ static int adreno_bind(struct device *dev, struct device *master, void *data)
> if (ret)
> return ret;
>
> - if (config.rev.core >= 6)
> - if (!adreno_has_gmu_wrapper(to_adreno_gpu(gpu)))
> - priv->has_cached_coherent = true;
> + priv->has_cached_coherent =
> + !!(info->quirks & ADRENO_QUIRK_HAS_CACHED_COHERENT) &&
> + !adreno_has_gmu_wrapper(to_adreno_gpu(gpu));
>
> return 0;
> }
> diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> index a7c4a2c536e3..e08d41337169 100644
> --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> @@ -33,6 +33,7 @@ enum {
> #define ADRENO_QUIRK_FAULT_DETECT_MASK BIT(1)
> #define ADRENO_QUIRK_LMLOADKILL_DISABLE BIT(2)
> #define ADRENO_QUIRK_HAS_HW_APRIV BIT(3)
> +#define ADRENO_QUIRK_HAS_CACHED_COHERENT BIT(4)
>
> struct adreno_rev {
> uint8_t core;
^ permalink raw reply [flat|nested] 73+ messages in thread
* Re: [PATCH 08/12] drm/msm/adreno: Bring the a630 family together
2023-07-06 21:10 ` [PATCH 08/12] drm/msm/adreno: Bring the a630 family together Rob Clark
@ 2023-07-06 23:32 ` Konrad Dybcio
0 siblings, 0 replies; 73+ messages in thread
From: Konrad Dybcio @ 2023-07-06 23:32 UTC (permalink / raw)
To: Rob Clark, dri-devel; +Cc: Rob Clark, linux-arm-msm, freedreno
On 6.07.2023 23:10, Rob Clark wrote:
> From: Rob Clark <robdclark@chromium.org>
>
> All of these are derivatives of a630.
>
> Signed-off-by: Rob Clark <robdclark@chromium.org>
> ---
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Konrad
> drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 2 +-
> drivers/gpu/drm/msm/adreno/adreno_gpu.h | 7 ++++---
> 2 files changed, 5 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
> index 5deb79924897..f1bb20574018 100644
> --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
> @@ -1617,7 +1617,7 @@ int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node)
> SZ_256K - SZ_16K, 0x44000, "dcache");
> if (ret)
> goto err_memory;
> - } else if (adreno_is_a630(adreno_gpu) || adreno_is_a615_family(adreno_gpu)) {
> + } else if (adreno_is_a630_family(adreno_gpu)) {
> /* HFI v1, has sptprac */
> gmu->legacy = true;
>
> diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> index 994ac26ce731..6066cfaaea52 100644
> --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> @@ -335,10 +335,11 @@ static inline int adreno_is_a690(const struct adreno_gpu *gpu)
> /* The order of args is important here to handle ANY_ID correctly */
> return adreno_cmp_rev(ADRENO_REV(6, 9, 0, ANY_ID), gpu->rev);
> };
> -/* check for a615, a616, a618, a619 or any derivatives */
> -static inline int adreno_is_a615_family(const struct adreno_gpu *gpu)
> +/* check for a615, a616, a618, a619 or any a630 derivatives */
> +static inline int adreno_is_a630_family(const struct adreno_gpu *gpu)
> {
> - return adreno_is_revn(gpu, 615) ||
> + return adreno_is_revn(gpu, 630) ||
> + adreno_is_revn(gpu, 615) ||
> adreno_is_revn(gpu, 616) ||
> adreno_is_revn(gpu, 618) ||
> adreno_is_revn(gpu, 619);
^ permalink raw reply [flat|nested] 73+ messages in thread
* Re: [PATCH 09/12] drm/msm/adreno: Add adreno family
2023-07-06 21:10 ` [PATCH 09/12] drm/msm/adreno: Add adreno family Rob Clark
@ 2023-07-06 23:35 ` Konrad Dybcio
2023-07-07 3:16 ` Dmitry Baryshkov
2023-07-07 2:49 ` [Freedreno] " Dmitry Baryshkov
1 sibling, 1 reply; 73+ messages in thread
From: Konrad Dybcio @ 2023-07-06 23:35 UTC (permalink / raw)
To: Rob Clark, dri-devel; +Cc: Rob Clark, linux-arm-msm, freedreno
On 6.07.2023 23:10, Rob Clark wrote:
> From: Rob Clark <robdclark@chromium.org>
>
> Sometimes it is useful to know the sub-generation (or "family"). And in
> any case, this helps us get away from infering the generation from the
> numerical chip-id.
>
> Signed-off-by: Rob Clark <robdclark@chromium.org>
> ---
[...]
> .rev = ADRENO_REV(5, 0, 8, ANY_ID),
> + .family = ADRENO_5XX,
> .revn = 508,
508 is from 530 fam
> .fw = {
> [ADRENO_FW_PM4] = "a530_pm4.fw",
> @@ -156,6 +168,7 @@ static const struct adreno_info gpulist[] = {
> .zapfw = "a508_zap.mdt",
> }, {
> .rev = ADRENO_REV(5, 0, 9, ANY_ID),
> + .family = ADRENO_5XX,
> .revn = 509,
509 and 512 are from 540 fam
> .fw = {
> [ADRENO_FW_PM4] = "a530_pm4.fw",
> @@ -173,6 +186,7 @@ static const struct adreno_info gpulist[] = {
> .zapfw = "a512_zap.mdt",
> }, {
> .rev = ADRENO_REV(5, 1, 0, ANY_ID),
> + .family = ADRENO_5XX,
> .revn = 510,
510 is 530ish but I think it's closer to 505 or whatever the
8953 gpu was called
[...]
> - priv->is_a2xx = config.rev.core == 2;
> + priv->is_a2xx = info->family < ADRENO_3XX;
is this variable even needed now that there are explicit family values?
Konrad
> priv->has_cached_coherent =
> !!(info->quirks & ADRENO_QUIRK_HAS_CACHED_COHERENT);
>
> diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
> index 2e62a7ce9f13..75ff7fb46099 100644
> --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c
> +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
> @@ -1079,8 +1079,13 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev,
> u32 speedbin;
> int ret;
>
> + adreno_gpu->funcs = funcs;
> + adreno_gpu->info = adreno_info(config->rev);
> + adreno_gpu->rev = *rev;
> +
> /* Only handle the core clock when GMU is not in use (or is absent). */
> - if (adreno_has_gmu_wrapper(adreno_gpu) || config->rev.core < 6) {
> + if (adreno_has_gmu_wrapper(adreno_gpu) ||
> + adreno_gpu->info->family < ADRENO_6XX_GEN1) {
> /*
> * This can only be done before devm_pm_opp_of_add_table(), or
> * dev_pm_opp_set_config() will WARN_ON()
> @@ -1096,10 +1101,6 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev,
> devm_pm_opp_set_clkname(dev, "core");
> }
>
> - adreno_gpu->funcs = funcs;
> - adreno_gpu->info = adreno_info(config->rev);
> - adreno_gpu->rev = *rev;
> -
> if (adreno_read_speedbin(dev, &speedbin) || !speedbin)
> speedbin = 0xffff;
> adreno_gpu->speedbin = (uint16_t) (0xffff & speedbin);
> diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> index 6066cfaaea52..2fa14dcd4e40 100644
> --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> @@ -29,6 +29,25 @@ enum {
> ADRENO_FW_MAX,
> };
>
> +/**
> + * @enum adreno_family: identify generation and possibly sub-generation
> + *
> + * In some cases there are distinct sub-generations within a major revision
> + * so it helps to be able to group the GPU devices by generation and if
> + * necessary sub-generation.
> + */
> +enum adreno_family {
> + ADRENO_2XX_GEN1, /* a20x */
> + ADRENO_2XX_GEN2, /* a22x */
> + ADRENO_3XX,
> + ADRENO_4XX,
> + ADRENO_5XX,
> + ADRENO_6XX_GEN1, /* a630 family */
> + ADRENO_6XX_GEN2, /* a640 family */
> + ADRENO_6XX_GEN3, /* a650 family */
> + ADRENO_6XX_GEN4, /* a660 family */
> +};
> +
> #define ADRENO_QUIRK_TWO_PASS_USE_WFI BIT(0)
> #define ADRENO_QUIRK_FAULT_DETECT_MASK BIT(1)
> #define ADRENO_QUIRK_LMLOADKILL_DISABLE BIT(2)
> @@ -63,6 +82,7 @@ extern const struct adreno_reglist a660_hwcg[], a690_hwcg[];
> struct adreno_info {
> const char *machine;
> struct adreno_rev rev;
> + enum adreno_family family;
> uint32_t revn;
> const char *fw[ADRENO_FW_MAX];
> uint32_t gmem;
> @@ -188,14 +208,14 @@ static inline bool adreno_is_a2xx(const struct adreno_gpu *gpu)
> {
> if (WARN_ON_ONCE(!gpu->info))
> return false;
> - return (gpu->info->revn < 300);
> + return gpu->info->family < ADRENO_2XX_GEN2;
> }
>
> static inline bool adreno_is_a20x(const struct adreno_gpu *gpu)
> {
> if (WARN_ON_ONCE(!gpu->info))
> return false;
> - return (gpu->info->revn < 210);
> + return gpu->info->family == ADRENO_2XX_GEN1;
> }
>
> static inline bool adreno_is_a225(const struct adreno_gpu *gpu)
> @@ -338,29 +358,31 @@ static inline int adreno_is_a690(const struct adreno_gpu *gpu)
> /* check for a615, a616, a618, a619 or any a630 derivatives */
> static inline int adreno_is_a630_family(const struct adreno_gpu *gpu)
> {
> - return adreno_is_revn(gpu, 630) ||
> - adreno_is_revn(gpu, 615) ||
> - adreno_is_revn(gpu, 616) ||
> - adreno_is_revn(gpu, 618) ||
> - adreno_is_revn(gpu, 619);
> + if (WARN_ON_ONCE(!gpu->info))
> + return false;
> + return gpu->info->family == ADRENO_6XX_GEN1;
> }
>
> static inline int adreno_is_a660_family(const struct adreno_gpu *gpu)
> {
> - return adreno_is_a660(gpu) || adreno_is_a690(gpu) || adreno_is_7c3(gpu);
> + if (WARN_ON_ONCE(!gpu->info))
> + return false;
> + return gpu->info->family == ADRENO_6XX_GEN4;
> }
>
> /* check for a650, a660, or any derivatives */
> static inline int adreno_is_a650_family(const struct adreno_gpu *gpu)
> {
> - return adreno_is_revn(gpu, 650) ||
> - adreno_is_revn(gpu, 620) ||
> - adreno_is_a660_family(gpu);
> + if (WARN_ON_ONCE(!gpu->info))
> + return false;
> + return gpu->info->family >= ADRENO_6XX_GEN3;
> }
>
> static inline int adreno_is_a640_family(const struct adreno_gpu *gpu)
> {
> - return adreno_is_a640(gpu) || adreno_is_a680(gpu);
> + if (WARN_ON_ONCE(!gpu->info))
> + return false;
> + return gpu->info->family == ADRENO_6XX_GEN2;
> }
>
> u64 adreno_private_address_space_size(struct msm_gpu *gpu);
^ permalink raw reply [flat|nested] 73+ messages in thread
* Re: [PATCH 10/12] drm/msm/adreno: Add helper for formating chip-id
2023-07-06 21:10 ` [PATCH 10/12] drm/msm/adreno: Add helper for formating chip-id Rob Clark
@ 2023-07-06 23:36 ` Konrad Dybcio
2023-07-10 20:21 ` Rob Clark
2023-07-07 2:50 ` [Freedreno] " Dmitry Baryshkov
1 sibling, 1 reply; 73+ messages in thread
From: Konrad Dybcio @ 2023-07-06 23:36 UTC (permalink / raw)
To: Rob Clark, dri-devel; +Cc: Rob Clark, linux-arm-msm, freedreno
On 6.07.2023 23:10, Rob Clark wrote:
> From: Rob Clark <robdclark@chromium.org>
>
> This is used in a few places, including one that is parsed by userspace
> tools. So let's standardize it a bit better.
>
> Signed-off-by: Rob Clark <robdclark@chromium.org>
> ---
Userspace parsed this weird string instead of the hex-based chipid?
weird^2
Konrad
> drivers/gpu/drm/msm/adreno/adreno_device.c | 8 +++-----
> drivers/gpu/drm/msm/adreno/adreno_gpu.c | 19 ++++++++-----------
> drivers/gpu/drm/msm/adreno/adreno_gpu.h | 6 ++++++
> 3 files changed, 17 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c
> index dcd6363ac7b0..fd2e183bce60 100644
> --- a/drivers/gpu/drm/msm/adreno/adreno_device.c
> +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c
> @@ -661,14 +661,12 @@ static int adreno_bind(struct device *dev, struct device *master, void *data)
> info = adreno_info(config.rev);
>
> if (!info) {
> - dev_warn(drm->dev, "Unknown GPU revision: %u.%u.%u.%u\n",
> - config.rev.core, config.rev.major,
> - config.rev.minor, config.rev.patchid);
> + dev_warn(drm->dev, "Unknown GPU revision: %"ADRENO_CHIPID_FMT"\n",
> + ADRENO_CHIPID_ARGS(config.rev));
> return -ENXIO;
> }
>
> - DBG("Found GPU: %u.%u.%u.%u", config.rev.core, config.rev.major,
> - config.rev.minor, config.rev.patchid);
> + DBG("Found GPU: %"ADRENO_CHIPID_FMT, ADRENO_CHIPID_ARGS(config.rev));
>
> priv->is_a2xx = info->family < ADRENO_3XX;
> priv->has_cached_coherent =
> diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
> index 75ff7fb46099..1a982a926f21 100644
> --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c
> +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
> @@ -847,10 +847,9 @@ void adreno_show(struct msm_gpu *gpu, struct msm_gpu_state *state,
> if (IS_ERR_OR_NULL(state))
> return;
>
> - drm_printf(p, "revision: %d (%d.%d.%d.%d)\n",
> - adreno_gpu->info->revn, adreno_gpu->rev.core,
> - adreno_gpu->rev.major, adreno_gpu->rev.minor,
> - adreno_gpu->rev.patchid);
> + drm_printf(p, "revision: %u (%"ADRENO_CHIPID_FMT")\n",
> + adreno_gpu->info->revn,
> + ADRENO_CHIPID_ARGS(adreno_gpu->rev));
> /*
> * If this is state collected due to iova fault, so fault related info
> *
> @@ -921,10 +920,9 @@ void adreno_dump_info(struct msm_gpu *gpu)
> struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
> int i;
>
> - printk("revision: %d (%d.%d.%d.%d)\n",
> - adreno_gpu->info->revn, adreno_gpu->rev.core,
> - adreno_gpu->rev.major, adreno_gpu->rev.minor,
> - adreno_gpu->rev.patchid);
> + printk("revision: %u (%"ADRENO_CHIPID_FMT")\n",
> + adreno_gpu->info->revn,
> + ADRENO_CHIPID_ARGS(adreno_gpu->rev));
>
> for (i = 0; i < gpu->nr_rings; i++) {
> struct msm_ringbuffer *ring = gpu->rb[i];
> @@ -1105,9 +1103,8 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev,
> speedbin = 0xffff;
> adreno_gpu->speedbin = (uint16_t) (0xffff & speedbin);
>
> - gpu_name = devm_kasprintf(dev, GFP_KERNEL, "%d.%d.%d.%d",
> - rev->core, rev->major, rev->minor,
> - rev->patchid);
> + gpu_name = devm_kasprintf(dev, GFP_KERNEL, "%"ADRENO_CHIPID_FMT,
> + ADRENO_CHIPID_ARGS(config->rev));
> if (!gpu_name)
> return -ENOMEM;
>
> diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> index 2fa14dcd4e40..73e7155f164c 100644
> --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> @@ -66,6 +66,12 @@ struct adreno_rev {
> #define ADRENO_REV(core, major, minor, patchid) \
> ((struct adreno_rev){ core, major, minor, patchid })
>
> +/* Helper for formating the chip_id in the way that userspace tools like
> + * crashdec expect.
> + */
> +#define ADRENO_CHIPID_FMT "u.%u.%u.%u"
> +#define ADRENO_CHIPID_ARGS(_r) (_r).core, (_r).major, (_r).minor, (_r).patchid
> +
> struct adreno_gpu_funcs {
> struct msm_gpu_funcs base;
> int (*get_timestamp)(struct msm_gpu *gpu, uint64_t *value);
^ permalink raw reply [flat|nested] 73+ messages in thread
* Re: [Freedreno] [PATCH 01/12] drm/msm/adreno: Remove GPU name
2023-07-06 21:10 ` [PATCH 01/12] drm/msm/adreno: Remove GPU name Rob Clark
2023-07-06 23:21 ` Konrad Dybcio
@ 2023-07-07 0:04 ` Dmitry Baryshkov
1 sibling, 0 replies; 73+ messages in thread
From: Dmitry Baryshkov @ 2023-07-07 0:04 UTC (permalink / raw)
To: Rob Clark, dri-devel; +Cc: Konrad Dybcio, linux-arm-msm, Rob Clark, freedreno
On 07/07/2023 00:10, Rob Clark wrote:
> From: Rob Clark <robdclark@chromium.org>
>
> No real need to have marketing names in the kernel.
>
> Signed-off-by: Rob Clark <robdclark@chromium.org>
> ---
> drivers/gpu/drm/msm/adreno/adreno_device.c | 24 ----------------------
> drivers/gpu/drm/msm/adreno/adreno_gpu.c | 13 +++++-------
> drivers/gpu/drm/msm/adreno/adreno_gpu.h | 1 -
> 3 files changed, 5 insertions(+), 33 deletions(-)
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 73+ messages in thread
* Re: [PATCH 12/12] drm/msm/adreno: Switch to chip-id for identifying GPU
2023-07-06 21:10 ` [PATCH 12/12] drm/msm/adreno: Switch to chip-id for identifying GPU Rob Clark
@ 2023-07-07 0:25 ` Konrad Dybcio
2023-07-07 16:08 ` Rob Clark
2023-07-07 3:45 ` [Freedreno] " Dmitry Baryshkov
1 sibling, 1 reply; 73+ messages in thread
From: Konrad Dybcio @ 2023-07-07 0:25 UTC (permalink / raw)
To: Rob Clark, dri-devel; +Cc: Rob Clark, linux-arm-msm, freedreno
On 6.07.2023 23:10, Rob Clark wrote:
> From: Rob Clark <robdclark@chromium.org>
>
> Since the revision becomes an opaque identifier with future GPUs, move
> away from treating different ranges of bits as having a given meaning.
> This means that we need to explicitly list different patch revisions in
> the device table.
>
> Signed-off-by: Rob Clark <robdclark@chromium.org>
> ---
[...]
>
> - if (adreno_cmp_rev(ADRENO_REV(5, 1, 0, ANY_ID), config->rev))
> + /*
> + * Note that we wouldn't have been able to get this far if there is not
> + * a device table entry for this chip_id
> + */
Why error-check it then?
> + info = adreno_find_info(config->chip_id);
> + if (WARN_ON(!info))
> + return ERR_PTR(-EINVAL);
> +
> + if (info->revn == 510)
> nr_rings = 1;
[...]
>
> - chipid = adreno_gpu->rev.core << 24;
> - chipid |= adreno_gpu->rev.major << 16;
> - chipid |= adreno_gpu->rev.minor << 12;
> - chipid |= adreno_gpu->rev.patchid << 8;
> + /* Note that the GMU has a slightly different layout for
/*
* Note
You've almost joined the good side :D
> + * chip_id, for whatever reason, so a bit of massaging
> + * is needed. The upper 16b are the same, but minor and
> + * patchid are packed in four bits each with the lower
> + * 8b unused:
> + */
[...]
> - .rev = ADRENO_REV(3, 0, 5, ANY_ID),
> + .chip_ids = ADRENO_CHIP_IDS(0x03000500),
0x03000512 for msm8226-v2
0x03000520 for msm8610
> .family = ADRENO_3XX,
> .revn = 305,
> .fw = {
> @@ -66,7 +66,7 @@ static const struct adreno_info gpulist[] = {
> .inactive_period = DRM_MSM_INACTIVE_PERIOD,
> .init = a3xx_gpu_init,
> }, {
> - .rev = ADRENO_REV(3, 0, 6, 0),
> + .chip_ids = ADRENO_CHIP_IDS(0x03000600),
> .family = ADRENO_3XX,
> .revn = 307, /* because a305c is revn==306 */
> .fw = {
> @@ -77,7 +77,11 @@ static const struct adreno_info gpulist[] = {
> .inactive_period = DRM_MSM_INACTIVE_PERIOD,
> .init = a3xx_gpu_init,
> }, {
> - .rev = ADRENO_REV(3, 2, ANY_ID, ANY_ID),
> + .chip_ids = ADRENO_CHIP_IDS(
> + 0x03020000,
> + 0x03020001,
> + 0x03020002
> + ),
> .family = ADRENO_3XX,
> .revn = 320,
> .fw = {
> @@ -88,7 +92,11 @@ static const struct adreno_info gpulist[] = {
> .inactive_period = DRM_MSM_INACTIVE_PERIOD,
> .init = a3xx_gpu_init,
> }, {
> - .rev = ADRENO_REV(3, 3, 0, ANY_ID),
> + .chip_ids = ADRENO_CHIP_IDS(
> + 0x03030000,
drop, prototype broken hw
(I think there are also some specific codepaths for that junk,
let's rid them too)
> + 0x03030001,
v2 prod
> + 0x03030002
msm8974pro
> + ),
> .family = ADRENO_3XX,
> .revn = 330,
> .fw = {
> @@ -99,7 +107,7 @@ static const struct adreno_info gpulist[] = {
> .inactive_period = DRM_MSM_INACTIVE_PERIOD,
> .init = a3xx_gpu_init,
> }, {
> - .rev = ADRENO_REV(4, 0, 5, ANY_ID),
> + .chip_ids = ADRENO_CHIP_IDS(0x04000500),
0x04000500 msm8939
0x04000510 msm8952 (unsupported today)
> .family = ADRENO_4XX,
> .revn = 405,
> .fw = {
> @@ -110,7 +118,7 @@ static const struct adreno_info gpulist[] = {
> .inactive_period = DRM_MSM_INACTIVE_PERIOD,
> .init = a4xx_gpu_init,
> }, {
> - .rev = ADRENO_REV(4, 2, 0, ANY_ID),
> + .chip_ids = ADRENO_CHIP_IDS(0x04020000),
msm8992, ok
> .family = ADRENO_4XX,
> .revn = 420,
> .fw = {
> @@ -121,7 +129,7 @@ static const struct adreno_info gpulist[] = {
> .inactive_period = DRM_MSM_INACTIVE_PERIOD,
> .init = a4xx_gpu_init,
> }, {
> - .rev = ADRENO_REV(4, 3, 0, ANY_ID),
> + .chip_ids = ADRENO_CHIP_IDS(0x04030000),
0x04030002 msm8994-v2.1, earlier revs are probably trash piles held
together with duct tape knowing the track record of that soc
> .family = ADRENO_4XX,
> .revn = 430,
> .fw = {
> @@ -132,7 +140,7 @@ static const struct adreno_info gpulist[] = {
> .inactive_period = DRM_MSM_INACTIVE_PERIOD,
> .init = a4xx_gpu_init,
> }, {
> - .rev = ADRENO_REV(5, 0, 6, ANY_ID),
> + .chip_ids = ADRENO_CHIP_IDS(0x05000600),
msm8953 ok
> .family = ADRENO_5XX,
> .revn = 506,
> .fw = {
> @@ -150,7 +158,7 @@ static const struct adreno_info gpulist[] = {
> .init = a5xx_gpu_init,
> .zapfw = "a506_zap.mdt",
> }, {
> - .rev = ADRENO_REV(5, 0, 8, ANY_ID),
> + .chip_ids = ADRENO_CHIP_IDS(0x05000800),
630 ok
> .family = ADRENO_5XX,
> .revn = 508,
> .fw = {
> @@ -167,7 +175,7 @@ static const struct adreno_info gpulist[] = {
> .init = a5xx_gpu_init,
> .zapfw = "a508_zap.mdt",
> }, {
> - .rev = ADRENO_REV(5, 0, 9, ANY_ID),
> + .chip_ids = ADRENO_CHIP_IDS(0x05000900),
636 ok
> .family = ADRENO_5XX,
> .revn = 509,
> .fw = {
> @@ -185,7 +193,7 @@ static const struct adreno_info gpulist[] = {
> /* Adreno 509 uses the same ZAP as 512 */
> .zapfw = "a512_zap.mdt",
> }, {
> - .rev = ADRENO_REV(5, 1, 0, ANY_ID),
> + .chip_ids = ADRENO_CHIP_IDS(0x05010000),
8976 ok
> .family = ADRENO_5XX,
> .revn = 510,
> .fw = {
> @@ -200,7 +208,7 @@ static const struct adreno_info gpulist[] = {
> .inactive_period = 250,
> .init = a5xx_gpu_init,
> }, {
> - .rev = ADRENO_REV(5, 1, 2, ANY_ID),
> + .chip_ids = ADRENO_CHIP_IDS(0x05010200),
660 ok
> .family = ADRENO_5XX,
> .revn = 512,
> .fw = {
> @@ -217,7 +225,7 @@ static const struct adreno_info gpulist[] = {
> .init = a5xx_gpu_init,
> .zapfw = "a512_zap.mdt",
> }, {
> - .rev = ADRENO_REV(5, 3, 0, 2),
> + .chip_ids = ADRENO_CHIP_IDS(0x05030002),
8996 final
0x05030004 8996pro
> .family = ADRENO_5XX,
> .revn = 530,
> .fw = {
> @@ -236,7 +244,7 @@ static const struct adreno_info gpulist[] = {
> .init = a5xx_gpu_init,
> .zapfw = "a530_zap.mdt",
> }, {
> - .rev = ADRENO_REV(5, 4, 0, ANY_ID),
> + .chip_ids = ADRENO_CHIP_IDS(0x05040001),
8998 final ok
> .family = ADRENO_5XX,
> .revn = 540,
> .fw = {
> @@ -254,7 +262,7 @@ static const struct adreno_info gpulist[] = {
> .init = a5xx_gpu_init,
> .zapfw = "a540_zap.mdt",
> }, {
> - .rev = ADRENO_REV(6, 1, 0, ANY_ID),
> + .chip_ids = ADRENO_CHIP_IDS(0x06010000),
sm6125 ok
sm6115 ok
[...]
> }, {
> - .rev = ADRENO_REV(6, 3, 0, ANY_ID),
> + .chip_ids = ADRENO_CHIP_IDS(0x06030002),
my sources say that it should end in 1 for sdm845-v2 and newer
> .family = ADRENO_6XX_GEN1,
> .revn = 630,
> .fw = {
> @@ -370,7 +378,7 @@ static const struct adreno_info gpulist[] = {
> .zapfw = "a630_zap.mdt",
> .hwcg = a630_hwcg,
> }, {
> - .rev = ADRENO_REV(6, 4, 0, ANY_ID),
> + .chip_ids = ADRENO_CHIP_IDS(0x06040001),
8150 ok
> .family = ADRENO_6XX_GEN2,
> .revn = 640,
> .fw = {
> @@ -388,7 +396,7 @@ static const struct adreno_info gpulist[] = {
> 1, 1
> ),
> }, {
> - .rev = ADRENO_REV(6, 5, 0, ANY_ID),
> + .chip_ids = ADRENO_CHIP_IDS(0x06050002),
8250-v2.1 ok
> .family = ADRENO_6XX_GEN3,
> .revn = 650,
> .fw = {
> @@ -410,7 +418,7 @@ static const struct adreno_info gpulist[] = {
> 3, 2
> ),
> }, {
> - .rev = ADRENO_REV(6, 6, 0, ANY_ID),
> + .chip_ids = ADRENO_CHIP_IDS(0x06060001),
8350-v2 ok
> .family = ADRENO_6XX_GEN4,
> .revn = 660,
> .fw = {
> @@ -426,7 +434,7 @@ static const struct adreno_info gpulist[] = {
> .hwcg = a660_hwcg,
> .address_space_size = SZ_16G,
> }, {
> - .rev = ADRENO_REV(6, 3, 5, ANY_ID),
> + .chip_ids = ADRENO_CHIP_IDS(0x06030500),
7280 ok
> .family = ADRENO_6XX_GEN4,
> .fw = {
> [ADRENO_FW_SQE] = "a660_sqe.fw",
> @@ -445,7 +453,7 @@ static const struct adreno_info gpulist[] = {
> 190, 1
> ),
> }, {
> - .rev = ADRENO_REV(6, 8, 0, ANY_ID),
> + .chip_ids = ADRENO_CHIP_IDS(0x06080000),
8180 probably ok
> .family = ADRENO_6XX_GEN2,
> .revn = 680,
> .fw = {
> @@ -459,7 +467,7 @@ static const struct adreno_info gpulist[] = {
> .zapfw = "a640_zap.mdt",
> .hwcg = a640_hwcg,
> }, {
> - .rev = ADRENO_REV(6, 9, 0, ANY_ID),
> + .chip_ids = ADRENO_CHIP_IDS(0x06090000),
8280 probably ok
> .family = ADRENO_6XX_GEN4,
> .fw = {
> [ADRENO_FW_SQE] = "a660_sqe.fw",
> @@ -494,31 +502,16 @@ MODULE_FIRMWARE("qcom/a630_sqe.fw");
> MODULE_FIRMWARE("qcom/a630_gmu.bin");
> MODULE_FIRMWARE("qcom/a630_zap.mbn");
>
[...]
> @@ -612,32 +604,34 @@ static int find_chipid(struct device *dev, struct adreno_rev *rev)
>
> if (sscanf(compat, "qcom,adreno-%u.%u", &r, &patch) == 2 ||
> sscanf(compat, "amd,imageon-%u.%u", &r, &patch) == 2) {
> - rev->core = r / 100;
> + uint32_t core, major, minor;
> +
> + core = r / 100;
> r %= 100;
> - rev->major = r / 10;
> + major = r / 10;
> r %= 10;
> - rev->minor = r;
> - rev->patchid = patch;
> + minor = r;
> +
> + *chipid = (core << 24) |
> + (major << 16) |
> + (minor << 8) |
> + patch;
I think a define macro would be nice here
>
> return 0;
> }
> +
> + if (sscanf(compat, "qcom,adreno-%08x", chipid) == 1)
> + return 0;
> }
>
[...]
> static inline int adreno_is_7c3(const struct adreno_gpu *gpu)
> {
> - /* The order of args is important here to handle ANY_ID correctly */
> - return adreno_cmp_rev(ADRENO_REV(6, 3, 5, ANY_ID), gpu->rev);
> + return gpu->info->chip_ids[0] == 0x06030500;
> }
I'm sorry, but this screams trouble.. and doesn't sound very maintainable :/
Apart from all these comments, I don't really see the point of this patch,
other than trying to tie together Qualcomm's almost-meaningless chipids on
a7xx into the picture..
Since they can't even be read back from the hardware, I don't think trying
to force them into the upstream kernel makes any sense.
On a different note, I think we could try to blockify Adreno definitions a
bit by splitting things into:
- Core GPU propeties (revision, fw name, GMEM size)
- G(P)MU properties
- Family data (quirks, reg presets in some config struct which could be a
union of config structs per generation, hwcg, maybe protected regs ptr
should also be moved there)
- Generation data (init function, a2xx and a6xx specifics)
- Speedbin LUTs matched against socid
or something like that.. there's a whole lot of duplicated data atm
Konrad
>
> static inline int adreno_is_a660(const struct adreno_gpu *gpu)
> @@ -358,8 +364,7 @@ static inline int adreno_is_a680(const struct adreno_gpu *gpu)
>
> static inline int adreno_is_a690(const struct adreno_gpu *gpu)
> {
> - /* The order of args is important here to handle ANY_ID correctly */
> - return adreno_cmp_rev(ADRENO_REV(6, 9, 0, ANY_ID), gpu->rev);
> + return gpu->info->chip_ids[0] == 0x06090000;
> };
> /* check for a615, a616, a618, a619 or any a630 derivatives */
> static inline int adreno_is_a630_family(const struct adreno_gpu *gpu)
^ permalink raw reply [flat|nested] 73+ messages in thread
* Re: [PATCH 06/12] drm/msm/adreno: Allow SoC specific gpu device table entries
2023-07-06 21:10 ` [PATCH 06/12] drm/msm/adreno: Allow SoC specific gpu device table entries Rob Clark
@ 2023-07-07 0:40 ` Konrad Dybcio
2023-07-13 22:15 ` [Freedreno] " Akhil P Oommen
2023-07-07 2:34 ` Dmitry Baryshkov
1 sibling, 1 reply; 73+ messages in thread
From: Konrad Dybcio @ 2023-07-07 0:40 UTC (permalink / raw)
To: Rob Clark, dri-devel; +Cc: Rob Clark, linux-arm-msm, freedreno
On 6.07.2023 23:10, Rob Clark wrote:
> From: Rob Clark <robdclark@chromium.org>
>
> There are cases where there are differences due to SoC integration.
> Such as cache-coherency support, and (in the next patch) e-fuse to
> speedbin mappings.
>
> Signed-off-by: Rob Clark <robdclark@chromium.org>
> ---
of_machine_is_compatible is rather used in extremely desperate
situations :/ I'm not sure this is the correct way to do this..
Especially since there's a direct correlation between GMU presence
and ability to do cached coherent.
The GMU mandates presence of RPMh (as most of what the GMU does is
talk to AOSS through its RSC).
To achieve I/O coherency, there must be some memory that both the
CPU and GPU (and possibly others) can access through some sort of
a negotiator/manager.
In our case, I believe that's LLC. And guess what that implies.
MEMNOC instead of BIMC. And guess what that implies. RPMh!
Now, we know GMU => RPMh, but does it work the other way around?
Yes. GMU wrapper was a hack because probably nobody in the Adreno team
would have imagined that somebody would be crazy enough to fork
multiple year old designs multiple times and release them as new
SoCs with updated arm cores and 5G..
(Except for A612 which has a "Reduced GMU" but that zombie still talks
to RPMh. And A612 is IO-coherent. So I guess it works anyway.)
Konrad
> drivers/gpu/drm/msm/adreno/adreno_device.c | 34 +++++++++++++++++++---
> drivers/gpu/drm/msm/adreno/adreno_gpu.h | 1 +
> 2 files changed, 31 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c
> index 3c531da417b9..e62bc895a31f 100644
> --- a/drivers/gpu/drm/msm/adreno/adreno_device.c
> +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c
> @@ -258,6 +258,32 @@ static const struct adreno_info gpulist[] = {
> .inactive_period = DRM_MSM_INACTIVE_PERIOD,
> .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT,
> .init = a6xx_gpu_init,
> + }, {
> + .machine = "qcom,sm4350",
> + .rev = ADRENO_REV(6, 1, 9, ANY_ID),
> + .revn = 619,
> + .fw = {
> + [ADRENO_FW_SQE] = "a630_sqe.fw",
> + [ADRENO_FW_GMU] = "a619_gmu.bin",
> + },
> + .gmem = SZ_512K,
> + .inactive_period = DRM_MSM_INACTIVE_PERIOD,
> + .init = a6xx_gpu_init,
> + .zapfw = "a615_zap.mdt",
> + .hwcg = a615_hwcg,
> + }, {
> + .machine = "qcom,sm6375",
> + .rev = ADRENO_REV(6, 1, 9, ANY_ID),
> + .revn = 619,
> + .fw = {
> + [ADRENO_FW_SQE] = "a630_sqe.fw",
> + [ADRENO_FW_GMU] = "a619_gmu.bin",
> + },
> + .gmem = SZ_512K,
> + .inactive_period = DRM_MSM_INACTIVE_PERIOD,
> + .init = a6xx_gpu_init,
> + .zapfw = "a615_zap.mdt",
> + .hwcg = a615_hwcg,
> }, {
> .rev = ADRENO_REV(6, 1, 9, ANY_ID),
> .revn = 619,
> @@ -409,6 +435,8 @@ const struct adreno_info *adreno_info(struct adreno_rev rev)
> /* identify gpu: */
> for (i = 0; i < ARRAY_SIZE(gpulist); i++) {
> const struct adreno_info *info = &gpulist[i];
> + if (info->machine && !of_machine_is_compatible(info->machine))
> + continue;
> if (adreno_cmp_rev(info->rev, rev))
> return info;
> }
> @@ -563,6 +591,8 @@ static int adreno_bind(struct device *dev, struct device *master, void *data)
> config.rev.minor, config.rev.patchid);
>
> priv->is_a2xx = config.rev.core == 2;
> + priv->has_cached_coherent =
> + !!(info->quirks & ADRENO_QUIRK_HAS_CACHED_COHERENT);
>
> gpu = info->init(drm);
> if (IS_ERR(gpu)) {
> @@ -574,10 +604,6 @@ static int adreno_bind(struct device *dev, struct device *master, void *data)
> if (ret)
> return ret;
>
> - priv->has_cached_coherent =
> - !!(info->quirks & ADRENO_QUIRK_HAS_CACHED_COHERENT) &&
> - !adreno_has_gmu_wrapper(to_adreno_gpu(gpu));
> -
> return 0;
> }
>
> diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> index e08d41337169..d5335b99c64c 100644
> --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> @@ -61,6 +61,7 @@ extern const struct adreno_reglist a612_hwcg[], a615_hwcg[], a630_hwcg[], a640_h
> extern const struct adreno_reglist a660_hwcg[], a690_hwcg[];
>
> struct adreno_info {
> + const char *machine;
> struct adreno_rev rev;
> uint32_t revn;
> const char *fw[ADRENO_FW_MAX];
^ permalink raw reply [flat|nested] 73+ messages in thread
* Re: [Freedreno] [PATCH 02/12] drm/msm/adreno: Remove redundant gmem size param
2023-07-06 21:10 ` [PATCH 02/12] drm/msm/adreno: Remove redundant gmem size param Rob Clark
2023-07-06 23:22 ` Konrad Dybcio
@ 2023-07-07 2:23 ` Dmitry Baryshkov
1 sibling, 0 replies; 73+ messages in thread
From: Dmitry Baryshkov @ 2023-07-07 2:23 UTC (permalink / raw)
To: Rob Clark, dri-devel; +Cc: Konrad Dybcio, linux-arm-msm, Rob Clark, freedreno
On 07/07/2023 00:10, Rob Clark wrote:
> From: Rob Clark <robdclark@chromium.org>
>
> Even in the ocmem case, the allocated ocmem buffer size should match the
> requested size.
>
> Signed-off-by: Rob Clark <robdclark@chromium.org>
> ---
> drivers/gpu/drm/msm/adreno/a2xx_gpu.c | 2 +-
> drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 2 +-
> drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 2 +-
> drivers/gpu/drm/msm/adreno/adreno_device.c | 1 -
> drivers/gpu/drm/msm/adreno/adreno_gpu.c | 8 ++++----
> drivers/gpu/drm/msm/adreno/adreno_gpu.h | 1 -
> 6 files changed, 7 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/adreno/a2xx_gpu.c b/drivers/gpu/drm/msm/adreno/a2xx_gpu.c
> index c67089a7ebc1..50ee03bc94b4 100644
> --- a/drivers/gpu/drm/msm/adreno/a2xx_gpu.c
> +++ b/drivers/gpu/drm/msm/adreno/a2xx_gpu.c
> @@ -205,7 +205,7 @@ static int a2xx_hw_init(struct msm_gpu *gpu)
> A2XX_MH_INTERRUPT_MASK_MMU_PAGE_FAULT);
>
> for (i = 3; i <= 5; i++)
> - if ((SZ_16K << i) == adreno_gpu->gmem)
> + if ((SZ_16K << i) == adreno_gpu->info->gmem)
> break;
> gpu_write(gpu, REG_A2XX_RB_EDRAM_INFO, i);
>
> diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
> index a99310b68793..f0803e94ebe5 100644
> --- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
> +++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
> @@ -749,7 +749,7 @@ static int a5xx_hw_init(struct msm_gpu *gpu)
> gpu_write(gpu, REG_A5XX_UCHE_GMEM_RANGE_MIN_LO, 0x00100000);
> gpu_write(gpu, REG_A5XX_UCHE_GMEM_RANGE_MIN_HI, 0x00000000);
> gpu_write(gpu, REG_A5XX_UCHE_GMEM_RANGE_MAX_LO,
> - 0x00100000 + adreno_gpu->gmem - 1);
> + 0x00100000 + adreno_gpu->info->gmem - 1);
> gpu_write(gpu, REG_A5XX_UCHE_GMEM_RANGE_MAX_HI, 0x00000000);
>
> if (adreno_is_a506(adreno_gpu) || adreno_is_a508(adreno_gpu) ||
> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> index b3ada1e7b598..edbade75020f 100644
> --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> @@ -1270,7 +1270,7 @@ static int hw_init(struct msm_gpu *gpu)
> gpu_write64(gpu, REG_A6XX_UCHE_GMEM_RANGE_MIN, 0x00100000);
>
> gpu_write64(gpu, REG_A6XX_UCHE_GMEM_RANGE_MAX,
> - 0x00100000 + adreno_gpu->gmem - 1);
> + 0x00100000 + adreno_gpu->info->gmem - 1);
> }
>
> gpu_write(gpu, REG_A6XX_UCHE_FILTER_CNTL, 0x804);
> diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c
> index 5eba0ae5c9a7..326912284a95 100644
> --- a/drivers/gpu/drm/msm/adreno/adreno_device.c
> +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c
> @@ -239,7 +239,6 @@ static const struct adreno_info gpulist[] = {
> }, {
> .rev = ADRENO_REV(6, 1, 0, ANY_ID),
> .revn = 610,
> - .name = "A610",
> .fw = {
> [ADRENO_FW_SQE] = "a630_sqe.fw",
> },
This one should go to the previous patch.
> diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
> index e3cd9ff6ff1d..4f59682f585e 100644
> --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c
> +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
> @@ -320,7 +320,7 @@ int adreno_get_param(struct msm_gpu *gpu, struct msm_file_private *ctx,
> *value = adreno_gpu->info->revn;
> return 0;
> case MSM_PARAM_GMEM_SIZE:
> - *value = adreno_gpu->gmem;
> + *value = adreno_gpu->info->gmem;
> return 0;
> case MSM_PARAM_GMEM_BASE:
> *value = !adreno_is_a650_family(adreno_gpu) ? 0x100000 : 0;
> @@ -1041,14 +1041,15 @@ int adreno_gpu_ocmem_init(struct device *dev, struct adreno_gpu *adreno_gpu,
> return PTR_ERR(ocmem);
> }
>
> - ocmem_hdl = ocmem_allocate(ocmem, OCMEM_GRAPHICS, adreno_gpu->gmem);
> + ocmem_hdl = ocmem_allocate(ocmem, OCMEM_GRAPHICS, adreno_gpu->info->gmem);
> if (IS_ERR(ocmem_hdl))
> return PTR_ERR(ocmem_hdl);
>
> adreno_ocmem->ocmem = ocmem;
> adreno_ocmem->base = ocmem_hdl->addr;
> adreno_ocmem->hdl = ocmem_hdl;
> - adreno_gpu->gmem = ocmem_hdl->len;
> +
> + WARN_ON(ocmem_hdl->len != adreno_gpu->info->gmem);
>
> return 0;
> }
> @@ -1097,7 +1098,6 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev,
>
> adreno_gpu->funcs = funcs;
> adreno_gpu->info = adreno_info(config->rev);
> - adreno_gpu->gmem = adreno_gpu->info->gmem;
> adreno_gpu->revn = adreno_gpu->info->revn;
> adreno_gpu->rev = *rev;
>
> diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> index 6830c3776c2d..aaf09c642dc6 100644
> --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> @@ -77,7 +77,6 @@ struct adreno_gpu {
> struct msm_gpu base;
> struct adreno_rev rev;
> const struct adreno_info *info;
> - uint32_t gmem; /* actual gmem size */
> uint32_t revn; /* numeric revision name */
> uint16_t speedbin;
> const struct adreno_gpu_funcs *funcs;
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 73+ messages in thread
* Re: [Freedreno] [PATCH 03/12] drm/msm/adreno: Remove redundant revn param
2023-07-06 21:10 ` [PATCH 03/12] drm/msm/adreno: Remove redundant revn param Rob Clark
2023-07-06 23:26 ` Konrad Dybcio
@ 2023-07-07 2:24 ` Dmitry Baryshkov
1 sibling, 0 replies; 73+ messages in thread
From: Dmitry Baryshkov @ 2023-07-07 2:24 UTC (permalink / raw)
To: Rob Clark, dri-devel; +Cc: Konrad Dybcio, linux-arm-msm, Rob Clark, freedreno
On 07/07/2023 00:10, Rob Clark wrote:
> From: Rob Clark <robdclark@chromium.org>
>
> This just duplicates what is in adreno_info, and can cause confusion if
> used before it is set.
>
> Signed-off-by: Rob Clark <robdclark@chromium.org>
> ---
> drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 2 --
> drivers/gpu/drm/msm/adreno/adreno_gpu.c | 1 -
> drivers/gpu/drm/msm/adreno/adreno_gpu.h | 22 +++++++++-------------
> 3 files changed, 9 insertions(+), 16 deletions(-)
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 73+ messages in thread
* Re: [Freedreno] [PATCH 04/12] drm/msm/adreno: Use quirk identify hw_apriv
2023-07-06 21:10 ` [PATCH 04/12] drm/msm/adreno: Use quirk identify hw_apriv Rob Clark
2023-07-06 23:27 ` Konrad Dybcio
@ 2023-07-07 2:25 ` Dmitry Baryshkov
1 sibling, 0 replies; 73+ messages in thread
From: Dmitry Baryshkov @ 2023-07-07 2:25 UTC (permalink / raw)
To: Rob Clark, dri-devel; +Cc: Konrad Dybcio, linux-arm-msm, Rob Clark, freedreno
On 07/07/2023 00:10, Rob Clark wrote:
> From: Rob Clark <robdclark@chromium.org>
>
> Rather than just open coding a list of gpu-id matches.
>
> Signed-off-by: Rob Clark <robdclark@chromium.org>
> ---
> drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 3 +--
> drivers/gpu/drm/msm/adreno/adreno_device.c | 4 ++++
> drivers/gpu/drm/msm/adreno/adreno_gpu.h | 1 +
> 3 files changed, 6 insertions(+), 2 deletions(-)
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 73+ messages in thread
* Re: [Freedreno] [PATCH 05/12] drm/msm/adreno: Use quirk to identify cached-coherent support
2023-07-06 21:10 ` [PATCH 05/12] drm/msm/adreno: Use quirk to identify cached-coherent support Rob Clark
2023-07-06 23:29 ` Konrad Dybcio
@ 2023-07-07 2:29 ` Dmitry Baryshkov
2023-07-07 15:53 ` Rob Clark
2023-07-13 20:05 ` Akhil P Oommen
2 siblings, 1 reply; 73+ messages in thread
From: Dmitry Baryshkov @ 2023-07-07 2:29 UTC (permalink / raw)
To: Rob Clark, dri-devel; +Cc: Konrad Dybcio, linux-arm-msm, Rob Clark, freedreno
On 07/07/2023 00:10, Rob Clark wrote:
> From: Rob Clark <robdclark@chromium.org>
>
> It is better to explicitly list it. With the move to opaque chip-id's
> for future devices, we should avoid trying to infer things like
> generation from the numerical value.
Would it be better to push this to DT? I mean, we already have a
'dma-cache-coherent' property for it.
>
> Signed-off-by: Rob Clark <robdclark@chromium.org>
> ---
> drivers/gpu/drm/msm/adreno/adreno_device.c | 23 +++++++++++++++-------
> drivers/gpu/drm/msm/adreno/adreno_gpu.h | 1 +
> 2 files changed, 17 insertions(+), 7 deletions(-)
>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 73+ messages in thread
* Re: [Freedreno] [PATCH 06/12] drm/msm/adreno: Allow SoC specific gpu device table entries
2023-07-06 21:10 ` [PATCH 06/12] drm/msm/adreno: Allow SoC specific gpu device table entries Rob Clark
2023-07-07 0:40 ` Konrad Dybcio
@ 2023-07-07 2:34 ` Dmitry Baryshkov
2023-07-13 20:26 ` Akhil P Oommen
1 sibling, 1 reply; 73+ messages in thread
From: Dmitry Baryshkov @ 2023-07-07 2:34 UTC (permalink / raw)
To: Rob Clark, dri-devel; +Cc: Konrad Dybcio, linux-arm-msm, Rob Clark, freedreno
On 07/07/2023 00:10, Rob Clark wrote:
> From: Rob Clark <robdclark@chromium.org>
>
> There are cases where there are differences due to SoC integration.
> Such as cache-coherency support, and (in the next patch) e-fuse to
> speedbin mappings.
I have the feeling that we are trying to circumvent the way DT works.
I'd suggest adding explicit SoC-compatible strings to Adreno bindings
and then using of_device_id::data and then of_device_get_match_data().
>
> Signed-off-by: Rob Clark <robdclark@chromium.org>
> ---
> drivers/gpu/drm/msm/adreno/adreno_device.c | 34 +++++++++++++++++++---
> drivers/gpu/drm/msm/adreno/adreno_gpu.h | 1 +
> 2 files changed, 31 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c
> index 3c531da417b9..e62bc895a31f 100644
> --- a/drivers/gpu/drm/msm/adreno/adreno_device.c
> +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c
> @@ -258,6 +258,32 @@ static const struct adreno_info gpulist[] = {
> .inactive_period = DRM_MSM_INACTIVE_PERIOD,
> .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT,
> .init = a6xx_gpu_init,
> + }, {
> + .machine = "qcom,sm4350",
> + .rev = ADRENO_REV(6, 1, 9, ANY_ID),
> + .revn = 619,
> + .fw = {
> + [ADRENO_FW_SQE] = "a630_sqe.fw",
> + [ADRENO_FW_GMU] = "a619_gmu.bin",
> + },
> + .gmem = SZ_512K,
> + .inactive_period = DRM_MSM_INACTIVE_PERIOD,
> + .init = a6xx_gpu_init,
> + .zapfw = "a615_zap.mdt",
> + .hwcg = a615_hwcg,
> + }, {
> + .machine = "qcom,sm6375",
> + .rev = ADRENO_REV(6, 1, 9, ANY_ID),
> + .revn = 619,
> + .fw = {
> + [ADRENO_FW_SQE] = "a630_sqe.fw",
> + [ADRENO_FW_GMU] = "a619_gmu.bin",
> + },
> + .gmem = SZ_512K,
> + .inactive_period = DRM_MSM_INACTIVE_PERIOD,
> + .init = a6xx_gpu_init,
> + .zapfw = "a615_zap.mdt",
> + .hwcg = a615_hwcg,
> }, {
> .rev = ADRENO_REV(6, 1, 9, ANY_ID),
> .revn = 619,
> @@ -409,6 +435,8 @@ const struct adreno_info *adreno_info(struct adreno_rev rev)
> /* identify gpu: */
> for (i = 0; i < ARRAY_SIZE(gpulist); i++) {
> const struct adreno_info *info = &gpulist[i];
> + if (info->machine && !of_machine_is_compatible(info->machine))
> + continue;
> if (adreno_cmp_rev(info->rev, rev))
> return info;
> }
> @@ -563,6 +591,8 @@ static int adreno_bind(struct device *dev, struct device *master, void *data)
> config.rev.minor, config.rev.patchid);
>
> priv->is_a2xx = config.rev.core == 2;
> + priv->has_cached_coherent =
> + !!(info->quirks & ADRENO_QUIRK_HAS_CACHED_COHERENT);
>
> gpu = info->init(drm);
> if (IS_ERR(gpu)) {
> @@ -574,10 +604,6 @@ static int adreno_bind(struct device *dev, struct device *master, void *data)
> if (ret)
> return ret;
>
> - priv->has_cached_coherent =
> - !!(info->quirks & ADRENO_QUIRK_HAS_CACHED_COHERENT) &&
> - !adreno_has_gmu_wrapper(to_adreno_gpu(gpu));
> -
> return 0;
> }
>
> diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> index e08d41337169..d5335b99c64c 100644
> --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> @@ -61,6 +61,7 @@ extern const struct adreno_reglist a612_hwcg[], a615_hwcg[], a630_hwcg[], a640_h
> extern const struct adreno_reglist a660_hwcg[], a690_hwcg[];
>
> struct adreno_info {
> + const char *machine;
> struct adreno_rev rev;
> uint32_t revn;
> const char *fw[ADRENO_FW_MAX];
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 73+ messages in thread
* Re: [Freedreno] [PATCH 09/12] drm/msm/adreno: Add adreno family
2023-07-06 21:10 ` [PATCH 09/12] drm/msm/adreno: Add adreno family Rob Clark
2023-07-06 23:35 ` Konrad Dybcio
@ 2023-07-07 2:49 ` Dmitry Baryshkov
1 sibling, 0 replies; 73+ messages in thread
From: Dmitry Baryshkov @ 2023-07-07 2:49 UTC (permalink / raw)
To: Rob Clark, dri-devel; +Cc: Konrad Dybcio, linux-arm-msm, Rob Clark, freedreno
On 07/07/2023 00:10, Rob Clark wrote:
> From: Rob Clark <robdclark@chromium.org>
>
> Sometimes it is useful to know the sub-generation (or "family"). And in
> any case, this helps us get away from infering the generation from the
> numerical chip-id.
>
> Signed-off-by: Rob Clark <robdclark@chromium.org>
> ---
> drivers/gpu/drm/msm/adreno/adreno_device.c | 31 ++++++++++++++-
> drivers/gpu/drm/msm/adreno/adreno_gpu.c | 11 +++---
> drivers/gpu/drm/msm/adreno/adreno_gpu.h | 46 ++++++++++++++++------
> 3 files changed, 70 insertions(+), 18 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c
> index b7f70cfe6081..dcd6363ac7b0 100644
> --- a/drivers/gpu/drm/msm/adreno/adreno_device.c
> +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c
> @@ -23,6 +23,7 @@ module_param_named(allow_vram_carveout, allow_vram_carveout, bool, 0600);
> static const struct adreno_info gpulist[] = {
> {
> .rev = ADRENO_REV(2, 0, 0, 0),
> + .family = ADRENO_2XX_GEN1,
> .revn = 200,
> .fw = {
> [ADRENO_FW_PM4] = "yamato_pm4.fw",
> @@ -33,6 +34,7 @@ static const struct adreno_info gpulist[] = {
> .init = a2xx_gpu_init,
> }, { /* a200 on i.mx51 has only 128kib gmem */
> .rev = ADRENO_REV(2, 0, 0, 1),
> + .family = ADRENO_2XX_GEN1,
> .revn = 201,
> .fw = {
> [ADRENO_FW_PM4] = "yamato_pm4.fw",
> @@ -43,6 +45,7 @@ static const struct adreno_info gpulist[] = {
> .init = a2xx_gpu_init,
> }, {
> .rev = ADRENO_REV(2, 2, 0, ANY_ID),
> + .family = ADRENO_2XX_GEN2,
> .revn = 220,
> .fw = {
> [ADRENO_FW_PM4] = "leia_pm4_470.fw",
> @@ -53,6 +56,7 @@ static const struct adreno_info gpulist[] = {
> .init = a2xx_gpu_init,
> }, {
> .rev = ADRENO_REV(3, 0, 5, ANY_ID),
> + .family = ADRENO_3XX,
> .revn = 305,
> .fw = {
> [ADRENO_FW_PM4] = "a300_pm4.fw",
> @@ -63,6 +67,7 @@ static const struct adreno_info gpulist[] = {
> .init = a3xx_gpu_init,
> }, {
> .rev = ADRENO_REV(3, 0, 6, 0),
> + .family = ADRENO_3XX,
> .revn = 307, /* because a305c is revn==306 */
> .fw = {
> [ADRENO_FW_PM4] = "a300_pm4.fw",
> @@ -73,6 +78,7 @@ static const struct adreno_info gpulist[] = {
> .init = a3xx_gpu_init,
> }, {
> .rev = ADRENO_REV(3, 2, ANY_ID, ANY_ID),
> + .family = ADRENO_3XX,
> .revn = 320,
> .fw = {
> [ADRENO_FW_PM4] = "a300_pm4.fw",
> @@ -83,6 +89,7 @@ static const struct adreno_info gpulist[] = {
> .init = a3xx_gpu_init,
> }, {
> .rev = ADRENO_REV(3, 3, 0, ANY_ID),
> + .family = ADRENO_3XX,
> .revn = 330,
> .fw = {
> [ADRENO_FW_PM4] = "a330_pm4.fw",
> @@ -93,6 +100,7 @@ static const struct adreno_info gpulist[] = {
> .init = a3xx_gpu_init,
> }, {
> .rev = ADRENO_REV(4, 0, 5, ANY_ID),
> + .family = ADRENO_4XX,
> .revn = 405,
> .fw = {
> [ADRENO_FW_PM4] = "a420_pm4.fw",
> @@ -103,6 +111,7 @@ static const struct adreno_info gpulist[] = {
> .init = a4xx_gpu_init,
> }, {
> .rev = ADRENO_REV(4, 2, 0, ANY_ID),
> + .family = ADRENO_4XX,
> .revn = 420,
> .fw = {
> [ADRENO_FW_PM4] = "a420_pm4.fw",
> @@ -113,6 +122,7 @@ static const struct adreno_info gpulist[] = {
> .init = a4xx_gpu_init,
> }, {
> .rev = ADRENO_REV(4, 3, 0, ANY_ID),
> + .family = ADRENO_4XX,
> .revn = 430,
> .fw = {
> [ADRENO_FW_PM4] = "a420_pm4.fw",
> @@ -123,6 +133,7 @@ static const struct adreno_info gpulist[] = {
> .init = a4xx_gpu_init,
> }, {
> .rev = ADRENO_REV(5, 0, 6, ANY_ID),
> + .family = ADRENO_5XX,
> .revn = 506,
> .fw = {
> [ADRENO_FW_PM4] = "a530_pm4.fw",
> @@ -140,6 +151,7 @@ static const struct adreno_info gpulist[] = {
> .zapfw = "a506_zap.mdt",
> }, {
> .rev = ADRENO_REV(5, 0, 8, ANY_ID),
> + .family = ADRENO_5XX,
> .revn = 508,
> .fw = {
> [ADRENO_FW_PM4] = "a530_pm4.fw",
> @@ -156,6 +168,7 @@ static const struct adreno_info gpulist[] = {
> .zapfw = "a508_zap.mdt",
> }, {
> .rev = ADRENO_REV(5, 0, 9, ANY_ID),
> + .family = ADRENO_5XX,
> .revn = 509,
> .fw = {
> [ADRENO_FW_PM4] = "a530_pm4.fw",
> @@ -173,6 +186,7 @@ static const struct adreno_info gpulist[] = {
> .zapfw = "a512_zap.mdt",
> }, {
> .rev = ADRENO_REV(5, 1, 0, ANY_ID),
> + .family = ADRENO_5XX,
> .revn = 510,
> .fw = {
> [ADRENO_FW_PM4] = "a530_pm4.fw",
> @@ -187,6 +201,7 @@ static const struct adreno_info gpulist[] = {
> .init = a5xx_gpu_init,
> }, {
> .rev = ADRENO_REV(5, 1, 2, ANY_ID),
> + .family = ADRENO_5XX,
> .revn = 512,
> .fw = {
> [ADRENO_FW_PM4] = "a530_pm4.fw",
> @@ -203,6 +218,7 @@ static const struct adreno_info gpulist[] = {
> .zapfw = "a512_zap.mdt",
> }, {
> .rev = ADRENO_REV(5, 3, 0, 2),
> + .family = ADRENO_5XX,
> .revn = 530,
> .fw = {
> [ADRENO_FW_PM4] = "a530_pm4.fw",
> @@ -221,6 +237,7 @@ static const struct adreno_info gpulist[] = {
> .zapfw = "a530_zap.mdt",
> }, {
> .rev = ADRENO_REV(5, 4, 0, ANY_ID),
> + .family = ADRENO_5XX,
> .revn = 540,
> .fw = {
> [ADRENO_FW_PM4] = "a530_pm4.fw",
> @@ -238,6 +255,7 @@ static const struct adreno_info gpulist[] = {
> .zapfw = "a540_zap.mdt",
> }, {
> .rev = ADRENO_REV(6, 1, 0, ANY_ID),
> + .family = ADRENO_6XX_GEN1,
> .revn = 610,
> .fw = {
> [ADRENO_FW_SQE] = "a630_sqe.fw",
> @@ -263,6 +281,7 @@ static const struct adreno_info gpulist[] = {
> ),
> }, {
> .rev = ADRENO_REV(6, 1, 8, ANY_ID),
> + .family = ADRENO_6XX_GEN1,
> .revn = 618,
> .fw = {
> [ADRENO_FW_SQE] = "a630_sqe.fw",
> @@ -280,6 +299,7 @@ static const struct adreno_info gpulist[] = {
> }, {
> .machine = "qcom,sm4350",
> .rev = ADRENO_REV(6, 1, 9, ANY_ID),
> + .family = ADRENO_6XX_GEN1,
> .revn = 619,
> .fw = {
> [ADRENO_FW_SQE] = "a630_sqe.fw",
> @@ -298,6 +318,7 @@ static const struct adreno_info gpulist[] = {
> }, {
> .machine = "qcom,sm6375",
> .rev = ADRENO_REV(6, 1, 9, ANY_ID),
> + .family = ADRENO_6XX_GEN1,
> .revn = 619,
> .fw = {
> [ADRENO_FW_SQE] = "a630_sqe.fw",
> @@ -315,6 +336,7 @@ static const struct adreno_info gpulist[] = {
> ),
> }, {
> .rev = ADRENO_REV(6, 1, 9, ANY_ID),
> + .family = ADRENO_6XX_GEN1,
> .revn = 619,
> .fw = {
> [ADRENO_FW_SQE] = "a630_sqe.fw",
> @@ -335,6 +357,7 @@ static const struct adreno_info gpulist[] = {
> ),
> }, {
> .rev = ADRENO_REV(6, 3, 0, ANY_ID),
> + .family = ADRENO_6XX_GEN1,
> .revn = 630,
> .fw = {
> [ADRENO_FW_SQE] = "a630_sqe.fw",
> @@ -348,6 +371,7 @@ static const struct adreno_info gpulist[] = {
> .hwcg = a630_hwcg,
> }, {
> .rev = ADRENO_REV(6, 4, 0, ANY_ID),
> + .family = ADRENO_6XX_GEN2,
> .revn = 640,
> .fw = {
> [ADRENO_FW_SQE] = "a630_sqe.fw",
> @@ -365,6 +389,7 @@ static const struct adreno_info gpulist[] = {
> ),
> }, {
> .rev = ADRENO_REV(6, 5, 0, ANY_ID),
> + .family = ADRENO_6XX_GEN3,
> .revn = 650,
> .fw = {
> [ADRENO_FW_SQE] = "a650_sqe.fw",
> @@ -386,6 +411,7 @@ static const struct adreno_info gpulist[] = {
> ),
> }, {
> .rev = ADRENO_REV(6, 6, 0, ANY_ID),
> + .family = ADRENO_6XX_GEN4,
> .revn = 660,
> .fw = {
> [ADRENO_FW_SQE] = "a660_sqe.fw",
> @@ -401,6 +427,7 @@ static const struct adreno_info gpulist[] = {
> .address_space_size = SZ_16G,
> }, {
> .rev = ADRENO_REV(6, 3, 5, ANY_ID),
> + .family = ADRENO_6XX_GEN4,
> .fw = {
> [ADRENO_FW_SQE] = "a660_sqe.fw",
> [ADRENO_FW_GMU] = "a660_gmu.bin",
> @@ -419,6 +446,7 @@ static const struct adreno_info gpulist[] = {
> ),
> }, {
> .rev = ADRENO_REV(6, 8, 0, ANY_ID),
> + .family = ADRENO_6XX_GEN2,
> .revn = 680,
> .fw = {
> [ADRENO_FW_SQE] = "a630_sqe.fw",
> @@ -432,6 +460,7 @@ static const struct adreno_info gpulist[] = {
> .hwcg = a640_hwcg,
> }, {
> .rev = ADRENO_REV(6, 9, 0, ANY_ID),
> + .family = ADRENO_6XX_GEN4,
> .fw = {
> [ADRENO_FW_SQE] = "a660_sqe.fw",
> [ADRENO_FW_GMU] = "a690_gmu.bin",
> @@ -641,7 +670,7 @@ static int adreno_bind(struct device *dev, struct device *master, void *data)
> DBG("Found GPU: %u.%u.%u.%u", config.rev.core, config.rev.major,
> config.rev.minor, config.rev.patchid);
>
> - priv->is_a2xx = config.rev.core == 2;
> + priv->is_a2xx = info->family < ADRENO_3XX;
> priv->has_cached_coherent =
> !!(info->quirks & ADRENO_QUIRK_HAS_CACHED_COHERENT);
>
> diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
> index 2e62a7ce9f13..75ff7fb46099 100644
> --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c
> +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
> @@ -1079,8 +1079,13 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev,
> u32 speedbin;
> int ret;
>
> + adreno_gpu->funcs = funcs;
> + adreno_gpu->info = adreno_info(config->rev);
> + adreno_gpu->rev = *rev;
> +
> /* Only handle the core clock when GMU is not in use (or is absent). */
> - if (adreno_has_gmu_wrapper(adreno_gpu) || config->rev.core < 6) {
> + if (adreno_has_gmu_wrapper(adreno_gpu) ||
> + adreno_gpu->info->family < ADRENO_6XX_GEN1) {
> /*
> * This can only be done before devm_pm_opp_of_add_table(), or
> * dev_pm_opp_set_config() will WARN_ON()
> @@ -1096,10 +1101,6 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev,
> devm_pm_opp_set_clkname(dev, "core");
> }
>
> - adreno_gpu->funcs = funcs;
> - adreno_gpu->info = adreno_info(config->rev);
> - adreno_gpu->rev = *rev;
> -
> if (adreno_read_speedbin(dev, &speedbin) || !speedbin)
> speedbin = 0xffff;
> adreno_gpu->speedbin = (uint16_t) (0xffff & speedbin);
> diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> index 6066cfaaea52..2fa14dcd4e40 100644
> --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> @@ -29,6 +29,25 @@ enum {
> ADRENO_FW_MAX,
> };
>
> +/**
> + * @enum adreno_family: identify generation and possibly sub-generation
> + *
> + * In some cases there are distinct sub-generations within a major revision
> + * so it helps to be able to group the GPU devices by generation and if
> + * necessary sub-generation.
> + */
> +enum adreno_family {
> + ADRENO_2XX_GEN1, /* a20x */
> + ADRENO_2XX_GEN2, /* a22x */
> + ADRENO_3XX,
Would it be logical to separate a300 vs a330? I'm not sure if there were
any other sensible sub-divisions in 3xx.
> + ADRENO_4XX,
I'd say, there were three gnerations there:
- a405,
- a420,
- a430, a418
But this be an artifact of my memory due to slight programming
differences there. WDYT?
> + ADRENO_5XX,
I'll comment this separately.
> + ADRENO_6XX_GEN1, /* a630 family */
> + ADRENO_6XX_GEN2, /* a640 family */
> + ADRENO_6XX_GEN3, /* a650 family */
> + ADRENO_6XX_GEN4, /* a660 family */
It might be good to list family contents here.
> +};
> +
> #define ADRENO_QUIRK_TWO_PASS_USE_WFI BIT(0)
> #define ADRENO_QUIRK_FAULT_DETECT_MASK BIT(1)
> #define ADRENO_QUIRK_LMLOADKILL_DISABLE BIT(2)
> @@ -63,6 +82,7 @@ extern const struct adreno_reglist a660_hwcg[], a690_hwcg[];
> struct adreno_info {
> const char *machine;
> struct adreno_rev rev;
> + enum adreno_family family;
> uint32_t revn;
> const char *fw[ADRENO_FW_MAX];
> uint32_t gmem;
> @@ -188,14 +208,14 @@ static inline bool adreno_is_a2xx(const struct adreno_gpu *gpu)
> {
> if (WARN_ON_ONCE(!gpu->info))
> return false;
> - return (gpu->info->revn < 300);
> + return gpu->info->family < ADRENO_2XX_GEN2;
Probably this should be `<= ADRENO_2XX_GEN2`. Maybe we'd better list
those two generations explcitly? like `family == ADRENO_2XX_GEN1 ||
family == ADRENO_2XX_GEN2` ?
> }
>
> static inline bool adreno_is_a20x(const struct adreno_gpu *gpu)
> {
> if (WARN_ON_ONCE(!gpu->info))
> return false;
> - return (gpu->info->revn < 210);
> + return gpu->info->family == ADRENO_2XX_GEN1;
> }
>
> static inline bool adreno_is_a225(const struct adreno_gpu *gpu)
> @@ -338,29 +358,31 @@ static inline int adreno_is_a690(const struct adreno_gpu *gpu)
> /* check for a615, a616, a618, a619 or any a630 derivatives */
> static inline int adreno_is_a630_family(const struct adreno_gpu *gpu)
> {
> - return adreno_is_revn(gpu, 630) ||
> - adreno_is_revn(gpu, 615) ||
> - adreno_is_revn(gpu, 616) ||
> - adreno_is_revn(gpu, 618) ||
> - adreno_is_revn(gpu, 619);
> + if (WARN_ON_ONCE(!gpu->info))
> + return false;
> + return gpu->info->family == ADRENO_6XX_GEN1;
> }
>
> static inline int adreno_is_a660_family(const struct adreno_gpu *gpu)
> {
> - return adreno_is_a660(gpu) || adreno_is_a690(gpu) || adreno_is_7c3(gpu);
> + if (WARN_ON_ONCE(!gpu->info))
> + return false;
> + return gpu->info->family == ADRENO_6XX_GEN4;
> }
>
> /* check for a650, a660, or any derivatives */
> static inline int adreno_is_a650_family(const struct adreno_gpu *gpu)
> {
> - return adreno_is_revn(gpu, 650) ||
> - adreno_is_revn(gpu, 620) ||
> - adreno_is_a660_family(gpu);
> + if (WARN_ON_ONCE(!gpu->info))
> + return false;
> + return gpu->info->family >= ADRENO_6XX_GEN3;
> }
>
> static inline int adreno_is_a640_family(const struct adreno_gpu *gpu)
> {
> - return adreno_is_a640(gpu) || adreno_is_a680(gpu);
> + if (WARN_ON_ONCE(!gpu->info))
> + return false;
> + return gpu->info->family == ADRENO_6XX_GEN2;
> }
>
> u64 adreno_private_address_space_size(struct msm_gpu *gpu);
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 73+ messages in thread
* Re: [Freedreno] [PATCH 10/12] drm/msm/adreno: Add helper for formating chip-id
2023-07-06 21:10 ` [PATCH 10/12] drm/msm/adreno: Add helper for formating chip-id Rob Clark
2023-07-06 23:36 ` Konrad Dybcio
@ 2023-07-07 2:50 ` Dmitry Baryshkov
1 sibling, 0 replies; 73+ messages in thread
From: Dmitry Baryshkov @ 2023-07-07 2:50 UTC (permalink / raw)
To: Rob Clark, dri-devel; +Cc: Konrad Dybcio, linux-arm-msm, Rob Clark, freedreno
On 07/07/2023 00:10, Rob Clark wrote:
> From: Rob Clark <robdclark@chromium.org>
>
> This is used in a few places, including one that is parsed by userspace
> tools. So let's standardize it a bit better.
>
> Signed-off-by: Rob Clark <robdclark@chromium.org>
> ---
> drivers/gpu/drm/msm/adreno/adreno_device.c | 8 +++-----
> drivers/gpu/drm/msm/adreno/adreno_gpu.c | 19 ++++++++-----------
> drivers/gpu/drm/msm/adreno/adreno_gpu.h | 6 ++++++
> 3 files changed, 17 insertions(+), 16 deletions(-)
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 73+ messages in thread
* Re: [Freedreno] [PATCH 07/12] drm/msm/adreno: Move speedbin mapping to device table
2023-07-06 21:10 ` [PATCH 07/12] drm/msm/adreno: Move speedbin mapping to device table Rob Clark
@ 2023-07-07 2:54 ` Dmitry Baryshkov
2023-07-10 19:56 ` Rob Clark
0 siblings, 1 reply; 73+ messages in thread
From: Dmitry Baryshkov @ 2023-07-07 2:54 UTC (permalink / raw)
To: Rob Clark, dri-devel; +Cc: Konrad Dybcio, linux-arm-msm, Rob Clark, freedreno
On 07/07/2023 00:10, Rob Clark wrote:
> From: Rob Clark <robdclark@chromium.org>
>
> This simplifies the code.
>
> Signed-off-by: Rob Clark <robdclark@chromium.org>
> ---
> drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 171 ++-------------------
> drivers/gpu/drm/msm/adreno/adreno_device.c | 51 ++++++
> drivers/gpu/drm/msm/adreno/adreno_gpu.h | 25 +++
> 3 files changed, 92 insertions(+), 155 deletions(-)
Interesting hack, I'd say.
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Minor nit below.
>
> diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> index d5335b99c64c..994ac26ce731 100644
> --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> @@ -72,8 +72,33 @@ struct adreno_info {
> u32 inactive_period;
> const struct adreno_reglist *hwcg;
> u64 address_space_size;
> + /**
> + * @speedbins: Optional table of fuse to speedbin mappings
> + *
> + * Consists of pairs of fuse, index mappings, terminated with
> + * UINT_MAX sentinal.
> + */
> + uint32_t *speedbins;
Would it be better to explicitly list this as pairs of uint32_t? And
then use braces in ADRENO_SPEEDBIN initialisation.
> };
>
> +/*
> + * Helper to build a speedbin table, ie. the table:
> + * fuse | speedbin
> + * -----+---------
> + * 0 | 0
> + * 169 | 1
> + * 174 | 2
> + *
> + * would be declared as:
> + *
> + * .speedbins = ADRENO_SPEEDBINS(
> + * 0, 0,
> + * 169, 1,
> + * 174, 2
> + * ),
> + */
> +#define ADRENO_SPEEDBINS(tbl...) (uint32_t[]) { tbl, UINT_MAX }
> +
> const struct adreno_info *adreno_info(struct adreno_rev rev);
>
> struct adreno_gpu {
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 73+ messages in thread
* Re: [PATCH 09/12] drm/msm/adreno: Add adreno family
2023-07-06 23:35 ` Konrad Dybcio
@ 2023-07-07 3:16 ` Dmitry Baryshkov
2023-07-07 23:52 ` Rob Clark
0 siblings, 1 reply; 73+ messages in thread
From: Dmitry Baryshkov @ 2023-07-07 3:16 UTC (permalink / raw)
To: Konrad Dybcio, Rob Clark, dri-devel; +Cc: Rob Clark, linux-arm-msm, freedreno
On 07/07/2023 02:35, Konrad Dybcio wrote:
> On 6.07.2023 23:10, Rob Clark wrote:
>> From: Rob Clark <robdclark@chromium.org>
>>
>> Sometimes it is useful to know the sub-generation (or "family"). And in
>> any case, this helps us get away from infering the generation from the
>> numerical chip-id.
>>
>> Signed-off-by: Rob Clark <robdclark@chromium.org>
>> ---
> [...]
>
>> .rev = ADRENO_REV(5, 0, 8, ANY_ID),
>> + .family = ADRENO_5XX,
>> .revn = 508,
> 508 is from 530 fam
>
>> .fw = {
>> [ADRENO_FW_PM4] = "a530_pm4.fw",
>> @@ -156,6 +168,7 @@ static const struct adreno_info gpulist[] = {
>> .zapfw = "a508_zap.mdt",
>> }, {
>> .rev = ADRENO_REV(5, 0, 9, ANY_ID),
>> + .family = ADRENO_5XX,
>> .revn = 509,
> 509 and 512 are from 540 fam
>
>> .fw = {
>> [ADRENO_FW_PM4] = "a530_pm4.fw",
>> @@ -173,6 +186,7 @@ static const struct adreno_info gpulist[] = {
>> .zapfw = "a512_zap.mdt",
>> }, {
>> .rev = ADRENO_REV(5, 1, 0, ANY_ID),
>> + .family = ADRENO_5XX,
>> .revn = 510,
> 510 is 530ish but I think it's closer to 505 or whatever the
> 8953 gpu was called
I'd say, there were following generations here:
- a505 / a506 / a508
- a509 / a512
- a510
- a530
- a540
Indeed a50x were close to a530 in some aspects and a509/512 being closer
to a540, but I don't think they were the same family.
>
> [...]
>
>> - priv->is_a2xx = config.rev.core == 2;
>> + priv->is_a2xx = info->family < ADRENO_3XX;
> is this variable even needed now that there are explicit family values?
>
> Konrad
>> priv->has_cached_coherent =
>> !!(info->quirks & ADRENO_QUIRK_HAS_CACHED_COHERENT);
>>
>> diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
>> index 2e62a7ce9f13..75ff7fb46099 100644
>> --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c
>> +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
>> @@ -1079,8 +1079,13 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev,
>> u32 speedbin;
>> int ret;
>>
>> + adreno_gpu->funcs = funcs;
>> + adreno_gpu->info = adreno_info(config->rev);
>> + adreno_gpu->rev = *rev;
>> +
>> /* Only handle the core clock when GMU is not in use (or is absent). */
>> - if (adreno_has_gmu_wrapper(adreno_gpu) || config->rev.core < 6) {
>> + if (adreno_has_gmu_wrapper(adreno_gpu) ||
>> + adreno_gpu->info->family < ADRENO_6XX_GEN1) {
>> /*
>> * This can only be done before devm_pm_opp_of_add_table(), or
>> * dev_pm_opp_set_config() will WARN_ON()
>> @@ -1096,10 +1101,6 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev,
>> devm_pm_opp_set_clkname(dev, "core");
>> }
>>
>> - adreno_gpu->funcs = funcs;
>> - adreno_gpu->info = adreno_info(config->rev);
>> - adreno_gpu->rev = *rev;
>> -
>> if (adreno_read_speedbin(dev, &speedbin) || !speedbin)
>> speedbin = 0xffff;
>> adreno_gpu->speedbin = (uint16_t) (0xffff & speedbin);
>> diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
>> index 6066cfaaea52..2fa14dcd4e40 100644
>> --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
>> +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
>> @@ -29,6 +29,25 @@ enum {
>> ADRENO_FW_MAX,
>> };
>>
>> +/**
>> + * @enum adreno_family: identify generation and possibly sub-generation
>> + *
>> + * In some cases there are distinct sub-generations within a major revision
>> + * so it helps to be able to group the GPU devices by generation and if
>> + * necessary sub-generation.
>> + */
>> +enum adreno_family {
>> + ADRENO_2XX_GEN1, /* a20x */
>> + ADRENO_2XX_GEN2, /* a22x */
>> + ADRENO_3XX,
>> + ADRENO_4XX,
>> + ADRENO_5XX,
>> + ADRENO_6XX_GEN1, /* a630 family */
>> + ADRENO_6XX_GEN2, /* a640 family */
>> + ADRENO_6XX_GEN3, /* a650 family */
>> + ADRENO_6XX_GEN4, /* a660 family */
>> +};
>> +
>> #define ADRENO_QUIRK_TWO_PASS_USE_WFI BIT(0)
>> #define ADRENO_QUIRK_FAULT_DETECT_MASK BIT(1)
>> #define ADRENO_QUIRK_LMLOADKILL_DISABLE BIT(2)
>> @@ -63,6 +82,7 @@ extern const struct adreno_reglist a660_hwcg[], a690_hwcg[];
>> struct adreno_info {
>> const char *machine;
>> struct adreno_rev rev;
>> + enum adreno_family family;
>> uint32_t revn;
>> const char *fw[ADRENO_FW_MAX];
>> uint32_t gmem;
>> @@ -188,14 +208,14 @@ static inline bool adreno_is_a2xx(const struct adreno_gpu *gpu)
>> {
>> if (WARN_ON_ONCE(!gpu->info))
>> return false;
>> - return (gpu->info->revn < 300);
>> + return gpu->info->family < ADRENO_2XX_GEN2;
>> }
>>
>> static inline bool adreno_is_a20x(const struct adreno_gpu *gpu)
>> {
>> if (WARN_ON_ONCE(!gpu->info))
>> return false;
>> - return (gpu->info->revn < 210);
>> + return gpu->info->family == ADRENO_2XX_GEN1;
>> }
>>
>> static inline bool adreno_is_a225(const struct adreno_gpu *gpu)
>> @@ -338,29 +358,31 @@ static inline int adreno_is_a690(const struct adreno_gpu *gpu)
>> /* check for a615, a616, a618, a619 or any a630 derivatives */
>> static inline int adreno_is_a630_family(const struct adreno_gpu *gpu)
>> {
>> - return adreno_is_revn(gpu, 630) ||
>> - adreno_is_revn(gpu, 615) ||
>> - adreno_is_revn(gpu, 616) ||
>> - adreno_is_revn(gpu, 618) ||
>> - adreno_is_revn(gpu, 619);
>> + if (WARN_ON_ONCE(!gpu->info))
>> + return false;
>> + return gpu->info->family == ADRENO_6XX_GEN1;
>> }
>>
>> static inline int adreno_is_a660_family(const struct adreno_gpu *gpu)
>> {
>> - return adreno_is_a660(gpu) || adreno_is_a690(gpu) || adreno_is_7c3(gpu);
>> + if (WARN_ON_ONCE(!gpu->info))
>> + return false;
>> + return gpu->info->family == ADRENO_6XX_GEN4;
>> }
>>
>> /* check for a650, a660, or any derivatives */
>> static inline int adreno_is_a650_family(const struct adreno_gpu *gpu)
>> {
>> - return adreno_is_revn(gpu, 650) ||
>> - adreno_is_revn(gpu, 620) ||
>> - adreno_is_a660_family(gpu);
>> + if (WARN_ON_ONCE(!gpu->info))
>> + return false;
>> + return gpu->info->family >= ADRENO_6XX_GEN3;
>> }
>>
>> static inline int adreno_is_a640_family(const struct adreno_gpu *gpu)
>> {
>> - return adreno_is_a640(gpu) || adreno_is_a680(gpu);
>> + if (WARN_ON_ONCE(!gpu->info))
>> + return false;
>> + return gpu->info->family == ADRENO_6XX_GEN2;
>> }
>>
>> u64 adreno_private_address_space_size(struct msm_gpu *gpu);
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 73+ messages in thread
* Re: [Freedreno] [PATCH 12/12] drm/msm/adreno: Switch to chip-id for identifying GPU
2023-07-06 21:10 ` [PATCH 12/12] drm/msm/adreno: Switch to chip-id for identifying GPU Rob Clark
2023-07-07 0:25 ` Konrad Dybcio
@ 2023-07-07 3:45 ` Dmitry Baryshkov
2023-07-13 21:39 ` Akhil P Oommen
2023-07-26 21:37 ` Rob Clark
1 sibling, 2 replies; 73+ messages in thread
From: Dmitry Baryshkov @ 2023-07-07 3:45 UTC (permalink / raw)
To: Rob Clark, dri-devel; +Cc: Konrad Dybcio, linux-arm-msm, Rob Clark, freedreno
On 07/07/2023 00:10, Rob Clark wrote:
> From: Rob Clark <robdclark@chromium.org>
>
> Since the revision becomes an opaque identifier with future GPUs, move
> away from treating different ranges of bits as having a given meaning.
> This means that we need to explicitly list different patch revisions in
> the device table.
>
> Signed-off-by: Rob Clark <robdclark@chromium.org>
> ---
> drivers/gpu/drm/msm/adreno/a4xx_gpu.c | 2 +-
> drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 11 +-
> drivers/gpu/drm/msm/adreno/a5xx_power.c | 2 +-
> drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 13 ++-
> drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 9 +-
> drivers/gpu/drm/msm/adreno/adreno_device.c | 128 ++++++++++-----------
> drivers/gpu/drm/msm/adreno/adreno_gpu.c | 16 +--
> drivers/gpu/drm/msm/adreno/adreno_gpu.h | 51 ++++----
> 8 files changed, 122 insertions(+), 110 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/adreno/a4xx_gpu.c b/drivers/gpu/drm/msm/adreno/a4xx_gpu.c
> index 715436cb3996..8b4cdf95f445 100644
> --- a/drivers/gpu/drm/msm/adreno/a4xx_gpu.c
> +++ b/drivers/gpu/drm/msm/adreno/a4xx_gpu.c
> @@ -145,7 +145,7 @@ static void a4xx_enable_hwcg(struct msm_gpu *gpu)
> gpu_write(gpu, REG_A4XX_RBBM_CLOCK_DELAY_HLSQ, 0x00220000);
> /* Early A430's have a timing issue with SP/TP power collapse;
> disabling HW clock gating prevents it. */
> - if (adreno_is_a430(adreno_gpu) && adreno_gpu->rev.patchid < 2)
> + if (adreno_is_a430(adreno_gpu) && adreno_patchid(adreno_gpu) < 2)
> gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL, 0);
> else
> gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL, 0xAAAAAAAA);
> diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
> index f0803e94ebe5..70d2b5342cd9 100644
> --- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
> +++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
> @@ -1744,6 +1744,7 @@ struct msm_gpu *a5xx_gpu_init(struct drm_device *dev)
> struct msm_drm_private *priv = dev->dev_private;
> struct platform_device *pdev = priv->gpu_pdev;
> struct adreno_platform_config *config = pdev->dev.platform_data;
> + const struct adreno_info *info;
> struct a5xx_gpu *a5xx_gpu = NULL;
> struct adreno_gpu *adreno_gpu;
> struct msm_gpu *gpu;
> @@ -1770,7 +1771,15 @@ struct msm_gpu *a5xx_gpu_init(struct drm_device *dev)
>
> nr_rings = 4;
>
> - if (adreno_cmp_rev(ADRENO_REV(5, 1, 0, ANY_ID), config->rev))
> + /*
> + * Note that we wouldn't have been able to get this far if there is not
> + * a device table entry for this chip_id
> + */
> + info = adreno_find_info(config->chip_id);
> + if (WARN_ON(!info))
> + return ERR_PTR(-EINVAL);
> +
> + if (info->revn == 510)
> nr_rings = 1;
>
> ret = adreno_gpu_init(dev, pdev, adreno_gpu, &funcs, nr_rings);
> diff --git a/drivers/gpu/drm/msm/adreno/a5xx_power.c b/drivers/gpu/drm/msm/adreno/a5xx_power.c
> index 0e63a1429189..7705f8010484 100644
> --- a/drivers/gpu/drm/msm/adreno/a5xx_power.c
> +++ b/drivers/gpu/drm/msm/adreno/a5xx_power.c
> @@ -179,7 +179,7 @@ static void a540_lm_setup(struct msm_gpu *gpu)
>
> /* The battery current limiter isn't enabled for A540 */
> config = AGC_LM_CONFIG_BCL_DISABLED;
> - config |= adreno_gpu->rev.patchid << AGC_LM_CONFIG_GPU_VERSION_SHIFT;
> + config |= adreno_patchid(adreno_gpu) << AGC_LM_CONFIG_GPU_VERSION_SHIFT;
>
> /* For now disable GPMU side throttling */
> config |= AGC_LM_CONFIG_THROTTLE_DISABLE;
> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
> index f1bb20574018..a9ba547a120c 100644
> --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
> @@ -790,10 +790,15 @@ static int a6xx_gmu_fw_start(struct a6xx_gmu *gmu, unsigned int state)
> gmu_write(gmu, REG_A6XX_GMU_AHB_FENCE_RANGE_0,
> (1 << 31) | (0xa << 18) | (0xa0));
>
> - chipid = adreno_gpu->rev.core << 24;
> - chipid |= adreno_gpu->rev.major << 16;
> - chipid |= adreno_gpu->rev.minor << 12;
> - chipid |= adreno_gpu->rev.patchid << 8;
> + /* Note that the GMU has a slightly different layout for
> + * chip_id, for whatever reason, so a bit of massaging
> + * is needed. The upper 16b are the same, but minor and
> + * patchid are packed in four bits each with the lower
> + * 8b unused:
> + */
> + chipid = adreno_gpu->chip_id & 0xffff0000;
> + chipid |= (adreno_gpu->chip_id << 4) & 0xf000; /* minor */
> + chipid |= (adreno_gpu->chip_id << 8) & 0x0f00; /* patchid */
I'd beg for explicit FIELD_GET and FIELD_PREP here.
>
> gmu_write(gmu, REG_A6XX_GMU_HFI_SFR_ADDR, chipid);
>
> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> index 77b23c004b94..ed075729ca09 100644
> --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> @@ -2344,10 +2344,13 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev)
> /*
> * We need to know the platform type before calling into adreno_gpu_init
> * so that the hw_apriv flag can be correctly set. Snoop into the info
> - * and grab the revision number
> + * and grab the revision number.
> + *
> + * Note that we wouldn't have been able to get this far if there is not
> + * a device table entry for this chip_id
Having seen this note twice, shouldn't we explicitly pass adreno_info to
our aNxx_gpu_init() functions and then further to adreno_gpu_init()?
> */
> - info = adreno_info(config->rev);
> - if (!info)
> + info = adreno_find_info(config->chip_id);
> + if (WARN_ON(!info))
> return ERR_PTR(-EINVAL);
>
> adreno_gpu->base.hw_apriv = !!(info->quirks & ADRENO_QUIRK_HAS_HW_APRIV);
> diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c
> index fd2e183bce60..4a718ff33635 100644
> --- a/drivers/gpu/drm/msm/adreno/adreno_device.c
> +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c
> @@ -22,7 +22,7 @@ module_param_named(allow_vram_carveout, allow_vram_carveout, bool, 0600);
>
> static const struct adreno_info gpulist[] = {
> {
> - .rev = ADRENO_REV(2, 0, 0, 0),
> + .chip_ids = ADRENO_CHIP_IDS(0x02000000),
This begs to use bit masks, but see below
> .family = ADRENO_2XX_GEN1,
> .revn = 200,
> .fw = {
[skipped]
> @@ -77,7 +77,11 @@ static const struct adreno_info gpulist[] = {
> .inactive_period = DRM_MSM_INACTIVE_PERIOD,
> .init = a3xx_gpu_init,
> }, {
> - .rev = ADRENO_REV(3, 2, ANY_ID, ANY_ID),
> + .chip_ids = ADRENO_CHIP_IDS(
> + 0x03020000,
> + 0x03020001,
> + 0x03020002
definitely a bitmask would help
> + ),
> .family = ADRENO_3XX,
> .revn = 320,
> .fw = {
[skipped the rest]
> @@ -494,31 +502,16 @@ MODULE_FIRMWARE("qcom/a630_sqe.fw");
> MODULE_FIRMWARE("qcom/a630_gmu.bin");
> MODULE_FIRMWARE("qcom/a630_zap.mbn");
>
> -static inline bool _rev_match(uint8_t entry, uint8_t id)
> -{
> - return (entry == ANY_ID) || (entry == id);
> -}
> -
> -bool adreno_cmp_rev(struct adreno_rev rev1, struct adreno_rev rev2)
> -{
> -
> - return _rev_match(rev1.core, rev2.core) &&
> - _rev_match(rev1.major, rev2.major) &&
> - _rev_match(rev1.minor, rev2.minor) &&
> - _rev_match(rev1.patchid, rev2.patchid);
> -}
> -
> -const struct adreno_info *adreno_info(struct adreno_rev rev)
> +const struct adreno_info *adreno_find_info(uint32_t chip_id)
> {
> - int i;
> -
> /* identify gpu: */
> - for (i = 0; i < ARRAY_SIZE(gpulist); i++) {
> + for (int i = 0; i < ARRAY_SIZE(gpulist); i++) {
> const struct adreno_info *info = &gpulist[i];
> if (info->machine && !of_machine_is_compatible(info->machine))
> continue;
> - if (adreno_cmp_rev(info->rev, rev))
> - return info;
> + for (int j = 0; info->chip_ids[j]; j++)
> + if (info->chip_ids[j] == chip_id)
> + return info;
> }
>
> return NULL;
> @@ -598,12 +591,11 @@ struct msm_gpu *adreno_load_gpu(struct drm_device *dev)
> return NULL;
> }
>
> -static int find_chipid(struct device *dev, struct adreno_rev *rev)
> +static int find_chipid(struct device *dev, uint32_t *chipid)
> {
> struct device_node *node = dev->of_node;
> const char *compat;
> int ret;
> - u32 chipid;
>
> /* first search the compat strings for qcom,adreno-XYZ.W: */
> ret = of_property_read_string_index(node, "compatible", 0, &compat);
> @@ -612,32 +604,34 @@ static int find_chipid(struct device *dev, struct adreno_rev *rev)
>
> if (sscanf(compat, "qcom,adreno-%u.%u", &r, &patch) == 2 ||
> sscanf(compat, "amd,imageon-%u.%u", &r, &patch) == 2) {
> - rev->core = r / 100;
> + uint32_t core, major, minor;
> +
> + core = r / 100;
> r %= 100;
> - rev->major = r / 10;
> + major = r / 10;
> r %= 10;
> - rev->minor = r;
> - rev->patchid = patch;
> + minor = r;
> +
> + *chipid = (core << 24) |
> + (major << 16) |
> + (minor << 8) |
> + patch;
This starts to look realy crazy. I'd repeat my suggestion of moving
towards of_device match data. This would result in some duplication,
we'd have to explicitly list all supported compatibles in the
of_match_table. But then we can drop all the CHIPID lists from device
table and/or manual parsing of the chipid from the compat field.
This way we can have per-SoC overrides, etc.
>
> return 0;
> }
> +
> + if (sscanf(compat, "qcom,adreno-%08x", chipid) == 1)
> + return 0;
> }
>
> /* and if that fails, fall back to legacy "qcom,chipid" property: */
> - ret = of_property_read_u32(node, "qcom,chipid", &chipid);
> + ret = of_property_read_u32(node, "qcom,chipid", chipid);
> if (ret) {
> DRM_DEV_ERROR(dev, "could not parse qcom,chipid: %d\n", ret);
> return ret;
> }
>
> - rev->core = (chipid >> 24) & 0xff;
> - rev->major = (chipid >> 16) & 0xff;
> - rev->minor = (chipid >> 8) & 0xff;
> - rev->patchid = (chipid & 0xff);
> -
> dev_warn(dev, "Using legacy qcom,chipid binding!\n");
> - dev_warn(dev, "Use compatible qcom,adreno-%u%u%u.%u instead.\n",
> - rev->core, rev->major, rev->minor, rev->patchid);
>
> return 0;
> }
> @@ -651,22 +645,22 @@ static int adreno_bind(struct device *dev, struct device *master, void *data)
> struct msm_gpu *gpu;
> int ret;
>
> - ret = find_chipid(dev, &config.rev);
> + ret = find_chipid(dev, &config.chip_id);
> if (ret)
> return ret;
>
> dev->platform_data = &config;
> priv->gpu_pdev = to_platform_device(dev);
>
> - info = adreno_info(config.rev);
> + info = adreno_find_info(config.chip_id);
>
> if (!info) {
> dev_warn(drm->dev, "Unknown GPU revision: %"ADRENO_CHIPID_FMT"\n",
> - ADRENO_CHIPID_ARGS(config.rev));
> + ADRENO_CHIPID_ARGS(config.chip_id));
> return -ENXIO;
> }
>
> - DBG("Found GPU: %"ADRENO_CHIPID_FMT, ADRENO_CHIPID_ARGS(config.rev));
> + DBG("Found GPU: %"ADRENO_CHIPID_FMT, ADRENO_CHIPID_ARGS(config.chip_id));
>
> priv->is_a2xx = info->family < ADRENO_3XX;
> priv->has_cached_coherent =
> diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
> index 1a982a926f21..1274609a74b1 100644
> --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c
> +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
> @@ -326,10 +326,7 @@ int adreno_get_param(struct msm_gpu *gpu, struct msm_file_private *ctx,
> *value = !adreno_is_a650_family(adreno_gpu) ? 0x100000 : 0;
> return 0;
> case MSM_PARAM_CHIP_ID:
> - *value = (uint64_t)adreno_gpu->rev.patchid |
> - ((uint64_t)adreno_gpu->rev.minor << 8) |
> - ((uint64_t)adreno_gpu->rev.major << 16) |
> - ((uint64_t)adreno_gpu->rev.core << 24);
> + *value = adreno_gpu->chip_id;
> if (!adreno_gpu->info->revn)
> *value |= ((uint64_t) adreno_gpu->speedbin) << 32;
> return 0;
> @@ -849,7 +846,7 @@ void adreno_show(struct msm_gpu *gpu, struct msm_gpu_state *state,
>
> drm_printf(p, "revision: %u (%"ADRENO_CHIPID_FMT")\n",
> adreno_gpu->info->revn,
> - ADRENO_CHIPID_ARGS(adreno_gpu->rev));
> + ADRENO_CHIPID_ARGS(adreno_gpu->chip_id));
> /*
> * If this is state collected due to iova fault, so fault related info
> *
> @@ -922,7 +919,7 @@ void adreno_dump_info(struct msm_gpu *gpu)
>
> printk("revision: %u (%"ADRENO_CHIPID_FMT")\n",
> adreno_gpu->info->revn,
> - ADRENO_CHIPID_ARGS(adreno_gpu->rev));
> + ADRENO_CHIPID_ARGS(adreno_gpu->chip_id));
>
> for (i = 0; i < gpu->nr_rings; i++) {
> struct msm_ringbuffer *ring = gpu->rb[i];
> @@ -1072,14 +1069,13 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev,
> struct adreno_platform_config *config = dev->platform_data;
> struct msm_gpu_config adreno_gpu_config = { 0 };
> struct msm_gpu *gpu = &adreno_gpu->base;
> - struct adreno_rev *rev = &config->rev;
> const char *gpu_name;
> u32 speedbin;
> int ret;
>
> adreno_gpu->funcs = funcs;
> - adreno_gpu->info = adreno_info(config->rev);
> - adreno_gpu->rev = *rev;
> + adreno_gpu->info = adreno_find_info(config->chip_id);
> + adreno_gpu->chip_id = config->chip_id;
>
> /* Only handle the core clock when GMU is not in use (or is absent). */
> if (adreno_has_gmu_wrapper(adreno_gpu) ||
> @@ -1104,7 +1100,7 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev,
> adreno_gpu->speedbin = (uint16_t) (0xffff & speedbin);
>
> gpu_name = devm_kasprintf(dev, GFP_KERNEL, "%"ADRENO_CHIPID_FMT,
> - ADRENO_CHIPID_ARGS(config->rev));
> + ADRENO_CHIPID_ARGS(config->chip_id));
> if (!gpu_name)
> return -ENOMEM;
>
> diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> index 73e7155f164c..18f53c7ab589 100644
> --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> @@ -54,23 +54,15 @@ enum adreno_family {
> #define ADRENO_QUIRK_HAS_HW_APRIV BIT(3)
> #define ADRENO_QUIRK_HAS_CACHED_COHERENT BIT(4)
>
> -struct adreno_rev {
> - uint8_t core;
> - uint8_t major;
> - uint8_t minor;
> - uint8_t patchid;
> -};
> -
> -#define ANY_ID 0xff
> -
> -#define ADRENO_REV(core, major, minor, patchid) \
> - ((struct adreno_rev){ core, major, minor, patchid })
> -
> /* Helper for formating the chip_id in the way that userspace tools like
> * crashdec expect.
> */
> #define ADRENO_CHIPID_FMT "u.%u.%u.%u"
> -#define ADRENO_CHIPID_ARGS(_r) (_r).core, (_r).major, (_r).minor, (_r).patchid
> +#define ADRENO_CHIPID_ARGS(_c) \
> + (((_c) >> 24) & 0xff), \
> + (((_c) >> 16) & 0xff), \
> + (((_c) >> 8) & 0xff), \
> + ((_c) & 0xff)
So, we still have some meaning for chipid?
>
> struct adreno_gpu_funcs {
> struct msm_gpu_funcs base;
> @@ -87,7 +79,12 @@ extern const struct adreno_reglist a660_hwcg[], a690_hwcg[];
>
> struct adreno_info {
> const char *machine;
> - struct adreno_rev rev;
> + /**
> + * @chipids: Table of matching chip-ids
> + *
> + * Terminated with 0 sentinal
> + */
> + uint32_t *chip_ids;
> enum adreno_family family;
> uint32_t revn;
> const char *fw[ADRENO_FW_MAX];
> @@ -107,6 +104,8 @@ struct adreno_info {
> uint32_t *speedbins;
> };
>
> +#define ADRENO_CHIP_IDS(tbl...) (uint32_t[]) { tbl, 0 }
> +
> /*
> * Helper to build a speedbin table, ie. the table:
> * fuse | speedbin
> @@ -125,12 +124,12 @@ struct adreno_info {
> */
> #define ADRENO_SPEEDBINS(tbl...) (uint32_t[]) { tbl, UINT_MAX }
>
> -const struct adreno_info *adreno_info(struct adreno_rev rev);
> +const struct adreno_info *adreno_find_info(uint32_t chip_id);
>
> struct adreno_gpu {
> struct msm_gpu base;
> - struct adreno_rev rev;
> const struct adreno_info *info;
> + uint32_t chip_id;
> uint16_t speedbin;
> const struct adreno_gpu_funcs *funcs;
>
> @@ -179,7 +178,7 @@ struct adreno_ocmem {
>
> /* platform config data (ie. from DT, or pdata) */
> struct adreno_platform_config {
> - struct adreno_rev rev;
> + uint32_t chip_id;
> };
>
> #define ADRENO_IDLE_TIMEOUT msecs_to_jiffies(1000)
> @@ -196,7 +195,15 @@ struct adreno_platform_config {
> __ret; \
> })
>
> -bool adreno_cmp_rev(struct adreno_rev rev1, struct adreno_rev rev2);
> +static inline uint8_t adreno_patchid(const struct adreno_gpu *gpu)
> +{
> + /* It is probably ok to assume legacy "adreno_rev" format
> + * for all a6xx devices, but probably best to limit this
> + * to older things.
> + */
> + WARN_ON_ONCE(gpu->info->family >= ADRENO_6XX_GEN1);
> + return gpu->chip_id & 0xff;
> +}
>
> static inline bool adreno_is_revn(const struct adreno_gpu *gpu, uint32_t revn)
> {
> @@ -252,7 +259,7 @@ static inline bool adreno_is_a330(const struct adreno_gpu *gpu)
>
> static inline bool adreno_is_a330v2(const struct adreno_gpu *gpu)
> {
> - return adreno_is_a330(gpu) && (gpu->rev.patchid > 0);
> + return adreno_is_a330(gpu) && (adreno_patchid(gpu) > 0);
> }
>
> static inline int adreno_is_a405(const struct adreno_gpu *gpu)
> @@ -342,8 +349,7 @@ static inline int adreno_is_a650(const struct adreno_gpu *gpu)
>
> static inline int adreno_is_7c3(const struct adreno_gpu *gpu)
> {
> - /* The order of args is important here to handle ANY_ID correctly */
> - return adreno_cmp_rev(ADRENO_REV(6, 3, 5, ANY_ID), gpu->rev);
> + return gpu->info->chip_ids[0] == 0x06030500;
Ugh. The thing that bugs me isn't even the manual comparison of
chip_ids[0], but the fact that these two platforms stand aside. I think
at the end we should have a single mechanism for checking GPU's SKUs.
Or maybe we should get rid of that completely.
If we get rid of a single gpulist table and move individual GPU info
definitions to aNxx_gpu.c, we can subclass a generic info structure with
generation-specific data, for example generation-specific quirks,
pointers to hcwg or VBIF registers, etc. And then instead of having
adreno_is_foo all over the code we can migrate most of these checks to
data in the gpu info data.
> }
>
> static inline int adreno_is_a660(const struct adreno_gpu *gpu)
> @@ -358,8 +364,7 @@ static inline int adreno_is_a680(const struct adreno_gpu *gpu)
>
> static inline int adreno_is_a690(const struct adreno_gpu *gpu)
> {
> - /* The order of args is important here to handle ANY_ID correctly */
> - return adreno_cmp_rev(ADRENO_REV(6, 9, 0, ANY_ID), gpu->rev);
> + return gpu->info->chip_ids[0] == 0x06090000;
> };
> /* check for a615, a616, a618, a619 or any a630 derivatives */
> static inline int adreno_is_a630_family(const struct adreno_gpu *gpu)
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 73+ messages in thread
* Re: [PATCH 11/12] dt-bindings: drm/msm/gpu: Extend bindings for chip-id
2023-07-06 21:10 ` [PATCH 11/12] dt-bindings: drm/msm/gpu: Extend bindings for chip-id Rob Clark
@ 2023-07-07 7:26 ` Krzysztof Kozlowski
2023-07-07 13:09 ` Rob Clark
0 siblings, 1 reply; 73+ messages in thread
From: Krzysztof Kozlowski @ 2023-07-07 7:26 UTC (permalink / raw)
To: Rob Clark, dri-devel; +Cc: Konrad Dybcio, linux-arm-msm, Rob Clark, freedreno
On 06/07/2023 23:10, Rob Clark wrote:
> From: Rob Clark <robdclark@chromium.org>
>
> Upcoming GPUs use an opaque chip-id for identifying the GPU.
Please use scripts/get_maintainers.pl to get a list of necessary people
and lists to CC. It might happen, that command when run on an older
kernel, gives you outdated entries. Therefore please be sure you base
your patches on recent Linux kernel.
You missed at least DT list (maybe more), so this won't be tested by
automated tooling. Performing review on untested code might be a waste
of time, thus I will skip this patch entirely till you follow the
process allowing the patch to be tested.
Please kindly resend and include all necessary To/Cc entries.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 73+ messages in thread
* Re: [PATCH 11/12] dt-bindings: drm/msm/gpu: Extend bindings for chip-id
2023-07-07 7:26 ` Krzysztof Kozlowski
@ 2023-07-07 13:09 ` Rob Clark
0 siblings, 0 replies; 73+ messages in thread
From: Rob Clark @ 2023-07-07 13:09 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Konrad Dybcio, linux-arm-msm, Rob Clark, freedreno, dri-devel
On Fri, Jul 7, 2023 at 12:26 AM Krzysztof Kozlowski <krzk@kernel.org> wrote:
>
> On 06/07/2023 23:10, Rob Clark wrote:
> > From: Rob Clark <robdclark@chromium.org>
> >
> > Upcoming GPUs use an opaque chip-id for identifying the GPU.
>
> Please use scripts/get_maintainers.pl to get a list of necessary people
> and lists to CC. It might happen, that command when run on an older
> kernel, gives you outdated entries. Therefore please be sure you base
> your patches on recent Linux kernel.
Oh, whoops, I'd overlooked that I hadn't configured sendemail.cccmd on
the laptop I was sending this from. I'll fix that before resending.
BR,
-R
> You missed at least DT list (maybe more), so this won't be tested by
> automated tooling. Performing review on untested code might be a waste
> of time, thus I will skip this patch entirely till you follow the
> process allowing the patch to be tested.
>
> Please kindly resend and include all necessary To/Cc entries.
>
> Best regards,
> Krzysztof
>
^ permalink raw reply [flat|nested] 73+ messages in thread
* Re: [Freedreno] [PATCH 05/12] drm/msm/adreno: Use quirk to identify cached-coherent support
2023-07-07 2:29 ` [Freedreno] " Dmitry Baryshkov
@ 2023-07-07 15:53 ` Rob Clark
0 siblings, 0 replies; 73+ messages in thread
From: Rob Clark @ 2023-07-07 15:53 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Konrad Dybcio, linux-arm-msm, Rob Clark, freedreno, dri-devel
On Thu, Jul 6, 2023 at 7:29 PM Dmitry Baryshkov
<dmitry.baryshkov@linaro.org> wrote:
>
> On 07/07/2023 00:10, Rob Clark wrote:
> > From: Rob Clark <robdclark@chromium.org>
> >
> > It is better to explicitly list it. With the move to opaque chip-id's
> > for future devices, we should avoid trying to infer things like
> > generation from the numerical value.
>
> Would it be better to push this to DT? I mean, we already have a
> 'dma-cache-coherent' property for it.
I suppose that would also handle the case where some a6xy are coherent
but others aren't.. OTOH it isn't the case that dma operations are
coherent, just that they can be. It depends on smmu pte bits. Maybe
that bit of pedanticism doesn't matter since we mostly bypass the dma
api, but we still do need to (ab)use dma_map_sgtable/dma_unmap_sgtable
for cache ops
BR,
-R
> >
> > Signed-off-by: Rob Clark <robdclark@chromium.org>
> > ---
> > drivers/gpu/drm/msm/adreno/adreno_device.c | 23 +++++++++++++++-------
> > drivers/gpu/drm/msm/adreno/adreno_gpu.h | 1 +
> > 2 files changed, 17 insertions(+), 7 deletions(-)
> >
>
> --
> With best wishes
> Dmitry
>
^ permalink raw reply [flat|nested] 73+ messages in thread
* Re: [PATCH 12/12] drm/msm/adreno: Switch to chip-id for identifying GPU
2023-07-07 0:25 ` Konrad Dybcio
@ 2023-07-07 16:08 ` Rob Clark
2023-07-15 13:38 ` Konrad Dybcio
0 siblings, 1 reply; 73+ messages in thread
From: Rob Clark @ 2023-07-07 16:08 UTC (permalink / raw)
To: Konrad Dybcio; +Cc: Rob Clark, linux-arm-msm, freedreno, dri-devel
On Thu, Jul 6, 2023 at 5:25 PM Konrad Dybcio <konrad.dybcio@linaro.org> wrote:
>
> On 6.07.2023 23:10, Rob Clark wrote:
> > From: Rob Clark <robdclark@chromium.org>
> >
> > Since the revision becomes an opaque identifier with future GPUs, move
> > away from treating different ranges of bits as having a given meaning.
> > This means that we need to explicitly list different patch revisions in
> > the device table.
> >
> > Signed-off-by: Rob Clark <robdclark@chromium.org>
> > ---
> [...]
>
> >
> > - if (adreno_cmp_rev(ADRENO_REV(5, 1, 0, ANY_ID), config->rev))
> > + /*
> > + * Note that we wouldn't have been able to get this far if there is not
> > + * a device table entry for this chip_id
> > + */
> Why error-check it then?
>
> > + info = adreno_find_info(config->chip_id);
> > + if (WARN_ON(!info))
> > + return ERR_PTR(-EINVAL);
> > +
> > + if (info->revn == 510)
> > nr_rings = 1;
> [...]
>
> >
> > - chipid = adreno_gpu->rev.core << 24;
> > - chipid |= adreno_gpu->rev.major << 16;
> > - chipid |= adreno_gpu->rev.minor << 12;
> > - chipid |= adreno_gpu->rev.patchid << 8;
> > + /* Note that the GMU has a slightly different layout for
>
> /*
> * Note
>
> You've almost joined the good side :D
> > + * chip_id, for whatever reason, so a bit of massaging
> > + * is needed. The upper 16b are the same, but minor and
> > + * patchid are packed in four bits each with the lower
> > + * 8b unused:
> > + */
> [...]
>
> > - .rev = ADRENO_REV(3, 0, 5, ANY_ID),
> > + .chip_ids = ADRENO_CHIP_IDS(0x03000500),
>
> 0x03000512 for msm8226-v2
> 0x03000520 for msm8610
>
> > .family = ADRENO_3XX,
> > .revn = 305,
> > .fw = {
> > @@ -66,7 +66,7 @@ static const struct adreno_info gpulist[] = {
> > .inactive_period = DRM_MSM_INACTIVE_PERIOD,
> > .init = a3xx_gpu_init,
> > }, {
> > - .rev = ADRENO_REV(3, 0, 6, 0),
> > + .chip_ids = ADRENO_CHIP_IDS(0x03000600),
> > .family = ADRENO_3XX,
> > .revn = 307, /* because a305c is revn==306 */
> > .fw = {
> > @@ -77,7 +77,11 @@ static const struct adreno_info gpulist[] = {
> > .inactive_period = DRM_MSM_INACTIVE_PERIOD,
> > .init = a3xx_gpu_init,
> > }, {
> > - .rev = ADRENO_REV(3, 2, ANY_ID, ANY_ID),
> > + .chip_ids = ADRENO_CHIP_IDS(
> > + 0x03020000,
> > + 0x03020001,
> > + 0x03020002
> > + ),
> > .family = ADRENO_3XX,
> > .revn = 320,
> > .fw = {
> > @@ -88,7 +92,11 @@ static const struct adreno_info gpulist[] = {
> > .inactive_period = DRM_MSM_INACTIVE_PERIOD,
> > .init = a3xx_gpu_init,
> > }, {
> > - .rev = ADRENO_REV(3, 3, 0, ANY_ID),
> > + .chip_ids = ADRENO_CHIP_IDS(
> > + 0x03030000,
> drop, prototype broken hw
> (I think there are also some specific codepaths for that junk,
> let's rid them too)
>
> > + 0x03030001,
> v2 prod
>
> > + 0x03030002
> msm8974pro
>
> > + ),
> > .family = ADRENO_3XX,
> > .revn = 330,
> > .fw = {
> > @@ -99,7 +107,7 @@ static const struct adreno_info gpulist[] = {
> > .inactive_period = DRM_MSM_INACTIVE_PERIOD,
> > .init = a3xx_gpu_init,
> > }, {
> > - .rev = ADRENO_REV(4, 0, 5, ANY_ID),
> > + .chip_ids = ADRENO_CHIP_IDS(0x04000500),
> 0x04000500 msm8939
> 0x04000510 msm8952 (unsupported today)
>
> > .family = ADRENO_4XX,
> > .revn = 405,
> > .fw = {
> > @@ -110,7 +118,7 @@ static const struct adreno_info gpulist[] = {
> > .inactive_period = DRM_MSM_INACTIVE_PERIOD,
> > .init = a4xx_gpu_init,
> > }, {
> > - .rev = ADRENO_REV(4, 2, 0, ANY_ID),
> > + .chip_ids = ADRENO_CHIP_IDS(0x04020000),
> msm8992, ok
>
> > .family = ADRENO_4XX,
> > .revn = 420,
> > .fw = {
> > @@ -121,7 +129,7 @@ static const struct adreno_info gpulist[] = {
> > .inactive_period = DRM_MSM_INACTIVE_PERIOD,
> > .init = a4xx_gpu_init,
> > }, {
> > - .rev = ADRENO_REV(4, 3, 0, ANY_ID),
> > + .chip_ids = ADRENO_CHIP_IDS(0x04030000),
> 0x04030002 msm8994-v2.1, earlier revs are probably trash piles held
> together with duct tape knowing the track record of that soc
>
> > .family = ADRENO_4XX,
> > .revn = 430,
> > .fw = {
> > @@ -132,7 +140,7 @@ static const struct adreno_info gpulist[] = {
> > .inactive_period = DRM_MSM_INACTIVE_PERIOD,
> > .init = a4xx_gpu_init,
> > }, {
> > - .rev = ADRENO_REV(5, 0, 6, ANY_ID),
> > + .chip_ids = ADRENO_CHIP_IDS(0x05000600),
> msm8953 ok
>
> > .family = ADRENO_5XX,
> > .revn = 506,
> > .fw = {
> > @@ -150,7 +158,7 @@ static const struct adreno_info gpulist[] = {
> > .init = a5xx_gpu_init,
> > .zapfw = "a506_zap.mdt",
> > }, {
> > - .rev = ADRENO_REV(5, 0, 8, ANY_ID),
> > + .chip_ids = ADRENO_CHIP_IDS(0x05000800),
> 630 ok
>
> > .family = ADRENO_5XX,
> > .revn = 508,
> > .fw = {
> > @@ -167,7 +175,7 @@ static const struct adreno_info gpulist[] = {
> > .init = a5xx_gpu_init,
> > .zapfw = "a508_zap.mdt",
> > }, {
> > - .rev = ADRENO_REV(5, 0, 9, ANY_ID),
> > + .chip_ids = ADRENO_CHIP_IDS(0x05000900),
> 636 ok
>
> > .family = ADRENO_5XX,
> > .revn = 509,
> > .fw = {
> > @@ -185,7 +193,7 @@ static const struct adreno_info gpulist[] = {
> > /* Adreno 509 uses the same ZAP as 512 */
> > .zapfw = "a512_zap.mdt",
> > }, {
> > - .rev = ADRENO_REV(5, 1, 0, ANY_ID),
> > + .chip_ids = ADRENO_CHIP_IDS(0x05010000),
> 8976 ok
>
> > .family = ADRENO_5XX,
> > .revn = 510,
> > .fw = {
> > @@ -200,7 +208,7 @@ static const struct adreno_info gpulist[] = {
> > .inactive_period = 250,
> > .init = a5xx_gpu_init,
> > }, {
> > - .rev = ADRENO_REV(5, 1, 2, ANY_ID),
> > + .chip_ids = ADRENO_CHIP_IDS(0x05010200),
> 660 ok
>
> > .family = ADRENO_5XX,
> > .revn = 512,
> > .fw = {
> > @@ -217,7 +225,7 @@ static const struct adreno_info gpulist[] = {
> > .init = a5xx_gpu_init,
> > .zapfw = "a512_zap.mdt",
> > }, {
> > - .rev = ADRENO_REV(5, 3, 0, 2),
> > + .chip_ids = ADRENO_CHIP_IDS(0x05030002),
> 8996 final
>
> 0x05030004 8996pro
>
> > .family = ADRENO_5XX,
> > .revn = 530,
> > .fw = {
> > @@ -236,7 +244,7 @@ static const struct adreno_info gpulist[] = {
> > .init = a5xx_gpu_init,
> > .zapfw = "a530_zap.mdt",
> > }, {
> > - .rev = ADRENO_REV(5, 4, 0, ANY_ID),
> > + .chip_ids = ADRENO_CHIP_IDS(0x05040001),
> 8998 final ok
>
> > .family = ADRENO_5XX,
> > .revn = 540,
> > .fw = {
> > @@ -254,7 +262,7 @@ static const struct adreno_info gpulist[] = {
> > .init = a5xx_gpu_init,
> > .zapfw = "a540_zap.mdt",
> > }, {
> > - .rev = ADRENO_REV(6, 1, 0, ANY_ID),
> > + .chip_ids = ADRENO_CHIP_IDS(0x06010000),
> sm6125 ok
> sm6115 ok
>
> [...]
> > }, {
> > - .rev = ADRENO_REV(6, 3, 0, ANY_ID),
> > + .chip_ids = ADRENO_CHIP_IDS(0x06030002),
> my sources say that it should end in 1 for sdm845-v2 and newer
>
> > .family = ADRENO_6XX_GEN1,
> > .revn = 630,
> > .fw = {
> > @@ -370,7 +378,7 @@ static const struct adreno_info gpulist[] = {
> > .zapfw = "a630_zap.mdt",
> > .hwcg = a630_hwcg,
> > }, {
> > - .rev = ADRENO_REV(6, 4, 0, ANY_ID),
> > + .chip_ids = ADRENO_CHIP_IDS(0x06040001),
> 8150 ok
>
> > .family = ADRENO_6XX_GEN2,
> > .revn = 640,
> > .fw = {
> > @@ -388,7 +396,7 @@ static const struct adreno_info gpulist[] = {
> > 1, 1
> > ),
> > }, {
> > - .rev = ADRENO_REV(6, 5, 0, ANY_ID),
> > + .chip_ids = ADRENO_CHIP_IDS(0x06050002),
> 8250-v2.1 ok
>
> > .family = ADRENO_6XX_GEN3,
> > .revn = 650,
> > .fw = {
> > @@ -410,7 +418,7 @@ static const struct adreno_info gpulist[] = {
> > 3, 2
> > ),
> > }, {
> > - .rev = ADRENO_REV(6, 6, 0, ANY_ID),
> > + .chip_ids = ADRENO_CHIP_IDS(0x06060001),
> 8350-v2 ok
>
> > .family = ADRENO_6XX_GEN4,
> > .revn = 660,
> > .fw = {
> > @@ -426,7 +434,7 @@ static const struct adreno_info gpulist[] = {
> > .hwcg = a660_hwcg,
> > .address_space_size = SZ_16G,
> > }, {
> > - .rev = ADRENO_REV(6, 3, 5, ANY_ID),
> > + .chip_ids = ADRENO_CHIP_IDS(0x06030500),
> 7280 ok
>
> > .family = ADRENO_6XX_GEN4,
> > .fw = {
> > [ADRENO_FW_SQE] = "a660_sqe.fw",
> > @@ -445,7 +453,7 @@ static const struct adreno_info gpulist[] = {
> > 190, 1
> > ),
> > }, {
> > - .rev = ADRENO_REV(6, 8, 0, ANY_ID),
> > + .chip_ids = ADRENO_CHIP_IDS(0x06080000),
> 8180 probably ok
>
> > .family = ADRENO_6XX_GEN2,
> > .revn = 680,
> > .fw = {
> > @@ -459,7 +467,7 @@ static const struct adreno_info gpulist[] = {
> > .zapfw = "a640_zap.mdt",
> > .hwcg = a640_hwcg,
> > }, {
> > - .rev = ADRENO_REV(6, 9, 0, ANY_ID),
> > + .chip_ids = ADRENO_CHIP_IDS(0x06090000),
> 8280 probably ok
>
> > .family = ADRENO_6XX_GEN4,
> > .fw = {
> > [ADRENO_FW_SQE] = "a660_sqe.fw",
> > @@ -494,31 +502,16 @@ MODULE_FIRMWARE("qcom/a630_sqe.fw");
> > MODULE_FIRMWARE("qcom/a630_gmu.bin");
> > MODULE_FIRMWARE("qcom/a630_zap.mbn");
> >
> [...]
>
> > @@ -612,32 +604,34 @@ static int find_chipid(struct device *dev, struct adreno_rev *rev)
> >
> > if (sscanf(compat, "qcom,adreno-%u.%u", &r, &patch) == 2 ||
> > sscanf(compat, "amd,imageon-%u.%u", &r, &patch) == 2) {
> > - rev->core = r / 100;
> > + uint32_t core, major, minor;
> > +
> > + core = r / 100;
> > r %= 100;
> > - rev->major = r / 10;
> > + major = r / 10;
> > r %= 10;
> > - rev->minor = r;
> > - rev->patchid = patch;
> > + minor = r;
> > +
> > + *chipid = (core << 24) |
> > + (major << 16) |
> > + (minor << 8) |
> > + patch;
> I think a define macro would be nice here
hmm, a macro would just encourage thinking about chip-id as having
bitfields, which is what I'm trying to get away from ;-)
> >
> > return 0;
> > }
> > +
> > + if (sscanf(compat, "qcom,adreno-%08x", chipid) == 1)
> > + return 0;
> > }
> >
> [...]
>
> > static inline int adreno_is_7c3(const struct adreno_gpu *gpu)
> > {
> > - /* The order of args is important here to handle ANY_ID correctly */
> > - return adreno_cmp_rev(ADRENO_REV(6, 3, 5, ANY_ID), gpu->rev);
> > + return gpu->info->chip_ids[0] == 0x06030500;
> > }
> I'm sorry, but this screams trouble.. and doesn't sound very maintainable :/
>
why? It is intentionally checking the first chip-id so that nothing
breaks if later chip-ids are added
> Apart from all these comments, I don't really see the point of this patch,
> other than trying to tie together Qualcomm's almost-meaningless chipids on
> a7xx into the picture..
>
> Since they can't even be read back from the hardware, I don't think trying
> to force them into the upstream kernel makes any sense.
Sure, we _could_ pick our own arbitrary identifiers, we don't have to
align with kgsl. But that would be a super huge PITA for mesa, which
has support for both kernels.
> On a different note, I think we could try to blockify Adreno definitions a
> bit by splitting things into:
>
> - Core GPU propeties (revision, fw name, GMEM size)
>
> - G(P)MU properties
>
> - Family data (quirks, reg presets in some config struct which could be a
> union of config structs per generation, hwcg, maybe protected regs ptr
> should also be moved there)
We do something like this on the mesa side. But we also get to use
python tricks to generate code as part of the build process which
makes things a bit more elegant.
Fwiw, I was already thinking about splitting the gpu "hw catalog" from
a flat table, to probably something more like a table of tables, so
that we can split a2xx/a3xx/a4xx/a5xx/a6xx tables into separate files.
And then we could move hwcg/protect/etc tables into the same file.
But I thought that might be a bit too conflicty for the a7xx series so
was thinking to wait until after that landed.. unless you don't think
it will be a problem.
BR,
-R
> - Generation data (init function, a2xx and a6xx specifics)
>
> - Speedbin LUTs matched against socid
>
>
> or something like that.. there's a whole lot of duplicated data atm
>
> Konrad
> >
> > static inline int adreno_is_a660(const struct adreno_gpu *gpu)
> > @@ -358,8 +364,7 @@ static inline int adreno_is_a680(const struct adreno_gpu *gpu)
> >
> > static inline int adreno_is_a690(const struct adreno_gpu *gpu)
> > {
> > - /* The order of args is important here to handle ANY_ID correctly */
> > - return adreno_cmp_rev(ADRENO_REV(6, 9, 0, ANY_ID), gpu->rev);
> > + return gpu->info->chip_ids[0] == 0x06090000;
> > };
> > /* check for a615, a616, a618, a619 or any a630 derivatives */
> > static inline int adreno_is_a630_family(const struct adreno_gpu *gpu)
^ permalink raw reply [flat|nested] 73+ messages in thread
* Re: [PATCH 09/12] drm/msm/adreno: Add adreno family
2023-07-07 3:16 ` Dmitry Baryshkov
@ 2023-07-07 23:52 ` Rob Clark
2023-07-07 23:54 ` Dmitry Baryshkov
0 siblings, 1 reply; 73+ messages in thread
From: Rob Clark @ 2023-07-07 23:52 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Konrad Dybcio, linux-arm-msm, Rob Clark, freedreno, dri-devel
On Thu, Jul 6, 2023 at 8:16 PM Dmitry Baryshkov
<dmitry.baryshkov@linaro.org> wrote:
>
> On 07/07/2023 02:35, Konrad Dybcio wrote:
> > On 6.07.2023 23:10, Rob Clark wrote:
> >> From: Rob Clark <robdclark@chromium.org>
> >>
> >> Sometimes it is useful to know the sub-generation (or "family"). And in
> >> any case, this helps us get away from infering the generation from the
> >> numerical chip-id.
> >>
> >> Signed-off-by: Rob Clark <robdclark@chromium.org>
> >> ---
> > [...]
> >
> >> .rev = ADRENO_REV(5, 0, 8, ANY_ID),
> >> + .family = ADRENO_5XX,
> >> .revn = 508,
> > 508 is from 530 fam
> >
> >> .fw = {
> >> [ADRENO_FW_PM4] = "a530_pm4.fw",
> >> @@ -156,6 +168,7 @@ static const struct adreno_info gpulist[] = {
> >> .zapfw = "a508_zap.mdt",
> >> }, {
> >> .rev = ADRENO_REV(5, 0, 9, ANY_ID),
> >> + .family = ADRENO_5XX,
> >> .revn = 509,
> > 509 and 512 are from 540 fam
> >
> >> .fw = {
> >> [ADRENO_FW_PM4] = "a530_pm4.fw",
> >> @@ -173,6 +186,7 @@ static const struct adreno_info gpulist[] = {
> >> .zapfw = "a512_zap.mdt",
> >> }, {
> >> .rev = ADRENO_REV(5, 1, 0, ANY_ID),
> >> + .family = ADRENO_5XX,
> >> .revn = 510,
> > 510 is 530ish but I think it's closer to 505 or whatever the
> > 8953 gpu was called
>
> I'd say, there were following generations here:
>
> - a505 / a506 / a508
> - a509 / a512
> - a510
> - a530
> - a540
>
> Indeed a50x were close to a530 in some aspects and a509/512 being closer
> to a540, but I don't think they were the same family.
As a practical matter, I chose to defer splitting a3xx/a4xx/a5xx into
sub-generations, simply because we didn't have any use for that yet.
For a2xx and a6xx there was a clear immediate use for (most of) it,
and what isn't used falls out of usage of sub-generation
classification we have in mesa, so I have a lot of confidence in the
split.
We can try and map it all out for the other gens now.. or simply just
wait until there is a use for it. I'm not super against mapping it
out better now, but didn't feel that there was any down side to just
punting on that. It would be easy enough to do follow-up patches that
refactor the code and split out the subgen enums at the same time.
BR,
-R
> >
> > [...]
> >
> >> - priv->is_a2xx = config.rev.core == 2;
> >> + priv->is_a2xx = info->family < ADRENO_3XX;
> > is this variable even needed now that there are explicit family values?
> >
> > Konrad
> >> priv->has_cached_coherent =
> >> !!(info->quirks & ADRENO_QUIRK_HAS_CACHED_COHERENT);
> >>
> >> diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
> >> index 2e62a7ce9f13..75ff7fb46099 100644
> >> --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c
> >> +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
> >> @@ -1079,8 +1079,13 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev,
> >> u32 speedbin;
> >> int ret;
> >>
> >> + adreno_gpu->funcs = funcs;
> >> + adreno_gpu->info = adreno_info(config->rev);
> >> + adreno_gpu->rev = *rev;
> >> +
> >> /* Only handle the core clock when GMU is not in use (or is absent). */
> >> - if (adreno_has_gmu_wrapper(adreno_gpu) || config->rev.core < 6) {
> >> + if (adreno_has_gmu_wrapper(adreno_gpu) ||
> >> + adreno_gpu->info->family < ADRENO_6XX_GEN1) {
> >> /*
> >> * This can only be done before devm_pm_opp_of_add_table(), or
> >> * dev_pm_opp_set_config() will WARN_ON()
> >> @@ -1096,10 +1101,6 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev,
> >> devm_pm_opp_set_clkname(dev, "core");
> >> }
> >>
> >> - adreno_gpu->funcs = funcs;
> >> - adreno_gpu->info = adreno_info(config->rev);
> >> - adreno_gpu->rev = *rev;
> >> -
> >> if (adreno_read_speedbin(dev, &speedbin) || !speedbin)
> >> speedbin = 0xffff;
> >> adreno_gpu->speedbin = (uint16_t) (0xffff & speedbin);
> >> diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> >> index 6066cfaaea52..2fa14dcd4e40 100644
> >> --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> >> +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> >> @@ -29,6 +29,25 @@ enum {
> >> ADRENO_FW_MAX,
> >> };
> >>
> >> +/**
> >> + * @enum adreno_family: identify generation and possibly sub-generation
> >> + *
> >> + * In some cases there are distinct sub-generations within a major revision
> >> + * so it helps to be able to group the GPU devices by generation and if
> >> + * necessary sub-generation.
> >> + */
> >> +enum adreno_family {
> >> + ADRENO_2XX_GEN1, /* a20x */
> >> + ADRENO_2XX_GEN2, /* a22x */
> >> + ADRENO_3XX,
> >> + ADRENO_4XX,
> >> + ADRENO_5XX,
> >> + ADRENO_6XX_GEN1, /* a630 family */
> >> + ADRENO_6XX_GEN2, /* a640 family */
> >> + ADRENO_6XX_GEN3, /* a650 family */
> >> + ADRENO_6XX_GEN4, /* a660 family */
> >> +};
> >> +
> >> #define ADRENO_QUIRK_TWO_PASS_USE_WFI BIT(0)
> >> #define ADRENO_QUIRK_FAULT_DETECT_MASK BIT(1)
> >> #define ADRENO_QUIRK_LMLOADKILL_DISABLE BIT(2)
> >> @@ -63,6 +82,7 @@ extern const struct adreno_reglist a660_hwcg[], a690_hwcg[];
> >> struct adreno_info {
> >> const char *machine;
> >> struct adreno_rev rev;
> >> + enum adreno_family family;
> >> uint32_t revn;
> >> const char *fw[ADRENO_FW_MAX];
> >> uint32_t gmem;
> >> @@ -188,14 +208,14 @@ static inline bool adreno_is_a2xx(const struct adreno_gpu *gpu)
> >> {
> >> if (WARN_ON_ONCE(!gpu->info))
> >> return false;
> >> - return (gpu->info->revn < 300);
> >> + return gpu->info->family < ADRENO_2XX_GEN2;
> >> }
> >>
> >> static inline bool adreno_is_a20x(const struct adreno_gpu *gpu)
> >> {
> >> if (WARN_ON_ONCE(!gpu->info))
> >> return false;
> >> - return (gpu->info->revn < 210);
> >> + return gpu->info->family == ADRENO_2XX_GEN1;
> >> }
> >>
> >> static inline bool adreno_is_a225(const struct adreno_gpu *gpu)
> >> @@ -338,29 +358,31 @@ static inline int adreno_is_a690(const struct adreno_gpu *gpu)
> >> /* check for a615, a616, a618, a619 or any a630 derivatives */
> >> static inline int adreno_is_a630_family(const struct adreno_gpu *gpu)
> >> {
> >> - return adreno_is_revn(gpu, 630) ||
> >> - adreno_is_revn(gpu, 615) ||
> >> - adreno_is_revn(gpu, 616) ||
> >> - adreno_is_revn(gpu, 618) ||
> >> - adreno_is_revn(gpu, 619);
> >> + if (WARN_ON_ONCE(!gpu->info))
> >> + return false;
> >> + return gpu->info->family == ADRENO_6XX_GEN1;
> >> }
> >>
> >> static inline int adreno_is_a660_family(const struct adreno_gpu *gpu)
> >> {
> >> - return adreno_is_a660(gpu) || adreno_is_a690(gpu) || adreno_is_7c3(gpu);
> >> + if (WARN_ON_ONCE(!gpu->info))
> >> + return false;
> >> + return gpu->info->family == ADRENO_6XX_GEN4;
> >> }
> >>
> >> /* check for a650, a660, or any derivatives */
> >> static inline int adreno_is_a650_family(const struct adreno_gpu *gpu)
> >> {
> >> - return adreno_is_revn(gpu, 650) ||
> >> - adreno_is_revn(gpu, 620) ||
> >> - adreno_is_a660_family(gpu);
> >> + if (WARN_ON_ONCE(!gpu->info))
> >> + return false;
> >> + return gpu->info->family >= ADRENO_6XX_GEN3;
> >> }
> >>
> >> static inline int adreno_is_a640_family(const struct adreno_gpu *gpu)
> >> {
> >> - return adreno_is_a640(gpu) || adreno_is_a680(gpu);
> >> + if (WARN_ON_ONCE(!gpu->info))
> >> + return false;
> >> + return gpu->info->family == ADRENO_6XX_GEN2;
> >> }
> >>
> >> u64 adreno_private_address_space_size(struct msm_gpu *gpu);
>
> --
> With best wishes
> Dmitry
>
^ permalink raw reply [flat|nested] 73+ messages in thread
* Re: [PATCH 09/12] drm/msm/adreno: Add adreno family
2023-07-07 23:52 ` Rob Clark
@ 2023-07-07 23:54 ` Dmitry Baryshkov
0 siblings, 0 replies; 73+ messages in thread
From: Dmitry Baryshkov @ 2023-07-07 23:54 UTC (permalink / raw)
To: Rob Clark; +Cc: Konrad Dybcio, linux-arm-msm, Rob Clark, freedreno, dri-devel
On 08/07/2023 02:52, Rob Clark wrote:
> On Thu, Jul 6, 2023 at 8:16 PM Dmitry Baryshkov
> <dmitry.baryshkov@linaro.org> wrote:
>>
>> On 07/07/2023 02:35, Konrad Dybcio wrote:
>>> On 6.07.2023 23:10, Rob Clark wrote:
>>>> From: Rob Clark <robdclark@chromium.org>
>>>>
>>>> Sometimes it is useful to know the sub-generation (or "family"). And in
>>>> any case, this helps us get away from infering the generation from the
>>>> numerical chip-id.
>>>>
>>>> Signed-off-by: Rob Clark <robdclark@chromium.org>
>>>> ---
>>> [...]
>>>
>>>> .rev = ADRENO_REV(5, 0, 8, ANY_ID),
>>>> + .family = ADRENO_5XX,
>>>> .revn = 508,
>>> 508 is from 530 fam
>>>
>>>> .fw = {
>>>> [ADRENO_FW_PM4] = "a530_pm4.fw",
>>>> @@ -156,6 +168,7 @@ static const struct adreno_info gpulist[] = {
>>>> .zapfw = "a508_zap.mdt",
>>>> }, {
>>>> .rev = ADRENO_REV(5, 0, 9, ANY_ID),
>>>> + .family = ADRENO_5XX,
>>>> .revn = 509,
>>> 509 and 512 are from 540 fam
>>>
>>>> .fw = {
>>>> [ADRENO_FW_PM4] = "a530_pm4.fw",
>>>> @@ -173,6 +186,7 @@ static const struct adreno_info gpulist[] = {
>>>> .zapfw = "a512_zap.mdt",
>>>> }, {
>>>> .rev = ADRENO_REV(5, 1, 0, ANY_ID),
>>>> + .family = ADRENO_5XX,
>>>> .revn = 510,
>>> 510 is 530ish but I think it's closer to 505 or whatever the
>>> 8953 gpu was called
>>
>> I'd say, there were following generations here:
>>
>> - a505 / a506 / a508
>> - a509 / a512
>> - a510
>> - a530
>> - a540
>>
>> Indeed a50x were close to a530 in some aspects and a509/512 being closer
>> to a540, but I don't think they were the same family.
>
> As a practical matter, I chose to defer splitting a3xx/a4xx/a5xx into
> sub-generations, simply because we didn't have any use for that yet.
> For a2xx and a6xx there was a clear immediate use for (most of) it,
> and what isn't used falls out of usage of sub-generation
> classification we have in mesa, so I have a lot of confidence in the
> split.
>
> We can try and map it all out for the other gens now.. or simply just
> wait until there is a use for it. I'm not super against mapping it
> out better now, but didn't feel that there was any down side to just
> punting on that. It would be easy enough to do follow-up patches that
> refactor the code and split out the subgen enums at the same time.
Sure. I think this can be coupled with split of the gpulist.
>
> BR,
> -R
>
>>>
>>> [...]
>>>
>>>> - priv->is_a2xx = config.rev.core == 2;
>>>> + priv->is_a2xx = info->family < ADRENO_3XX;
>>> is this variable even needed now that there are explicit family values?
>>>
>>> Konrad
>>>> priv->has_cached_coherent =
>>>> !!(info->quirks & ADRENO_QUIRK_HAS_CACHED_COHERENT);
>>>>
>>>> diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
>>>> index 2e62a7ce9f13..75ff7fb46099 100644
>>>> --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c
>>>> +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
>>>> @@ -1079,8 +1079,13 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev,
>>>> u32 speedbin;
>>>> int ret;
>>>>
>>>> + adreno_gpu->funcs = funcs;
>>>> + adreno_gpu->info = adreno_info(config->rev);
>>>> + adreno_gpu->rev = *rev;
>>>> +
>>>> /* Only handle the core clock when GMU is not in use (or is absent). */
>>>> - if (adreno_has_gmu_wrapper(adreno_gpu) || config->rev.core < 6) {
>>>> + if (adreno_has_gmu_wrapper(adreno_gpu) ||
>>>> + adreno_gpu->info->family < ADRENO_6XX_GEN1) {
>>>> /*
>>>> * This can only be done before devm_pm_opp_of_add_table(), or
>>>> * dev_pm_opp_set_config() will WARN_ON()
>>>> @@ -1096,10 +1101,6 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev,
>>>> devm_pm_opp_set_clkname(dev, "core");
>>>> }
>>>>
>>>> - adreno_gpu->funcs = funcs;
>>>> - adreno_gpu->info = adreno_info(config->rev);
>>>> - adreno_gpu->rev = *rev;
>>>> -
>>>> if (adreno_read_speedbin(dev, &speedbin) || !speedbin)
>>>> speedbin = 0xffff;
>>>> adreno_gpu->speedbin = (uint16_t) (0xffff & speedbin);
>>>> diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
>>>> index 6066cfaaea52..2fa14dcd4e40 100644
>>>> --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
>>>> +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
>>>> @@ -29,6 +29,25 @@ enum {
>>>> ADRENO_FW_MAX,
>>>> };
>>>>
>>>> +/**
>>>> + * @enum adreno_family: identify generation and possibly sub-generation
>>>> + *
>>>> + * In some cases there are distinct sub-generations within a major revision
>>>> + * so it helps to be able to group the GPU devices by generation and if
>>>> + * necessary sub-generation.
>>>> + */
>>>> +enum adreno_family {
>>>> + ADRENO_2XX_GEN1, /* a20x */
>>>> + ADRENO_2XX_GEN2, /* a22x */
>>>> + ADRENO_3XX,
>>>> + ADRENO_4XX,
>>>> + ADRENO_5XX,
>>>> + ADRENO_6XX_GEN1, /* a630 family */
>>>> + ADRENO_6XX_GEN2, /* a640 family */
>>>> + ADRENO_6XX_GEN3, /* a650 family */
>>>> + ADRENO_6XX_GEN4, /* a660 family */
>>>> +};
>>>> +
>>>> #define ADRENO_QUIRK_TWO_PASS_USE_WFI BIT(0)
>>>> #define ADRENO_QUIRK_FAULT_DETECT_MASK BIT(1)
>>>> #define ADRENO_QUIRK_LMLOADKILL_DISABLE BIT(2)
>>>> @@ -63,6 +82,7 @@ extern const struct adreno_reglist a660_hwcg[], a690_hwcg[];
>>>> struct adreno_info {
>>>> const char *machine;
>>>> struct adreno_rev rev;
>>>> + enum adreno_family family;
>>>> uint32_t revn;
>>>> const char *fw[ADRENO_FW_MAX];
>>>> uint32_t gmem;
>>>> @@ -188,14 +208,14 @@ static inline bool adreno_is_a2xx(const struct adreno_gpu *gpu)
>>>> {
>>>> if (WARN_ON_ONCE(!gpu->info))
>>>> return false;
>>>> - return (gpu->info->revn < 300);
>>>> + return gpu->info->family < ADRENO_2XX_GEN2;
>>>> }
>>>>
>>>> static inline bool adreno_is_a20x(const struct adreno_gpu *gpu)
>>>> {
>>>> if (WARN_ON_ONCE(!gpu->info))
>>>> return false;
>>>> - return (gpu->info->revn < 210);
>>>> + return gpu->info->family == ADRENO_2XX_GEN1;
>>>> }
>>>>
>>>> static inline bool adreno_is_a225(const struct adreno_gpu *gpu)
>>>> @@ -338,29 +358,31 @@ static inline int adreno_is_a690(const struct adreno_gpu *gpu)
>>>> /* check for a615, a616, a618, a619 or any a630 derivatives */
>>>> static inline int adreno_is_a630_family(const struct adreno_gpu *gpu)
>>>> {
>>>> - return adreno_is_revn(gpu, 630) ||
>>>> - adreno_is_revn(gpu, 615) ||
>>>> - adreno_is_revn(gpu, 616) ||
>>>> - adreno_is_revn(gpu, 618) ||
>>>> - adreno_is_revn(gpu, 619);
>>>> + if (WARN_ON_ONCE(!gpu->info))
>>>> + return false;
>>>> + return gpu->info->family == ADRENO_6XX_GEN1;
>>>> }
>>>>
>>>> static inline int adreno_is_a660_family(const struct adreno_gpu *gpu)
>>>> {
>>>> - return adreno_is_a660(gpu) || adreno_is_a690(gpu) || adreno_is_7c3(gpu);
>>>> + if (WARN_ON_ONCE(!gpu->info))
>>>> + return false;
>>>> + return gpu->info->family == ADRENO_6XX_GEN4;
>>>> }
>>>>
>>>> /* check for a650, a660, or any derivatives */
>>>> static inline int adreno_is_a650_family(const struct adreno_gpu *gpu)
>>>> {
>>>> - return adreno_is_revn(gpu, 650) ||
>>>> - adreno_is_revn(gpu, 620) ||
>>>> - adreno_is_a660_family(gpu);
>>>> + if (WARN_ON_ONCE(!gpu->info))
>>>> + return false;
>>>> + return gpu->info->family >= ADRENO_6XX_GEN3;
>>>> }
>>>>
>>>> static inline int adreno_is_a640_family(const struct adreno_gpu *gpu)
>>>> {
>>>> - return adreno_is_a640(gpu) || adreno_is_a680(gpu);
>>>> + if (WARN_ON_ONCE(!gpu->info))
>>>> + return false;
>>>> + return gpu->info->family == ADRENO_6XX_GEN2;
>>>> }
>>>>
>>>> u64 adreno_private_address_space_size(struct msm_gpu *gpu);
>>
>> --
>> With best wishes
>> Dmitry
>>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 73+ messages in thread
* Re: [Freedreno] [PATCH 07/12] drm/msm/adreno: Move speedbin mapping to device table
2023-07-07 2:54 ` [Freedreno] " Dmitry Baryshkov
@ 2023-07-10 19:56 ` Rob Clark
2023-07-10 20:54 ` Dmitry Baryshkov
0 siblings, 1 reply; 73+ messages in thread
From: Rob Clark @ 2023-07-10 19:56 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Konrad Dybcio, linux-arm-msm, Rob Clark, freedreno, dri-devel
On Thu, Jul 6, 2023 at 7:54 PM Dmitry Baryshkov
<dmitry.baryshkov@linaro.org> wrote:
>
> On 07/07/2023 00:10, Rob Clark wrote:
> > From: Rob Clark <robdclark@chromium.org>
> >
> > This simplifies the code.
> >
> > Signed-off-by: Rob Clark <robdclark@chromium.org>
> > ---
> > drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 171 ++-------------------
> > drivers/gpu/drm/msm/adreno/adreno_device.c | 51 ++++++
> > drivers/gpu/drm/msm/adreno/adreno_gpu.h | 25 +++
> > 3 files changed, 92 insertions(+), 155 deletions(-)
>
>
> Interesting hack, I'd say.
>
> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>
> Minor nit below.
>
> >
>
> > diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> > index d5335b99c64c..994ac26ce731 100644
> > --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> > +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> > @@ -72,8 +72,33 @@ struct adreno_info {
> > u32 inactive_period;
> > const struct adreno_reglist *hwcg;
> > u64 address_space_size;
> > + /**
> > + * @speedbins: Optional table of fuse to speedbin mappings
> > + *
> > + * Consists of pairs of fuse, index mappings, terminated with
> > + * UINT_MAX sentinal.
> > + */
> > + uint32_t *speedbins;
>
> Would it be better to explicitly list this as pairs of uint32_t? And
> then use braces in ADRENO_SPEEDBIN initialisation.
It would mean the sentinel would take 8 bytes instead of 4.. maybe
that is over-thinking it, but it was the reason I just stuck with a
flat table
BR,
-R
> > };
> >
> > +/*
> > + * Helper to build a speedbin table, ie. the table:
> > + * fuse | speedbin
> > + * -----+---------
> > + * 0 | 0
> > + * 169 | 1
> > + * 174 | 2
> > + *
> > + * would be declared as:
> > + *
> > + * .speedbins = ADRENO_SPEEDBINS(
> > + * 0, 0,
> > + * 169, 1,
> > + * 174, 2
> > + * ),
> > + */
> > +#define ADRENO_SPEEDBINS(tbl...) (uint32_t[]) { tbl, UINT_MAX }
> > +
> > const struct adreno_info *adreno_info(struct adreno_rev rev);
> >
> > struct adreno_gpu {
>
> --
> With best wishes
> Dmitry
>
^ permalink raw reply [flat|nested] 73+ messages in thread
* Re: [PATCH 10/12] drm/msm/adreno: Add helper for formating chip-id
2023-07-06 23:36 ` Konrad Dybcio
@ 2023-07-10 20:21 ` Rob Clark
0 siblings, 0 replies; 73+ messages in thread
From: Rob Clark @ 2023-07-10 20:21 UTC (permalink / raw)
To: Konrad Dybcio; +Cc: Rob Clark, linux-arm-msm, freedreno, dri-devel
On Thu, Jul 6, 2023 at 4:36 PM Konrad Dybcio <konrad.dybcio@linaro.org> wrote:
>
> On 6.07.2023 23:10, Rob Clark wrote:
> > From: Rob Clark <robdclark@chromium.org>
> >
> > This is used in a few places, including one that is parsed by userspace
> > tools. So let's standardize it a bit better.
> >
> > Signed-off-by: Rob Clark <robdclark@chromium.org>
> > ---
> Userspace parsed this weird string instead of the hex-based chipid?
>
> weird^2
AFAICT it is just crashdec (the creatively named tool for parsing gpu
devcore dumps) which parses using "%u.%u.%u.%u".. I suppose one
_could_ make the argument that, since userspace doesn't yet support
any device where "%x.%x.%x.%x" parsing would be different, we could
get away with switching to hex without it being an ABI break..
BR,
-R
> Konrad
> > drivers/gpu/drm/msm/adreno/adreno_device.c | 8 +++-----
> > drivers/gpu/drm/msm/adreno/adreno_gpu.c | 19 ++++++++-----------
> > drivers/gpu/drm/msm/adreno/adreno_gpu.h | 6 ++++++
> > 3 files changed, 17 insertions(+), 16 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c
> > index dcd6363ac7b0..fd2e183bce60 100644
> > --- a/drivers/gpu/drm/msm/adreno/adreno_device.c
> > +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c
> > @@ -661,14 +661,12 @@ static int adreno_bind(struct device *dev, struct device *master, void *data)
> > info = adreno_info(config.rev);
> >
> > if (!info) {
> > - dev_warn(drm->dev, "Unknown GPU revision: %u.%u.%u.%u\n",
> > - config.rev.core, config.rev.major,
> > - config.rev.minor, config.rev.patchid);
> > + dev_warn(drm->dev, "Unknown GPU revision: %"ADRENO_CHIPID_FMT"\n",
> > + ADRENO_CHIPID_ARGS(config.rev));
> > return -ENXIO;
> > }
> >
> > - DBG("Found GPU: %u.%u.%u.%u", config.rev.core, config.rev.major,
> > - config.rev.minor, config.rev.patchid);
> > + DBG("Found GPU: %"ADRENO_CHIPID_FMT, ADRENO_CHIPID_ARGS(config.rev));
> >
> > priv->is_a2xx = info->family < ADRENO_3XX;
> > priv->has_cached_coherent =
> > diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
> > index 75ff7fb46099..1a982a926f21 100644
> > --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c
> > +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
> > @@ -847,10 +847,9 @@ void adreno_show(struct msm_gpu *gpu, struct msm_gpu_state *state,
> > if (IS_ERR_OR_NULL(state))
> > return;
> >
> > - drm_printf(p, "revision: %d (%d.%d.%d.%d)\n",
> > - adreno_gpu->info->revn, adreno_gpu->rev.core,
> > - adreno_gpu->rev.major, adreno_gpu->rev.minor,
> > - adreno_gpu->rev.patchid);
> > + drm_printf(p, "revision: %u (%"ADRENO_CHIPID_FMT")\n",
> > + adreno_gpu->info->revn,
> > + ADRENO_CHIPID_ARGS(adreno_gpu->rev));
> > /*
> > * If this is state collected due to iova fault, so fault related info
> > *
> > @@ -921,10 +920,9 @@ void adreno_dump_info(struct msm_gpu *gpu)
> > struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
> > int i;
> >
> > - printk("revision: %d (%d.%d.%d.%d)\n",
> > - adreno_gpu->info->revn, adreno_gpu->rev.core,
> > - adreno_gpu->rev.major, adreno_gpu->rev.minor,
> > - adreno_gpu->rev.patchid);
> > + printk("revision: %u (%"ADRENO_CHIPID_FMT")\n",
> > + adreno_gpu->info->revn,
> > + ADRENO_CHIPID_ARGS(adreno_gpu->rev));
> >
> > for (i = 0; i < gpu->nr_rings; i++) {
> > struct msm_ringbuffer *ring = gpu->rb[i];
> > @@ -1105,9 +1103,8 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev,
> > speedbin = 0xffff;
> > adreno_gpu->speedbin = (uint16_t) (0xffff & speedbin);
> >
> > - gpu_name = devm_kasprintf(dev, GFP_KERNEL, "%d.%d.%d.%d",
> > - rev->core, rev->major, rev->minor,
> > - rev->patchid);
> > + gpu_name = devm_kasprintf(dev, GFP_KERNEL, "%"ADRENO_CHIPID_FMT,
> > + ADRENO_CHIPID_ARGS(config->rev));
> > if (!gpu_name)
> > return -ENOMEM;
> >
> > diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> > index 2fa14dcd4e40..73e7155f164c 100644
> > --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> > +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> > @@ -66,6 +66,12 @@ struct adreno_rev {
> > #define ADRENO_REV(core, major, minor, patchid) \
> > ((struct adreno_rev){ core, major, minor, patchid })
> >
> > +/* Helper for formating the chip_id in the way that userspace tools like
> > + * crashdec expect.
> > + */
> > +#define ADRENO_CHIPID_FMT "u.%u.%u.%u"
> > +#define ADRENO_CHIPID_ARGS(_r) (_r).core, (_r).major, (_r).minor, (_r).patchid
> > +
> > struct adreno_gpu_funcs {
> > struct msm_gpu_funcs base;
> > int (*get_timestamp)(struct msm_gpu *gpu, uint64_t *value);
^ permalink raw reply [flat|nested] 73+ messages in thread
* Re: [Freedreno] [PATCH 07/12] drm/msm/adreno: Move speedbin mapping to device table
2023-07-10 19:56 ` Rob Clark
@ 2023-07-10 20:54 ` Dmitry Baryshkov
0 siblings, 0 replies; 73+ messages in thread
From: Dmitry Baryshkov @ 2023-07-10 20:54 UTC (permalink / raw)
To: Rob Clark; +Cc: Konrad Dybcio, linux-arm-msm, Rob Clark, freedreno, dri-devel
On 10/07/2023 22:56, Rob Clark wrote:
> On Thu, Jul 6, 2023 at 7:54 PM Dmitry Baryshkov
> <dmitry.baryshkov@linaro.org> wrote:
>>
>> On 07/07/2023 00:10, Rob Clark wrote:
>>> From: Rob Clark <robdclark@chromium.org>
>>>
>>> This simplifies the code.
>>>
>>> Signed-off-by: Rob Clark <robdclark@chromium.org>
>>> ---
>>> drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 171 ++-------------------
>>> drivers/gpu/drm/msm/adreno/adreno_device.c | 51 ++++++
>>> drivers/gpu/drm/msm/adreno/adreno_gpu.h | 25 +++
>>> 3 files changed, 92 insertions(+), 155 deletions(-)
>>
>>
>> Interesting hack, I'd say.
>>
>> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>>
>> Minor nit below.
>>
>>>
>>
>>> diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
>>> index d5335b99c64c..994ac26ce731 100644
>>> --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
>>> +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
>>> @@ -72,8 +72,33 @@ struct adreno_info {
>>> u32 inactive_period;
>>> const struct adreno_reglist *hwcg;
>>> u64 address_space_size;
>>> + /**
>>> + * @speedbins: Optional table of fuse to speedbin mappings
>>> + *
>>> + * Consists of pairs of fuse, index mappings, terminated with
>>> + * UINT_MAX sentinal.
>>> + */
>>> + uint32_t *speedbins;
>>
>> Would it be better to explicitly list this as pairs of uint32_t? And
>> then use braces in ADRENO_SPEEDBIN initialisation.
>
> It would mean the sentinel would take 8 bytes instead of 4.. maybe
> that is over-thinking it, but it was the reason I just stuck with a
> flat table
Guessed so. But we are wasting so much memory already... I think that
the paired structure would better reflect the data - it's not a flat
list, but a list of nvmem <-> speedbin pairs.
>
> BR,
> -R
>
>>> };
>>>
>>> +/*
>>> + * Helper to build a speedbin table, ie. the table:
>>> + * fuse | speedbin
>>> + * -----+---------
>>> + * 0 | 0
>>> + * 169 | 1
>>> + * 174 | 2
>>> + *
>>> + * would be declared as:
>>> + *
>>> + * .speedbins = ADRENO_SPEEDBINS(
>>> + * 0, 0,
>>> + * 169, 1,
>>> + * 174, 2
>>> + * ),
>>> + */
>>> +#define ADRENO_SPEEDBINS(tbl...) (uint32_t[]) { tbl, UINT_MAX }
>>> +
>>> const struct adreno_info *adreno_info(struct adreno_rev rev);
>>>
>>> struct adreno_gpu {
>>
>> --
>> With best wishes
>> Dmitry
>>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 73+ messages in thread
* Re: [PATCH 02/12] drm/msm/adreno: Remove redundant gmem size param
2023-07-06 23:22 ` Konrad Dybcio
@ 2023-07-13 19:46 ` Akhil P Oommen
0 siblings, 0 replies; 73+ messages in thread
From: Akhil P Oommen @ 2023-07-13 19:46 UTC (permalink / raw)
To: Konrad Dybcio; +Cc: Rob Clark, linux-arm-msm, freedreno, dri-devel
On Fri, Jul 07, 2023 at 01:22:56AM +0200, Konrad Dybcio wrote:
>
> On 6.07.2023 23:10, Rob Clark wrote:
> > From: Rob Clark <robdclark@chromium.org>
> >
> > Even in the ocmem case, the allocated ocmem buffer size should match the
> > requested size.
> >
> > Signed-off-by: Rob Clark <robdclark@chromium.org>
> > ---
> [...]
>
> > +
> > + WARN_ON(ocmem_hdl->len != adreno_gpu->info->gmem);
> I believe this should be an error condition. If the sizes are mismatched,
> best case scenario you get suboptimal perf and worst case scenario your
> system explodes.
No, the worst case scenarios are subtle bugs like random corruptions,
pagefaults etc which you debug for months. ;)
-Akhil.
>
> Very nice cleanup though!
>
> Konrad
> >
> > return 0;
> > }
> > @@ -1097,7 +1098,6 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev,
> >
> > adreno_gpu->funcs = funcs;
> > adreno_gpu->info = adreno_info(config->rev);
> > - adreno_gpu->gmem = adreno_gpu->info->gmem;
> > adreno_gpu->revn = adreno_gpu->info->revn;
> > adreno_gpu->rev = *rev;
> >
> > diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> > index 6830c3776c2d..aaf09c642dc6 100644
> > --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> > +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> > @@ -77,7 +77,6 @@ struct adreno_gpu {
> > struct msm_gpu base;
> > struct adreno_rev rev;
> > const struct adreno_info *info;
> > - uint32_t gmem; /* actual gmem size */
> > uint32_t revn; /* numeric revision name */
> > uint16_t speedbin;
> > const struct adreno_gpu_funcs *funcs;
^ permalink raw reply [flat|nested] 73+ messages in thread
* Re: [Freedreno] [PATCH 05/12] drm/msm/adreno: Use quirk to identify cached-coherent support
2023-07-06 21:10 ` [PATCH 05/12] drm/msm/adreno: Use quirk to identify cached-coherent support Rob Clark
2023-07-06 23:29 ` Konrad Dybcio
2023-07-07 2:29 ` [Freedreno] " Dmitry Baryshkov
@ 2023-07-13 20:05 ` Akhil P Oommen
2023-07-13 22:25 ` Rob Clark
2 siblings, 1 reply; 73+ messages in thread
From: Akhil P Oommen @ 2023-07-13 20:05 UTC (permalink / raw)
To: Rob Clark; +Cc: Konrad Dybcio, linux-arm-msm, Rob Clark, freedreno, dri-devel
On Thu, Jul 06, 2023 at 02:10:38PM -0700, Rob Clark wrote:
>
> From: Rob Clark <robdclark@chromium.org>
>
> It is better to explicitly list it. With the move to opaque chip-id's
> for future devices, we should avoid trying to infer things like
> generation from the numerical value.
>
> Signed-off-by: Rob Clark <robdclark@chromium.org>
> ---
> drivers/gpu/drm/msm/adreno/adreno_device.c | 23 +++++++++++++++-------
> drivers/gpu/drm/msm/adreno/adreno_gpu.h | 1 +
> 2 files changed, 17 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c
> index f469f951a907..3c531da417b9 100644
> --- a/drivers/gpu/drm/msm/adreno/adreno_device.c
> +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c
> @@ -256,6 +256,7 @@ static const struct adreno_info gpulist[] = {
> },
> .gmem = SZ_512K,
> .inactive_period = DRM_MSM_INACTIVE_PERIOD,
> + .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT,
> .init = a6xx_gpu_init,
> }, {
> .rev = ADRENO_REV(6, 1, 9, ANY_ID),
> @@ -266,6 +267,7 @@ static const struct adreno_info gpulist[] = {
> },
> .gmem = SZ_512K,
> .inactive_period = DRM_MSM_INACTIVE_PERIOD,
> + .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT,
> .init = a6xx_gpu_init,
> .zapfw = "a615_zap.mdt",
> .hwcg = a615_hwcg,
> @@ -278,6 +280,7 @@ static const struct adreno_info gpulist[] = {
> },
> .gmem = SZ_1M,
> .inactive_period = DRM_MSM_INACTIVE_PERIOD,
> + .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT,
> .init = a6xx_gpu_init,
> .zapfw = "a630_zap.mdt",
> .hwcg = a630_hwcg,
> @@ -290,6 +293,7 @@ static const struct adreno_info gpulist[] = {
> },
> .gmem = SZ_1M,
> .inactive_period = DRM_MSM_INACTIVE_PERIOD,
> + .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT,
> .init = a6xx_gpu_init,
> .zapfw = "a640_zap.mdt",
> .hwcg = a640_hwcg,
> @@ -302,7 +306,8 @@ static const struct adreno_info gpulist[] = {
> },
> .gmem = SZ_1M + SZ_128K,
> .inactive_period = DRM_MSM_INACTIVE_PERIOD,
> - .quirks = ADRENO_QUIRK_HAS_HW_APRIV,
> + .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |
> + ADRENO_QUIRK_HAS_HW_APRIV,
> .init = a6xx_gpu_init,
> .zapfw = "a650_zap.mdt",
> .hwcg = a650_hwcg,
> @@ -316,7 +321,8 @@ static const struct adreno_info gpulist[] = {
> },
> .gmem = SZ_1M + SZ_512K,
> .inactive_period = DRM_MSM_INACTIVE_PERIOD,
> - .quirks = ADRENO_QUIRK_HAS_HW_APRIV,
> + .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |
> + ADRENO_QUIRK_HAS_HW_APRIV,
> .init = a6xx_gpu_init,
> .zapfw = "a660_zap.mdt",
> .hwcg = a660_hwcg,
> @@ -329,7 +335,8 @@ static const struct adreno_info gpulist[] = {
> },
> .gmem = SZ_512K,
> .inactive_period = DRM_MSM_INACTIVE_PERIOD,
> - .quirks = ADRENO_QUIRK_HAS_HW_APRIV,
> + .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |
> + ADRENO_QUIRK_HAS_HW_APRIV,
> .init = a6xx_gpu_init,
> .hwcg = a660_hwcg,
> .address_space_size = SZ_16G,
> @@ -342,6 +349,7 @@ static const struct adreno_info gpulist[] = {
> },
> .gmem = SZ_2M,
> .inactive_period = DRM_MSM_INACTIVE_PERIOD,
> + .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT,
> .init = a6xx_gpu_init,
> .zapfw = "a640_zap.mdt",
> .hwcg = a640_hwcg,
> @@ -353,7 +361,8 @@ static const struct adreno_info gpulist[] = {
> },
> .gmem = SZ_4M,
> .inactive_period = DRM_MSM_INACTIVE_PERIOD,
> - .quirks = ADRENO_QUIRK_HAS_HW_APRIV,
> + .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |
> + ADRENO_QUIRK_HAS_HW_APRIV,
> .init = a6xx_gpu_init,
> .zapfw = "a690_zap.mdt",
> .hwcg = a690_hwcg,
> @@ -565,9 +574,9 @@ static int adreno_bind(struct device *dev, struct device *master, void *data)
> if (ret)
> return ret;
>
> - if (config.rev.core >= 6)
> - if (!adreno_has_gmu_wrapper(to_adreno_gpu(gpu)))
> - priv->has_cached_coherent = true;
> + priv->has_cached_coherent =
> + !!(info->quirks & ADRENO_QUIRK_HAS_CACHED_COHERENT) &&
> + !adreno_has_gmu_wrapper(to_adreno_gpu(gpu));
>
> return 0;
> }
> diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> index a7c4a2c536e3..e08d41337169 100644
> --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> @@ -33,6 +33,7 @@ enum {
> #define ADRENO_QUIRK_FAULT_DETECT_MASK BIT(1)
> #define ADRENO_QUIRK_LMLOADKILL_DISABLE BIT(2)
> #define ADRENO_QUIRK_HAS_HW_APRIV BIT(3)
> +#define ADRENO_QUIRK_HAS_CACHED_COHERENT BIT(4)
a shorter ADRENO_IS_IOCOHERENT?
-Akhil
>
> struct adreno_rev {
> uint8_t core;
> --
> 2.41.0
>
^ permalink raw reply [flat|nested] 73+ messages in thread
* Re: [Freedreno] [PATCH 06/12] drm/msm/adreno: Allow SoC specific gpu device table entries
2023-07-07 2:34 ` Dmitry Baryshkov
@ 2023-07-13 20:26 ` Akhil P Oommen
2023-07-26 18:28 ` Rob Clark
0 siblings, 1 reply; 73+ messages in thread
From: Akhil P Oommen @ 2023-07-13 20:26 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Rob Clark, linux-arm-msm, dri-devel, Konrad Dybcio, freedreno
On Fri, Jul 07, 2023 at 05:34:04AM +0300, Dmitry Baryshkov wrote:
>
> On 07/07/2023 00:10, Rob Clark wrote:
> > From: Rob Clark <robdclark@chromium.org>
> >
> > There are cases where there are differences due to SoC integration.
> > Such as cache-coherency support, and (in the next patch) e-fuse to
> > speedbin mappings.
>
> I have the feeling that we are trying to circumvent the way DT works. I'd
> suggest adding explicit SoC-compatible strings to Adreno bindings and then
> using of_device_id::data and then of_device_get_match_data().
>
Just thinking, then how about a unique compatible string which we match
to identify gpu->info and drop chip-id check completely here?
-Akhil
> >
> > Signed-off-by: Rob Clark <robdclark@chromium.org>
> > ---
> > drivers/gpu/drm/msm/adreno/adreno_device.c | 34 +++++++++++++++++++---
> > drivers/gpu/drm/msm/adreno/adreno_gpu.h | 1 +
> > 2 files changed, 31 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c
> > index 3c531da417b9..e62bc895a31f 100644
> > --- a/drivers/gpu/drm/msm/adreno/adreno_device.c
> > +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c
> > @@ -258,6 +258,32 @@ static const struct adreno_info gpulist[] = {
> > .inactive_period = DRM_MSM_INACTIVE_PERIOD,
> > .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT,
> > .init = a6xx_gpu_init,
> > + }, {
> > + .machine = "qcom,sm4350",
> > + .rev = ADRENO_REV(6, 1, 9, ANY_ID),
> > + .revn = 619,
> > + .fw = {
> > + [ADRENO_FW_SQE] = "a630_sqe.fw",
> > + [ADRENO_FW_GMU] = "a619_gmu.bin",
> > + },
> > + .gmem = SZ_512K,
> > + .inactive_period = DRM_MSM_INACTIVE_PERIOD,
> > + .init = a6xx_gpu_init,
> > + .zapfw = "a615_zap.mdt",
> > + .hwcg = a615_hwcg,
> > + }, {
> > + .machine = "qcom,sm6375",
> > + .rev = ADRENO_REV(6, 1, 9, ANY_ID),
> > + .revn = 619,
> > + .fw = {
> > + [ADRENO_FW_SQE] = "a630_sqe.fw",
> > + [ADRENO_FW_GMU] = "a619_gmu.bin",
> > + },
> > + .gmem = SZ_512K,
> > + .inactive_period = DRM_MSM_INACTIVE_PERIOD,
> > + .init = a6xx_gpu_init,
> > + .zapfw = "a615_zap.mdt",
> > + .hwcg = a615_hwcg,
> > }, {
> > .rev = ADRENO_REV(6, 1, 9, ANY_ID),
> > .revn = 619,
> > @@ -409,6 +435,8 @@ const struct adreno_info *adreno_info(struct adreno_rev rev)
> > /* identify gpu: */
> > for (i = 0; i < ARRAY_SIZE(gpulist); i++) {
> > const struct adreno_info *info = &gpulist[i];
> > + if (info->machine && !of_machine_is_compatible(info->machine))
> > + continue;
> > if (adreno_cmp_rev(info->rev, rev))
> > return info;
> > }
> > @@ -563,6 +591,8 @@ static int adreno_bind(struct device *dev, struct device *master, void *data)
> > config.rev.minor, config.rev.patchid);
> > priv->is_a2xx = config.rev.core == 2;
> > + priv->has_cached_coherent =
> > + !!(info->quirks & ADRENO_QUIRK_HAS_CACHED_COHERENT);
> > gpu = info->init(drm);
> > if (IS_ERR(gpu)) {
> > @@ -574,10 +604,6 @@ static int adreno_bind(struct device *dev, struct device *master, void *data)
> > if (ret)
> > return ret;
> > - priv->has_cached_coherent =
> > - !!(info->quirks & ADRENO_QUIRK_HAS_CACHED_COHERENT) &&
> > - !adreno_has_gmu_wrapper(to_adreno_gpu(gpu));
> > -
> > return 0;
> > }
> > diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> > index e08d41337169..d5335b99c64c 100644
> > --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> > +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> > @@ -61,6 +61,7 @@ extern const struct adreno_reglist a612_hwcg[], a615_hwcg[], a630_hwcg[], a640_h
> > extern const struct adreno_reglist a660_hwcg[], a690_hwcg[];
> > struct adreno_info {
> > + const char *machine;
> > struct adreno_rev rev;
> > uint32_t revn;
> > const char *fw[ADRENO_FW_MAX];
>
> --
> With best wishes
> Dmitry
>
^ permalink raw reply [flat|nested] 73+ messages in thread
* Re: [Freedreno] [PATCH 12/12] drm/msm/adreno: Switch to chip-id for identifying GPU
2023-07-07 3:45 ` [Freedreno] " Dmitry Baryshkov
@ 2023-07-13 21:39 ` Akhil P Oommen
2023-07-13 22:06 ` Rob Clark
2023-07-26 21:37 ` Rob Clark
1 sibling, 1 reply; 73+ messages in thread
From: Akhil P Oommen @ 2023-07-13 21:39 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Rob Clark, linux-arm-msm, dri-devel, Konrad Dybcio, freedreno
On Fri, Jul 07, 2023 at 06:45:42AM +0300, Dmitry Baryshkov wrote:
>
> On 07/07/2023 00:10, Rob Clark wrote:
> > From: Rob Clark <robdclark@chromium.org>
> >
> > Since the revision becomes an opaque identifier with future GPUs, move
> > away from treating different ranges of bits as having a given meaning.
> > This means that we need to explicitly list different patch revisions in
> > the device table.
> >
> > Signed-off-by: Rob Clark <robdclark@chromium.org>
> > ---
> > drivers/gpu/drm/msm/adreno/a4xx_gpu.c | 2 +-
> > drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 11 +-
> > drivers/gpu/drm/msm/adreno/a5xx_power.c | 2 +-
> > drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 13 ++-
> > drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 9 +-
> > drivers/gpu/drm/msm/adreno/adreno_device.c | 128 ++++++++++-----------
> > drivers/gpu/drm/msm/adreno/adreno_gpu.c | 16 +--
> > drivers/gpu/drm/msm/adreno/adreno_gpu.h | 51 ++++----
> > 8 files changed, 122 insertions(+), 110 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/msm/adreno/a4xx_gpu.c b/drivers/gpu/drm/msm/adreno/a4xx_gpu.c
> > index 715436cb3996..8b4cdf95f445 100644
> > --- a/drivers/gpu/drm/msm/adreno/a4xx_gpu.c
> > +++ b/drivers/gpu/drm/msm/adreno/a4xx_gpu.c
> > @@ -145,7 +145,7 @@ static void a4xx_enable_hwcg(struct msm_gpu *gpu)
> > gpu_write(gpu, REG_A4XX_RBBM_CLOCK_DELAY_HLSQ, 0x00220000);
> > /* Early A430's have a timing issue with SP/TP power collapse;
> > disabling HW clock gating prevents it. */
> > - if (adreno_is_a430(adreno_gpu) && adreno_gpu->rev.patchid < 2)
> > + if (adreno_is_a430(adreno_gpu) && adreno_patchid(adreno_gpu) < 2)
> > gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL, 0);
> > else
> > gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL, 0xAAAAAAAA);
> > diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
> > index f0803e94ebe5..70d2b5342cd9 100644
> > --- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
> > +++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
> > @@ -1744,6 +1744,7 @@ struct msm_gpu *a5xx_gpu_init(struct drm_device *dev)
> > struct msm_drm_private *priv = dev->dev_private;
> > struct platform_device *pdev = priv->gpu_pdev;
> > struct adreno_platform_config *config = pdev->dev.platform_data;
> > + const struct adreno_info *info;
> > struct a5xx_gpu *a5xx_gpu = NULL;
> > struct adreno_gpu *adreno_gpu;
> > struct msm_gpu *gpu;
> > @@ -1770,7 +1771,15 @@ struct msm_gpu *a5xx_gpu_init(struct drm_device *dev)
> > nr_rings = 4;
> > - if (adreno_cmp_rev(ADRENO_REV(5, 1, 0, ANY_ID), config->rev))
> > + /*
> > + * Note that we wouldn't have been able to get this far if there is not
> > + * a device table entry for this chip_id
> > + */
> > + info = adreno_find_info(config->chip_id);
> > + if (WARN_ON(!info))
> > + return ERR_PTR(-EINVAL);
> > +
> > + if (info->revn == 510)
> > nr_rings = 1;
> > ret = adreno_gpu_init(dev, pdev, adreno_gpu, &funcs, nr_rings);
> > diff --git a/drivers/gpu/drm/msm/adreno/a5xx_power.c b/drivers/gpu/drm/msm/adreno/a5xx_power.c
> > index 0e63a1429189..7705f8010484 100644
> > --- a/drivers/gpu/drm/msm/adreno/a5xx_power.c
> > +++ b/drivers/gpu/drm/msm/adreno/a5xx_power.c
> > @@ -179,7 +179,7 @@ static void a540_lm_setup(struct msm_gpu *gpu)
> > /* The battery current limiter isn't enabled for A540 */
> > config = AGC_LM_CONFIG_BCL_DISABLED;
> > - config |= adreno_gpu->rev.patchid << AGC_LM_CONFIG_GPU_VERSION_SHIFT;
> > + config |= adreno_patchid(adreno_gpu) << AGC_LM_CONFIG_GPU_VERSION_SHIFT;
> > /* For now disable GPMU side throttling */
> > config |= AGC_LM_CONFIG_THROTTLE_DISABLE;
> > diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
> > index f1bb20574018..a9ba547a120c 100644
> > --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
> > +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
> > @@ -790,10 +790,15 @@ static int a6xx_gmu_fw_start(struct a6xx_gmu *gmu, unsigned int state)
> > gmu_write(gmu, REG_A6XX_GMU_AHB_FENCE_RANGE_0,
> > (1 << 31) | (0xa << 18) | (0xa0));
> > - chipid = adreno_gpu->rev.core << 24;
> > - chipid |= adreno_gpu->rev.major << 16;
> > - chipid |= adreno_gpu->rev.minor << 12;
> > - chipid |= adreno_gpu->rev.patchid << 8;
> > + /* Note that the GMU has a slightly different layout for
> > + * chip_id, for whatever reason, so a bit of massaging
> > + * is needed. The upper 16b are the same, but minor and
> > + * patchid are packed in four bits each with the lower
> > + * 8b unused:
> > + */
> > + chipid = adreno_gpu->chip_id & 0xffff0000;
> > + chipid |= (adreno_gpu->chip_id << 4) & 0xf000; /* minor */
> > + chipid |= (adreno_gpu->chip_id << 8) & 0x0f00; /* patchid */
>
> I'd beg for explicit FIELD_GET and FIELD_PREP here.
>
> > gmu_write(gmu, REG_A6XX_GMU_HFI_SFR_ADDR, chipid);
> > diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> > index 77b23c004b94..ed075729ca09 100644
> > --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> > +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> > @@ -2344,10 +2344,13 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev)
> > /*
> > * We need to know the platform type before calling into adreno_gpu_init
> > * so that the hw_apriv flag can be correctly set. Snoop into the info
> > - * and grab the revision number
> > + * and grab the revision number.
> > + *
> > + * Note that we wouldn't have been able to get this far if there is not
> > + * a device table entry for this chip_id
>
> Having seen this note twice, shouldn't we explicitly pass adreno_info to our
> aNxx_gpu_init() functions and then further to adreno_gpu_init()?
>
> > */
> > - info = adreno_info(config->rev);
> > - if (!info)
> > + info = adreno_find_info(config->chip_id);
> > + if (WARN_ON(!info))
> > return ERR_PTR(-EINVAL);
> > adreno_gpu->base.hw_apriv = !!(info->quirks & ADRENO_QUIRK_HAS_HW_APRIV);
> > diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c
> > index fd2e183bce60..4a718ff33635 100644
> > --- a/drivers/gpu/drm/msm/adreno/adreno_device.c
> > +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c
> > @@ -22,7 +22,7 @@ module_param_named(allow_vram_carveout, allow_vram_carveout, bool, 0600);
> > static const struct adreno_info gpulist[] = {
> > {
> > - .rev = ADRENO_REV(2, 0, 0, 0),
> > + .chip_ids = ADRENO_CHIP_IDS(0x02000000),
>
> This begs to use bit masks, but see below
>
> > .family = ADRENO_2XX_GEN1,
> > .revn = 200,
> > .fw = {
>
> [skipped]
>
> > @@ -77,7 +77,11 @@ static const struct adreno_info gpulist[] = {
> > .inactive_period = DRM_MSM_INACTIVE_PERIOD,
> > .init = a3xx_gpu_init,
> > }, {
> > - .rev = ADRENO_REV(3, 2, ANY_ID, ANY_ID),
> > + .chip_ids = ADRENO_CHIP_IDS(
> > + 0x03020000,
> > + 0x03020001,
> > + 0x03020002
>
> definitely a bitmask would help
>
> > + ),
> > .family = ADRENO_3XX,
> > .revn = 320,
> > .fw = {
>
> [skipped the rest]
>
> > @@ -494,31 +502,16 @@ MODULE_FIRMWARE("qcom/a630_sqe.fw");
> > MODULE_FIRMWARE("qcom/a630_gmu.bin");
> > MODULE_FIRMWARE("qcom/a630_zap.mbn");
> > -static inline bool _rev_match(uint8_t entry, uint8_t id)
> > -{
> > - return (entry == ANY_ID) || (entry == id);
> > -}
> > -
> > -bool adreno_cmp_rev(struct adreno_rev rev1, struct adreno_rev rev2)
> > -{
> > -
> > - return _rev_match(rev1.core, rev2.core) &&
> > - _rev_match(rev1.major, rev2.major) &&
> > - _rev_match(rev1.minor, rev2.minor) &&
> > - _rev_match(rev1.patchid, rev2.patchid);
> > -}
> > -
> > -const struct adreno_info *adreno_info(struct adreno_rev rev)
> > +const struct adreno_info *adreno_find_info(uint32_t chip_id)
> > {
> > - int i;
> > -
> > /* identify gpu: */
> > - for (i = 0; i < ARRAY_SIZE(gpulist); i++) {
> > + for (int i = 0; i < ARRAY_SIZE(gpulist); i++) {
> > const struct adreno_info *info = &gpulist[i];
> > if (info->machine && !of_machine_is_compatible(info->machine))
> > continue;
> > - if (adreno_cmp_rev(info->rev, rev))
> > - return info;
> > + for (int j = 0; info->chip_ids[j]; j++)
> > + if (info->chip_ids[j] == chip_id)
> > + return info;
> > }
> > return NULL;
> > @@ -598,12 +591,11 @@ struct msm_gpu *adreno_load_gpu(struct drm_device *dev)
> > return NULL;
> > }
> > -static int find_chipid(struct device *dev, struct adreno_rev *rev)
> > +static int find_chipid(struct device *dev, uint32_t *chipid)
> > {
> > struct device_node *node = dev->of_node;
> > const char *compat;
> > int ret;
> > - u32 chipid;
> > /* first search the compat strings for qcom,adreno-XYZ.W: */
> > ret = of_property_read_string_index(node, "compatible", 0, &compat);
> > @@ -612,32 +604,34 @@ static int find_chipid(struct device *dev, struct adreno_rev *rev)
> > if (sscanf(compat, "qcom,adreno-%u.%u", &r, &patch) == 2 ||
> > sscanf(compat, "amd,imageon-%u.%u", &r, &patch) == 2) {
> > - rev->core = r / 100;
> > + uint32_t core, major, minor;
> > +
> > + core = r / 100;
> > r %= 100;
> > - rev->major = r / 10;
> > + major = r / 10;
> > r %= 10;
> > - rev->minor = r;
> > - rev->patchid = patch;
> > + minor = r;
> > +
> > + *chipid = (core << 24) |
> > + (major << 16) |
> > + (minor << 8) |
> > + patch;
>
> This starts to look realy crazy. I'd repeat my suggestion of moving towards
> of_device match data. This would result in some duplication, we'd have to
> explicitly list all supported compatibles in the of_match_table. But then we
> can drop all the CHIPID lists from device table and/or manual parsing of the
> chipid from the compat field.
>
> This way we can have per-SoC overrides, etc.
>
> > return 0;
> > }
> > +
> > + if (sscanf(compat, "qcom,adreno-%08x", chipid) == 1)
> > + return 0;
> > }
> > /* and if that fails, fall back to legacy "qcom,chipid" property: */
> > - ret = of_property_read_u32(node, "qcom,chipid", &chipid);
> > + ret = of_property_read_u32(node, "qcom,chipid", chipid);
> > if (ret) {
> > DRM_DEV_ERROR(dev, "could not parse qcom,chipid: %d\n", ret);
> > return ret;
> > }
> > - rev->core = (chipid >> 24) & 0xff;
> > - rev->major = (chipid >> 16) & 0xff;
> > - rev->minor = (chipid >> 8) & 0xff;
> > - rev->patchid = (chipid & 0xff);
> > -
> > dev_warn(dev, "Using legacy qcom,chipid binding!\n");
> > - dev_warn(dev, "Use compatible qcom,adreno-%u%u%u.%u instead.\n",
> > - rev->core, rev->major, rev->minor, rev->patchid);
> > return 0;
> > }
> > @@ -651,22 +645,22 @@ static int adreno_bind(struct device *dev, struct device *master, void *data)
> > struct msm_gpu *gpu;
> > int ret;
> > - ret = find_chipid(dev, &config.rev);
> > + ret = find_chipid(dev, &config.chip_id);
> > if (ret)
> > return ret;
> > dev->platform_data = &config;
> > priv->gpu_pdev = to_platform_device(dev);
> > - info = adreno_info(config.rev);
> > + info = adreno_find_info(config.chip_id);
> > if (!info) {
> > dev_warn(drm->dev, "Unknown GPU revision: %"ADRENO_CHIPID_FMT"\n",
> > - ADRENO_CHIPID_ARGS(config.rev));
> > + ADRENO_CHIPID_ARGS(config.chip_id));
> > return -ENXIO;
> > }
> > - DBG("Found GPU: %"ADRENO_CHIPID_FMT, ADRENO_CHIPID_ARGS(config.rev));
> > + DBG("Found GPU: %"ADRENO_CHIPID_FMT, ADRENO_CHIPID_ARGS(config.chip_id));
> > priv->is_a2xx = info->family < ADRENO_3XX;
> > priv->has_cached_coherent =
> > diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
> > index 1a982a926f21..1274609a74b1 100644
> > --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c
> > +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
> > @@ -326,10 +326,7 @@ int adreno_get_param(struct msm_gpu *gpu, struct msm_file_private *ctx,
> > *value = !adreno_is_a650_family(adreno_gpu) ? 0x100000 : 0;
> > return 0;
> > case MSM_PARAM_CHIP_ID:
> > - *value = (uint64_t)adreno_gpu->rev.patchid |
> > - ((uint64_t)adreno_gpu->rev.minor << 8) |
> > - ((uint64_t)adreno_gpu->rev.major << 16) |
> > - ((uint64_t)adreno_gpu->rev.core << 24);
> > + *value = adreno_gpu->chip_id;
> > if (!adreno_gpu->info->revn)
> > *value |= ((uint64_t) adreno_gpu->speedbin) << 32;
> > return 0;
> > @@ -849,7 +846,7 @@ void adreno_show(struct msm_gpu *gpu, struct msm_gpu_state *state,
> > drm_printf(p, "revision: %u (%"ADRENO_CHIPID_FMT")\n",
> > adreno_gpu->info->revn,
> > - ADRENO_CHIPID_ARGS(adreno_gpu->rev));
> > + ADRENO_CHIPID_ARGS(adreno_gpu->chip_id));
> > /*
> > * If this is state collected due to iova fault, so fault related info
> > *
> > @@ -922,7 +919,7 @@ void adreno_dump_info(struct msm_gpu *gpu)
> > printk("revision: %u (%"ADRENO_CHIPID_FMT")\n",
> > adreno_gpu->info->revn,
> > - ADRENO_CHIPID_ARGS(adreno_gpu->rev));
> > + ADRENO_CHIPID_ARGS(adreno_gpu->chip_id));
> > for (i = 0; i < gpu->nr_rings; i++) {
> > struct msm_ringbuffer *ring = gpu->rb[i];
> > @@ -1072,14 +1069,13 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev,
> > struct adreno_platform_config *config = dev->platform_data;
> > struct msm_gpu_config adreno_gpu_config = { 0 };
> > struct msm_gpu *gpu = &adreno_gpu->base;
> > - struct adreno_rev *rev = &config->rev;
> > const char *gpu_name;
> > u32 speedbin;
> > int ret;
> > adreno_gpu->funcs = funcs;
> > - adreno_gpu->info = adreno_info(config->rev);
> > - adreno_gpu->rev = *rev;
> > + adreno_gpu->info = adreno_find_info(config->chip_id);
> > + adreno_gpu->chip_id = config->chip_id;
> > /* Only handle the core clock when GMU is not in use (or is absent). */
> > if (adreno_has_gmu_wrapper(adreno_gpu) ||
> > @@ -1104,7 +1100,7 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev,
> > adreno_gpu->speedbin = (uint16_t) (0xffff & speedbin);
> > gpu_name = devm_kasprintf(dev, GFP_KERNEL, "%"ADRENO_CHIPID_FMT,
> > - ADRENO_CHIPID_ARGS(config->rev));
> > + ADRENO_CHIPID_ARGS(config->chip_id));
> > if (!gpu_name)
> > return -ENOMEM;
> > diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> > index 73e7155f164c..18f53c7ab589 100644
> > --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> > +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> > @@ -54,23 +54,15 @@ enum adreno_family {
> > #define ADRENO_QUIRK_HAS_HW_APRIV BIT(3)
> > #define ADRENO_QUIRK_HAS_CACHED_COHERENT BIT(4)
> > -struct adreno_rev {
> > - uint8_t core;
> > - uint8_t major;
> > - uint8_t minor;
> > - uint8_t patchid;
> > -};
> > -
> > -#define ANY_ID 0xff
> > -
> > -#define ADRENO_REV(core, major, minor, patchid) \
> > - ((struct adreno_rev){ core, major, minor, patchid })
> > -
> > /* Helper for formating the chip_id in the way that userspace tools like
> > * crashdec expect.
> > */
> > #define ADRENO_CHIPID_FMT "u.%u.%u.%u"
> > -#define ADRENO_CHIPID_ARGS(_r) (_r).core, (_r).major, (_r).minor, (_r).patchid
> > +#define ADRENO_CHIPID_ARGS(_c) \
> > + (((_c) >> 24) & 0xff), \
> > + (((_c) >> 16) & 0xff), \
> > + (((_c) >> 8) & 0xff), \
> > + ((_c) & 0xff)
>
> So, we still have some meaning for chipid?
>
> > struct adreno_gpu_funcs {
> > struct msm_gpu_funcs base;
> > @@ -87,7 +79,12 @@ extern const struct adreno_reglist a660_hwcg[], a690_hwcg[];
> > struct adreno_info {
> > const char *machine;
> > - struct adreno_rev rev;
> > + /**
> > + * @chipids: Table of matching chip-ids
> > + *
> > + * Terminated with 0 sentinal
> > + */
> > + uint32_t *chip_ids;
> > enum adreno_family family;
> > uint32_t revn;
> > const char *fw[ADRENO_FW_MAX];
> > @@ -107,6 +104,8 @@ struct adreno_info {
> > uint32_t *speedbins;
> > };
> > +#define ADRENO_CHIP_IDS(tbl...) (uint32_t[]) { tbl, 0 }
> > +
> > /*
> > * Helper to build a speedbin table, ie. the table:
> > * fuse | speedbin
> > @@ -125,12 +124,12 @@ struct adreno_info {
> > */
> > #define ADRENO_SPEEDBINS(tbl...) (uint32_t[]) { tbl, UINT_MAX }
> > -const struct adreno_info *adreno_info(struct adreno_rev rev);
> > +const struct adreno_info *adreno_find_info(uint32_t chip_id);
> > struct adreno_gpu {
> > struct msm_gpu base;
> > - struct adreno_rev rev;
> > const struct adreno_info *info;
> > + uint32_t chip_id;
> > uint16_t speedbin;
> > const struct adreno_gpu_funcs *funcs;
> > @@ -179,7 +178,7 @@ struct adreno_ocmem {
> > /* platform config data (ie. from DT, or pdata) */
> > struct adreno_platform_config {
> > - struct adreno_rev rev;
> > + uint32_t chip_id;
> > };
> > #define ADRENO_IDLE_TIMEOUT msecs_to_jiffies(1000)
> > @@ -196,7 +195,15 @@ struct adreno_platform_config {
> > __ret; \
> > })
> > -bool adreno_cmp_rev(struct adreno_rev rev1, struct adreno_rev rev2);
> > +static inline uint8_t adreno_patchid(const struct adreno_gpu *gpu)
> > +{
> > + /* It is probably ok to assume legacy "adreno_rev" format
> > + * for all a6xx devices, but probably best to limit this
> > + * to older things.
> > + */
> > + WARN_ON_ONCE(gpu->info->family >= ADRENO_6XX_GEN1);
> > + return gpu->chip_id & 0xff;
> > +}
> > static inline bool adreno_is_revn(const struct adreno_gpu *gpu, uint32_t revn)
> > {
> > @@ -252,7 +259,7 @@ static inline bool adreno_is_a330(const struct adreno_gpu *gpu)
> > static inline bool adreno_is_a330v2(const struct adreno_gpu *gpu)
> > {
> > - return adreno_is_a330(gpu) && (gpu->rev.patchid > 0);
> > + return adreno_is_a330(gpu) && (adreno_patchid(gpu) > 0);
> > }
> > static inline int adreno_is_a405(const struct adreno_gpu *gpu)
> > @@ -342,8 +349,7 @@ static inline int adreno_is_a650(const struct adreno_gpu *gpu)
> > static inline int adreno_is_7c3(const struct adreno_gpu *gpu)
> > {
> > - /* The order of args is important here to handle ANY_ID correctly */
> > - return adreno_cmp_rev(ADRENO_REV(6, 3, 5, ANY_ID), gpu->rev);
> > + return gpu->info->chip_ids[0] == 0x06030500;
Why not use adreno_gpu->chip_id here? Or do we need this check before
adreno_gpu_init()? I thought we got rid of those.
>
> Ugh. The thing that bugs me isn't even the manual comparison of chip_ids[0],
> but the fact that these two platforms stand aside. I think at the end we
> should have a single mechanism for checking GPU's SKUs.
>
> Or maybe we should get rid of that completely.
>
> If we get rid of a single gpulist table and move individual GPU info
> definitions to aNxx_gpu.c, we can subclass a generic info structure with
> generation-specific data, for example generation-specific quirks, pointers
> to hcwg or VBIF registers, etc. And then instead of having adreno_is_foo all
> over the code we can migrate most of these checks to data in the gpu info
> data.
I think the downstream driver does what you described here. It helps to
move more generation-specific data to the table without inflating the
gpu table size.
-Akhil
>
> > }
> > static inline int adreno_is_a660(const struct adreno_gpu *gpu)
> > @@ -358,8 +364,7 @@ static inline int adreno_is_a680(const struct adreno_gpu *gpu)
> > static inline int adreno_is_a690(const struct adreno_gpu *gpu)
> > {
> > - /* The order of args is important here to handle ANY_ID correctly */
> > - return adreno_cmp_rev(ADRENO_REV(6, 9, 0, ANY_ID), gpu->rev);
> > + return gpu->info->chip_ids[0] == 0x06090000;
> > };
> > /* check for a615, a616, a618, a619 or any a630 derivatives */
> > static inline int adreno_is_a630_family(const struct adreno_gpu *gpu)
>
> --
> With best wishes
> Dmitry
>
^ permalink raw reply [flat|nested] 73+ messages in thread
* Re: [Freedreno] [PATCH 12/12] drm/msm/adreno: Switch to chip-id for identifying GPU
2023-07-13 21:39 ` Akhil P Oommen
@ 2023-07-13 22:06 ` Rob Clark
2023-07-13 22:53 ` Dmitry Baryshkov
2023-07-17 22:09 ` Akhil P Oommen
0 siblings, 2 replies; 73+ messages in thread
From: Rob Clark @ 2023-07-13 22:06 UTC (permalink / raw)
To: Akhil P Oommen
Cc: Rob Clark, linux-arm-msm, dri-devel, Konrad Dybcio,
Dmitry Baryshkov, freedreno
On Thu, Jul 13, 2023 at 2:39 PM Akhil P Oommen <quic_akhilpo@quicinc.com> wrote:
>
> On Fri, Jul 07, 2023 at 06:45:42AM +0300, Dmitry Baryshkov wrote:
> >
> > On 07/07/2023 00:10, Rob Clark wrote:
> > > From: Rob Clark <robdclark@chromium.org>
> > >
> > > Since the revision becomes an opaque identifier with future GPUs, move
> > > away from treating different ranges of bits as having a given meaning.
> > > This means that we need to explicitly list different patch revisions in
> > > the device table.
> > >
> > > Signed-off-by: Rob Clark <robdclark@chromium.org>
> > > ---
> > > drivers/gpu/drm/msm/adreno/a4xx_gpu.c | 2 +-
> > > drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 11 +-
> > > drivers/gpu/drm/msm/adreno/a5xx_power.c | 2 +-
> > > drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 13 ++-
> > > drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 9 +-
> > > drivers/gpu/drm/msm/adreno/adreno_device.c | 128 ++++++++++-----------
> > > drivers/gpu/drm/msm/adreno/adreno_gpu.c | 16 +--
> > > drivers/gpu/drm/msm/adreno/adreno_gpu.h | 51 ++++----
> > > 8 files changed, 122 insertions(+), 110 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/msm/adreno/a4xx_gpu.c b/drivers/gpu/drm/msm/adreno/a4xx_gpu.c
> > > index 715436cb3996..8b4cdf95f445 100644
> > > --- a/drivers/gpu/drm/msm/adreno/a4xx_gpu.c
> > > +++ b/drivers/gpu/drm/msm/adreno/a4xx_gpu.c
> > > @@ -145,7 +145,7 @@ static void a4xx_enable_hwcg(struct msm_gpu *gpu)
> > > gpu_write(gpu, REG_A4XX_RBBM_CLOCK_DELAY_HLSQ, 0x00220000);
> > > /* Early A430's have a timing issue with SP/TP power collapse;
> > > disabling HW clock gating prevents it. */
> > > - if (adreno_is_a430(adreno_gpu) && adreno_gpu->rev.patchid < 2)
> > > + if (adreno_is_a430(adreno_gpu) && adreno_patchid(adreno_gpu) < 2)
> > > gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL, 0);
> > > else
> > > gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL, 0xAAAAAAAA);
> > > diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
> > > index f0803e94ebe5..70d2b5342cd9 100644
> > > --- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
> > > +++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
> > > @@ -1744,6 +1744,7 @@ struct msm_gpu *a5xx_gpu_init(struct drm_device *dev)
> > > struct msm_drm_private *priv = dev->dev_private;
> > > struct platform_device *pdev = priv->gpu_pdev;
> > > struct adreno_platform_config *config = pdev->dev.platform_data;
> > > + const struct adreno_info *info;
> > > struct a5xx_gpu *a5xx_gpu = NULL;
> > > struct adreno_gpu *adreno_gpu;
> > > struct msm_gpu *gpu;
> > > @@ -1770,7 +1771,15 @@ struct msm_gpu *a5xx_gpu_init(struct drm_device *dev)
> > > nr_rings = 4;
> > > - if (adreno_cmp_rev(ADRENO_REV(5, 1, 0, ANY_ID), config->rev))
> > > + /*
> > > + * Note that we wouldn't have been able to get this far if there is not
> > > + * a device table entry for this chip_id
> > > + */
> > > + info = adreno_find_info(config->chip_id);
> > > + if (WARN_ON(!info))
> > > + return ERR_PTR(-EINVAL);
> > > +
> > > + if (info->revn == 510)
> > > nr_rings = 1;
> > > ret = adreno_gpu_init(dev, pdev, adreno_gpu, &funcs, nr_rings);
> > > diff --git a/drivers/gpu/drm/msm/adreno/a5xx_power.c b/drivers/gpu/drm/msm/adreno/a5xx_power.c
> > > index 0e63a1429189..7705f8010484 100644
> > > --- a/drivers/gpu/drm/msm/adreno/a5xx_power.c
> > > +++ b/drivers/gpu/drm/msm/adreno/a5xx_power.c
> > > @@ -179,7 +179,7 @@ static void a540_lm_setup(struct msm_gpu *gpu)
> > > /* The battery current limiter isn't enabled for A540 */
> > > config = AGC_LM_CONFIG_BCL_DISABLED;
> > > - config |= adreno_gpu->rev.patchid << AGC_LM_CONFIG_GPU_VERSION_SHIFT;
> > > + config |= adreno_patchid(adreno_gpu) << AGC_LM_CONFIG_GPU_VERSION_SHIFT;
> > > /* For now disable GPMU side throttling */
> > > config |= AGC_LM_CONFIG_THROTTLE_DISABLE;
> > > diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
> > > index f1bb20574018..a9ba547a120c 100644
> > > --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
> > > +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
> > > @@ -790,10 +790,15 @@ static int a6xx_gmu_fw_start(struct a6xx_gmu *gmu, unsigned int state)
> > > gmu_write(gmu, REG_A6XX_GMU_AHB_FENCE_RANGE_0,
> > > (1 << 31) | (0xa << 18) | (0xa0));
> > > - chipid = adreno_gpu->rev.core << 24;
> > > - chipid |= adreno_gpu->rev.major << 16;
> > > - chipid |= adreno_gpu->rev.minor << 12;
> > > - chipid |= adreno_gpu->rev.patchid << 8;
> > > + /* Note that the GMU has a slightly different layout for
> > > + * chip_id, for whatever reason, so a bit of massaging
> > > + * is needed. The upper 16b are the same, but minor and
> > > + * patchid are packed in four bits each with the lower
> > > + * 8b unused:
> > > + */
> > > + chipid = adreno_gpu->chip_id & 0xffff0000;
> > > + chipid |= (adreno_gpu->chip_id << 4) & 0xf000; /* minor */
> > > + chipid |= (adreno_gpu->chip_id << 8) & 0x0f00; /* patchid */
> >
> > I'd beg for explicit FIELD_GET and FIELD_PREP here.
> >
> > > gmu_write(gmu, REG_A6XX_GMU_HFI_SFR_ADDR, chipid);
> > > diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> > > index 77b23c004b94..ed075729ca09 100644
> > > --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> > > +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> > > @@ -2344,10 +2344,13 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev)
> > > /*
> > > * We need to know the platform type before calling into adreno_gpu_init
> > > * so that the hw_apriv flag can be correctly set. Snoop into the info
> > > - * and grab the revision number
> > > + * and grab the revision number.
> > > + *
> > > + * Note that we wouldn't have been able to get this far if there is not
> > > + * a device table entry for this chip_id
> >
> > Having seen this note twice, shouldn't we explicitly pass adreno_info to our
> > aNxx_gpu_init() functions and then further to adreno_gpu_init()?
> >
> > > */
> > > - info = adreno_info(config->rev);
> > > - if (!info)
> > > + info = adreno_find_info(config->chip_id);
> > > + if (WARN_ON(!info))
> > > return ERR_PTR(-EINVAL);
> > > adreno_gpu->base.hw_apriv = !!(info->quirks & ADRENO_QUIRK_HAS_HW_APRIV);
> > > diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c
> > > index fd2e183bce60..4a718ff33635 100644
> > > --- a/drivers/gpu/drm/msm/adreno/adreno_device.c
> > > +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c
> > > @@ -22,7 +22,7 @@ module_param_named(allow_vram_carveout, allow_vram_carveout, bool, 0600);
> > > static const struct adreno_info gpulist[] = {
> > > {
> > > - .rev = ADRENO_REV(2, 0, 0, 0),
> > > + .chip_ids = ADRENO_CHIP_IDS(0x02000000),
> >
> > This begs to use bit masks, but see below
> >
> > > .family = ADRENO_2XX_GEN1,
> > > .revn = 200,
> > > .fw = {
> >
> > [skipped]
> >
> > > @@ -77,7 +77,11 @@ static const struct adreno_info gpulist[] = {
> > > .inactive_period = DRM_MSM_INACTIVE_PERIOD,
> > > .init = a3xx_gpu_init,
> > > }, {
> > > - .rev = ADRENO_REV(3, 2, ANY_ID, ANY_ID),
> > > + .chip_ids = ADRENO_CHIP_IDS(
> > > + 0x03020000,
> > > + 0x03020001,
> > > + 0x03020002
> >
> > definitely a bitmask would help
> >
> > > + ),
> > > .family = ADRENO_3XX,
> > > .revn = 320,
> > > .fw = {
> >
> > [skipped the rest]
> >
> > > @@ -494,31 +502,16 @@ MODULE_FIRMWARE("qcom/a630_sqe.fw");
> > > MODULE_FIRMWARE("qcom/a630_gmu.bin");
> > > MODULE_FIRMWARE("qcom/a630_zap.mbn");
> > > -static inline bool _rev_match(uint8_t entry, uint8_t id)
> > > -{
> > > - return (entry == ANY_ID) || (entry == id);
> > > -}
> > > -
> > > -bool adreno_cmp_rev(struct adreno_rev rev1, struct adreno_rev rev2)
> > > -{
> > > -
> > > - return _rev_match(rev1.core, rev2.core) &&
> > > - _rev_match(rev1.major, rev2.major) &&
> > > - _rev_match(rev1.minor, rev2.minor) &&
> > > - _rev_match(rev1.patchid, rev2.patchid);
> > > -}
> > > -
> > > -const struct adreno_info *adreno_info(struct adreno_rev rev)
> > > +const struct adreno_info *adreno_find_info(uint32_t chip_id)
> > > {
> > > - int i;
> > > -
> > > /* identify gpu: */
> > > - for (i = 0; i < ARRAY_SIZE(gpulist); i++) {
> > > + for (int i = 0; i < ARRAY_SIZE(gpulist); i++) {
> > > const struct adreno_info *info = &gpulist[i];
> > > if (info->machine && !of_machine_is_compatible(info->machine))
> > > continue;
> > > - if (adreno_cmp_rev(info->rev, rev))
> > > - return info;
> > > + for (int j = 0; info->chip_ids[j]; j++)
> > > + if (info->chip_ids[j] == chip_id)
> > > + return info;
> > > }
> > > return NULL;
> > > @@ -598,12 +591,11 @@ struct msm_gpu *adreno_load_gpu(struct drm_device *dev)
> > > return NULL;
> > > }
> > > -static int find_chipid(struct device *dev, struct adreno_rev *rev)
> > > +static int find_chipid(struct device *dev, uint32_t *chipid)
> > > {
> > > struct device_node *node = dev->of_node;
> > > const char *compat;
> > > int ret;
> > > - u32 chipid;
> > > /* first search the compat strings for qcom,adreno-XYZ.W: */
> > > ret = of_property_read_string_index(node, "compatible", 0, &compat);
> > > @@ -612,32 +604,34 @@ static int find_chipid(struct device *dev, struct adreno_rev *rev)
> > > if (sscanf(compat, "qcom,adreno-%u.%u", &r, &patch) == 2 ||
> > > sscanf(compat, "amd,imageon-%u.%u", &r, &patch) == 2) {
> > > - rev->core = r / 100;
> > > + uint32_t core, major, minor;
> > > +
> > > + core = r / 100;
> > > r %= 100;
> > > - rev->major = r / 10;
> > > + major = r / 10;
> > > r %= 10;
> > > - rev->minor = r;
> > > - rev->patchid = patch;
> > > + minor = r;
> > > +
> > > + *chipid = (core << 24) |
> > > + (major << 16) |
> > > + (minor << 8) |
> > > + patch;
> >
> > This starts to look realy crazy. I'd repeat my suggestion of moving towards
> > of_device match data. This would result in some duplication, we'd have to
> > explicitly list all supported compatibles in the of_match_table. But then we
> > can drop all the CHIPID lists from device table and/or manual parsing of the
> > chipid from the compat field.
> >
> > This way we can have per-SoC overrides, etc.
> >
> > > return 0;
> > > }
> > > +
> > > + if (sscanf(compat, "qcom,adreno-%08x", chipid) == 1)
> > > + return 0;
> > > }
> > > /* and if that fails, fall back to legacy "qcom,chipid" property: */
> > > - ret = of_property_read_u32(node, "qcom,chipid", &chipid);
> > > + ret = of_property_read_u32(node, "qcom,chipid", chipid);
> > > if (ret) {
> > > DRM_DEV_ERROR(dev, "could not parse qcom,chipid: %d\n", ret);
> > > return ret;
> > > }
> > > - rev->core = (chipid >> 24) & 0xff;
> > > - rev->major = (chipid >> 16) & 0xff;
> > > - rev->minor = (chipid >> 8) & 0xff;
> > > - rev->patchid = (chipid & 0xff);
> > > -
> > > dev_warn(dev, "Using legacy qcom,chipid binding!\n");
> > > - dev_warn(dev, "Use compatible qcom,adreno-%u%u%u.%u instead.\n",
> > > - rev->core, rev->major, rev->minor, rev->patchid);
> > > return 0;
> > > }
> > > @@ -651,22 +645,22 @@ static int adreno_bind(struct device *dev, struct device *master, void *data)
> > > struct msm_gpu *gpu;
> > > int ret;
> > > - ret = find_chipid(dev, &config.rev);
> > > + ret = find_chipid(dev, &config.chip_id);
> > > if (ret)
> > > return ret;
> > > dev->platform_data = &config;
> > > priv->gpu_pdev = to_platform_device(dev);
> > > - info = adreno_info(config.rev);
> > > + info = adreno_find_info(config.chip_id);
> > > if (!info) {
> > > dev_warn(drm->dev, "Unknown GPU revision: %"ADRENO_CHIPID_FMT"\n",
> > > - ADRENO_CHIPID_ARGS(config.rev));
> > > + ADRENO_CHIPID_ARGS(config.chip_id));
> > > return -ENXIO;
> > > }
> > > - DBG("Found GPU: %"ADRENO_CHIPID_FMT, ADRENO_CHIPID_ARGS(config.rev));
> > > + DBG("Found GPU: %"ADRENO_CHIPID_FMT, ADRENO_CHIPID_ARGS(config.chip_id));
> > > priv->is_a2xx = info->family < ADRENO_3XX;
> > > priv->has_cached_coherent =
> > > diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
> > > index 1a982a926f21..1274609a74b1 100644
> > > --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c
> > > +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
> > > @@ -326,10 +326,7 @@ int adreno_get_param(struct msm_gpu *gpu, struct msm_file_private *ctx,
> > > *value = !adreno_is_a650_family(adreno_gpu) ? 0x100000 : 0;
> > > return 0;
> > > case MSM_PARAM_CHIP_ID:
> > > - *value = (uint64_t)adreno_gpu->rev.patchid |
> > > - ((uint64_t)adreno_gpu->rev.minor << 8) |
> > > - ((uint64_t)adreno_gpu->rev.major << 16) |
> > > - ((uint64_t)adreno_gpu->rev.core << 24);
> > > + *value = adreno_gpu->chip_id;
> > > if (!adreno_gpu->info->revn)
> > > *value |= ((uint64_t) adreno_gpu->speedbin) << 32;
> > > return 0;
> > > @@ -849,7 +846,7 @@ void adreno_show(struct msm_gpu *gpu, struct msm_gpu_state *state,
> > > drm_printf(p, "revision: %u (%"ADRENO_CHIPID_FMT")\n",
> > > adreno_gpu->info->revn,
> > > - ADRENO_CHIPID_ARGS(adreno_gpu->rev));
> > > + ADRENO_CHIPID_ARGS(adreno_gpu->chip_id));
> > > /*
> > > * If this is state collected due to iova fault, so fault related info
> > > *
> > > @@ -922,7 +919,7 @@ void adreno_dump_info(struct msm_gpu *gpu)
> > > printk("revision: %u (%"ADRENO_CHIPID_FMT")\n",
> > > adreno_gpu->info->revn,
> > > - ADRENO_CHIPID_ARGS(adreno_gpu->rev));
> > > + ADRENO_CHIPID_ARGS(adreno_gpu->chip_id));
> > > for (i = 0; i < gpu->nr_rings; i++) {
> > > struct msm_ringbuffer *ring = gpu->rb[i];
> > > @@ -1072,14 +1069,13 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev,
> > > struct adreno_platform_config *config = dev->platform_data;
> > > struct msm_gpu_config adreno_gpu_config = { 0 };
> > > struct msm_gpu *gpu = &adreno_gpu->base;
> > > - struct adreno_rev *rev = &config->rev;
> > > const char *gpu_name;
> > > u32 speedbin;
> > > int ret;
> > > adreno_gpu->funcs = funcs;
> > > - adreno_gpu->info = adreno_info(config->rev);
> > > - adreno_gpu->rev = *rev;
> > > + adreno_gpu->info = adreno_find_info(config->chip_id);
> > > + adreno_gpu->chip_id = config->chip_id;
> > > /* Only handle the core clock when GMU is not in use (or is absent). */
> > > if (adreno_has_gmu_wrapper(adreno_gpu) ||
> > > @@ -1104,7 +1100,7 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev,
> > > adreno_gpu->speedbin = (uint16_t) (0xffff & speedbin);
> > > gpu_name = devm_kasprintf(dev, GFP_KERNEL, "%"ADRENO_CHIPID_FMT,
> > > - ADRENO_CHIPID_ARGS(config->rev));
> > > + ADRENO_CHIPID_ARGS(config->chip_id));
> > > if (!gpu_name)
> > > return -ENOMEM;
> > > diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> > > index 73e7155f164c..18f53c7ab589 100644
> > > --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> > > +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> > > @@ -54,23 +54,15 @@ enum adreno_family {
> > > #define ADRENO_QUIRK_HAS_HW_APRIV BIT(3)
> > > #define ADRENO_QUIRK_HAS_CACHED_COHERENT BIT(4)
> > > -struct adreno_rev {
> > > - uint8_t core;
> > > - uint8_t major;
> > > - uint8_t minor;
> > > - uint8_t patchid;
> > > -};
> > > -
> > > -#define ANY_ID 0xff
> > > -
> > > -#define ADRENO_REV(core, major, minor, patchid) \
> > > - ((struct adreno_rev){ core, major, minor, patchid })
> > > -
> > > /* Helper for formating the chip_id in the way that userspace tools like
> > > * crashdec expect.
> > > */
> > > #define ADRENO_CHIPID_FMT "u.%u.%u.%u"
> > > -#define ADRENO_CHIPID_ARGS(_r) (_r).core, (_r).major, (_r).minor, (_r).patchid
> > > +#define ADRENO_CHIPID_ARGS(_c) \
> > > + (((_c) >> 24) & 0xff), \
> > > + (((_c) >> 16) & 0xff), \
> > > + (((_c) >> 8) & 0xff), \
> > > + ((_c) & 0xff)
> >
> > So, we still have some meaning for chipid?
> >
> > > struct adreno_gpu_funcs {
> > > struct msm_gpu_funcs base;
> > > @@ -87,7 +79,12 @@ extern const struct adreno_reglist a660_hwcg[], a690_hwcg[];
> > > struct adreno_info {
> > > const char *machine;
> > > - struct adreno_rev rev;
> > > + /**
> > > + * @chipids: Table of matching chip-ids
> > > + *
> > > + * Terminated with 0 sentinal
> > > + */
> > > + uint32_t *chip_ids;
> > > enum adreno_family family;
> > > uint32_t revn;
> > > const char *fw[ADRENO_FW_MAX];
> > > @@ -107,6 +104,8 @@ struct adreno_info {
> > > uint32_t *speedbins;
> > > };
> > > +#define ADRENO_CHIP_IDS(tbl...) (uint32_t[]) { tbl, 0 }
> > > +
> > > /*
> > > * Helper to build a speedbin table, ie. the table:
> > > * fuse | speedbin
> > > @@ -125,12 +124,12 @@ struct adreno_info {
> > > */
> > > #define ADRENO_SPEEDBINS(tbl...) (uint32_t[]) { tbl, UINT_MAX }
> > > -const struct adreno_info *adreno_info(struct adreno_rev rev);
> > > +const struct adreno_info *adreno_find_info(uint32_t chip_id);
> > > struct adreno_gpu {
> > > struct msm_gpu base;
> > > - struct adreno_rev rev;
> > > const struct adreno_info *info;
> > > + uint32_t chip_id;
> > > uint16_t speedbin;
> > > const struct adreno_gpu_funcs *funcs;
> > > @@ -179,7 +178,7 @@ struct adreno_ocmem {
> > > /* platform config data (ie. from DT, or pdata) */
> > > struct adreno_platform_config {
> > > - struct adreno_rev rev;
> > > + uint32_t chip_id;
> > > };
> > > #define ADRENO_IDLE_TIMEOUT msecs_to_jiffies(1000)
> > > @@ -196,7 +195,15 @@ struct adreno_platform_config {
> > > __ret; \
> > > })
> > > -bool adreno_cmp_rev(struct adreno_rev rev1, struct adreno_rev rev2);
> > > +static inline uint8_t adreno_patchid(const struct adreno_gpu *gpu)
> > > +{
> > > + /* It is probably ok to assume legacy "adreno_rev" format
> > > + * for all a6xx devices, but probably best to limit this
> > > + * to older things.
> > > + */
> > > + WARN_ON_ONCE(gpu->info->family >= ADRENO_6XX_GEN1);
> > > + return gpu->chip_id & 0xff;
> > > +}
> > > static inline bool adreno_is_revn(const struct adreno_gpu *gpu, uint32_t revn)
> > > {
> > > @@ -252,7 +259,7 @@ static inline bool adreno_is_a330(const struct adreno_gpu *gpu)
> > > static inline bool adreno_is_a330v2(const struct adreno_gpu *gpu)
> > > {
> > > - return adreno_is_a330(gpu) && (gpu->rev.patchid > 0);
> > > + return adreno_is_a330(gpu) && (adreno_patchid(gpu) > 0);
> > > }
> > > static inline int adreno_is_a405(const struct adreno_gpu *gpu)
> > > @@ -342,8 +349,7 @@ static inline int adreno_is_a650(const struct adreno_gpu *gpu)
> > > static inline int adreno_is_7c3(const struct adreno_gpu *gpu)
> > > {
> > > - /* The order of args is important here to handle ANY_ID correctly */
> > > - return adreno_cmp_rev(ADRENO_REV(6, 3, 5, ANY_ID), gpu->rev);
> > > + return gpu->info->chip_ids[0] == 0x06030500;
>
> Why not use adreno_gpu->chip_id here? Or do we need this check before
> adreno_gpu_init()? I thought we got rid of those.
This is intentional, because there can be multiple chip-id's for a
single table entry, in theory. But the first chip_id in the gpu table
entry should suffice, and is simpler than comparing
adreno_gpu->chip_id against each possible match.
BR,
-R
> >
> > Ugh. The thing that bugs me isn't even the manual comparison of chip_ids[0],
> > but the fact that these two platforms stand aside. I think at the end we
> > should have a single mechanism for checking GPU's SKUs.
> >
> > Or maybe we should get rid of that completely.
> >
> > If we get rid of a single gpulist table and move individual GPU info
> > definitions to aNxx_gpu.c, we can subclass a generic info structure with
> > generation-specific data, for example generation-specific quirks, pointers
> > to hcwg or VBIF registers, etc. And then instead of having adreno_is_foo all
> > over the code we can migrate most of these checks to data in the gpu info
> > data.
>
> I think the downstream driver does what you described here. It helps to
> move more generation-specific data to the table without inflating the
> gpu table size.
>
> -Akhil
>
> >
> > > }
> > > static inline int adreno_is_a660(const struct adreno_gpu *gpu)
> > > @@ -358,8 +364,7 @@ static inline int adreno_is_a680(const struct adreno_gpu *gpu)
> > > static inline int adreno_is_a690(const struct adreno_gpu *gpu)
> > > {
> > > - /* The order of args is important here to handle ANY_ID correctly */
> > > - return adreno_cmp_rev(ADRENO_REV(6, 9, 0, ANY_ID), gpu->rev);
> > > + return gpu->info->chip_ids[0] == 0x06090000;
> > > };
> > > /* check for a615, a616, a618, a619 or any a630 derivatives */
> > > static inline int adreno_is_a630_family(const struct adreno_gpu *gpu)
> >
> > --
> > With best wishes
> > Dmitry
> >
^ permalink raw reply [flat|nested] 73+ messages in thread
* Re: [Freedreno] [PATCH 06/12] drm/msm/adreno: Allow SoC specific gpu device table entries
2023-07-07 0:40 ` Konrad Dybcio
@ 2023-07-13 22:15 ` Akhil P Oommen
0 siblings, 0 replies; 73+ messages in thread
From: Akhil P Oommen @ 2023-07-13 22:15 UTC (permalink / raw)
To: Konrad Dybcio; +Cc: Rob Clark, linux-arm-msm, freedreno, dri-devel
On Fri, Jul 07, 2023 at 02:40:47AM +0200, Konrad Dybcio wrote:
>
> On 6.07.2023 23:10, Rob Clark wrote:
> > From: Rob Clark <robdclark@chromium.org>
> >
> > There are cases where there are differences due to SoC integration.
> > Such as cache-coherency support, and (in the next patch) e-fuse to
> > speedbin mappings.
> >
> > Signed-off-by: Rob Clark <robdclark@chromium.org>
> > ---
> of_machine_is_compatible is rather used in extremely desperate
> situations :/ I'm not sure this is the correct way to do this..
>
> Especially since there's a direct correlation between GMU presence
> and ability to do cached coherent.
>
> The GMU mandates presence of RPMh (as most of what the GMU does is
> talk to AOSS through its RSC).
>
> To achieve I/O coherency, there must be some memory that both the
> CPU and GPU (and possibly others) can access through some sort of
> a negotiator/manager.
>
> In our case, I believe that's LLC. And guess what that implies.
> MEMNOC instead of BIMC. And guess what that implies. RPMh!
>
> Now, we know GMU => RPMh, but does it work the other way around?
I don't think we should tie gpu io-coherency with rpmh or llc. These
features are more dependent on SoC architecture than GPU arch.
-Akhil
>
> Yes. GMU wrapper was a hack because probably nobody in the Adreno team
> would have imagined that somebody would be crazy enough to fork
> multiple year old designs multiple times and release them as new
> SoCs with updated arm cores and 5G..
>
> (Except for A612 which has a "Reduced GMU" but that zombie still talks
> to RPMh. And A612 is IO-coherent. So I guess it works anyway.)
>
> Konrad
>
> > drivers/gpu/drm/msm/adreno/adreno_device.c | 34 +++++++++++++++++++---
> > drivers/gpu/drm/msm/adreno/adreno_gpu.h | 1 +
> > 2 files changed, 31 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c
> > index 3c531da417b9..e62bc895a31f 100644
> > --- a/drivers/gpu/drm/msm/adreno/adreno_device.c
> > +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c
> > @@ -258,6 +258,32 @@ static const struct adreno_info gpulist[] = {
> > .inactive_period = DRM_MSM_INACTIVE_PERIOD,
> > .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT,
> > .init = a6xx_gpu_init,
> > + }, {
> > + .machine = "qcom,sm4350",
> > + .rev = ADRENO_REV(6, 1, 9, ANY_ID),
> > + .revn = 619,
> > + .fw = {
> > + [ADRENO_FW_SQE] = "a630_sqe.fw",
> > + [ADRENO_FW_GMU] = "a619_gmu.bin",
> > + },
> > + .gmem = SZ_512K,
> > + .inactive_period = DRM_MSM_INACTIVE_PERIOD,
> > + .init = a6xx_gpu_init,
> > + .zapfw = "a615_zap.mdt",
> > + .hwcg = a615_hwcg,
> > + }, {
> > + .machine = "qcom,sm6375",
> > + .rev = ADRENO_REV(6, 1, 9, ANY_ID),
> > + .revn = 619,
> > + .fw = {
> > + [ADRENO_FW_SQE] = "a630_sqe.fw",
> > + [ADRENO_FW_GMU] = "a619_gmu.bin",
> > + },
> > + .gmem = SZ_512K,
> > + .inactive_period = DRM_MSM_INACTIVE_PERIOD,
> > + .init = a6xx_gpu_init,
> > + .zapfw = "a615_zap.mdt",
> > + .hwcg = a615_hwcg,
> > }, {
> > .rev = ADRENO_REV(6, 1, 9, ANY_ID),
> > .revn = 619,
> > @@ -409,6 +435,8 @@ const struct adreno_info *adreno_info(struct adreno_rev rev)
> > /* identify gpu: */
> > for (i = 0; i < ARRAY_SIZE(gpulist); i++) {
> > const struct adreno_info *info = &gpulist[i];
> > + if (info->machine && !of_machine_is_compatible(info->machine))
> > + continue;
> > if (adreno_cmp_rev(info->rev, rev))
> > return info;
> > }
> > @@ -563,6 +591,8 @@ static int adreno_bind(struct device *dev, struct device *master, void *data)
> > config.rev.minor, config.rev.patchid);
> >
> > priv->is_a2xx = config.rev.core == 2;
> > + priv->has_cached_coherent =
> > + !!(info->quirks & ADRENO_QUIRK_HAS_CACHED_COHERENT);
> >
> > gpu = info->init(drm);
> > if (IS_ERR(gpu)) {
> > @@ -574,10 +604,6 @@ static int adreno_bind(struct device *dev, struct device *master, void *data)
> > if (ret)
> > return ret;
> >
> > - priv->has_cached_coherent =
> > - !!(info->quirks & ADRENO_QUIRK_HAS_CACHED_COHERENT) &&
> > - !adreno_has_gmu_wrapper(to_adreno_gpu(gpu));
> > -
> > return 0;
> > }
> >
> > diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> > index e08d41337169..d5335b99c64c 100644
> > --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> > +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> > @@ -61,6 +61,7 @@ extern const struct adreno_reglist a612_hwcg[], a615_hwcg[], a630_hwcg[], a640_h
> > extern const struct adreno_reglist a660_hwcg[], a690_hwcg[];
> >
> > struct adreno_info {
> > + const char *machine;
> > struct adreno_rev rev;
> > uint32_t revn;
> > const char *fw[ADRENO_FW_MAX];
^ permalink raw reply [flat|nested] 73+ messages in thread
* Re: [Freedreno] [PATCH 05/12] drm/msm/adreno: Use quirk to identify cached-coherent support
2023-07-13 20:05 ` Akhil P Oommen
@ 2023-07-13 22:25 ` Rob Clark
2023-07-17 22:00 ` Akhil P Oommen
0 siblings, 1 reply; 73+ messages in thread
From: Rob Clark @ 2023-07-13 22:25 UTC (permalink / raw)
To: Akhil P Oommen
Cc: Konrad Dybcio, linux-arm-msm, Rob Clark, freedreno, dri-devel
On Thu, Jul 13, 2023 at 1:06 PM Akhil P Oommen <quic_akhilpo@quicinc.com> wrote:
>
> On Thu, Jul 06, 2023 at 02:10:38PM -0700, Rob Clark wrote:
> >
> > From: Rob Clark <robdclark@chromium.org>
> >
> > It is better to explicitly list it. With the move to opaque chip-id's
> > for future devices, we should avoid trying to infer things like
> > generation from the numerical value.
> >
> > Signed-off-by: Rob Clark <robdclark@chromium.org>
> > ---
> > drivers/gpu/drm/msm/adreno/adreno_device.c | 23 +++++++++++++++-------
> > drivers/gpu/drm/msm/adreno/adreno_gpu.h | 1 +
> > 2 files changed, 17 insertions(+), 7 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c
> > index f469f951a907..3c531da417b9 100644
> > --- a/drivers/gpu/drm/msm/adreno/adreno_device.c
> > +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c
> > @@ -256,6 +256,7 @@ static const struct adreno_info gpulist[] = {
> > },
> > .gmem = SZ_512K,
> > .inactive_period = DRM_MSM_INACTIVE_PERIOD,
> > + .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT,
> > .init = a6xx_gpu_init,
> > }, {
> > .rev = ADRENO_REV(6, 1, 9, ANY_ID),
> > @@ -266,6 +267,7 @@ static const struct adreno_info gpulist[] = {
> > },
> > .gmem = SZ_512K,
> > .inactive_period = DRM_MSM_INACTIVE_PERIOD,
> > + .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT,
> > .init = a6xx_gpu_init,
> > .zapfw = "a615_zap.mdt",
> > .hwcg = a615_hwcg,
> > @@ -278,6 +280,7 @@ static const struct adreno_info gpulist[] = {
> > },
> > .gmem = SZ_1M,
> > .inactive_period = DRM_MSM_INACTIVE_PERIOD,
> > + .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT,
> > .init = a6xx_gpu_init,
> > .zapfw = "a630_zap.mdt",
> > .hwcg = a630_hwcg,
> > @@ -290,6 +293,7 @@ static const struct adreno_info gpulist[] = {
> > },
> > .gmem = SZ_1M,
> > .inactive_period = DRM_MSM_INACTIVE_PERIOD,
> > + .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT,
> > .init = a6xx_gpu_init,
> > .zapfw = "a640_zap.mdt",
> > .hwcg = a640_hwcg,
> > @@ -302,7 +306,8 @@ static const struct adreno_info gpulist[] = {
> > },
> > .gmem = SZ_1M + SZ_128K,
> > .inactive_period = DRM_MSM_INACTIVE_PERIOD,
> > - .quirks = ADRENO_QUIRK_HAS_HW_APRIV,
> > + .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |
> > + ADRENO_QUIRK_HAS_HW_APRIV,
> > .init = a6xx_gpu_init,
> > .zapfw = "a650_zap.mdt",
> > .hwcg = a650_hwcg,
> > @@ -316,7 +321,8 @@ static const struct adreno_info gpulist[] = {
> > },
> > .gmem = SZ_1M + SZ_512K,
> > .inactive_period = DRM_MSM_INACTIVE_PERIOD,
> > - .quirks = ADRENO_QUIRK_HAS_HW_APRIV,
> > + .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |
> > + ADRENO_QUIRK_HAS_HW_APRIV,
> > .init = a6xx_gpu_init,
> > .zapfw = "a660_zap.mdt",
> > .hwcg = a660_hwcg,
> > @@ -329,7 +335,8 @@ static const struct adreno_info gpulist[] = {
> > },
> > .gmem = SZ_512K,
> > .inactive_period = DRM_MSM_INACTIVE_PERIOD,
> > - .quirks = ADRENO_QUIRK_HAS_HW_APRIV,
> > + .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |
> > + ADRENO_QUIRK_HAS_HW_APRIV,
> > .init = a6xx_gpu_init,
> > .hwcg = a660_hwcg,
> > .address_space_size = SZ_16G,
> > @@ -342,6 +349,7 @@ static const struct adreno_info gpulist[] = {
> > },
> > .gmem = SZ_2M,
> > .inactive_period = DRM_MSM_INACTIVE_PERIOD,
> > + .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT,
> > .init = a6xx_gpu_init,
> > .zapfw = "a640_zap.mdt",
> > .hwcg = a640_hwcg,
> > @@ -353,7 +361,8 @@ static const struct adreno_info gpulist[] = {
> > },
> > .gmem = SZ_4M,
> > .inactive_period = DRM_MSM_INACTIVE_PERIOD,
> > - .quirks = ADRENO_QUIRK_HAS_HW_APRIV,
> > + .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |
> > + ADRENO_QUIRK_HAS_HW_APRIV,
> > .init = a6xx_gpu_init,
> > .zapfw = "a690_zap.mdt",
> > .hwcg = a690_hwcg,
> > @@ -565,9 +574,9 @@ static int adreno_bind(struct device *dev, struct device *master, void *data)
> > if (ret)
> > return ret;
> >
> > - if (config.rev.core >= 6)
> > - if (!adreno_has_gmu_wrapper(to_adreno_gpu(gpu)))
> > - priv->has_cached_coherent = true;
> > + priv->has_cached_coherent =
> > + !!(info->quirks & ADRENO_QUIRK_HAS_CACHED_COHERENT) &&
> > + !adreno_has_gmu_wrapper(to_adreno_gpu(gpu));
> >
> > return 0;
> > }
> > diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> > index a7c4a2c536e3..e08d41337169 100644
> > --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> > +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> > @@ -33,6 +33,7 @@ enum {
> > #define ADRENO_QUIRK_FAULT_DETECT_MASK BIT(1)
> > #define ADRENO_QUIRK_LMLOADKILL_DISABLE BIT(2)
> > #define ADRENO_QUIRK_HAS_HW_APRIV BIT(3)
> > +#define ADRENO_QUIRK_HAS_CACHED_COHERENT BIT(4)
> a shorter ADRENO_IS_IOCOHERENT?
I prefer "HAS" to "IS".. maybe it is just me but "IS" sounds to me
like all dma is coherent, while in fact gpu mappings can be either
coherent or not.
I suppose it could be "HAS_IOCOHERENT" but we do use "CACHED_COHERENT"
elsewhere.
BR,
-R
>
> -Akhil
>
> >
> > struct adreno_rev {
> > uint8_t core;
> > --
> > 2.41.0
> >
^ permalink raw reply [flat|nested] 73+ messages in thread
* Re: [Freedreno] [PATCH 12/12] drm/msm/adreno: Switch to chip-id for identifying GPU
2023-07-13 22:06 ` Rob Clark
@ 2023-07-13 22:53 ` Dmitry Baryshkov
2023-07-17 22:09 ` Akhil P Oommen
1 sibling, 0 replies; 73+ messages in thread
From: Dmitry Baryshkov @ 2023-07-13 22:53 UTC (permalink / raw)
To: Rob Clark
Cc: Rob Clark, Akhil P Oommen, linux-arm-msm, dri-devel,
Konrad Dybcio, freedreno
On Fri, 14 Jul 2023 at 01:06, Rob Clark <robdclark@gmail.com> wrote:
>
> On Thu, Jul 13, 2023 at 2:39 PM Akhil P Oommen <quic_akhilpo@quicinc.com> wrote:
> >
> > On Fri, Jul 07, 2023 at 06:45:42AM +0300, Dmitry Baryshkov wrote:
> > >
> > > On 07/07/2023 00:10, Rob Clark wrote:
> > > > From: Rob Clark <robdclark@chromium.org>
> > > >
> > > > Since the revision becomes an opaque identifier with future GPUs, move
> > > > away from treating different ranges of bits as having a given meaning.
> > > > This means that we need to explicitly list different patch revisions in
> > > > the device table.
> > > >
> > > > Signed-off-by: Rob Clark <robdclark@chromium.org>
> > > > ---
> > > > drivers/gpu/drm/msm/adreno/a4xx_gpu.c | 2 +-
> > > > drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 11 +-
> > > > drivers/gpu/drm/msm/adreno/a5xx_power.c | 2 +-
> > > > drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 13 ++-
> > > > drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 9 +-
> > > > drivers/gpu/drm/msm/adreno/adreno_device.c | 128 ++++++++++-----------
> > > > drivers/gpu/drm/msm/adreno/adreno_gpu.c | 16 +--
> > > > drivers/gpu/drm/msm/adreno/adreno_gpu.h | 51 ++++----
> > > > 8 files changed, 122 insertions(+), 110 deletions(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/msm/adreno/a4xx_gpu.c b/drivers/gpu/drm/msm/adreno/a4xx_gpu.c
> > > > index 715436cb3996..8b4cdf95f445 100644
> > > > --- a/drivers/gpu/drm/msm/adreno/a4xx_gpu.c
> > > > +++ b/drivers/gpu/drm/msm/adreno/a4xx_gpu.c
> > > > @@ -145,7 +145,7 @@ static void a4xx_enable_hwcg(struct msm_gpu *gpu)
> > > > gpu_write(gpu, REG_A4XX_RBBM_CLOCK_DELAY_HLSQ, 0x00220000);
> > > > /* Early A430's have a timing issue with SP/TP power collapse;
> > > > disabling HW clock gating prevents it. */
> > > > - if (adreno_is_a430(adreno_gpu) && adreno_gpu->rev.patchid < 2)
> > > > + if (adreno_is_a430(adreno_gpu) && adreno_patchid(adreno_gpu) < 2)
> > > > gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL, 0);
> > > > else
> > > > gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL, 0xAAAAAAAA);
> > > > diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
> > > > index f0803e94ebe5..70d2b5342cd9 100644
> > > > --- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
> > > > +++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
> > > > @@ -1744,6 +1744,7 @@ struct msm_gpu *a5xx_gpu_init(struct drm_device *dev)
> > > > struct msm_drm_private *priv = dev->dev_private;
> > > > struct platform_device *pdev = priv->gpu_pdev;
> > > > struct adreno_platform_config *config = pdev->dev.platform_data;
> > > > + const struct adreno_info *info;
> > > > struct a5xx_gpu *a5xx_gpu = NULL;
> > > > struct adreno_gpu *adreno_gpu;
> > > > struct msm_gpu *gpu;
> > > > @@ -1770,7 +1771,15 @@ struct msm_gpu *a5xx_gpu_init(struct drm_device *dev)
> > > > nr_rings = 4;
> > > > - if (adreno_cmp_rev(ADRENO_REV(5, 1, 0, ANY_ID), config->rev))
> > > > + /*
> > > > + * Note that we wouldn't have been able to get this far if there is not
> > > > + * a device table entry for this chip_id
> > > > + */
> > > > + info = adreno_find_info(config->chip_id);
> > > > + if (WARN_ON(!info))
> > > > + return ERR_PTR(-EINVAL);
> > > > +
> > > > + if (info->revn == 510)
> > > > nr_rings = 1;
> > > > ret = adreno_gpu_init(dev, pdev, adreno_gpu, &funcs, nr_rings);
> > > > diff --git a/drivers/gpu/drm/msm/adreno/a5xx_power.c b/drivers/gpu/drm/msm/adreno/a5xx_power.c
> > > > index 0e63a1429189..7705f8010484 100644
> > > > --- a/drivers/gpu/drm/msm/adreno/a5xx_power.c
> > > > +++ b/drivers/gpu/drm/msm/adreno/a5xx_power.c
> > > > @@ -179,7 +179,7 @@ static void a540_lm_setup(struct msm_gpu *gpu)
> > > > /* The battery current limiter isn't enabled for A540 */
> > > > config = AGC_LM_CONFIG_BCL_DISABLED;
> > > > - config |= adreno_gpu->rev.patchid << AGC_LM_CONFIG_GPU_VERSION_SHIFT;
> > > > + config |= adreno_patchid(adreno_gpu) << AGC_LM_CONFIG_GPU_VERSION_SHIFT;
> > > > /* For now disable GPMU side throttling */
> > > > config |= AGC_LM_CONFIG_THROTTLE_DISABLE;
> > > > diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
> > > > index f1bb20574018..a9ba547a120c 100644
> > > > --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
> > > > +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
> > > > @@ -790,10 +790,15 @@ static int a6xx_gmu_fw_start(struct a6xx_gmu *gmu, unsigned int state)
> > > > gmu_write(gmu, REG_A6XX_GMU_AHB_FENCE_RANGE_0,
> > > > (1 << 31) | (0xa << 18) | (0xa0));
> > > > - chipid = adreno_gpu->rev.core << 24;
> > > > - chipid |= adreno_gpu->rev.major << 16;
> > > > - chipid |= adreno_gpu->rev.minor << 12;
> > > > - chipid |= adreno_gpu->rev.patchid << 8;
> > > > + /* Note that the GMU has a slightly different layout for
> > > > + * chip_id, for whatever reason, so a bit of massaging
> > > > + * is needed. The upper 16b are the same, but minor and
> > > > + * patchid are packed in four bits each with the lower
> > > > + * 8b unused:
> > > > + */
> > > > + chipid = adreno_gpu->chip_id & 0xffff0000;
> > > > + chipid |= (adreno_gpu->chip_id << 4) & 0xf000; /* minor */
> > > > + chipid |= (adreno_gpu->chip_id << 8) & 0x0f00; /* patchid */
> > >
> > > I'd beg for explicit FIELD_GET and FIELD_PREP here.
> > >
> > > > gmu_write(gmu, REG_A6XX_GMU_HFI_SFR_ADDR, chipid);
> > > > diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> > > > index 77b23c004b94..ed075729ca09 100644
> > > > --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> > > > +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> > > > @@ -2344,10 +2344,13 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev)
> > > > /*
> > > > * We need to know the platform type before calling into adreno_gpu_init
> > > > * so that the hw_apriv flag can be correctly set. Snoop into the info
> > > > - * and grab the revision number
> > > > + * and grab the revision number.
> > > > + *
> > > > + * Note that we wouldn't have been able to get this far if there is not
> > > > + * a device table entry for this chip_id
> > >
> > > Having seen this note twice, shouldn't we explicitly pass adreno_info to our
> > > aNxx_gpu_init() functions and then further to adreno_gpu_init()?
> > >
> > > > */
> > > > - info = adreno_info(config->rev);
> > > > - if (!info)
> > > > + info = adreno_find_info(config->chip_id);
> > > > + if (WARN_ON(!info))
> > > > return ERR_PTR(-EINVAL);
> > > > adreno_gpu->base.hw_apriv = !!(info->quirks & ADRENO_QUIRK_HAS_HW_APRIV);
> > > > diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c
> > > > index fd2e183bce60..4a718ff33635 100644
> > > > --- a/drivers/gpu/drm/msm/adreno/adreno_device.c
> > > > +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c
> > > > @@ -22,7 +22,7 @@ module_param_named(allow_vram_carveout, allow_vram_carveout, bool, 0600);
> > > > static const struct adreno_info gpulist[] = {
> > > > {
> > > > - .rev = ADRENO_REV(2, 0, 0, 0),
> > > > + .chip_ids = ADRENO_CHIP_IDS(0x02000000),
> > >
> > > This begs to use bit masks, but see below
> > >
> > > > .family = ADRENO_2XX_GEN1,
> > > > .revn = 200,
> > > > .fw = {
> > >
> > > [skipped]
> > >
> > > > @@ -77,7 +77,11 @@ static const struct adreno_info gpulist[] = {
> > > > .inactive_period = DRM_MSM_INACTIVE_PERIOD,
> > > > .init = a3xx_gpu_init,
> > > > }, {
> > > > - .rev = ADRENO_REV(3, 2, ANY_ID, ANY_ID),
> > > > + .chip_ids = ADRENO_CHIP_IDS(
> > > > + 0x03020000,
> > > > + 0x03020001,
> > > > + 0x03020002
> > >
> > > definitely a bitmask would help
> > >
> > > > + ),
> > > > .family = ADRENO_3XX,
> > > > .revn = 320,
> > > > .fw = {
> > >
> > > [skipped the rest]
> > >
> > > > @@ -494,31 +502,16 @@ MODULE_FIRMWARE("qcom/a630_sqe.fw");
> > > > MODULE_FIRMWARE("qcom/a630_gmu.bin");
> > > > MODULE_FIRMWARE("qcom/a630_zap.mbn");
> > > > -static inline bool _rev_match(uint8_t entry, uint8_t id)
> > > > -{
> > > > - return (entry == ANY_ID) || (entry == id);
> > > > -}
> > > > -
> > > > -bool adreno_cmp_rev(struct adreno_rev rev1, struct adreno_rev rev2)
> > > > -{
> > > > -
> > > > - return _rev_match(rev1.core, rev2.core) &&
> > > > - _rev_match(rev1.major, rev2.major) &&
> > > > - _rev_match(rev1.minor, rev2.minor) &&
> > > > - _rev_match(rev1.patchid, rev2.patchid);
> > > > -}
> > > > -
> > > > -const struct adreno_info *adreno_info(struct adreno_rev rev)
> > > > +const struct adreno_info *adreno_find_info(uint32_t chip_id)
> > > > {
> > > > - int i;
> > > > -
> > > > /* identify gpu: */
> > > > - for (i = 0; i < ARRAY_SIZE(gpulist); i++) {
> > > > + for (int i = 0; i < ARRAY_SIZE(gpulist); i++) {
> > > > const struct adreno_info *info = &gpulist[i];
> > > > if (info->machine && !of_machine_is_compatible(info->machine))
> > > > continue;
> > > > - if (adreno_cmp_rev(info->rev, rev))
> > > > - return info;
> > > > + for (int j = 0; info->chip_ids[j]; j++)
> > > > + if (info->chip_ids[j] == chip_id)
> > > > + return info;
> > > > }
> > > > return NULL;
> > > > @@ -598,12 +591,11 @@ struct msm_gpu *adreno_load_gpu(struct drm_device *dev)
> > > > return NULL;
> > > > }
> > > > -static int find_chipid(struct device *dev, struct adreno_rev *rev)
> > > > +static int find_chipid(struct device *dev, uint32_t *chipid)
> > > > {
> > > > struct device_node *node = dev->of_node;
> > > > const char *compat;
> > > > int ret;
> > > > - u32 chipid;
> > > > /* first search the compat strings for qcom,adreno-XYZ.W: */
> > > > ret = of_property_read_string_index(node, "compatible", 0, &compat);
> > > > @@ -612,32 +604,34 @@ static int find_chipid(struct device *dev, struct adreno_rev *rev)
> > > > if (sscanf(compat, "qcom,adreno-%u.%u", &r, &patch) == 2 ||
> > > > sscanf(compat, "amd,imageon-%u.%u", &r, &patch) == 2) {
> > > > - rev->core = r / 100;
> > > > + uint32_t core, major, minor;
> > > > +
> > > > + core = r / 100;
> > > > r %= 100;
> > > > - rev->major = r / 10;
> > > > + major = r / 10;
> > > > r %= 10;
> > > > - rev->minor = r;
> > > > - rev->patchid = patch;
> > > > + minor = r;
> > > > +
> > > > + *chipid = (core << 24) |
> > > > + (major << 16) |
> > > > + (minor << 8) |
> > > > + patch;
> > >
> > > This starts to look realy crazy. I'd repeat my suggestion of moving towards
> > > of_device match data. This would result in some duplication, we'd have to
> > > explicitly list all supported compatibles in the of_match_table. But then we
> > > can drop all the CHIPID lists from device table and/or manual parsing of the
> > > chipid from the compat field.
> > >
> > > This way we can have per-SoC overrides, etc.
> > >
> > > > return 0;
> > > > }
> > > > +
> > > > + if (sscanf(compat, "qcom,adreno-%08x", chipid) == 1)
> > > > + return 0;
> > > > }
> > > > /* and if that fails, fall back to legacy "qcom,chipid" property: */
> > > > - ret = of_property_read_u32(node, "qcom,chipid", &chipid);
> > > > + ret = of_property_read_u32(node, "qcom,chipid", chipid);
> > > > if (ret) {
> > > > DRM_DEV_ERROR(dev, "could not parse qcom,chipid: %d\n", ret);
> > > > return ret;
> > > > }
> > > > - rev->core = (chipid >> 24) & 0xff;
> > > > - rev->major = (chipid >> 16) & 0xff;
> > > > - rev->minor = (chipid >> 8) & 0xff;
> > > > - rev->patchid = (chipid & 0xff);
> > > > -
> > > > dev_warn(dev, "Using legacy qcom,chipid binding!\n");
> > > > - dev_warn(dev, "Use compatible qcom,adreno-%u%u%u.%u instead.\n",
> > > > - rev->core, rev->major, rev->minor, rev->patchid);
> > > > return 0;
> > > > }
> > > > @@ -651,22 +645,22 @@ static int adreno_bind(struct device *dev, struct device *master, void *data)
> > > > struct msm_gpu *gpu;
> > > > int ret;
> > > > - ret = find_chipid(dev, &config.rev);
> > > > + ret = find_chipid(dev, &config.chip_id);
> > > > if (ret)
> > > > return ret;
> > > > dev->platform_data = &config;
> > > > priv->gpu_pdev = to_platform_device(dev);
> > > > - info = adreno_info(config.rev);
> > > > + info = adreno_find_info(config.chip_id);
> > > > if (!info) {
> > > > dev_warn(drm->dev, "Unknown GPU revision: %"ADRENO_CHIPID_FMT"\n",
> > > > - ADRENO_CHIPID_ARGS(config.rev));
> > > > + ADRENO_CHIPID_ARGS(config.chip_id));
> > > > return -ENXIO;
> > > > }
> > > > - DBG("Found GPU: %"ADRENO_CHIPID_FMT, ADRENO_CHIPID_ARGS(config.rev));
> > > > + DBG("Found GPU: %"ADRENO_CHIPID_FMT, ADRENO_CHIPID_ARGS(config.chip_id));
> > > > priv->is_a2xx = info->family < ADRENO_3XX;
> > > > priv->has_cached_coherent =
> > > > diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
> > > > index 1a982a926f21..1274609a74b1 100644
> > > > --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c
> > > > +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
> > > > @@ -326,10 +326,7 @@ int adreno_get_param(struct msm_gpu *gpu, struct msm_file_private *ctx,
> > > > *value = !adreno_is_a650_family(adreno_gpu) ? 0x100000 : 0;
> > > > return 0;
> > > > case MSM_PARAM_CHIP_ID:
> > > > - *value = (uint64_t)adreno_gpu->rev.patchid |
> > > > - ((uint64_t)adreno_gpu->rev.minor << 8) |
> > > > - ((uint64_t)adreno_gpu->rev.major << 16) |
> > > > - ((uint64_t)adreno_gpu->rev.core << 24);
> > > > + *value = adreno_gpu->chip_id;
> > > > if (!adreno_gpu->info->revn)
> > > > *value |= ((uint64_t) adreno_gpu->speedbin) << 32;
> > > > return 0;
> > > > @@ -849,7 +846,7 @@ void adreno_show(struct msm_gpu *gpu, struct msm_gpu_state *state,
> > > > drm_printf(p, "revision: %u (%"ADRENO_CHIPID_FMT")\n",
> > > > adreno_gpu->info->revn,
> > > > - ADRENO_CHIPID_ARGS(adreno_gpu->rev));
> > > > + ADRENO_CHIPID_ARGS(adreno_gpu->chip_id));
> > > > /*
> > > > * If this is state collected due to iova fault, so fault related info
> > > > *
> > > > @@ -922,7 +919,7 @@ void adreno_dump_info(struct msm_gpu *gpu)
> > > > printk("revision: %u (%"ADRENO_CHIPID_FMT")\n",
> > > > adreno_gpu->info->revn,
> > > > - ADRENO_CHIPID_ARGS(adreno_gpu->rev));
> > > > + ADRENO_CHIPID_ARGS(adreno_gpu->chip_id));
> > > > for (i = 0; i < gpu->nr_rings; i++) {
> > > > struct msm_ringbuffer *ring = gpu->rb[i];
> > > > @@ -1072,14 +1069,13 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev,
> > > > struct adreno_platform_config *config = dev->platform_data;
> > > > struct msm_gpu_config adreno_gpu_config = { 0 };
> > > > struct msm_gpu *gpu = &adreno_gpu->base;
> > > > - struct adreno_rev *rev = &config->rev;
> > > > const char *gpu_name;
> > > > u32 speedbin;
> > > > int ret;
> > > > adreno_gpu->funcs = funcs;
> > > > - adreno_gpu->info = adreno_info(config->rev);
> > > > - adreno_gpu->rev = *rev;
> > > > + adreno_gpu->info = adreno_find_info(config->chip_id);
> > > > + adreno_gpu->chip_id = config->chip_id;
> > > > /* Only handle the core clock when GMU is not in use (or is absent). */
> > > > if (adreno_has_gmu_wrapper(adreno_gpu) ||
> > > > @@ -1104,7 +1100,7 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev,
> > > > adreno_gpu->speedbin = (uint16_t) (0xffff & speedbin);
> > > > gpu_name = devm_kasprintf(dev, GFP_KERNEL, "%"ADRENO_CHIPID_FMT,
> > > > - ADRENO_CHIPID_ARGS(config->rev));
> > > > + ADRENO_CHIPID_ARGS(config->chip_id));
> > > > if (!gpu_name)
> > > > return -ENOMEM;
> > > > diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> > > > index 73e7155f164c..18f53c7ab589 100644
> > > > --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> > > > +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> > > > @@ -54,23 +54,15 @@ enum adreno_family {
> > > > #define ADRENO_QUIRK_HAS_HW_APRIV BIT(3)
> > > > #define ADRENO_QUIRK_HAS_CACHED_COHERENT BIT(4)
> > > > -struct adreno_rev {
> > > > - uint8_t core;
> > > > - uint8_t major;
> > > > - uint8_t minor;
> > > > - uint8_t patchid;
> > > > -};
> > > > -
> > > > -#define ANY_ID 0xff
> > > > -
> > > > -#define ADRENO_REV(core, major, minor, patchid) \
> > > > - ((struct adreno_rev){ core, major, minor, patchid })
> > > > -
> > > > /* Helper for formating the chip_id in the way that userspace tools like
> > > > * crashdec expect.
> > > > */
> > > > #define ADRENO_CHIPID_FMT "u.%u.%u.%u"
> > > > -#define ADRENO_CHIPID_ARGS(_r) (_r).core, (_r).major, (_r).minor, (_r).patchid
> > > > +#define ADRENO_CHIPID_ARGS(_c) \
> > > > + (((_c) >> 24) & 0xff), \
> > > > + (((_c) >> 16) & 0xff), \
> > > > + (((_c) >> 8) & 0xff), \
> > > > + ((_c) & 0xff)
> > >
> > > So, we still have some meaning for chipid?
> > >
> > > > struct adreno_gpu_funcs {
> > > > struct msm_gpu_funcs base;
> > > > @@ -87,7 +79,12 @@ extern const struct adreno_reglist a660_hwcg[], a690_hwcg[];
> > > > struct adreno_info {
> > > > const char *machine;
> > > > - struct adreno_rev rev;
> > > > + /**
> > > > + * @chipids: Table of matching chip-ids
> > > > + *
> > > > + * Terminated with 0 sentinal
> > > > + */
> > > > + uint32_t *chip_ids;
> > > > enum adreno_family family;
> > > > uint32_t revn;
> > > > const char *fw[ADRENO_FW_MAX];
> > > > @@ -107,6 +104,8 @@ struct adreno_info {
> > > > uint32_t *speedbins;
> > > > };
> > > > +#define ADRENO_CHIP_IDS(tbl...) (uint32_t[]) { tbl, 0 }
> > > > +
> > > > /*
> > > > * Helper to build a speedbin table, ie. the table:
> > > > * fuse | speedbin
> > > > @@ -125,12 +124,12 @@ struct adreno_info {
> > > > */
> > > > #define ADRENO_SPEEDBINS(tbl...) (uint32_t[]) { tbl, UINT_MAX }
> > > > -const struct adreno_info *adreno_info(struct adreno_rev rev);
> > > > +const struct adreno_info *adreno_find_info(uint32_t chip_id);
> > > > struct adreno_gpu {
> > > > struct msm_gpu base;
> > > > - struct adreno_rev rev;
> > > > const struct adreno_info *info;
> > > > + uint32_t chip_id;
> > > > uint16_t speedbin;
> > > > const struct adreno_gpu_funcs *funcs;
> > > > @@ -179,7 +178,7 @@ struct adreno_ocmem {
> > > > /* platform config data (ie. from DT, or pdata) */
> > > > struct adreno_platform_config {
> > > > - struct adreno_rev rev;
> > > > + uint32_t chip_id;
> > > > };
> > > > #define ADRENO_IDLE_TIMEOUT msecs_to_jiffies(1000)
> > > > @@ -196,7 +195,15 @@ struct adreno_platform_config {
> > > > __ret; \
> > > > })
> > > > -bool adreno_cmp_rev(struct adreno_rev rev1, struct adreno_rev rev2);
> > > > +static inline uint8_t adreno_patchid(const struct adreno_gpu *gpu)
> > > > +{
> > > > + /* It is probably ok to assume legacy "adreno_rev" format
> > > > + * for all a6xx devices, but probably best to limit this
> > > > + * to older things.
> > > > + */
> > > > + WARN_ON_ONCE(gpu->info->family >= ADRENO_6XX_GEN1);
> > > > + return gpu->chip_id & 0xff;
> > > > +}
> > > > static inline bool adreno_is_revn(const struct adreno_gpu *gpu, uint32_t revn)
> > > > {
> > > > @@ -252,7 +259,7 @@ static inline bool adreno_is_a330(const struct adreno_gpu *gpu)
> > > > static inline bool adreno_is_a330v2(const struct adreno_gpu *gpu)
> > > > {
> > > > - return adreno_is_a330(gpu) && (gpu->rev.patchid > 0);
> > > > + return adreno_is_a330(gpu) && (adreno_patchid(gpu) > 0);
> > > > }
> > > > static inline int adreno_is_a405(const struct adreno_gpu *gpu)
> > > > @@ -342,8 +349,7 @@ static inline int adreno_is_a650(const struct adreno_gpu *gpu)
> > > > static inline int adreno_is_7c3(const struct adreno_gpu *gpu)
> > > > {
> > > > - /* The order of args is important here to handle ANY_ID correctly */
> > > > - return adreno_cmp_rev(ADRENO_REV(6, 3, 5, ANY_ID), gpu->rev);
> > > > + return gpu->info->chip_ids[0] == 0x06030500;
> >
> > Why not use adreno_gpu->chip_id here? Or do we need this check before
> > adreno_gpu_init()? I thought we got rid of those.
>
> This is intentional, because there can be multiple chip-id's for a
> single table entry, in theory. But the first chip_id in the gpu table
> entry should suffice, and is simpler than comparing
> adreno_gpu->chip_id against each possible match.
But why can't we use of_device_id::data ?
>
> BR,
> -R
>
> > >
> > > Ugh. The thing that bugs me isn't even the manual comparison of chip_ids[0],
> > > but the fact that these two platforms stand aside. I think at the end we
> > > should have a single mechanism for checking GPU's SKUs.
> > >
> > > Or maybe we should get rid of that completely.
> > >
> > > If we get rid of a single gpulist table and move individual GPU info
> > > definitions to aNxx_gpu.c, we can subclass a generic info structure with
> > > generation-specific data, for example generation-specific quirks, pointers
> > > to hcwg or VBIF registers, etc. And then instead of having adreno_is_foo all
> > > over the code we can migrate most of these checks to data in the gpu info
> > > data.
> >
> > I think the downstream driver does what you described here. It helps to
> > move more generation-specific data to the table without inflating the
> > gpu table size.
> >
> > -Akhil
> >
> > >
> > > > }
> > > > static inline int adreno_is_a660(const struct adreno_gpu *gpu)
> > > > @@ -358,8 +364,7 @@ static inline int adreno_is_a680(const struct adreno_gpu *gpu)
> > > > static inline int adreno_is_a690(const struct adreno_gpu *gpu)
> > > > {
> > > > - /* The order of args is important here to handle ANY_ID correctly */
> > > > - return adreno_cmp_rev(ADRENO_REV(6, 9, 0, ANY_ID), gpu->rev);
> > > > + return gpu->info->chip_ids[0] == 0x06090000;
> > > > };
> > > > /* check for a615, a616, a618, a619 or any a630 derivatives */
> > > > static inline int adreno_is_a630_family(const struct adreno_gpu *gpu)
> > >
> > > --
> > > With best wishes
> > > Dmitry
> > >
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 73+ messages in thread
* Re: [PATCH 12/12] drm/msm/adreno: Switch to chip-id for identifying GPU
2023-07-07 16:08 ` Rob Clark
@ 2023-07-15 13:38 ` Konrad Dybcio
2023-07-15 14:12 ` Rob Clark
2023-07-26 21:45 ` Rob Clark
0 siblings, 2 replies; 73+ messages in thread
From: Konrad Dybcio @ 2023-07-15 13:38 UTC (permalink / raw)
To: Rob Clark; +Cc: Rob Clark, linux-arm-msm, freedreno, dri-devel
On 7.07.2023 18:08, Rob Clark wrote:
> On Thu, Jul 6, 2023 at 5:25 PM Konrad Dybcio <konrad.dybcio@linaro.org> wrote:
>>
>> On 6.07.2023 23:10, Rob Clark wrote:
>>> From: Rob Clark <robdclark@chromium.org>
>>>
>>> Since the revision becomes an opaque identifier with future GPUs, move
>>> away from treating different ranges of bits as having a given meaning.
>>> This means that we need to explicitly list different patch revisions in
>>> the device table.
>>>
>>> Signed-off-by: Rob Clark <robdclark@chromium.org>
>>> ---
[...]
>>> static inline int adreno_is_7c3(const struct adreno_gpu *gpu)
>>> {
>>> - /* The order of args is important here to handle ANY_ID correctly */
>>> - return adreno_cmp_rev(ADRENO_REV(6, 3, 5, ANY_ID), gpu->rev);
>>> + return gpu->info->chip_ids[0] == 0x06030500;
>>> }
>> I'm sorry, but this screams trouble.. and doesn't sound very maintainable :/
>>
>
> why? It is intentionally checking the first chip-id so that nothing
> breaks if later chip-ids are added
checking for magic numbers and magic array indices at the same time is
very prone to breaking, as breaking this check would not at all be easy
to spot in code review.
>
>> Apart from all these comments, I don't really see the point of this patch,
>> other than trying to tie together Qualcomm's almost-meaningless chipids on
>> a7xx into the picture..
>>
>> Since they can't even be read back from the hardware, I don't think trying
>> to force them into the upstream kernel makes any sense.
>
> Sure, we _could_ pick our own arbitrary identifiers, we don't have to
> align with kgsl. But that would be a super huge PITA for mesa, which
> has support for both kernels.
Perhaps I'm biased towards keeping this kind of stuff out of the kernel,
but I'd say that Linux should decide on one logical path.
In between us starting this discussion, Qualcomm managed to introduce
yet another way of deciding what GPU is present on the system in their
downstream driver[1]. We're at like 5 now. Do we wanna keep up each time?
New ID rework for A8xx when that comes out one day?
>
>> On a different note, I think we could try to blockify Adreno definitions a
>> bit by splitting things into:
>>
>> - Core GPU propeties (revision, fw name, GMEM size)
>>
>> - G(P)MU properties
>>
>> - Family data (quirks, reg presets in some config struct which could be a
>> union of config structs per generation, hwcg, maybe protected regs ptr
>> should also be moved there)
>
> We do something like this on the mesa side. But we also get to use
> python tricks to generate code as part of the build process which
> makes things a bit more elegant.
>
> Fwiw, I was already thinking about splitting the gpu "hw catalog" from
> a flat table, to probably something more like a table of tables, so
> that we can split a2xx/a3xx/a4xx/a5xx/a6xx tables into separate files.
> And then we could move hwcg/protect/etc tables into the same file.
> But I thought that might be a bit too conflicty for the a7xx series so
> was thinking to wait until after that landed.. unless you don't think
> it will be a problem.
Yeah I'd like to get a7xx landed this season..
Konrad
[1] they now read parts of socinfo from smem and decide the CHIPID and
speedbin based on that, but it's not available on most existing SoCs,
that was thrown in with SOCID v17
>
> BR,
> -R
>
>> - Generation data (init function, a2xx and a6xx specifics)
>>
>> - Speedbin LUTs matched against socid
>>
>>
>> or something like that.. there's a whole lot of duplicated data atm
>>
>> Konrad
>>>
>>> static inline int adreno_is_a660(const struct adreno_gpu *gpu)
>>> @@ -358,8 +364,7 @@ static inline int adreno_is_a680(const struct adreno_gpu *gpu)
>>>
>>> static inline int adreno_is_a690(const struct adreno_gpu *gpu)
>>> {
>>> - /* The order of args is important here to handle ANY_ID correctly */
>>> - return adreno_cmp_rev(ADRENO_REV(6, 9, 0, ANY_ID), gpu->rev);
>>> + return gpu->info->chip_ids[0] == 0x06090000;
>>> };
>>> /* check for a615, a616, a618, a619 or any a630 derivatives */
>>> static inline int adreno_is_a630_family(const struct adreno_gpu *gpu)
^ permalink raw reply [flat|nested] 73+ messages in thread
* Re: [PATCH 12/12] drm/msm/adreno: Switch to chip-id for identifying GPU
2023-07-15 13:38 ` Konrad Dybcio
@ 2023-07-15 14:12 ` Rob Clark
2023-07-26 21:45 ` Rob Clark
1 sibling, 0 replies; 73+ messages in thread
From: Rob Clark @ 2023-07-15 14:12 UTC (permalink / raw)
To: Konrad Dybcio; +Cc: Rob Clark, linux-arm-msm, freedreno, dri-devel
On Sat, Jul 15, 2023 at 6:38 AM Konrad Dybcio <konrad.dybcio@linaro.org> wrote:
>
> On 7.07.2023 18:08, Rob Clark wrote:
> > On Thu, Jul 6, 2023 at 5:25 PM Konrad Dybcio <konrad.dybcio@linaro.org> wrote:
> >>
> >> On 6.07.2023 23:10, Rob Clark wrote:
> >>> From: Rob Clark <robdclark@chromium.org>
> >>>
> >>> Since the revision becomes an opaque identifier with future GPUs, move
> >>> away from treating different ranges of bits as having a given meaning.
> >>> This means that we need to explicitly list different patch revisions in
> >>> the device table.
> >>>
> >>> Signed-off-by: Rob Clark <robdclark@chromium.org>
> >>> ---
> [...]
>
> >>> static inline int adreno_is_7c3(const struct adreno_gpu *gpu)
> >>> {
> >>> - /* The order of args is important here to handle ANY_ID correctly */
> >>> - return adreno_cmp_rev(ADRENO_REV(6, 3, 5, ANY_ID), gpu->rev);
> >>> + return gpu->info->chip_ids[0] == 0x06030500;
> >>> }
> >> I'm sorry, but this screams trouble.. and doesn't sound very maintainable :/
> >>
> >
> > why? It is intentionally checking the first chip-id so that nothing
> > breaks if later chip-ids are added
> checking for magic numbers and magic array indices at the same time is
> very prone to breaking, as breaking this check would not at all be easy
> to spot in code review.
It isn't like we can arbitrarily change the chip-id's.. they are abi
between dt/kernel/userspace. If they aren't changing, there isn't
anything to break.
> >
> >> Apart from all these comments, I don't really see the point of this patch,
> >> other than trying to tie together Qualcomm's almost-meaningless chipids on
> >> a7xx into the picture..
> >>
> >> Since they can't even be read back from the hardware, I don't think trying
> >> to force them into the upstream kernel makes any sense.
> >
> > Sure, we _could_ pick our own arbitrary identifiers, we don't have to
> > align with kgsl. But that would be a super huge PITA for mesa, which
> > has support for both kernels.
> Perhaps I'm biased towards keeping this kind of stuff out of the kernel,
> but I'd say that Linux should decide on one logical path.
The kernel is the small part of the driver stack, and we have two
drivers above in userspace (vk and gallium) which can work on top of
three different kernels (msm, kgsl, and virtgpu). So what sounds like
an easy/clean answer to you, is not necessarily easy/clean in the big
picture.
So wherever it comes from (and dt is fine, or socid or whatever, and
it's fine for it to just be an opaque 32b value as long as we don't
get conflicting values, I don't mind explicitly listing all of the
possible patch-id's for the legacy scheme) we need to stick with
CHIP_ID.
> In between us starting this discussion, Qualcomm managed to introduce
> yet another way of deciding what GPU is present on the system in their
> downstream driver[1]. We're at like 5 now. Do we wanna keep up each time?
> New ID rework for A8xx when that comes out one day?
What matters is how they expose it to userspace, not where they get
the value from.
BR,
-R
> >
> >> On a different note, I think we could try to blockify Adreno definitions a
> >> bit by splitting things into:
> >>
> >> - Core GPU propeties (revision, fw name, GMEM size)
> >>
> >> - G(P)MU properties
> >>
> >> - Family data (quirks, reg presets in some config struct which could be a
> >> union of config structs per generation, hwcg, maybe protected regs ptr
> >> should also be moved there)
> >
> > We do something like this on the mesa side. But we also get to use
> > python tricks to generate code as part of the build process which
> > makes things a bit more elegant.
> >
> > Fwiw, I was already thinking about splitting the gpu "hw catalog" from
> > a flat table, to probably something more like a table of tables, so
> > that we can split a2xx/a3xx/a4xx/a5xx/a6xx tables into separate files.
> > And then we could move hwcg/protect/etc tables into the same file.
> > But I thought that might be a bit too conflicty for the a7xx series so
> > was thinking to wait until after that landed.. unless you don't think
> > it will be a problem.
> Yeah I'd like to get a7xx landed this season..
>
> Konrad
>
> [1] they now read parts of socinfo from smem and decide the CHIPID and
> speedbin based on that, but it's not available on most existing SoCs,
> that was thrown in with SOCID v17
> >
> > BR,
> > -R
> >
> >> - Generation data (init function, a2xx and a6xx specifics)
> >>
> >> - Speedbin LUTs matched against socid
> >>
> >>
> >> or something like that.. there's a whole lot of duplicated data atm
> >>
> >> Konrad
> >>>
> >>> static inline int adreno_is_a660(const struct adreno_gpu *gpu)
> >>> @@ -358,8 +364,7 @@ static inline int adreno_is_a680(const struct adreno_gpu *gpu)
> >>>
> >>> static inline int adreno_is_a690(const struct adreno_gpu *gpu)
> >>> {
> >>> - /* The order of args is important here to handle ANY_ID correctly */
> >>> - return adreno_cmp_rev(ADRENO_REV(6, 9, 0, ANY_ID), gpu->rev);
> >>> + return gpu->info->chip_ids[0] == 0x06090000;
> >>> };
> >>> /* check for a615, a616, a618, a619 or any a630 derivatives */
> >>> static inline int adreno_is_a630_family(const struct adreno_gpu *gpu)
^ permalink raw reply [flat|nested] 73+ messages in thread
* Re: [Freedreno] [PATCH 05/12] drm/msm/adreno: Use quirk to identify cached-coherent support
2023-07-13 22:25 ` Rob Clark
@ 2023-07-17 22:00 ` Akhil P Oommen
0 siblings, 0 replies; 73+ messages in thread
From: Akhil P Oommen @ 2023-07-17 22:00 UTC (permalink / raw)
To: Rob Clark; +Cc: Konrad Dybcio, linux-arm-msm, Rob Clark, freedreno, dri-devel
On Thu, Jul 13, 2023 at 03:25:33PM -0700, Rob Clark wrote:
>
> On Thu, Jul 13, 2023 at 1:06 PM Akhil P Oommen <quic_akhilpo@quicinc.com> wrote:
> >
> > On Thu, Jul 06, 2023 at 02:10:38PM -0700, Rob Clark wrote:
> > >
> > > From: Rob Clark <robdclark@chromium.org>
> > >
> > > It is better to explicitly list it. With the move to opaque chip-id's
> > > for future devices, we should avoid trying to infer things like
> > > generation from the numerical value.
> > >
> > > Signed-off-by: Rob Clark <robdclark@chromium.org>
> > > ---
> > > drivers/gpu/drm/msm/adreno/adreno_device.c | 23 +++++++++++++++-------
> > > drivers/gpu/drm/msm/adreno/adreno_gpu.h | 1 +
> > > 2 files changed, 17 insertions(+), 7 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c
> > > index f469f951a907..3c531da417b9 100644
> > > --- a/drivers/gpu/drm/msm/adreno/adreno_device.c
> > > +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c
> > > @@ -256,6 +256,7 @@ static const struct adreno_info gpulist[] = {
> > > },
> > > .gmem = SZ_512K,
> > > .inactive_period = DRM_MSM_INACTIVE_PERIOD,
> > > + .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT,
> > > .init = a6xx_gpu_init,
> > > }, {
> > > .rev = ADRENO_REV(6, 1, 9, ANY_ID),
> > > @@ -266,6 +267,7 @@ static const struct adreno_info gpulist[] = {
> > > },
> > > .gmem = SZ_512K,
> > > .inactive_period = DRM_MSM_INACTIVE_PERIOD,
> > > + .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT,
> > > .init = a6xx_gpu_init,
> > > .zapfw = "a615_zap.mdt",
> > > .hwcg = a615_hwcg,
> > > @@ -278,6 +280,7 @@ static const struct adreno_info gpulist[] = {
> > > },
> > > .gmem = SZ_1M,
> > > .inactive_period = DRM_MSM_INACTIVE_PERIOD,
> > > + .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT,
> > > .init = a6xx_gpu_init,
> > > .zapfw = "a630_zap.mdt",
> > > .hwcg = a630_hwcg,
> > > @@ -290,6 +293,7 @@ static const struct adreno_info gpulist[] = {
> > > },
> > > .gmem = SZ_1M,
> > > .inactive_period = DRM_MSM_INACTIVE_PERIOD,
> > > + .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT,
> > > .init = a6xx_gpu_init,
> > > .zapfw = "a640_zap.mdt",
> > > .hwcg = a640_hwcg,
> > > @@ -302,7 +306,8 @@ static const struct adreno_info gpulist[] = {
> > > },
> > > .gmem = SZ_1M + SZ_128K,
> > > .inactive_period = DRM_MSM_INACTIVE_PERIOD,
> > > - .quirks = ADRENO_QUIRK_HAS_HW_APRIV,
> > > + .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |
> > > + ADRENO_QUIRK_HAS_HW_APRIV,
> > > .init = a6xx_gpu_init,
> > > .zapfw = "a650_zap.mdt",
> > > .hwcg = a650_hwcg,
> > > @@ -316,7 +321,8 @@ static const struct adreno_info gpulist[] = {
> > > },
> > > .gmem = SZ_1M + SZ_512K,
> > > .inactive_period = DRM_MSM_INACTIVE_PERIOD,
> > > - .quirks = ADRENO_QUIRK_HAS_HW_APRIV,
> > > + .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |
> > > + ADRENO_QUIRK_HAS_HW_APRIV,
> > > .init = a6xx_gpu_init,
> > > .zapfw = "a660_zap.mdt",
> > > .hwcg = a660_hwcg,
> > > @@ -329,7 +335,8 @@ static const struct adreno_info gpulist[] = {
> > > },
> > > .gmem = SZ_512K,
> > > .inactive_period = DRM_MSM_INACTIVE_PERIOD,
> > > - .quirks = ADRENO_QUIRK_HAS_HW_APRIV,
> > > + .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |
> > > + ADRENO_QUIRK_HAS_HW_APRIV,
> > > .init = a6xx_gpu_init,
> > > .hwcg = a660_hwcg,
> > > .address_space_size = SZ_16G,
> > > @@ -342,6 +349,7 @@ static const struct adreno_info gpulist[] = {
> > > },
> > > .gmem = SZ_2M,
> > > .inactive_period = DRM_MSM_INACTIVE_PERIOD,
> > > + .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT,
> > > .init = a6xx_gpu_init,
> > > .zapfw = "a640_zap.mdt",
> > > .hwcg = a640_hwcg,
> > > @@ -353,7 +361,8 @@ static const struct adreno_info gpulist[] = {
> > > },
> > > .gmem = SZ_4M,
> > > .inactive_period = DRM_MSM_INACTIVE_PERIOD,
> > > - .quirks = ADRENO_QUIRK_HAS_HW_APRIV,
> > > + .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |
> > > + ADRENO_QUIRK_HAS_HW_APRIV,
> > > .init = a6xx_gpu_init,
> > > .zapfw = "a690_zap.mdt",
> > > .hwcg = a690_hwcg,
> > > @@ -565,9 +574,9 @@ static int adreno_bind(struct device *dev, struct device *master, void *data)
> > > if (ret)
> > > return ret;
> > >
> > > - if (config.rev.core >= 6)
> > > - if (!adreno_has_gmu_wrapper(to_adreno_gpu(gpu)))
> > > - priv->has_cached_coherent = true;
> > > + priv->has_cached_coherent =
> > > + !!(info->quirks & ADRENO_QUIRK_HAS_CACHED_COHERENT) &&
> > > + !adreno_has_gmu_wrapper(to_adreno_gpu(gpu));
> > >
> > > return 0;
> > > }
> > > diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> > > index a7c4a2c536e3..e08d41337169 100644
> > > --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> > > +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> > > @@ -33,6 +33,7 @@ enum {
> > > #define ADRENO_QUIRK_FAULT_DETECT_MASK BIT(1)
> > > #define ADRENO_QUIRK_LMLOADKILL_DISABLE BIT(2)
> > > #define ADRENO_QUIRK_HAS_HW_APRIV BIT(3)
> > > +#define ADRENO_QUIRK_HAS_CACHED_COHERENT BIT(4)
> > a shorter ADRENO_IS_IOCOHERENT?
>
> I prefer "HAS" to "IS".. maybe it is just me but "IS" sounds to me
> like all dma is coherent, while in fact gpu mappings can be either
> coherent or not.
Okay. Sounds good.
-Akhil.
>
> I suppose it could be "HAS_IOCOHERENT" but we do use "CACHED_COHERENT"
> elsewhere.
>
> BR,
> -R
>
> >
> > -Akhil
> >
> > >
> > > struct adreno_rev {
> > > uint8_t core;
> > > --
> > > 2.41.0
> > >
^ permalink raw reply [flat|nested] 73+ messages in thread
* Re: [Freedreno] [PATCH 12/12] drm/msm/adreno: Switch to chip-id for identifying GPU
2023-07-13 22:06 ` Rob Clark
2023-07-13 22:53 ` Dmitry Baryshkov
@ 2023-07-17 22:09 ` Akhil P Oommen
1 sibling, 0 replies; 73+ messages in thread
From: Akhil P Oommen @ 2023-07-17 22:09 UTC (permalink / raw)
To: Rob Clark
Cc: Rob Clark, linux-arm-msm, dri-devel, Konrad Dybcio,
Dmitry Baryshkov, freedreno
On Thu, Jul 13, 2023 at 03:06:36PM -0700, Rob Clark wrote:
>
> On Thu, Jul 13, 2023 at 2:39 PM Akhil P Oommen <quic_akhilpo@quicinc.com> wrote:
> >
> > On Fri, Jul 07, 2023 at 06:45:42AM +0300, Dmitry Baryshkov wrote:
> > >
> > > On 07/07/2023 00:10, Rob Clark wrote:
> > > > From: Rob Clark <robdclark@chromium.org>
> > > >
> > > > Since the revision becomes an opaque identifier with future GPUs, move
> > > > away from treating different ranges of bits as having a given meaning.
> > > > This means that we need to explicitly list different patch revisions in
> > > > the device table.
> > > >
> > > > Signed-off-by: Rob Clark <robdclark@chromium.org>
> > > > ---
> > > > drivers/gpu/drm/msm/adreno/a4xx_gpu.c | 2 +-
> > > > drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 11 +-
> > > > drivers/gpu/drm/msm/adreno/a5xx_power.c | 2 +-
> > > > drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 13 ++-
> > > > drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 9 +-
> > > > drivers/gpu/drm/msm/adreno/adreno_device.c | 128 ++++++++++-----------
> > > > drivers/gpu/drm/msm/adreno/adreno_gpu.c | 16 +--
> > > > drivers/gpu/drm/msm/adreno/adreno_gpu.h | 51 ++++----
> > > > 8 files changed, 122 insertions(+), 110 deletions(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/msm/adreno/a4xx_gpu.c b/drivers/gpu/drm/msm/adreno/a4xx_gpu.c
> > > > index 715436cb3996..8b4cdf95f445 100644
> > > > --- a/drivers/gpu/drm/msm/adreno/a4xx_gpu.c
> > > > +++ b/drivers/gpu/drm/msm/adreno/a4xx_gpu.c
> > > > @@ -145,7 +145,7 @@ static void a4xx_enable_hwcg(struct msm_gpu *gpu)
> > > > gpu_write(gpu, REG_A4XX_RBBM_CLOCK_DELAY_HLSQ, 0x00220000);
> > > > /* Early A430's have a timing issue with SP/TP power collapse;
> > > > disabling HW clock gating prevents it. */
> > > > - if (adreno_is_a430(adreno_gpu) && adreno_gpu->rev.patchid < 2)
> > > > + if (adreno_is_a430(adreno_gpu) && adreno_patchid(adreno_gpu) < 2)
> > > > gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL, 0);
> > > > else
> > > > gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL, 0xAAAAAAAA);
> > > > diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
> > > > index f0803e94ebe5..70d2b5342cd9 100644
> > > > --- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
> > > > +++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
> > > > @@ -1744,6 +1744,7 @@ struct msm_gpu *a5xx_gpu_init(struct drm_device *dev)
> > > > struct msm_drm_private *priv = dev->dev_private;
> > > > struct platform_device *pdev = priv->gpu_pdev;
> > > > struct adreno_platform_config *config = pdev->dev.platform_data;
> > > > + const struct adreno_info *info;
> > > > struct a5xx_gpu *a5xx_gpu = NULL;
> > > > struct adreno_gpu *adreno_gpu;
> > > > struct msm_gpu *gpu;
> > > > @@ -1770,7 +1771,15 @@ struct msm_gpu *a5xx_gpu_init(struct drm_device *dev)
> > > > nr_rings = 4;
> > > > - if (adreno_cmp_rev(ADRENO_REV(5, 1, 0, ANY_ID), config->rev))
> > > > + /*
> > > > + * Note that we wouldn't have been able to get this far if there is not
> > > > + * a device table entry for this chip_id
> > > > + */
> > > > + info = adreno_find_info(config->chip_id);
> > > > + if (WARN_ON(!info))
> > > > + return ERR_PTR(-EINVAL);
> > > > +
> > > > + if (info->revn == 510)
> > > > nr_rings = 1;
> > > > ret = adreno_gpu_init(dev, pdev, adreno_gpu, &funcs, nr_rings);
> > > > diff --git a/drivers/gpu/drm/msm/adreno/a5xx_power.c b/drivers/gpu/drm/msm/adreno/a5xx_power.c
> > > > index 0e63a1429189..7705f8010484 100644
> > > > --- a/drivers/gpu/drm/msm/adreno/a5xx_power.c
> > > > +++ b/drivers/gpu/drm/msm/adreno/a5xx_power.c
> > > > @@ -179,7 +179,7 @@ static void a540_lm_setup(struct msm_gpu *gpu)
> > > > /* The battery current limiter isn't enabled for A540 */
> > > > config = AGC_LM_CONFIG_BCL_DISABLED;
> > > > - config |= adreno_gpu->rev.patchid << AGC_LM_CONFIG_GPU_VERSION_SHIFT;
> > > > + config |= adreno_patchid(adreno_gpu) << AGC_LM_CONFIG_GPU_VERSION_SHIFT;
> > > > /* For now disable GPMU side throttling */
> > > > config |= AGC_LM_CONFIG_THROTTLE_DISABLE;
> > > > diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
> > > > index f1bb20574018..a9ba547a120c 100644
> > > > --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
> > > > +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
> > > > @@ -790,10 +790,15 @@ static int a6xx_gmu_fw_start(struct a6xx_gmu *gmu, unsigned int state)
> > > > gmu_write(gmu, REG_A6XX_GMU_AHB_FENCE_RANGE_0,
> > > > (1 << 31) | (0xa << 18) | (0xa0));
> > > > - chipid = adreno_gpu->rev.core << 24;
> > > > - chipid |= adreno_gpu->rev.major << 16;
> > > > - chipid |= adreno_gpu->rev.minor << 12;
> > > > - chipid |= adreno_gpu->rev.patchid << 8;
> > > > + /* Note that the GMU has a slightly different layout for
> > > > + * chip_id, for whatever reason, so a bit of massaging
> > > > + * is needed. The upper 16b are the same, but minor and
> > > > + * patchid are packed in four bits each with the lower
> > > > + * 8b unused:
> > > > + */
> > > > + chipid = adreno_gpu->chip_id & 0xffff0000;
> > > > + chipid |= (adreno_gpu->chip_id << 4) & 0xf000; /* minor */
> > > > + chipid |= (adreno_gpu->chip_id << 8) & 0x0f00; /* patchid */
> > >
> > > I'd beg for explicit FIELD_GET and FIELD_PREP here.
> > >
> > > > gmu_write(gmu, REG_A6XX_GMU_HFI_SFR_ADDR, chipid);
> > > > diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> > > > index 77b23c004b94..ed075729ca09 100644
> > > > --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> > > > +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> > > > @@ -2344,10 +2344,13 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev)
> > > > /*
> > > > * We need to know the platform type before calling into adreno_gpu_init
> > > > * so that the hw_apriv flag can be correctly set. Snoop into the info
> > > > - * and grab the revision number
> > > > + * and grab the revision number.
> > > > + *
> > > > + * Note that we wouldn't have been able to get this far if there is not
> > > > + * a device table entry for this chip_id
> > >
> > > Having seen this note twice, shouldn't we explicitly pass adreno_info to our
> > > aNxx_gpu_init() functions and then further to adreno_gpu_init()?
> > >
> > > > */
> > > > - info = adreno_info(config->rev);
> > > > - if (!info)
> > > > + info = adreno_find_info(config->chip_id);
> > > > + if (WARN_ON(!info))
> > > > return ERR_PTR(-EINVAL);
> > > > adreno_gpu->base.hw_apriv = !!(info->quirks & ADRENO_QUIRK_HAS_HW_APRIV);
> > > > diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c
> > > > index fd2e183bce60..4a718ff33635 100644
> > > > --- a/drivers/gpu/drm/msm/adreno/adreno_device.c
> > > > +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c
> > > > @@ -22,7 +22,7 @@ module_param_named(allow_vram_carveout, allow_vram_carveout, bool, 0600);
> > > > static const struct adreno_info gpulist[] = {
> > > > {
> > > > - .rev = ADRENO_REV(2, 0, 0, 0),
> > > > + .chip_ids = ADRENO_CHIP_IDS(0x02000000),
> > >
> > > This begs to use bit masks, but see below
> > >
> > > > .family = ADRENO_2XX_GEN1,
> > > > .revn = 200,
> > > > .fw = {
> > >
> > > [skipped]
> > >
> > > > @@ -77,7 +77,11 @@ static const struct adreno_info gpulist[] = {
> > > > .inactive_period = DRM_MSM_INACTIVE_PERIOD,
> > > > .init = a3xx_gpu_init,
> > > > }, {
> > > > - .rev = ADRENO_REV(3, 2, ANY_ID, ANY_ID),
> > > > + .chip_ids = ADRENO_CHIP_IDS(
> > > > + 0x03020000,
> > > > + 0x03020001,
> > > > + 0x03020002
> > >
> > > definitely a bitmask would help
> > >
> > > > + ),
> > > > .family = ADRENO_3XX,
> > > > .revn = 320,
> > > > .fw = {
> > >
> > > [skipped the rest]
> > >
> > > > @@ -494,31 +502,16 @@ MODULE_FIRMWARE("qcom/a630_sqe.fw");
> > > > MODULE_FIRMWARE("qcom/a630_gmu.bin");
> > > > MODULE_FIRMWARE("qcom/a630_zap.mbn");
> > > > -static inline bool _rev_match(uint8_t entry, uint8_t id)
> > > > -{
> > > > - return (entry == ANY_ID) || (entry == id);
> > > > -}
> > > > -
> > > > -bool adreno_cmp_rev(struct adreno_rev rev1, struct adreno_rev rev2)
> > > > -{
> > > > -
> > > > - return _rev_match(rev1.core, rev2.core) &&
> > > > - _rev_match(rev1.major, rev2.major) &&
> > > > - _rev_match(rev1.minor, rev2.minor) &&
> > > > - _rev_match(rev1.patchid, rev2.patchid);
> > > > -}
> > > > -
> > > > -const struct adreno_info *adreno_info(struct adreno_rev rev)
> > > > +const struct adreno_info *adreno_find_info(uint32_t chip_id)
> > > > {
> > > > - int i;
> > > > -
> > > > /* identify gpu: */
> > > > - for (i = 0; i < ARRAY_SIZE(gpulist); i++) {
> > > > + for (int i = 0; i < ARRAY_SIZE(gpulist); i++) {
> > > > const struct adreno_info *info = &gpulist[i];
> > > > if (info->machine && !of_machine_is_compatible(info->machine))
> > > > continue;
> > > > - if (adreno_cmp_rev(info->rev, rev))
> > > > - return info;
> > > > + for (int j = 0; info->chip_ids[j]; j++)
> > > > + if (info->chip_ids[j] == chip_id)
> > > > + return info;
> > > > }
> > > > return NULL;
> > > > @@ -598,12 +591,11 @@ struct msm_gpu *adreno_load_gpu(struct drm_device *dev)
> > > > return NULL;
> > > > }
> > > > -static int find_chipid(struct device *dev, struct adreno_rev *rev)
> > > > +static int find_chipid(struct device *dev, uint32_t *chipid)
> > > > {
> > > > struct device_node *node = dev->of_node;
> > > > const char *compat;
> > > > int ret;
> > > > - u32 chipid;
> > > > /* first search the compat strings for qcom,adreno-XYZ.W: */
> > > > ret = of_property_read_string_index(node, "compatible", 0, &compat);
> > > > @@ -612,32 +604,34 @@ static int find_chipid(struct device *dev, struct adreno_rev *rev)
> > > > if (sscanf(compat, "qcom,adreno-%u.%u", &r, &patch) == 2 ||
> > > > sscanf(compat, "amd,imageon-%u.%u", &r, &patch) == 2) {
> > > > - rev->core = r / 100;
> > > > + uint32_t core, major, minor;
> > > > +
> > > > + core = r / 100;
> > > > r %= 100;
> > > > - rev->major = r / 10;
> > > > + major = r / 10;
> > > > r %= 10;
> > > > - rev->minor = r;
> > > > - rev->patchid = patch;
> > > > + minor = r;
> > > > +
> > > > + *chipid = (core << 24) |
> > > > + (major << 16) |
> > > > + (minor << 8) |
> > > > + patch;
> > >
> > > This starts to look realy crazy. I'd repeat my suggestion of moving towards
> > > of_device match data. This would result in some duplication, we'd have to
> > > explicitly list all supported compatibles in the of_match_table. But then we
> > > can drop all the CHIPID lists from device table and/or manual parsing of the
> > > chipid from the compat field.
> > >
> > > This way we can have per-SoC overrides, etc.
> > >
> > > > return 0;
> > > > }
> > > > +
> > > > + if (sscanf(compat, "qcom,adreno-%08x", chipid) == 1)
> > > > + return 0;
> > > > }
> > > > /* and if that fails, fall back to legacy "qcom,chipid" property: */
> > > > - ret = of_property_read_u32(node, "qcom,chipid", &chipid);
> > > > + ret = of_property_read_u32(node, "qcom,chipid", chipid);
> > > > if (ret) {
> > > > DRM_DEV_ERROR(dev, "could not parse qcom,chipid: %d\n", ret);
> > > > return ret;
> > > > }
> > > > - rev->core = (chipid >> 24) & 0xff;
> > > > - rev->major = (chipid >> 16) & 0xff;
> > > > - rev->minor = (chipid >> 8) & 0xff;
> > > > - rev->patchid = (chipid & 0xff);
> > > > -
> > > > dev_warn(dev, "Using legacy qcom,chipid binding!\n");
> > > > - dev_warn(dev, "Use compatible qcom,adreno-%u%u%u.%u instead.\n",
> > > > - rev->core, rev->major, rev->minor, rev->patchid);
> > > > return 0;
> > > > }
> > > > @@ -651,22 +645,22 @@ static int adreno_bind(struct device *dev, struct device *master, void *data)
> > > > struct msm_gpu *gpu;
> > > > int ret;
> > > > - ret = find_chipid(dev, &config.rev);
> > > > + ret = find_chipid(dev, &config.chip_id);
> > > > if (ret)
> > > > return ret;
> > > > dev->platform_data = &config;
> > > > priv->gpu_pdev = to_platform_device(dev);
> > > > - info = adreno_info(config.rev);
> > > > + info = adreno_find_info(config.chip_id);
> > > > if (!info) {
> > > > dev_warn(drm->dev, "Unknown GPU revision: %"ADRENO_CHIPID_FMT"\n",
> > > > - ADRENO_CHIPID_ARGS(config.rev));
> > > > + ADRENO_CHIPID_ARGS(config.chip_id));
> > > > return -ENXIO;
> > > > }
> > > > - DBG("Found GPU: %"ADRENO_CHIPID_FMT, ADRENO_CHIPID_ARGS(config.rev));
> > > > + DBG("Found GPU: %"ADRENO_CHIPID_FMT, ADRENO_CHIPID_ARGS(config.chip_id));
> > > > priv->is_a2xx = info->family < ADRENO_3XX;
> > > > priv->has_cached_coherent =
> > > > diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
> > > > index 1a982a926f21..1274609a74b1 100644
> > > > --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c
> > > > +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
> > > > @@ -326,10 +326,7 @@ int adreno_get_param(struct msm_gpu *gpu, struct msm_file_private *ctx,
> > > > *value = !adreno_is_a650_family(adreno_gpu) ? 0x100000 : 0;
> > > > return 0;
> > > > case MSM_PARAM_CHIP_ID:
> > > > - *value = (uint64_t)adreno_gpu->rev.patchid |
> > > > - ((uint64_t)adreno_gpu->rev.minor << 8) |
> > > > - ((uint64_t)adreno_gpu->rev.major << 16) |
> > > > - ((uint64_t)adreno_gpu->rev.core << 24);
> > > > + *value = adreno_gpu->chip_id;
> > > > if (!adreno_gpu->info->revn)
> > > > *value |= ((uint64_t) adreno_gpu->speedbin) << 32;
> > > > return 0;
> > > > @@ -849,7 +846,7 @@ void adreno_show(struct msm_gpu *gpu, struct msm_gpu_state *state,
> > > > drm_printf(p, "revision: %u (%"ADRENO_CHIPID_FMT")\n",
> > > > adreno_gpu->info->revn,
> > > > - ADRENO_CHIPID_ARGS(adreno_gpu->rev));
> > > > + ADRENO_CHIPID_ARGS(adreno_gpu->chip_id));
> > > > /*
> > > > * If this is state collected due to iova fault, so fault related info
> > > > *
> > > > @@ -922,7 +919,7 @@ void adreno_dump_info(struct msm_gpu *gpu)
> > > > printk("revision: %u (%"ADRENO_CHIPID_FMT")\n",
> > > > adreno_gpu->info->revn,
> > > > - ADRENO_CHIPID_ARGS(adreno_gpu->rev));
> > > > + ADRENO_CHIPID_ARGS(adreno_gpu->chip_id));
> > > > for (i = 0; i < gpu->nr_rings; i++) {
> > > > struct msm_ringbuffer *ring = gpu->rb[i];
> > > > @@ -1072,14 +1069,13 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev,
> > > > struct adreno_platform_config *config = dev->platform_data;
> > > > struct msm_gpu_config adreno_gpu_config = { 0 };
> > > > struct msm_gpu *gpu = &adreno_gpu->base;
> > > > - struct adreno_rev *rev = &config->rev;
> > > > const char *gpu_name;
> > > > u32 speedbin;
> > > > int ret;
> > > > adreno_gpu->funcs = funcs;
> > > > - adreno_gpu->info = adreno_info(config->rev);
> > > > - adreno_gpu->rev = *rev;
> > > > + adreno_gpu->info = adreno_find_info(config->chip_id);
> > > > + adreno_gpu->chip_id = config->chip_id;
> > > > /* Only handle the core clock when GMU is not in use (or is absent). */
> > > > if (adreno_has_gmu_wrapper(adreno_gpu) ||
> > > > @@ -1104,7 +1100,7 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev,
> > > > adreno_gpu->speedbin = (uint16_t) (0xffff & speedbin);
> > > > gpu_name = devm_kasprintf(dev, GFP_KERNEL, "%"ADRENO_CHIPID_FMT,
> > > > - ADRENO_CHIPID_ARGS(config->rev));
> > > > + ADRENO_CHIPID_ARGS(config->chip_id));
> > > > if (!gpu_name)
> > > > return -ENOMEM;
> > > > diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> > > > index 73e7155f164c..18f53c7ab589 100644
> > > > --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> > > > +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> > > > @@ -54,23 +54,15 @@ enum adreno_family {
> > > > #define ADRENO_QUIRK_HAS_HW_APRIV BIT(3)
> > > > #define ADRENO_QUIRK_HAS_CACHED_COHERENT BIT(4)
> > > > -struct adreno_rev {
> > > > - uint8_t core;
> > > > - uint8_t major;
> > > > - uint8_t minor;
> > > > - uint8_t patchid;
> > > > -};
> > > > -
> > > > -#define ANY_ID 0xff
> > > > -
> > > > -#define ADRENO_REV(core, major, minor, patchid) \
> > > > - ((struct adreno_rev){ core, major, minor, patchid })
> > > > -
> > > > /* Helper for formating the chip_id in the way that userspace tools like
> > > > * crashdec expect.
> > > > */
> > > > #define ADRENO_CHIPID_FMT "u.%u.%u.%u"
> > > > -#define ADRENO_CHIPID_ARGS(_r) (_r).core, (_r).major, (_r).minor, (_r).patchid
> > > > +#define ADRENO_CHIPID_ARGS(_c) \
> > > > + (((_c) >> 24) & 0xff), \
> > > > + (((_c) >> 16) & 0xff), \
> > > > + (((_c) >> 8) & 0xff), \
> > > > + ((_c) & 0xff)
> > >
> > > So, we still have some meaning for chipid?
> > >
> > > > struct adreno_gpu_funcs {
> > > > struct msm_gpu_funcs base;
> > > > @@ -87,7 +79,12 @@ extern const struct adreno_reglist a660_hwcg[], a690_hwcg[];
> > > > struct adreno_info {
> > > > const char *machine;
> > > > - struct adreno_rev rev;
> > > > + /**
> > > > + * @chipids: Table of matching chip-ids
> > > > + *
> > > > + * Terminated with 0 sentinal
> > > > + */
> > > > + uint32_t *chip_ids;
> > > > enum adreno_family family;
> > > > uint32_t revn;
> > > > const char *fw[ADRENO_FW_MAX];
> > > > @@ -107,6 +104,8 @@ struct adreno_info {
> > > > uint32_t *speedbins;
> > > > };
> > > > +#define ADRENO_CHIP_IDS(tbl...) (uint32_t[]) { tbl, 0 }
> > > > +
> > > > /*
> > > > * Helper to build a speedbin table, ie. the table:
> > > > * fuse | speedbin
> > > > @@ -125,12 +124,12 @@ struct adreno_info {
> > > > */
> > > > #define ADRENO_SPEEDBINS(tbl...) (uint32_t[]) { tbl, UINT_MAX }
> > > > -const struct adreno_info *adreno_info(struct adreno_rev rev);
> > > > +const struct adreno_info *adreno_find_info(uint32_t chip_id);
> > > > struct adreno_gpu {
> > > > struct msm_gpu base;
> > > > - struct adreno_rev rev;
> > > > const struct adreno_info *info;
> > > > + uint32_t chip_id;
> > > > uint16_t speedbin;
> > > > const struct adreno_gpu_funcs *funcs;
> > > > @@ -179,7 +178,7 @@ struct adreno_ocmem {
> > > > /* platform config data (ie. from DT, or pdata) */
> > > > struct adreno_platform_config {
> > > > - struct adreno_rev rev;
> > > > + uint32_t chip_id;
> > > > };
> > > > #define ADRENO_IDLE_TIMEOUT msecs_to_jiffies(1000)
> > > > @@ -196,7 +195,15 @@ struct adreno_platform_config {
> > > > __ret; \
> > > > })
> > > > -bool adreno_cmp_rev(struct adreno_rev rev1, struct adreno_rev rev2);
> > > > +static inline uint8_t adreno_patchid(const struct adreno_gpu *gpu)
> > > > +{
> > > > + /* It is probably ok to assume legacy "adreno_rev" format
> > > > + * for all a6xx devices, but probably best to limit this
> > > > + * to older things.
> > > > + */
> > > > + WARN_ON_ONCE(gpu->info->family >= ADRENO_6XX_GEN1);
> > > > + return gpu->chip_id & 0xff;
> > > > +}
> > > > static inline bool adreno_is_revn(const struct adreno_gpu *gpu, uint32_t revn)
> > > > {
> > > > @@ -252,7 +259,7 @@ static inline bool adreno_is_a330(const struct adreno_gpu *gpu)
> > > > static inline bool adreno_is_a330v2(const struct adreno_gpu *gpu)
> > > > {
> > > > - return adreno_is_a330(gpu) && (gpu->rev.patchid > 0);
> > > > + return adreno_is_a330(gpu) && (adreno_patchid(gpu) > 0);
> > > > }
> > > > static inline int adreno_is_a405(const struct adreno_gpu *gpu)
> > > > @@ -342,8 +349,7 @@ static inline int adreno_is_a650(const struct adreno_gpu *gpu)
> > > > static inline int adreno_is_7c3(const struct adreno_gpu *gpu)
> > > > {
> > > > - /* The order of args is important here to handle ANY_ID correctly */
> > > > - return adreno_cmp_rev(ADRENO_REV(6, 3, 5, ANY_ID), gpu->rev);
> > > > + return gpu->info->chip_ids[0] == 0x06030500;
> >
> > Why not use adreno_gpu->chip_id here? Or do we need this check before
> > adreno_gpu_init()? I thought we got rid of those.
>
> This is intentional, because there can be multiple chip-id's for a
> single table entry, in theory. But the first chip_id in the gpu table
> entry should suffice, and is simpler than comparing
> adreno_gpu->chip_id against each possible match.
Sounds that would work, but please mention somewhere that a new chipid
should always be appended to the bottom of the array. Otherwise, it
would introduce be a silly subtle bug.
-Akhil
>
> BR,
> -R
>
> > >
> > > Ugh. The thing that bugs me isn't even the manual comparison of chip_ids[0],
> > > but the fact that these two platforms stand aside. I think at the end we
> > > should have a single mechanism for checking GPU's SKUs.
> > >
> > > Or maybe we should get rid of that completely.
> > >
> > > If we get rid of a single gpulist table and move individual GPU info
> > > definitions to aNxx_gpu.c, we can subclass a generic info structure with
> > > generation-specific data, for example generation-specific quirks, pointers
> > > to hcwg or VBIF registers, etc. And then instead of having adreno_is_foo all
> > > over the code we can migrate most of these checks to data in the gpu info
> > > data.
> >
> > I think the downstream driver does what you described here. It helps to
> > move more generation-specific data to the table without inflating the
> > gpu table size.
> >
> > -Akhil
> >
> > >
> > > > }
> > > > static inline int adreno_is_a660(const struct adreno_gpu *gpu)
> > > > @@ -358,8 +364,7 @@ static inline int adreno_is_a680(const struct adreno_gpu *gpu)
> > > > static inline int adreno_is_a690(const struct adreno_gpu *gpu)
> > > > {
> > > > - /* The order of args is important here to handle ANY_ID correctly */
> > > > - return adreno_cmp_rev(ADRENO_REV(6, 9, 0, ANY_ID), gpu->rev);
> > > > + return gpu->info->chip_ids[0] == 0x06090000;
> > > > };
> > > > /* check for a615, a616, a618, a619 or any a630 derivatives */
> > > > static inline int adreno_is_a630_family(const struct adreno_gpu *gpu)
> > >
> > > --
> > > With best wishes
> > > Dmitry
> > >
^ permalink raw reply [flat|nested] 73+ messages in thread
* Re: [Freedreno] [PATCH 06/12] drm/msm/adreno: Allow SoC specific gpu device table entries
2023-07-13 20:26 ` Akhil P Oommen
@ 2023-07-26 18:28 ` Rob Clark
2023-07-26 20:00 ` Dmitry Baryshkov
0 siblings, 1 reply; 73+ messages in thread
From: Rob Clark @ 2023-07-26 18:28 UTC (permalink / raw)
To: Akhil P Oommen
Cc: Rob Clark, linux-arm-msm, dri-devel, Konrad Dybcio,
Dmitry Baryshkov, freedreno
On Thu, Jul 13, 2023 at 1:26 PM Akhil P Oommen <quic_akhilpo@quicinc.com> wrote:
>
> On Fri, Jul 07, 2023 at 05:34:04AM +0300, Dmitry Baryshkov wrote:
> >
> > On 07/07/2023 00:10, Rob Clark wrote:
> > > From: Rob Clark <robdclark@chromium.org>
> > >
> > > There are cases where there are differences due to SoC integration.
> > > Such as cache-coherency support, and (in the next patch) e-fuse to
> > > speedbin mappings.
> >
> > I have the feeling that we are trying to circumvent the way DT works. I'd
> > suggest adding explicit SoC-compatible strings to Adreno bindings and then
> > using of_device_id::data and then of_device_get_match_data().
> >
> Just thinking, then how about a unique compatible string which we match
> to identify gpu->info and drop chip-id check completely here?
Ok, I think we could do this, so something like:
compatible = "qcom,sm4350-adreno-619.0", qcom,adreno-619.0", "qcom,adreno"
?
It looks like we don't have gpu dt bits upstream yet for either sm4350
or sm6375, so I suppose we could get away with this change
BR,
-R
> -Akhil
>
> > >
> > > Signed-off-by: Rob Clark <robdclark@chromium.org>
> > > ---
> > > drivers/gpu/drm/msm/adreno/adreno_device.c | 34 +++++++++++++++++++---
> > > drivers/gpu/drm/msm/adreno/adreno_gpu.h | 1 +
> > > 2 files changed, 31 insertions(+), 4 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c
> > > index 3c531da417b9..e62bc895a31f 100644
> > > --- a/drivers/gpu/drm/msm/adreno/adreno_device.c
> > > +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c
> > > @@ -258,6 +258,32 @@ static const struct adreno_info gpulist[] = {
> > > .inactive_period = DRM_MSM_INACTIVE_PERIOD,
> > > .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT,
> > > .init = a6xx_gpu_init,
> > > + }, {
> > > + .machine = "qcom,sm4350",
> > > + .rev = ADRENO_REV(6, 1, 9, ANY_ID),
> > > + .revn = 619,
> > > + .fw = {
> > > + [ADRENO_FW_SQE] = "a630_sqe.fw",
> > > + [ADRENO_FW_GMU] = "a619_gmu.bin",
> > > + },
> > > + .gmem = SZ_512K,
> > > + .inactive_period = DRM_MSM_INACTIVE_PERIOD,
> > > + .init = a6xx_gpu_init,
> > > + .zapfw = "a615_zap.mdt",
> > > + .hwcg = a615_hwcg,
> > > + }, {
> > > + .machine = "qcom,sm6375",
> > > + .rev = ADRENO_REV(6, 1, 9, ANY_ID),
> > > + .revn = 619,
> > > + .fw = {
> > > + [ADRENO_FW_SQE] = "a630_sqe.fw",
> > > + [ADRENO_FW_GMU] = "a619_gmu.bin",
> > > + },
> > > + .gmem = SZ_512K,
> > > + .inactive_period = DRM_MSM_INACTIVE_PERIOD,
> > > + .init = a6xx_gpu_init,
> > > + .zapfw = "a615_zap.mdt",
> > > + .hwcg = a615_hwcg,
> > > }, {
> > > .rev = ADRENO_REV(6, 1, 9, ANY_ID),
> > > .revn = 619,
> > > @@ -409,6 +435,8 @@ const struct adreno_info *adreno_info(struct adreno_rev rev)
> > > /* identify gpu: */
> > > for (i = 0; i < ARRAY_SIZE(gpulist); i++) {
> > > const struct adreno_info *info = &gpulist[i];
> > > + if (info->machine && !of_machine_is_compatible(info->machine))
> > > + continue;
> > > if (adreno_cmp_rev(info->rev, rev))
> > > return info;
> > > }
> > > @@ -563,6 +591,8 @@ static int adreno_bind(struct device *dev, struct device *master, void *data)
> > > config.rev.minor, config.rev.patchid);
> > > priv->is_a2xx = config.rev.core == 2;
> > > + priv->has_cached_coherent =
> > > + !!(info->quirks & ADRENO_QUIRK_HAS_CACHED_COHERENT);
> > > gpu = info->init(drm);
> > > if (IS_ERR(gpu)) {
> > > @@ -574,10 +604,6 @@ static int adreno_bind(struct device *dev, struct device *master, void *data)
> > > if (ret)
> > > return ret;
> > > - priv->has_cached_coherent =
> > > - !!(info->quirks & ADRENO_QUIRK_HAS_CACHED_COHERENT) &&
> > > - !adreno_has_gmu_wrapper(to_adreno_gpu(gpu));
> > > -
> > > return 0;
> > > }
> > > diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> > > index e08d41337169..d5335b99c64c 100644
> > > --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> > > +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> > > @@ -61,6 +61,7 @@ extern const struct adreno_reglist a612_hwcg[], a615_hwcg[], a630_hwcg[], a640_h
> > > extern const struct adreno_reglist a660_hwcg[], a690_hwcg[];
> > > struct adreno_info {
> > > + const char *machine;
> > > struct adreno_rev rev;
> > > uint32_t revn;
> > > const char *fw[ADRENO_FW_MAX];
> >
> > --
> > With best wishes
> > Dmitry
> >
^ permalink raw reply [flat|nested] 73+ messages in thread
* Re: [Freedreno] [PATCH 06/12] drm/msm/adreno: Allow SoC specific gpu device table entries
2023-07-26 18:28 ` Rob Clark
@ 2023-07-26 20:00 ` Dmitry Baryshkov
2023-07-26 20:11 ` Rob Clark
0 siblings, 1 reply; 73+ messages in thread
From: Dmitry Baryshkov @ 2023-07-26 20:00 UTC (permalink / raw)
To: Rob Clark
Cc: Rob Clark, Akhil P Oommen, linux-arm-msm, dri-devel,
Konrad Dybcio, freedreno
On Wed, 26 Jul 2023 at 21:28, Rob Clark <robdclark@gmail.com> wrote:
>
> On Thu, Jul 13, 2023 at 1:26 PM Akhil P Oommen <quic_akhilpo@quicinc.com> wrote:
> >
> > On Fri, Jul 07, 2023 at 05:34:04AM +0300, Dmitry Baryshkov wrote:
> > >
> > > On 07/07/2023 00:10, Rob Clark wrote:
> > > > From: Rob Clark <robdclark@chromium.org>
> > > >
> > > > There are cases where there are differences due to SoC integration.
> > > > Such as cache-coherency support, and (in the next patch) e-fuse to
> > > > speedbin mappings.
> > >
> > > I have the feeling that we are trying to circumvent the way DT works. I'd
> > > suggest adding explicit SoC-compatible strings to Adreno bindings and then
> > > using of_device_id::data and then of_device_get_match_data().
> > >
> > Just thinking, then how about a unique compatible string which we match
> > to identify gpu->info and drop chip-id check completely here?
>
> Ok, I think we could do this, so something like:
>
> compatible = "qcom,sm4350-adreno-619.0", qcom,adreno-619.0", "qcom,adreno"
>
> ?
>
> It looks like we don't have gpu dt bits upstream yet for either sm4350
> or sm6375, so I suppose we could get away with this change
I think we can even skip the 619.0 part in the SoC compat string.
So it will be:
compatible = "qcom,sm4350-adreno", qcom,adreno-619.0", "qcom,adreno";
In future we can drop the chipid part completely and handle that as a
part of SoC data:
compatible = "qcom,sm4350-adreno", "qcom,adreno";
With the driver knowing that sm4350-adreno means ADRENO_ID(6,1,9,0)
>
> BR,
> -R
>
> > -Akhil
> >
> > > >
> > > > Signed-off-by: Rob Clark <robdclark@chromium.org>
> > > > ---
> > > > drivers/gpu/drm/msm/adreno/adreno_device.c | 34 +++++++++++++++++++---
> > > > drivers/gpu/drm/msm/adreno/adreno_gpu.h | 1 +
> > > > 2 files changed, 31 insertions(+), 4 deletions(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c
> > > > index 3c531da417b9..e62bc895a31f 100644
> > > > --- a/drivers/gpu/drm/msm/adreno/adreno_device.c
> > > > +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c
> > > > @@ -258,6 +258,32 @@ static const struct adreno_info gpulist[] = {
> > > > .inactive_period = DRM_MSM_INACTIVE_PERIOD,
> > > > .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT,
> > > > .init = a6xx_gpu_init,
> > > > + }, {
> > > > + .machine = "qcom,sm4350",
> > > > + .rev = ADRENO_REV(6, 1, 9, ANY_ID),
> > > > + .revn = 619,
> > > > + .fw = {
> > > > + [ADRENO_FW_SQE] = "a630_sqe.fw",
> > > > + [ADRENO_FW_GMU] = "a619_gmu.bin",
> > > > + },
> > > > + .gmem = SZ_512K,
> > > > + .inactive_period = DRM_MSM_INACTIVE_PERIOD,
> > > > + .init = a6xx_gpu_init,
> > > > + .zapfw = "a615_zap.mdt",
> > > > + .hwcg = a615_hwcg,
> > > > + }, {
> > > > + .machine = "qcom,sm6375",
> > > > + .rev = ADRENO_REV(6, 1, 9, ANY_ID),
> > > > + .revn = 619,
> > > > + .fw = {
> > > > + [ADRENO_FW_SQE] = "a630_sqe.fw",
> > > > + [ADRENO_FW_GMU] = "a619_gmu.bin",
> > > > + },
> > > > + .gmem = SZ_512K,
> > > > + .inactive_period = DRM_MSM_INACTIVE_PERIOD,
> > > > + .init = a6xx_gpu_init,
> > > > + .zapfw = "a615_zap.mdt",
> > > > + .hwcg = a615_hwcg,
> > > > }, {
> > > > .rev = ADRENO_REV(6, 1, 9, ANY_ID),
> > > > .revn = 619,
> > > > @@ -409,6 +435,8 @@ const struct adreno_info *adreno_info(struct adreno_rev rev)
> > > > /* identify gpu: */
> > > > for (i = 0; i < ARRAY_SIZE(gpulist); i++) {
> > > > const struct adreno_info *info = &gpulist[i];
> > > > + if (info->machine && !of_machine_is_compatible(info->machine))
> > > > + continue;
> > > > if (adreno_cmp_rev(info->rev, rev))
> > > > return info;
> > > > }
> > > > @@ -563,6 +591,8 @@ static int adreno_bind(struct device *dev, struct device *master, void *data)
> > > > config.rev.minor, config.rev.patchid);
> > > > priv->is_a2xx = config.rev.core == 2;
> > > > + priv->has_cached_coherent =
> > > > + !!(info->quirks & ADRENO_QUIRK_HAS_CACHED_COHERENT);
> > > > gpu = info->init(drm);
> > > > if (IS_ERR(gpu)) {
> > > > @@ -574,10 +604,6 @@ static int adreno_bind(struct device *dev, struct device *master, void *data)
> > > > if (ret)
> > > > return ret;
> > > > - priv->has_cached_coherent =
> > > > - !!(info->quirks & ADRENO_QUIRK_HAS_CACHED_COHERENT) &&
> > > > - !adreno_has_gmu_wrapper(to_adreno_gpu(gpu));
> > > > -
> > > > return 0;
> > > > }
> > > > diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> > > > index e08d41337169..d5335b99c64c 100644
> > > > --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> > > > +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> > > > @@ -61,6 +61,7 @@ extern const struct adreno_reglist a612_hwcg[], a615_hwcg[], a630_hwcg[], a640_h
> > > > extern const struct adreno_reglist a660_hwcg[], a690_hwcg[];
> > > > struct adreno_info {
> > > > + const char *machine;
> > > > struct adreno_rev rev;
> > > > uint32_t revn;
> > > > const char *fw[ADRENO_FW_MAX];
> > >
> > > --
> > > With best wishes
> > > Dmitry
> > >
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 73+ messages in thread
* Re: [Freedreno] [PATCH 06/12] drm/msm/adreno: Allow SoC specific gpu device table entries
2023-07-26 20:00 ` Dmitry Baryshkov
@ 2023-07-26 20:11 ` Rob Clark
2023-07-26 21:43 ` Dmitry Baryshkov
0 siblings, 1 reply; 73+ messages in thread
From: Rob Clark @ 2023-07-26 20:11 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Rob Clark, Akhil P Oommen, linux-arm-msm, dri-devel,
Konrad Dybcio, freedreno
On Wed, Jul 26, 2023 at 1:00 PM Dmitry Baryshkov
<dmitry.baryshkov@linaro.org> wrote:
>
> On Wed, 26 Jul 2023 at 21:28, Rob Clark <robdclark@gmail.com> wrote:
> >
> > On Thu, Jul 13, 2023 at 1:26 PM Akhil P Oommen <quic_akhilpo@quicinc.com> wrote:
> > >
> > > On Fri, Jul 07, 2023 at 05:34:04AM +0300, Dmitry Baryshkov wrote:
> > > >
> > > > On 07/07/2023 00:10, Rob Clark wrote:
> > > > > From: Rob Clark <robdclark@chromium.org>
> > > > >
> > > > > There are cases where there are differences due to SoC integration.
> > > > > Such as cache-coherency support, and (in the next patch) e-fuse to
> > > > > speedbin mappings.
> > > >
> > > > I have the feeling that we are trying to circumvent the way DT works. I'd
> > > > suggest adding explicit SoC-compatible strings to Adreno bindings and then
> > > > using of_device_id::data and then of_device_get_match_data().
> > > >
> > > Just thinking, then how about a unique compatible string which we match
> > > to identify gpu->info and drop chip-id check completely here?
> >
> > Ok, I think we could do this, so something like:
> >
> > compatible = "qcom,sm4350-adreno-619.0", qcom,adreno-619.0", "qcom,adreno"
> >
> > ?
> >
> > It looks like we don't have gpu dt bits upstream yet for either sm4350
> > or sm6375, so I suppose we could get away with this change
>
> I think we can even skip the 619.0 part in the SoC compat string.
> So it will be:
>
> compatible = "qcom,sm4350-adreno", qcom,adreno-619.0", "qcom,adreno";
>
> In future we can drop the chipid part completely and handle that as a
> part of SoC data:
>
> compatible = "qcom,sm4350-adreno", "qcom,adreno";
>
> With the driver knowing that sm4350-adreno means ADRENO_ID(6,1,9,0)
>
I don't think we can do that, there are cases where the same SoC had
multiple revisions of adreno. We could possibly do that with future
things where we can read the chip-id from fw.
What we _could_ do at the expense of making the compatible parsing a
tiny bit more complex is something like:
compatible = "qcom,sm4350-adreno-619.0", "qcom,adreno"
BR,
-R
> >
> > BR,
> > -R
> >
> > > -Akhil
> > >
> > > > >
> > > > > Signed-off-by: Rob Clark <robdclark@chromium.org>
> > > > > ---
> > > > > drivers/gpu/drm/msm/adreno/adreno_device.c | 34 +++++++++++++++++++---
> > > > > drivers/gpu/drm/msm/adreno/adreno_gpu.h | 1 +
> > > > > 2 files changed, 31 insertions(+), 4 deletions(-)
> > > > >
> > > > > diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c
> > > > > index 3c531da417b9..e62bc895a31f 100644
> > > > > --- a/drivers/gpu/drm/msm/adreno/adreno_device.c
> > > > > +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c
> > > > > @@ -258,6 +258,32 @@ static const struct adreno_info gpulist[] = {
> > > > > .inactive_period = DRM_MSM_INACTIVE_PERIOD,
> > > > > .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT,
> > > > > .init = a6xx_gpu_init,
> > > > > + }, {
> > > > > + .machine = "qcom,sm4350",
> > > > > + .rev = ADRENO_REV(6, 1, 9, ANY_ID),
> > > > > + .revn = 619,
> > > > > + .fw = {
> > > > > + [ADRENO_FW_SQE] = "a630_sqe.fw",
> > > > > + [ADRENO_FW_GMU] = "a619_gmu.bin",
> > > > > + },
> > > > > + .gmem = SZ_512K,
> > > > > + .inactive_period = DRM_MSM_INACTIVE_PERIOD,
> > > > > + .init = a6xx_gpu_init,
> > > > > + .zapfw = "a615_zap.mdt",
> > > > > + .hwcg = a615_hwcg,
> > > > > + }, {
> > > > > + .machine = "qcom,sm6375",
> > > > > + .rev = ADRENO_REV(6, 1, 9, ANY_ID),
> > > > > + .revn = 619,
> > > > > + .fw = {
> > > > > + [ADRENO_FW_SQE] = "a630_sqe.fw",
> > > > > + [ADRENO_FW_GMU] = "a619_gmu.bin",
> > > > > + },
> > > > > + .gmem = SZ_512K,
> > > > > + .inactive_period = DRM_MSM_INACTIVE_PERIOD,
> > > > > + .init = a6xx_gpu_init,
> > > > > + .zapfw = "a615_zap.mdt",
> > > > > + .hwcg = a615_hwcg,
> > > > > }, {
> > > > > .rev = ADRENO_REV(6, 1, 9, ANY_ID),
> > > > > .revn = 619,
> > > > > @@ -409,6 +435,8 @@ const struct adreno_info *adreno_info(struct adreno_rev rev)
> > > > > /* identify gpu: */
> > > > > for (i = 0; i < ARRAY_SIZE(gpulist); i++) {
> > > > > const struct adreno_info *info = &gpulist[i];
> > > > > + if (info->machine && !of_machine_is_compatible(info->machine))
> > > > > + continue;
> > > > > if (adreno_cmp_rev(info->rev, rev))
> > > > > return info;
> > > > > }
> > > > > @@ -563,6 +591,8 @@ static int adreno_bind(struct device *dev, struct device *master, void *data)
> > > > > config.rev.minor, config.rev.patchid);
> > > > > priv->is_a2xx = config.rev.core == 2;
> > > > > + priv->has_cached_coherent =
> > > > > + !!(info->quirks & ADRENO_QUIRK_HAS_CACHED_COHERENT);
> > > > > gpu = info->init(drm);
> > > > > if (IS_ERR(gpu)) {
> > > > > @@ -574,10 +604,6 @@ static int adreno_bind(struct device *dev, struct device *master, void *data)
> > > > > if (ret)
> > > > > return ret;
> > > > > - priv->has_cached_coherent =
> > > > > - !!(info->quirks & ADRENO_QUIRK_HAS_CACHED_COHERENT) &&
> > > > > - !adreno_has_gmu_wrapper(to_adreno_gpu(gpu));
> > > > > -
> > > > > return 0;
> > > > > }
> > > > > diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> > > > > index e08d41337169..d5335b99c64c 100644
> > > > > --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> > > > > +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> > > > > @@ -61,6 +61,7 @@ extern const struct adreno_reglist a612_hwcg[], a615_hwcg[], a630_hwcg[], a640_h
> > > > > extern const struct adreno_reglist a660_hwcg[], a690_hwcg[];
> > > > > struct adreno_info {
> > > > > + const char *machine;
> > > > > struct adreno_rev rev;
> > > > > uint32_t revn;
> > > > > const char *fw[ADRENO_FW_MAX];
> > > >
> > > > --
> > > > With best wishes
> > > > Dmitry
> > > >
>
>
>
> --
> With best wishes
> Dmitry
^ permalink raw reply [flat|nested] 73+ messages in thread
* Re: [Freedreno] [PATCH 12/12] drm/msm/adreno: Switch to chip-id for identifying GPU
2023-07-07 3:45 ` [Freedreno] " Dmitry Baryshkov
2023-07-13 21:39 ` Akhil P Oommen
@ 2023-07-26 21:37 ` Rob Clark
2023-07-26 21:38 ` Dmitry Baryshkov
1 sibling, 1 reply; 73+ messages in thread
From: Rob Clark @ 2023-07-26 21:37 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Konrad Dybcio, linux-arm-msm, Rob Clark, freedreno, dri-devel
On Thu, Jul 6, 2023 at 8:45 PM Dmitry Baryshkov
<dmitry.baryshkov@linaro.org> wrote:
>
> On 07/07/2023 00:10, Rob Clark wrote:
> > From: Rob Clark <robdclark@chromium.org>
> >
> > Since the revision becomes an opaque identifier with future GPUs, move
> > away from treating different ranges of bits as having a given meaning.
> > This means that we need to explicitly list different patch revisions in
> > the device table.
> >
> > Signed-off-by: Rob Clark <robdclark@chromium.org>
> > ---
> > drivers/gpu/drm/msm/adreno/a4xx_gpu.c | 2 +-
> > drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 11 +-
> > drivers/gpu/drm/msm/adreno/a5xx_power.c | 2 +-
> > drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 13 ++-
> > drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 9 +-
> > drivers/gpu/drm/msm/adreno/adreno_device.c | 128 ++++++++++-----------
> > drivers/gpu/drm/msm/adreno/adreno_gpu.c | 16 +--
> > drivers/gpu/drm/msm/adreno/adreno_gpu.h | 51 ++++----
> > 8 files changed, 122 insertions(+), 110 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/msm/adreno/a4xx_gpu.c b/drivers/gpu/drm/msm/adreno/a4xx_gpu.c
> > index 715436cb3996..8b4cdf95f445 100644
> > --- a/drivers/gpu/drm/msm/adreno/a4xx_gpu.c
> > +++ b/drivers/gpu/drm/msm/adreno/a4xx_gpu.c
> > @@ -145,7 +145,7 @@ static void a4xx_enable_hwcg(struct msm_gpu *gpu)
> > gpu_write(gpu, REG_A4XX_RBBM_CLOCK_DELAY_HLSQ, 0x00220000);
> > /* Early A430's have a timing issue with SP/TP power collapse;
> > disabling HW clock gating prevents it. */
> > - if (adreno_is_a430(adreno_gpu) && adreno_gpu->rev.patchid < 2)
> > + if (adreno_is_a430(adreno_gpu) && adreno_patchid(adreno_gpu) < 2)
> > gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL, 0);
> > else
> > gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL, 0xAAAAAAAA);
> > diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
> > index f0803e94ebe5..70d2b5342cd9 100644
> > --- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
> > +++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
> > @@ -1744,6 +1744,7 @@ struct msm_gpu *a5xx_gpu_init(struct drm_device *dev)
> > struct msm_drm_private *priv = dev->dev_private;
> > struct platform_device *pdev = priv->gpu_pdev;
> > struct adreno_platform_config *config = pdev->dev.platform_data;
> > + const struct adreno_info *info;
> > struct a5xx_gpu *a5xx_gpu = NULL;
> > struct adreno_gpu *adreno_gpu;
> > struct msm_gpu *gpu;
> > @@ -1770,7 +1771,15 @@ struct msm_gpu *a5xx_gpu_init(struct drm_device *dev)
> >
> > nr_rings = 4;
> >
> > - if (adreno_cmp_rev(ADRENO_REV(5, 1, 0, ANY_ID), config->rev))
> > + /*
> > + * Note that we wouldn't have been able to get this far if there is not
> > + * a device table entry for this chip_id
> > + */
> > + info = adreno_find_info(config->chip_id);
> > + if (WARN_ON(!info))
> > + return ERR_PTR(-EINVAL);
> > +
> > + if (info->revn == 510)
> > nr_rings = 1;
> >
> > ret = adreno_gpu_init(dev, pdev, adreno_gpu, &funcs, nr_rings);
> > diff --git a/drivers/gpu/drm/msm/adreno/a5xx_power.c b/drivers/gpu/drm/msm/adreno/a5xx_power.c
> > index 0e63a1429189..7705f8010484 100644
> > --- a/drivers/gpu/drm/msm/adreno/a5xx_power.c
> > +++ b/drivers/gpu/drm/msm/adreno/a5xx_power.c
> > @@ -179,7 +179,7 @@ static void a540_lm_setup(struct msm_gpu *gpu)
> >
> > /* The battery current limiter isn't enabled for A540 */
> > config = AGC_LM_CONFIG_BCL_DISABLED;
> > - config |= adreno_gpu->rev.patchid << AGC_LM_CONFIG_GPU_VERSION_SHIFT;
> > + config |= adreno_patchid(adreno_gpu) << AGC_LM_CONFIG_GPU_VERSION_SHIFT;
> >
> > /* For now disable GPMU side throttling */
> > config |= AGC_LM_CONFIG_THROTTLE_DISABLE;
> > diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
> > index f1bb20574018..a9ba547a120c 100644
> > --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
> > +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
> > @@ -790,10 +790,15 @@ static int a6xx_gmu_fw_start(struct a6xx_gmu *gmu, unsigned int state)
> > gmu_write(gmu, REG_A6XX_GMU_AHB_FENCE_RANGE_0,
> > (1 << 31) | (0xa << 18) | (0xa0));
> >
> > - chipid = adreno_gpu->rev.core << 24;
> > - chipid |= adreno_gpu->rev.major << 16;
> > - chipid |= adreno_gpu->rev.minor << 12;
> > - chipid |= adreno_gpu->rev.patchid << 8;
> > + /* Note that the GMU has a slightly different layout for
> > + * chip_id, for whatever reason, so a bit of massaging
> > + * is needed. The upper 16b are the same, but minor and
> > + * patchid are packed in four bits each with the lower
> > + * 8b unused:
> > + */
> > + chipid = adreno_gpu->chip_id & 0xffff0000;
> > + chipid |= (adreno_gpu->chip_id << 4) & 0xf000; /* minor */
> > + chipid |= (adreno_gpu->chip_id << 8) & 0x0f00; /* patchid */
>
> I'd beg for explicit FIELD_GET and FIELD_PREP here.
>
> >
> > gmu_write(gmu, REG_A6XX_GMU_HFI_SFR_ADDR, chipid);
> >
> > diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> > index 77b23c004b94..ed075729ca09 100644
> > --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> > +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> > @@ -2344,10 +2344,13 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev)
> > /*
> > * We need to know the platform type before calling into adreno_gpu_init
> > * so that the hw_apriv flag can be correctly set. Snoop into the info
> > - * and grab the revision number
> > + * and grab the revision number.
> > + *
> > + * Note that we wouldn't have been able to get this far if there is not
> > + * a device table entry for this chip_id
>
> Having seen this note twice, shouldn't we explicitly pass adreno_info to
> our aNxx_gpu_init() functions and then further to adreno_gpu_init()?
>
> > */
> > - info = adreno_info(config->rev);
> > - if (!info)
> > + info = adreno_find_info(config->chip_id);
> > + if (WARN_ON(!info))
> > return ERR_PTR(-EINVAL);
> >
> > adreno_gpu->base.hw_apriv = !!(info->quirks & ADRENO_QUIRK_HAS_HW_APRIV);
> > diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c
> > index fd2e183bce60..4a718ff33635 100644
> > --- a/drivers/gpu/drm/msm/adreno/adreno_device.c
> > +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c
> > @@ -22,7 +22,7 @@ module_param_named(allow_vram_carveout, allow_vram_carveout, bool, 0600);
> >
> > static const struct adreno_info gpulist[] = {
> > {
> > - .rev = ADRENO_REV(2, 0, 0, 0),
> > + .chip_ids = ADRENO_CHIP_IDS(0x02000000),
>
> This begs to use bit masks, but see below
>
> > .family = ADRENO_2XX_GEN1,
> > .revn = 200,
> > .fw = {
>
> [skipped]
>
> > @@ -77,7 +77,11 @@ static const struct adreno_info gpulist[] = {
> > .inactive_period = DRM_MSM_INACTIVE_PERIOD,
> > .init = a3xx_gpu_init,
> > }, {
> > - .rev = ADRENO_REV(3, 2, ANY_ID, ANY_ID),
> > + .chip_ids = ADRENO_CHIP_IDS(
> > + 0x03020000,
> > + 0x03020001,
> > + 0x03020002
>
> definitely a bitmask would help
>
> > + ),
> > .family = ADRENO_3XX,
> > .revn = 320,
> > .fw = {
>
> [skipped the rest]
>
> > @@ -494,31 +502,16 @@ MODULE_FIRMWARE("qcom/a630_sqe.fw");
> > MODULE_FIRMWARE("qcom/a630_gmu.bin");
> > MODULE_FIRMWARE("qcom/a630_zap.mbn");
> >
> > -static inline bool _rev_match(uint8_t entry, uint8_t id)
> > -{
> > - return (entry == ANY_ID) || (entry == id);
> > -}
> > -
> > -bool adreno_cmp_rev(struct adreno_rev rev1, struct adreno_rev rev2)
> > -{
> > -
> > - return _rev_match(rev1.core, rev2.core) &&
> > - _rev_match(rev1.major, rev2.major) &&
> > - _rev_match(rev1.minor, rev2.minor) &&
> > - _rev_match(rev1.patchid, rev2.patchid);
> > -}
> > -
> > -const struct adreno_info *adreno_info(struct adreno_rev rev)
> > +const struct adreno_info *adreno_find_info(uint32_t chip_id)
> > {
> > - int i;
> > -
> > /* identify gpu: */
> > - for (i = 0; i < ARRAY_SIZE(gpulist); i++) {
> > + for (int i = 0; i < ARRAY_SIZE(gpulist); i++) {
> > const struct adreno_info *info = &gpulist[i];
> > if (info->machine && !of_machine_is_compatible(info->machine))
> > continue;
> > - if (adreno_cmp_rev(info->rev, rev))
> > - return info;
> > + for (int j = 0; info->chip_ids[j]; j++)
> > + if (info->chip_ids[j] == chip_id)
> > + return info;
> > }
> >
> > return NULL;
> > @@ -598,12 +591,11 @@ struct msm_gpu *adreno_load_gpu(struct drm_device *dev)
> > return NULL;
> > }
> >
> > -static int find_chipid(struct device *dev, struct adreno_rev *rev)
> > +static int find_chipid(struct device *dev, uint32_t *chipid)
> > {
> > struct device_node *node = dev->of_node;
> > const char *compat;
> > int ret;
> > - u32 chipid;
> >
> > /* first search the compat strings for qcom,adreno-XYZ.W: */
> > ret = of_property_read_string_index(node, "compatible", 0, &compat);
> > @@ -612,32 +604,34 @@ static int find_chipid(struct device *dev, struct adreno_rev *rev)
> >
> > if (sscanf(compat, "qcom,adreno-%u.%u", &r, &patch) == 2 ||
> > sscanf(compat, "amd,imageon-%u.%u", &r, &patch) == 2) {
> > - rev->core = r / 100;
> > + uint32_t core, major, minor;
> > +
> > + core = r / 100;
> > r %= 100;
> > - rev->major = r / 10;
> > + major = r / 10;
> > r %= 10;
> > - rev->minor = r;
> > - rev->patchid = patch;
> > + minor = r;
> > +
> > + *chipid = (core << 24) |
> > + (major << 16) |
> > + (minor << 8) |
> > + patch;
>
> This starts to look realy crazy. I'd repeat my suggestion of moving
> towards of_device match data. This would result in some duplication,
> we'd have to explicitly list all supported compatibles in the
> of_match_table. But then we can drop all the CHIPID lists from device
> table and/or manual parsing of the chipid from the compat field.
>
> This way we can have per-SoC overrides, etc.
>
> >
> > return 0;
> > }
> > +
> > + if (sscanf(compat, "qcom,adreno-%08x", chipid) == 1)
> > + return 0;
> > }
> >
> > /* and if that fails, fall back to legacy "qcom,chipid" property: */
> > - ret = of_property_read_u32(node, "qcom,chipid", &chipid);
> > + ret = of_property_read_u32(node, "qcom,chipid", chipid);
> > if (ret) {
> > DRM_DEV_ERROR(dev, "could not parse qcom,chipid: %d\n", ret);
> > return ret;
> > }
> >
> > - rev->core = (chipid >> 24) & 0xff;
> > - rev->major = (chipid >> 16) & 0xff;
> > - rev->minor = (chipid >> 8) & 0xff;
> > - rev->patchid = (chipid & 0xff);
> > -
> > dev_warn(dev, "Using legacy qcom,chipid binding!\n");
> > - dev_warn(dev, "Use compatible qcom,adreno-%u%u%u.%u instead.\n",
> > - rev->core, rev->major, rev->minor, rev->patchid);
> >
> > return 0;
> > }
> > @@ -651,22 +645,22 @@ static int adreno_bind(struct device *dev, struct device *master, void *data)
> > struct msm_gpu *gpu;
> > int ret;
> >
> > - ret = find_chipid(dev, &config.rev);
> > + ret = find_chipid(dev, &config.chip_id);
> > if (ret)
> > return ret;
> >
> > dev->platform_data = &config;
> > priv->gpu_pdev = to_platform_device(dev);
> >
> > - info = adreno_info(config.rev);
> > + info = adreno_find_info(config.chip_id);
> >
> > if (!info) {
> > dev_warn(drm->dev, "Unknown GPU revision: %"ADRENO_CHIPID_FMT"\n",
> > - ADRENO_CHIPID_ARGS(config.rev));
> > + ADRENO_CHIPID_ARGS(config.chip_id));
> > return -ENXIO;
> > }
> >
> > - DBG("Found GPU: %"ADRENO_CHIPID_FMT, ADRENO_CHIPID_ARGS(config.rev));
> > + DBG("Found GPU: %"ADRENO_CHIPID_FMT, ADRENO_CHIPID_ARGS(config.chip_id));
> >
> > priv->is_a2xx = info->family < ADRENO_3XX;
> > priv->has_cached_coherent =
> > diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
> > index 1a982a926f21..1274609a74b1 100644
> > --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c
> > +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
> > @@ -326,10 +326,7 @@ int adreno_get_param(struct msm_gpu *gpu, struct msm_file_private *ctx,
> > *value = !adreno_is_a650_family(adreno_gpu) ? 0x100000 : 0;
> > return 0;
> > case MSM_PARAM_CHIP_ID:
> > - *value = (uint64_t)adreno_gpu->rev.patchid |
> > - ((uint64_t)adreno_gpu->rev.minor << 8) |
> > - ((uint64_t)adreno_gpu->rev.major << 16) |
> > - ((uint64_t)adreno_gpu->rev.core << 24);
> > + *value = adreno_gpu->chip_id;
> > if (!adreno_gpu->info->revn)
> > *value |= ((uint64_t) adreno_gpu->speedbin) << 32;
> > return 0;
> > @@ -849,7 +846,7 @@ void adreno_show(struct msm_gpu *gpu, struct msm_gpu_state *state,
> >
> > drm_printf(p, "revision: %u (%"ADRENO_CHIPID_FMT")\n",
> > adreno_gpu->info->revn,
> > - ADRENO_CHIPID_ARGS(adreno_gpu->rev));
> > + ADRENO_CHIPID_ARGS(adreno_gpu->chip_id));
> > /*
> > * If this is state collected due to iova fault, so fault related info
> > *
> > @@ -922,7 +919,7 @@ void adreno_dump_info(struct msm_gpu *gpu)
> >
> > printk("revision: %u (%"ADRENO_CHIPID_FMT")\n",
> > adreno_gpu->info->revn,
> > - ADRENO_CHIPID_ARGS(adreno_gpu->rev));
> > + ADRENO_CHIPID_ARGS(adreno_gpu->chip_id));
> >
> > for (i = 0; i < gpu->nr_rings; i++) {
> > struct msm_ringbuffer *ring = gpu->rb[i];
> > @@ -1072,14 +1069,13 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev,
> > struct adreno_platform_config *config = dev->platform_data;
> > struct msm_gpu_config adreno_gpu_config = { 0 };
> > struct msm_gpu *gpu = &adreno_gpu->base;
> > - struct adreno_rev *rev = &config->rev;
> > const char *gpu_name;
> > u32 speedbin;
> > int ret;
> >
> > adreno_gpu->funcs = funcs;
> > - adreno_gpu->info = adreno_info(config->rev);
> > - adreno_gpu->rev = *rev;
> > + adreno_gpu->info = adreno_find_info(config->chip_id);
> > + adreno_gpu->chip_id = config->chip_id;
> >
> > /* Only handle the core clock when GMU is not in use (or is absent). */
> > if (adreno_has_gmu_wrapper(adreno_gpu) ||
> > @@ -1104,7 +1100,7 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev,
> > adreno_gpu->speedbin = (uint16_t) (0xffff & speedbin);
> >
> > gpu_name = devm_kasprintf(dev, GFP_KERNEL, "%"ADRENO_CHIPID_FMT,
> > - ADRENO_CHIPID_ARGS(config->rev));
> > + ADRENO_CHIPID_ARGS(config->chip_id));
> > if (!gpu_name)
> > return -ENOMEM;
> >
> > diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> > index 73e7155f164c..18f53c7ab589 100644
> > --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> > +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> > @@ -54,23 +54,15 @@ enum adreno_family {
> > #define ADRENO_QUIRK_HAS_HW_APRIV BIT(3)
> > #define ADRENO_QUIRK_HAS_CACHED_COHERENT BIT(4)
> >
> > -struct adreno_rev {
> > - uint8_t core;
> > - uint8_t major;
> > - uint8_t minor;
> > - uint8_t patchid;
> > -};
> > -
> > -#define ANY_ID 0xff
> > -
> > -#define ADRENO_REV(core, major, minor, patchid) \
> > - ((struct adreno_rev){ core, major, minor, patchid })
> > -
> > /* Helper for formating the chip_id in the way that userspace tools like
> > * crashdec expect.
> > */
> > #define ADRENO_CHIPID_FMT "u.%u.%u.%u"
> > -#define ADRENO_CHIPID_ARGS(_r) (_r).core, (_r).major, (_r).minor, (_r).patchid
> > +#define ADRENO_CHIPID_ARGS(_c) \
> > + (((_c) >> 24) & 0xff), \
> > + (((_c) >> 16) & 0xff), \
> > + (((_c) >> 8) & 0xff), \
> > + ((_c) & 0xff)
>
> So, we still have some meaning for chipid?
Only enough to do the inverse of what userspace does when parsing
devcoredump to construct chip-id. Basically it is just a different
way to represent a 32b #
BR,
-R
> >
> > struct adreno_gpu_funcs {
> > struct msm_gpu_funcs base;
> > @@ -87,7 +79,12 @@ extern const struct adreno_reglist a660_hwcg[], a690_hwcg[];
> >
> > struct adreno_info {
> > const char *machine;
> > - struct adreno_rev rev;
> > + /**
> > + * @chipids: Table of matching chip-ids
> > + *
> > + * Terminated with 0 sentinal
> > + */
> > + uint32_t *chip_ids;
> > enum adreno_family family;
> > uint32_t revn;
> > const char *fw[ADRENO_FW_MAX];
> > @@ -107,6 +104,8 @@ struct adreno_info {
> > uint32_t *speedbins;
> > };
> >
> > +#define ADRENO_CHIP_IDS(tbl...) (uint32_t[]) { tbl, 0 }
> > +
> > /*
> > * Helper to build a speedbin table, ie. the table:
> > * fuse | speedbin
> > @@ -125,12 +124,12 @@ struct adreno_info {
> > */
> > #define ADRENO_SPEEDBINS(tbl...) (uint32_t[]) { tbl, UINT_MAX }
> >
> > -const struct adreno_info *adreno_info(struct adreno_rev rev);
> > +const struct adreno_info *adreno_find_info(uint32_t chip_id);
> >
> > struct adreno_gpu {
> > struct msm_gpu base;
> > - struct adreno_rev rev;
> > const struct adreno_info *info;
> > + uint32_t chip_id;
> > uint16_t speedbin;
> > const struct adreno_gpu_funcs *funcs;
> >
> > @@ -179,7 +178,7 @@ struct adreno_ocmem {
> >
> > /* platform config data (ie. from DT, or pdata) */
> > struct adreno_platform_config {
> > - struct adreno_rev rev;
> > + uint32_t chip_id;
> > };
> >
> > #define ADRENO_IDLE_TIMEOUT msecs_to_jiffies(1000)
> > @@ -196,7 +195,15 @@ struct adreno_platform_config {
> > __ret; \
> > })
> >
> > -bool adreno_cmp_rev(struct adreno_rev rev1, struct adreno_rev rev2);
> > +static inline uint8_t adreno_patchid(const struct adreno_gpu *gpu)
> > +{
> > + /* It is probably ok to assume legacy "adreno_rev" format
> > + * for all a6xx devices, but probably best to limit this
> > + * to older things.
> > + */
> > + WARN_ON_ONCE(gpu->info->family >= ADRENO_6XX_GEN1);
> > + return gpu->chip_id & 0xff;
> > +}
> >
> > static inline bool adreno_is_revn(const struct adreno_gpu *gpu, uint32_t revn)
> > {
> > @@ -252,7 +259,7 @@ static inline bool adreno_is_a330(const struct adreno_gpu *gpu)
> >
> > static inline bool adreno_is_a330v2(const struct adreno_gpu *gpu)
> > {
> > - return adreno_is_a330(gpu) && (gpu->rev.patchid > 0);
> > + return adreno_is_a330(gpu) && (adreno_patchid(gpu) > 0);
> > }
> >
> > static inline int adreno_is_a405(const struct adreno_gpu *gpu)
> > @@ -342,8 +349,7 @@ static inline int adreno_is_a650(const struct adreno_gpu *gpu)
> >
> > static inline int adreno_is_7c3(const struct adreno_gpu *gpu)
> > {
> > - /* The order of args is important here to handle ANY_ID correctly */
> > - return adreno_cmp_rev(ADRENO_REV(6, 3, 5, ANY_ID), gpu->rev);
> > + return gpu->info->chip_ids[0] == 0x06030500;
>
> Ugh. The thing that bugs me isn't even the manual comparison of
> chip_ids[0], but the fact that these two platforms stand aside. I think
> at the end we should have a single mechanism for checking GPU's SKUs.
>
> Or maybe we should get rid of that completely.
>
> If we get rid of a single gpulist table and move individual GPU info
> definitions to aNxx_gpu.c, we can subclass a generic info structure with
> generation-specific data, for example generation-specific quirks,
> pointers to hcwg or VBIF registers, etc. And then instead of having
> adreno_is_foo all over the code we can migrate most of these checks to
> data in the gpu info data.
>
> > }
> >
> > static inline int adreno_is_a660(const struct adreno_gpu *gpu)
> > @@ -358,8 +364,7 @@ static inline int adreno_is_a680(const struct adreno_gpu *gpu)
> >
> > static inline int adreno_is_a690(const struct adreno_gpu *gpu)
> > {
> > - /* The order of args is important here to handle ANY_ID correctly */
> > - return adreno_cmp_rev(ADRENO_REV(6, 9, 0, ANY_ID), gpu->rev);
> > + return gpu->info->chip_ids[0] == 0x06090000;
> > };
> > /* check for a615, a616, a618, a619 or any a630 derivatives */
> > static inline int adreno_is_a630_family(const struct adreno_gpu *gpu)
>
> --
> With best wishes
> Dmitry
>
^ permalink raw reply [flat|nested] 73+ messages in thread
* Re: [Freedreno] [PATCH 12/12] drm/msm/adreno: Switch to chip-id for identifying GPU
2023-07-26 21:37 ` Rob Clark
@ 2023-07-26 21:38 ` Dmitry Baryshkov
2023-07-26 21:44 ` Rob Clark
0 siblings, 1 reply; 73+ messages in thread
From: Dmitry Baryshkov @ 2023-07-26 21:38 UTC (permalink / raw)
To: Rob Clark; +Cc: Konrad Dybcio, linux-arm-msm, Rob Clark, freedreno, dri-devel
On 27/07/2023 00:37, Rob Clark wrote:
> On Thu, Jul 6, 2023 at 8:45 PM Dmitry Baryshkov
> <dmitry.baryshkov@linaro.org> wrote:
>>
>> On 07/07/2023 00:10, Rob Clark wrote:
>>> From: Rob Clark <robdclark@chromium.org>
>>>
>>> Since the revision becomes an opaque identifier with future GPUs, move
>>> away from treating different ranges of bits as having a given meaning.
>>> This means that we need to explicitly list different patch revisions in
>>> the device table.
>>>
>>> Signed-off-by: Rob Clark <robdclark@chromium.org>
>>> ---
>>> drivers/gpu/drm/msm/adreno/a4xx_gpu.c | 2 +-
>>> drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 11 +-
>>> drivers/gpu/drm/msm/adreno/a5xx_power.c | 2 +-
>>> drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 13 ++-
>>> drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 9 +-
>>> drivers/gpu/drm/msm/adreno/adreno_device.c | 128 ++++++++++-----------
>>> drivers/gpu/drm/msm/adreno/adreno_gpu.c | 16 +--
>>> drivers/gpu/drm/msm/adreno/adreno_gpu.h | 51 ++++----
>>> 8 files changed, 122 insertions(+), 110 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/msm/adreno/a4xx_gpu.c b/drivers/gpu/drm/msm/adreno/a4xx_gpu.c
>>> index 715436cb3996..8b4cdf95f445 100644
>>> --- a/drivers/gpu/drm/msm/adreno/a4xx_gpu.c
>>> +++ b/drivers/gpu/drm/msm/adreno/a4xx_gpu.c
>>> @@ -145,7 +145,7 @@ static void a4xx_enable_hwcg(struct msm_gpu *gpu)
>>> gpu_write(gpu, REG_A4XX_RBBM_CLOCK_DELAY_HLSQ, 0x00220000);
>>> /* Early A430's have a timing issue with SP/TP power collapse;
>>> disabling HW clock gating prevents it. */
>>> - if (adreno_is_a430(adreno_gpu) && adreno_gpu->rev.patchid < 2)
>>> + if (adreno_is_a430(adreno_gpu) && adreno_patchid(adreno_gpu) < 2)
>>> gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL, 0);
>>> else
>>> gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL, 0xAAAAAAAA);
>>> diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
>>> index f0803e94ebe5..70d2b5342cd9 100644
>>> --- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
>>> +++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
>>> @@ -1744,6 +1744,7 @@ struct msm_gpu *a5xx_gpu_init(struct drm_device *dev)
>>> struct msm_drm_private *priv = dev->dev_private;
>>> struct platform_device *pdev = priv->gpu_pdev;
>>> struct adreno_platform_config *config = pdev->dev.platform_data;
>>> + const struct adreno_info *info;
>>> struct a5xx_gpu *a5xx_gpu = NULL;
>>> struct adreno_gpu *adreno_gpu;
>>> struct msm_gpu *gpu;
>>> @@ -1770,7 +1771,15 @@ struct msm_gpu *a5xx_gpu_init(struct drm_device *dev)
>>>
>>> nr_rings = 4;
>>>
>>> - if (adreno_cmp_rev(ADRENO_REV(5, 1, 0, ANY_ID), config->rev))
>>> + /*
>>> + * Note that we wouldn't have been able to get this far if there is not
>>> + * a device table entry for this chip_id
>>> + */
>>> + info = adreno_find_info(config->chip_id);
>>> + if (WARN_ON(!info))
>>> + return ERR_PTR(-EINVAL);
>>> +
>>> + if (info->revn == 510)
>>> nr_rings = 1;
>>>
>>> ret = adreno_gpu_init(dev, pdev, adreno_gpu, &funcs, nr_rings);
>>> diff --git a/drivers/gpu/drm/msm/adreno/a5xx_power.c b/drivers/gpu/drm/msm/adreno/a5xx_power.c
>>> index 0e63a1429189..7705f8010484 100644
>>> --- a/drivers/gpu/drm/msm/adreno/a5xx_power.c
>>> +++ b/drivers/gpu/drm/msm/adreno/a5xx_power.c
>>> @@ -179,7 +179,7 @@ static void a540_lm_setup(struct msm_gpu *gpu)
>>>
>>> /* The battery current limiter isn't enabled for A540 */
>>> config = AGC_LM_CONFIG_BCL_DISABLED;
>>> - config |= adreno_gpu->rev.patchid << AGC_LM_CONFIG_GPU_VERSION_SHIFT;
>>> + config |= adreno_patchid(adreno_gpu) << AGC_LM_CONFIG_GPU_VERSION_SHIFT;
>>>
>>> /* For now disable GPMU side throttling */
>>> config |= AGC_LM_CONFIG_THROTTLE_DISABLE;
>>> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
>>> index f1bb20574018..a9ba547a120c 100644
>>> --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
>>> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
>>> @@ -790,10 +790,15 @@ static int a6xx_gmu_fw_start(struct a6xx_gmu *gmu, unsigned int state)
>>> gmu_write(gmu, REG_A6XX_GMU_AHB_FENCE_RANGE_0,
>>> (1 << 31) | (0xa << 18) | (0xa0));
>>>
>>> - chipid = adreno_gpu->rev.core << 24;
>>> - chipid |= adreno_gpu->rev.major << 16;
>>> - chipid |= adreno_gpu->rev.minor << 12;
>>> - chipid |= adreno_gpu->rev.patchid << 8;
>>> + /* Note that the GMU has a slightly different layout for
>>> + * chip_id, for whatever reason, so a bit of massaging
>>> + * is needed. The upper 16b are the same, but minor and
>>> + * patchid are packed in four bits each with the lower
>>> + * 8b unused:
>>> + */
>>> + chipid = adreno_gpu->chip_id & 0xffff0000;
>>> + chipid |= (adreno_gpu->chip_id << 4) & 0xf000; /* minor */
>>> + chipid |= (adreno_gpu->chip_id << 8) & 0x0f00; /* patchid */
>>
>> I'd beg for explicit FIELD_GET and FIELD_PREP here.
>>
>>>
>>> gmu_write(gmu, REG_A6XX_GMU_HFI_SFR_ADDR, chipid);
>>>
>>> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
>>> index 77b23c004b94..ed075729ca09 100644
>>> --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
>>> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
>>> @@ -2344,10 +2344,13 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev)
>>> /*
>>> * We need to know the platform type before calling into adreno_gpu_init
>>> * so that the hw_apriv flag can be correctly set. Snoop into the info
>>> - * and grab the revision number
>>> + * and grab the revision number.
>>> + *
>>> + * Note that we wouldn't have been able to get this far if there is not
>>> + * a device table entry for this chip_id
>>
>> Having seen this note twice, shouldn't we explicitly pass adreno_info to
>> our aNxx_gpu_init() functions and then further to adreno_gpu_init()?
>>
>>> */
>>> - info = adreno_info(config->rev);
>>> - if (!info)
>>> + info = adreno_find_info(config->chip_id);
>>> + if (WARN_ON(!info))
>>> return ERR_PTR(-EINVAL);
>>>
>>> adreno_gpu->base.hw_apriv = !!(info->quirks & ADRENO_QUIRK_HAS_HW_APRIV);
>>> diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c
>>> index fd2e183bce60..4a718ff33635 100644
>>> --- a/drivers/gpu/drm/msm/adreno/adreno_device.c
>>> +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c
>>> @@ -22,7 +22,7 @@ module_param_named(allow_vram_carveout, allow_vram_carveout, bool, 0600);
>>>
>>> static const struct adreno_info gpulist[] = {
>>> {
>>> - .rev = ADRENO_REV(2, 0, 0, 0),
>>> + .chip_ids = ADRENO_CHIP_IDS(0x02000000),
>>
>> This begs to use bit masks, but see below
>>
>>> .family = ADRENO_2XX_GEN1,
>>> .revn = 200,
>>> .fw = {
>>
>> [skipped]
>>
>>> @@ -77,7 +77,11 @@ static const struct adreno_info gpulist[] = {
>>> .inactive_period = DRM_MSM_INACTIVE_PERIOD,
>>> .init = a3xx_gpu_init,
>>> }, {
>>> - .rev = ADRENO_REV(3, 2, ANY_ID, ANY_ID),
>>> + .chip_ids = ADRENO_CHIP_IDS(
>>> + 0x03020000,
>>> + 0x03020001,
>>> + 0x03020002
>>
>> definitely a bitmask would help
>>
>>> + ),
>>> .family = ADRENO_3XX,
>>> .revn = 320,
>>> .fw = {
>>
>> [skipped the rest]
>>
>>> @@ -494,31 +502,16 @@ MODULE_FIRMWARE("qcom/a630_sqe.fw");
>>> MODULE_FIRMWARE("qcom/a630_gmu.bin");
>>> MODULE_FIRMWARE("qcom/a630_zap.mbn");
>>>
>>> -static inline bool _rev_match(uint8_t entry, uint8_t id)
>>> -{
>>> - return (entry == ANY_ID) || (entry == id);
>>> -}
>>> -
>>> -bool adreno_cmp_rev(struct adreno_rev rev1, struct adreno_rev rev2)
>>> -{
>>> -
>>> - return _rev_match(rev1.core, rev2.core) &&
>>> - _rev_match(rev1.major, rev2.major) &&
>>> - _rev_match(rev1.minor, rev2.minor) &&
>>> - _rev_match(rev1.patchid, rev2.patchid);
>>> -}
>>> -
>>> -const struct adreno_info *adreno_info(struct adreno_rev rev)
>>> +const struct adreno_info *adreno_find_info(uint32_t chip_id)
>>> {
>>> - int i;
>>> -
>>> /* identify gpu: */
>>> - for (i = 0; i < ARRAY_SIZE(gpulist); i++) {
>>> + for (int i = 0; i < ARRAY_SIZE(gpulist); i++) {
>>> const struct adreno_info *info = &gpulist[i];
>>> if (info->machine && !of_machine_is_compatible(info->machine))
>>> continue;
>>> - if (adreno_cmp_rev(info->rev, rev))
>>> - return info;
>>> + for (int j = 0; info->chip_ids[j]; j++)
>>> + if (info->chip_ids[j] == chip_id)
>>> + return info;
>>> }
>>>
>>> return NULL;
>>> @@ -598,12 +591,11 @@ struct msm_gpu *adreno_load_gpu(struct drm_device *dev)
>>> return NULL;
>>> }
>>>
>>> -static int find_chipid(struct device *dev, struct adreno_rev *rev)
>>> +static int find_chipid(struct device *dev, uint32_t *chipid)
>>> {
>>> struct device_node *node = dev->of_node;
>>> const char *compat;
>>> int ret;
>>> - u32 chipid;
>>>
>>> /* first search the compat strings for qcom,adreno-XYZ.W: */
>>> ret = of_property_read_string_index(node, "compatible", 0, &compat);
>>> @@ -612,32 +604,34 @@ static int find_chipid(struct device *dev, struct adreno_rev *rev)
>>>
>>> if (sscanf(compat, "qcom,adreno-%u.%u", &r, &patch) == 2 ||
>>> sscanf(compat, "amd,imageon-%u.%u", &r, &patch) == 2) {
>>> - rev->core = r / 100;
>>> + uint32_t core, major, minor;
>>> +
>>> + core = r / 100;
>>> r %= 100;
>>> - rev->major = r / 10;
>>> + major = r / 10;
>>> r %= 10;
>>> - rev->minor = r;
>>> - rev->patchid = patch;
>>> + minor = r;
>>> +
>>> + *chipid = (core << 24) |
>>> + (major << 16) |
>>> + (minor << 8) |
>>> + patch;
>>
>> This starts to look realy crazy. I'd repeat my suggestion of moving
>> towards of_device match data. This would result in some duplication,
>> we'd have to explicitly list all supported compatibles in the
>> of_match_table. But then we can drop all the CHIPID lists from device
>> table and/or manual parsing of the chipid from the compat field.
>>
>> This way we can have per-SoC overrides, etc.
>>
>>>
>>> return 0;
>>> }
>>> +
>>> + if (sscanf(compat, "qcom,adreno-%08x", chipid) == 1)
>>> + return 0;
>>> }
>>>
>>> /* and if that fails, fall back to legacy "qcom,chipid" property: */
>>> - ret = of_property_read_u32(node, "qcom,chipid", &chipid);
>>> + ret = of_property_read_u32(node, "qcom,chipid", chipid);
>>> if (ret) {
>>> DRM_DEV_ERROR(dev, "could not parse qcom,chipid: %d\n", ret);
>>> return ret;
>>> }
>>>
>>> - rev->core = (chipid >> 24) & 0xff;
>>> - rev->major = (chipid >> 16) & 0xff;
>>> - rev->minor = (chipid >> 8) & 0xff;
>>> - rev->patchid = (chipid & 0xff);
>>> -
>>> dev_warn(dev, "Using legacy qcom,chipid binding!\n");
>>> - dev_warn(dev, "Use compatible qcom,adreno-%u%u%u.%u instead.\n",
>>> - rev->core, rev->major, rev->minor, rev->patchid);
>>>
>>> return 0;
>>> }
>>> @@ -651,22 +645,22 @@ static int adreno_bind(struct device *dev, struct device *master, void *data)
>>> struct msm_gpu *gpu;
>>> int ret;
>>>
>>> - ret = find_chipid(dev, &config.rev);
>>> + ret = find_chipid(dev, &config.chip_id);
>>> if (ret)
>>> return ret;
>>>
>>> dev->platform_data = &config;
>>> priv->gpu_pdev = to_platform_device(dev);
>>>
>>> - info = adreno_info(config.rev);
>>> + info = adreno_find_info(config.chip_id);
>>>
>>> if (!info) {
>>> dev_warn(drm->dev, "Unknown GPU revision: %"ADRENO_CHIPID_FMT"\n",
>>> - ADRENO_CHIPID_ARGS(config.rev));
>>> + ADRENO_CHIPID_ARGS(config.chip_id));
>>> return -ENXIO;
>>> }
>>>
>>> - DBG("Found GPU: %"ADRENO_CHIPID_FMT, ADRENO_CHIPID_ARGS(config.rev));
>>> + DBG("Found GPU: %"ADRENO_CHIPID_FMT, ADRENO_CHIPID_ARGS(config.chip_id));
>>>
>>> priv->is_a2xx = info->family < ADRENO_3XX;
>>> priv->has_cached_coherent =
>>> diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
>>> index 1a982a926f21..1274609a74b1 100644
>>> --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c
>>> +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
>>> @@ -326,10 +326,7 @@ int adreno_get_param(struct msm_gpu *gpu, struct msm_file_private *ctx,
>>> *value = !adreno_is_a650_family(adreno_gpu) ? 0x100000 : 0;
>>> return 0;
>>> case MSM_PARAM_CHIP_ID:
>>> - *value = (uint64_t)adreno_gpu->rev.patchid |
>>> - ((uint64_t)adreno_gpu->rev.minor << 8) |
>>> - ((uint64_t)adreno_gpu->rev.major << 16) |
>>> - ((uint64_t)adreno_gpu->rev.core << 24);
>>> + *value = adreno_gpu->chip_id;
>>> if (!adreno_gpu->info->revn)
>>> *value |= ((uint64_t) adreno_gpu->speedbin) << 32;
>>> return 0;
>>> @@ -849,7 +846,7 @@ void adreno_show(struct msm_gpu *gpu, struct msm_gpu_state *state,
>>>
>>> drm_printf(p, "revision: %u (%"ADRENO_CHIPID_FMT")\n",
>>> adreno_gpu->info->revn,
>>> - ADRENO_CHIPID_ARGS(adreno_gpu->rev));
>>> + ADRENO_CHIPID_ARGS(adreno_gpu->chip_id));
>>> /*
>>> * If this is state collected due to iova fault, so fault related info
>>> *
>>> @@ -922,7 +919,7 @@ void adreno_dump_info(struct msm_gpu *gpu)
>>>
>>> printk("revision: %u (%"ADRENO_CHIPID_FMT")\n",
>>> adreno_gpu->info->revn,
>>> - ADRENO_CHIPID_ARGS(adreno_gpu->rev));
>>> + ADRENO_CHIPID_ARGS(adreno_gpu->chip_id));
>>>
>>> for (i = 0; i < gpu->nr_rings; i++) {
>>> struct msm_ringbuffer *ring = gpu->rb[i];
>>> @@ -1072,14 +1069,13 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev,
>>> struct adreno_platform_config *config = dev->platform_data;
>>> struct msm_gpu_config adreno_gpu_config = { 0 };
>>> struct msm_gpu *gpu = &adreno_gpu->base;
>>> - struct adreno_rev *rev = &config->rev;
>>> const char *gpu_name;
>>> u32 speedbin;
>>> int ret;
>>>
>>> adreno_gpu->funcs = funcs;
>>> - adreno_gpu->info = adreno_info(config->rev);
>>> - adreno_gpu->rev = *rev;
>>> + adreno_gpu->info = adreno_find_info(config->chip_id);
>>> + adreno_gpu->chip_id = config->chip_id;
>>>
>>> /* Only handle the core clock when GMU is not in use (or is absent). */
>>> if (adreno_has_gmu_wrapper(adreno_gpu) ||
>>> @@ -1104,7 +1100,7 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev,
>>> adreno_gpu->speedbin = (uint16_t) (0xffff & speedbin);
>>>
>>> gpu_name = devm_kasprintf(dev, GFP_KERNEL, "%"ADRENO_CHIPID_FMT,
>>> - ADRENO_CHIPID_ARGS(config->rev));
>>> + ADRENO_CHIPID_ARGS(config->chip_id));
>>> if (!gpu_name)
>>> return -ENOMEM;
>>>
>>> diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
>>> index 73e7155f164c..18f53c7ab589 100644
>>> --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
>>> +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
>>> @@ -54,23 +54,15 @@ enum adreno_family {
>>> #define ADRENO_QUIRK_HAS_HW_APRIV BIT(3)
>>> #define ADRENO_QUIRK_HAS_CACHED_COHERENT BIT(4)
>>>
>>> -struct adreno_rev {
>>> - uint8_t core;
>>> - uint8_t major;
>>> - uint8_t minor;
>>> - uint8_t patchid;
>>> -};
>>> -
>>> -#define ANY_ID 0xff
>>> -
>>> -#define ADRENO_REV(core, major, minor, patchid) \
>>> - ((struct adreno_rev){ core, major, minor, patchid })
>>> -
>>> /* Helper for formating the chip_id in the way that userspace tools like
>>> * crashdec expect.
>>> */
>>> #define ADRENO_CHIPID_FMT "u.%u.%u.%u"
>>> -#define ADRENO_CHIPID_ARGS(_r) (_r).core, (_r).major, (_r).minor, (_r).patchid
>>> +#define ADRENO_CHIPID_ARGS(_c) \
>>> + (((_c) >> 24) & 0xff), \
>>> + (((_c) >> 16) & 0xff), \
>>> + (((_c) >> 8) & 0xff), \
>>> + ((_c) & 0xff)
>>
>> So, we still have some meaning for chipid?
>
> Only enough to do the inverse of what userspace does when parsing
> devcoredump to construct chip-id. Basically it is just a different
> way to represent a 32b #
What about passing it in the direct form? The macro adds assumptions.
>
> BR,
> -R
>
>>>
>>> struct adreno_gpu_funcs {
>>> struct msm_gpu_funcs base;
>>> @@ -87,7 +79,12 @@ extern const struct adreno_reglist a660_hwcg[], a690_hwcg[];
>>>
>>> struct adreno_info {
>>> const char *machine;
>>> - struct adreno_rev rev;
>>> + /**
>>> + * @chipids: Table of matching chip-ids
>>> + *
>>> + * Terminated with 0 sentinal
>>> + */
>>> + uint32_t *chip_ids;
>>> enum adreno_family family;
>>> uint32_t revn;
>>> const char *fw[ADRENO_FW_MAX];
>>> @@ -107,6 +104,8 @@ struct adreno_info {
>>> uint32_t *speedbins;
>>> };
>>>
>>> +#define ADRENO_CHIP_IDS(tbl...) (uint32_t[]) { tbl, 0 }
>>> +
>>> /*
>>> * Helper to build a speedbin table, ie. the table:
>>> * fuse | speedbin
>>> @@ -125,12 +124,12 @@ struct adreno_info {
>>> */
>>> #define ADRENO_SPEEDBINS(tbl...) (uint32_t[]) { tbl, UINT_MAX }
>>>
>>> -const struct adreno_info *adreno_info(struct adreno_rev rev);
>>> +const struct adreno_info *adreno_find_info(uint32_t chip_id);
>>>
>>> struct adreno_gpu {
>>> struct msm_gpu base;
>>> - struct adreno_rev rev;
>>> const struct adreno_info *info;
>>> + uint32_t chip_id;
>>> uint16_t speedbin;
>>> const struct adreno_gpu_funcs *funcs;
>>>
>>> @@ -179,7 +178,7 @@ struct adreno_ocmem {
>>>
>>> /* platform config data (ie. from DT, or pdata) */
>>> struct adreno_platform_config {
>>> - struct adreno_rev rev;
>>> + uint32_t chip_id;
>>> };
>>>
>>> #define ADRENO_IDLE_TIMEOUT msecs_to_jiffies(1000)
>>> @@ -196,7 +195,15 @@ struct adreno_platform_config {
>>> __ret; \
>>> })
>>>
>>> -bool adreno_cmp_rev(struct adreno_rev rev1, struct adreno_rev rev2);
>>> +static inline uint8_t adreno_patchid(const struct adreno_gpu *gpu)
>>> +{
>>> + /* It is probably ok to assume legacy "adreno_rev" format
>>> + * for all a6xx devices, but probably best to limit this
>>> + * to older things.
>>> + */
>>> + WARN_ON_ONCE(gpu->info->family >= ADRENO_6XX_GEN1);
>>> + return gpu->chip_id & 0xff;
>>> +}
>>>
>>> static inline bool adreno_is_revn(const struct adreno_gpu *gpu, uint32_t revn)
>>> {
>>> @@ -252,7 +259,7 @@ static inline bool adreno_is_a330(const struct adreno_gpu *gpu)
>>>
>>> static inline bool adreno_is_a330v2(const struct adreno_gpu *gpu)
>>> {
>>> - return adreno_is_a330(gpu) && (gpu->rev.patchid > 0);
>>> + return adreno_is_a330(gpu) && (adreno_patchid(gpu) > 0);
>>> }
>>>
>>> static inline int adreno_is_a405(const struct adreno_gpu *gpu)
>>> @@ -342,8 +349,7 @@ static inline int adreno_is_a650(const struct adreno_gpu *gpu)
>>>
>>> static inline int adreno_is_7c3(const struct adreno_gpu *gpu)
>>> {
>>> - /* The order of args is important here to handle ANY_ID correctly */
>>> - return adreno_cmp_rev(ADRENO_REV(6, 3, 5, ANY_ID), gpu->rev);
>>> + return gpu->info->chip_ids[0] == 0x06030500;
>>
>> Ugh. The thing that bugs me isn't even the manual comparison of
>> chip_ids[0], but the fact that these two platforms stand aside. I think
>> at the end we should have a single mechanism for checking GPU's SKUs.
>>
>> Or maybe we should get rid of that completely.
>>
>> If we get rid of a single gpulist table and move individual GPU info
>> definitions to aNxx_gpu.c, we can subclass a generic info structure with
>> generation-specific data, for example generation-specific quirks,
>> pointers to hcwg or VBIF registers, etc. And then instead of having
>> adreno_is_foo all over the code we can migrate most of these checks to
>> data in the gpu info data.
>>
>>> }
>>>
>>> static inline int adreno_is_a660(const struct adreno_gpu *gpu)
>>> @@ -358,8 +364,7 @@ static inline int adreno_is_a680(const struct adreno_gpu *gpu)
>>>
>>> static inline int adreno_is_a690(const struct adreno_gpu *gpu)
>>> {
>>> - /* The order of args is important here to handle ANY_ID correctly */
>>> - return adreno_cmp_rev(ADRENO_REV(6, 9, 0, ANY_ID), gpu->rev);
>>> + return gpu->info->chip_ids[0] == 0x06090000;
>>> };
>>> /* check for a615, a616, a618, a619 or any a630 derivatives */
>>> static inline int adreno_is_a630_family(const struct adreno_gpu *gpu)
>>
>> --
>> With best wishes
>> Dmitry
>>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 73+ messages in thread
* Re: [Freedreno] [PATCH 06/12] drm/msm/adreno: Allow SoC specific gpu device table entries
2023-07-26 20:11 ` Rob Clark
@ 2023-07-26 21:43 ` Dmitry Baryshkov
2023-07-26 22:03 ` Rob Clark
0 siblings, 1 reply; 73+ messages in thread
From: Dmitry Baryshkov @ 2023-07-26 21:43 UTC (permalink / raw)
To: Rob Clark
Cc: Rob Clark, Akhil P Oommen, linux-arm-msm, dri-devel,
Konrad Dybcio, freedreno
On 26/07/2023 23:11, Rob Clark wrote:
> On Wed, Jul 26, 2023 at 1:00 PM Dmitry Baryshkov
> <dmitry.baryshkov@linaro.org> wrote:
>>
>> On Wed, 26 Jul 2023 at 21:28, Rob Clark <robdclark@gmail.com> wrote:
>>>
>>> On Thu, Jul 13, 2023 at 1:26 PM Akhil P Oommen <quic_akhilpo@quicinc.com> wrote:
>>>>
>>>> On Fri, Jul 07, 2023 at 05:34:04AM +0300, Dmitry Baryshkov wrote:
>>>>>
>>>>> On 07/07/2023 00:10, Rob Clark wrote:
>>>>>> From: Rob Clark <robdclark@chromium.org>
>>>>>>
>>>>>> There are cases where there are differences due to SoC integration.
>>>>>> Such as cache-coherency support, and (in the next patch) e-fuse to
>>>>>> speedbin mappings.
>>>>>
>>>>> I have the feeling that we are trying to circumvent the way DT works. I'd
>>>>> suggest adding explicit SoC-compatible strings to Adreno bindings and then
>>>>> using of_device_id::data and then of_device_get_match_data().
>>>>>
>>>> Just thinking, then how about a unique compatible string which we match
>>>> to identify gpu->info and drop chip-id check completely here?
>>>
>>> Ok, I think we could do this, so something like:
>>>
>>> compatible = "qcom,sm4350-adreno-619.0", qcom,adreno-619.0", "qcom,adreno"
>>>
>>> ?
>>>
>>> It looks like we don't have gpu dt bits upstream yet for either sm4350
>>> or sm6375, so I suppose we could get away with this change
>>
>> I think we can even skip the 619.0 part in the SoC compat string.
>> So it will be:
>>
>> compatible = "qcom,sm4350-adreno", qcom,adreno-619.0", "qcom,adreno";
>>
>> In future we can drop the chipid part completely and handle that as a
>> part of SoC data:
>>
>> compatible = "qcom,sm4350-adreno", "qcom,adreno";
>>
>> With the driver knowing that sm4350-adreno means ADRENO_ID(6,1,9,0)
>>
>
> I don't think we can do that, there are cases where the same SoC had
> multiple revisions of adreno.
Is that the case for the production versions of the SoC? In other
subsystems what we usually do is that we add support only for the latest
SoC revision (which would probably mean the latest GPU patch revision).
Previous GPU revisions can be added in the following way (pure example):
qcom,sm4350-adreno -> 6,1,9,1 // assuming v2.0 or v1.1 is the commercial
sample
qcom,sm4350-v1-adreno -> 6,1,9,0
> We could possibly do that with future
> things where we can read the chip-id from fw.
>
> What we _could_ do at the expense of making the compatible parsing a
> tiny bit more complex is something like:
>
> compatible = "qcom,sm4350-adreno-619.0", "qcom,adreno"
>
> BR,
> -R
>
>>>
>>> BR,
>>> -R
>>>
>>>> -Akhil
>>>>
>>>>>>
>>>>>> Signed-off-by: Rob Clark <robdclark@chromium.org>
>>>>>> ---
>>>>>> drivers/gpu/drm/msm/adreno/adreno_device.c | 34 +++++++++++++++++++---
>>>>>> drivers/gpu/drm/msm/adreno/adreno_gpu.h | 1 +
>>>>>> 2 files changed, 31 insertions(+), 4 deletions(-)
>>>>>>
>>>>>> diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c
>>>>>> index 3c531da417b9..e62bc895a31f 100644
>>>>>> --- a/drivers/gpu/drm/msm/adreno/adreno_device.c
>>>>>> +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c
>>>>>> @@ -258,6 +258,32 @@ static const struct adreno_info gpulist[] = {
>>>>>> .inactive_period = DRM_MSM_INACTIVE_PERIOD,
>>>>>> .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT,
>>>>>> .init = a6xx_gpu_init,
>>>>>> + }, {
>>>>>> + .machine = "qcom,sm4350",
>>>>>> + .rev = ADRENO_REV(6, 1, 9, ANY_ID),
>>>>>> + .revn = 619,
>>>>>> + .fw = {
>>>>>> + [ADRENO_FW_SQE] = "a630_sqe.fw",
>>>>>> + [ADRENO_FW_GMU] = "a619_gmu.bin",
>>>>>> + },
>>>>>> + .gmem = SZ_512K,
>>>>>> + .inactive_period = DRM_MSM_INACTIVE_PERIOD,
>>>>>> + .init = a6xx_gpu_init,
>>>>>> + .zapfw = "a615_zap.mdt",
>>>>>> + .hwcg = a615_hwcg,
>>>>>> + }, {
>>>>>> + .machine = "qcom,sm6375",
>>>>>> + .rev = ADRENO_REV(6, 1, 9, ANY_ID),
>>>>>> + .revn = 619,
>>>>>> + .fw = {
>>>>>> + [ADRENO_FW_SQE] = "a630_sqe.fw",
>>>>>> + [ADRENO_FW_GMU] = "a619_gmu.bin",
>>>>>> + },
>>>>>> + .gmem = SZ_512K,
>>>>>> + .inactive_period = DRM_MSM_INACTIVE_PERIOD,
>>>>>> + .init = a6xx_gpu_init,
>>>>>> + .zapfw = "a615_zap.mdt",
>>>>>> + .hwcg = a615_hwcg,
>>>>>> }, {
>>>>>> .rev = ADRENO_REV(6, 1, 9, ANY_ID),
>>>>>> .revn = 619,
>>>>>> @@ -409,6 +435,8 @@ const struct adreno_info *adreno_info(struct adreno_rev rev)
>>>>>> /* identify gpu: */
>>>>>> for (i = 0; i < ARRAY_SIZE(gpulist); i++) {
>>>>>> const struct adreno_info *info = &gpulist[i];
>>>>>> + if (info->machine && !of_machine_is_compatible(info->machine))
>>>>>> + continue;
>>>>>> if (adreno_cmp_rev(info->rev, rev))
>>>>>> return info;
>>>>>> }
>>>>>> @@ -563,6 +591,8 @@ static int adreno_bind(struct device *dev, struct device *master, void *data)
>>>>>> config.rev.minor, config.rev.patchid);
>>>>>> priv->is_a2xx = config.rev.core == 2;
>>>>>> + priv->has_cached_coherent =
>>>>>> + !!(info->quirks & ADRENO_QUIRK_HAS_CACHED_COHERENT);
>>>>>> gpu = info->init(drm);
>>>>>> if (IS_ERR(gpu)) {
>>>>>> @@ -574,10 +604,6 @@ static int adreno_bind(struct device *dev, struct device *master, void *data)
>>>>>> if (ret)
>>>>>> return ret;
>>>>>> - priv->has_cached_coherent =
>>>>>> - !!(info->quirks & ADRENO_QUIRK_HAS_CACHED_COHERENT) &&
>>>>>> - !adreno_has_gmu_wrapper(to_adreno_gpu(gpu));
>>>>>> -
>>>>>> return 0;
>>>>>> }
>>>>>> diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
>>>>>> index e08d41337169..d5335b99c64c 100644
>>>>>> --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
>>>>>> +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
>>>>>> @@ -61,6 +61,7 @@ extern const struct adreno_reglist a612_hwcg[], a615_hwcg[], a630_hwcg[], a640_h
>>>>>> extern const struct adreno_reglist a660_hwcg[], a690_hwcg[];
>>>>>> struct adreno_info {
>>>>>> + const char *machine;
>>>>>> struct adreno_rev rev;
>>>>>> uint32_t revn;
>>>>>> const char *fw[ADRENO_FW_MAX];
>>>>>
>>>>> --
>>>>> With best wishes
>>>>> Dmitry
>>>>>
>>
>>
>>
>> --
>> With best wishes
>> Dmitry
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 73+ messages in thread
* Re: [Freedreno] [PATCH 12/12] drm/msm/adreno: Switch to chip-id for identifying GPU
2023-07-26 21:38 ` Dmitry Baryshkov
@ 2023-07-26 21:44 ` Rob Clark
2023-07-26 21:45 ` Dmitry Baryshkov
0 siblings, 1 reply; 73+ messages in thread
From: Rob Clark @ 2023-07-26 21:44 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Konrad Dybcio, linux-arm-msm, Rob Clark, freedreno, dri-devel
On Wed, Jul 26, 2023 at 2:38 PM Dmitry Baryshkov
<dmitry.baryshkov@linaro.org> wrote:
>
> On 27/07/2023 00:37, Rob Clark wrote:
> > On Thu, Jul 6, 2023 at 8:45 PM Dmitry Baryshkov
> > <dmitry.baryshkov@linaro.org> wrote:
> >>
> >> On 07/07/2023 00:10, Rob Clark wrote:
> >>> From: Rob Clark <robdclark@chromium.org>
> >>>
> >>> /* Helper for formating the chip_id in the way that userspace tools like
> >>> * crashdec expect.
> >>> */
> >>> #define ADRENO_CHIPID_FMT "u.%u.%u.%u"
> >>> -#define ADRENO_CHIPID_ARGS(_r) (_r).core, (_r).major, (_r).minor, (_r).patchid
> >>> +#define ADRENO_CHIPID_ARGS(_c) \
> >>> + (((_c) >> 24) & 0xff), \
> >>> + (((_c) >> 16) & 0xff), \
> >>> + (((_c) >> 8) & 0xff), \
> >>> + ((_c) & 0xff)
> >>
> >> So, we still have some meaning for chipid?
> >
> > Only enough to do the inverse of what userspace does when parsing
> > devcoredump to construct chip-id. Basically it is just a different
> > way to represent a 32b #
>
> What about passing it in the direct form? The macro adds assumptions.
It is uabi
I wouldn't call it adding assumptions as much as just a funny way to
format a number. In some cases it might work out to something that
vaguely resembles a marketing name (6.3.0.2), in other cases it won't
(12.34.56.78).. it's just formatting a 32b # to match the way existing
userspace parses it
BR,
-R
^ permalink raw reply [flat|nested] 73+ messages in thread
* Re: [Freedreno] [PATCH 12/12] drm/msm/adreno: Switch to chip-id for identifying GPU
2023-07-26 21:44 ` Rob Clark
@ 2023-07-26 21:45 ` Dmitry Baryshkov
0 siblings, 0 replies; 73+ messages in thread
From: Dmitry Baryshkov @ 2023-07-26 21:45 UTC (permalink / raw)
To: Rob Clark; +Cc: Konrad Dybcio, linux-arm-msm, Rob Clark, freedreno, dri-devel
On 27/07/2023 00:44, Rob Clark wrote:
> On Wed, Jul 26, 2023 at 2:38 PM Dmitry Baryshkov
> <dmitry.baryshkov@linaro.org> wrote:
>>
>> On 27/07/2023 00:37, Rob Clark wrote:
>>> On Thu, Jul 6, 2023 at 8:45 PM Dmitry Baryshkov
>>> <dmitry.baryshkov@linaro.org> wrote:
>>>>
>>>> On 07/07/2023 00:10, Rob Clark wrote:
>>>>> From: Rob Clark <robdclark@chromium.org>
>>>>>
>>>>> /* Helper for formating the chip_id in the way that userspace tools like
>>>>> * crashdec expect.
>>>>> */
>>>>> #define ADRENO_CHIPID_FMT "u.%u.%u.%u"
>>>>> -#define ADRENO_CHIPID_ARGS(_r) (_r).core, (_r).major, (_r).minor, (_r).patchid
>>>>> +#define ADRENO_CHIPID_ARGS(_c) \
>>>>> + (((_c) >> 24) & 0xff), \
>>>>> + (((_c) >> 16) & 0xff), \
>>>>> + (((_c) >> 8) & 0xff), \
>>>>> + ((_c) & 0xff)
>>>>
>>>> So, we still have some meaning for chipid?
>>>
>>> Only enough to do the inverse of what userspace does when parsing
>>> devcoredump to construct chip-id. Basically it is just a different
>>> way to represent a 32b #
>>
>> What about passing it in the direct form? The macro adds assumptions.
>
> It is uabi
>
> I wouldn't call it adding assumptions as much as just a funny way to
> format a number. In some cases it might work out to something that
> vaguely resembles a marketing name (6.3.0.2), in other cases it won't
> (12.34.56.78).. it's just formatting a 32b # to match the way existing
> userspace parses it
I see. Sounds fine then.
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 73+ messages in thread
* Re: [PATCH 12/12] drm/msm/adreno: Switch to chip-id for identifying GPU
2023-07-15 13:38 ` Konrad Dybcio
2023-07-15 14:12 ` Rob Clark
@ 2023-07-26 21:45 ` Rob Clark
1 sibling, 0 replies; 73+ messages in thread
From: Rob Clark @ 2023-07-26 21:45 UTC (permalink / raw)
To: Konrad Dybcio; +Cc: Rob Clark, linux-arm-msm, freedreno, dri-devel
On Sat, Jul 15, 2023 at 6:38 AM Konrad Dybcio <konrad.dybcio@linaro.org> wrote:
>
> On 7.07.2023 18:08, Rob Clark wrote:
> > On Thu, Jul 6, 2023 at 5:25 PM Konrad Dybcio <konrad.dybcio@linaro.org> wrote:
> >>
> >> Apart from all these comments, I don't really see the point of this patch,
> >> other than trying to tie together Qualcomm's almost-meaningless chipids on
> >> a7xx into the picture..
> >>
> >> Since they can't even be read back from the hardware, I don't think trying
> >> to force them into the upstream kernel makes any sense.
> >
> > Sure, we _could_ pick our own arbitrary identifiers, we don't have to
> > align with kgsl. But that would be a super huge PITA for mesa, which
> > has support for both kernels.
> Perhaps I'm biased towards keeping this kind of stuff out of the kernel,
> but I'd say that Linux should decide on one logical path.
>
> In between us starting this discussion, Qualcomm managed to introduce
> yet another way of deciding what GPU is present on the system in their
> downstream driver[1]. We're at like 5 now. Do we wanna keep up each time?
> New ID rework for A8xx when that comes out one day?
[snip]
> [1] they now read parts of socinfo from smem and decide the CHIPID and
> speedbin based on that, but it's not available on most existing SoCs,
> that was thrown in with SOCID v17
This is actually exactly what we want.. something that we can read
from hw/fw and that blob userspace also uses (so we don't have to
worry about qc forgetting to change the id, etc)
BR,
-R
^ permalink raw reply [flat|nested] 73+ messages in thread
* Re: [Freedreno] [PATCH 06/12] drm/msm/adreno: Allow SoC specific gpu device table entries
2023-07-26 21:43 ` Dmitry Baryshkov
@ 2023-07-26 22:03 ` Rob Clark
2023-07-26 22:33 ` Dmitry Baryshkov
0 siblings, 1 reply; 73+ messages in thread
From: Rob Clark @ 2023-07-26 22:03 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Rob Clark, Akhil P Oommen, linux-arm-msm, dri-devel,
Konrad Dybcio, freedreno
On Wed, Jul 26, 2023 at 2:43 PM Dmitry Baryshkov
<dmitry.baryshkov@linaro.org> wrote:
>
> On 26/07/2023 23:11, Rob Clark wrote:
> > On Wed, Jul 26, 2023 at 1:00 PM Dmitry Baryshkov
> > <dmitry.baryshkov@linaro.org> wrote:
> >>
> >> On Wed, 26 Jul 2023 at 21:28, Rob Clark <robdclark@gmail.com> wrote:
> >>>
> >>> On Thu, Jul 13, 2023 at 1:26 PM Akhil P Oommen <quic_akhilpo@quicinc.com> wrote:
> >>>>
> >>>> On Fri, Jul 07, 2023 at 05:34:04AM +0300, Dmitry Baryshkov wrote:
> >>>>>
> >>>>> On 07/07/2023 00:10, Rob Clark wrote:
> >>>>>> From: Rob Clark <robdclark@chromium.org>
> >>>>>>
> >>>>>> There are cases where there are differences due to SoC integration.
> >>>>>> Such as cache-coherency support, and (in the next patch) e-fuse to
> >>>>>> speedbin mappings.
> >>>>>
> >>>>> I have the feeling that we are trying to circumvent the way DT works. I'd
> >>>>> suggest adding explicit SoC-compatible strings to Adreno bindings and then
> >>>>> using of_device_id::data and then of_device_get_match_data().
> >>>>>
> >>>> Just thinking, then how about a unique compatible string which we match
> >>>> to identify gpu->info and drop chip-id check completely here?
> >>>
> >>> Ok, I think we could do this, so something like:
> >>>
> >>> compatible = "qcom,sm4350-adreno-619.0", qcom,adreno-619.0", "qcom,adreno"
> >>>
> >>> ?
> >>>
> >>> It looks like we don't have gpu dt bits upstream yet for either sm4350
> >>> or sm6375, so I suppose we could get away with this change
> >>
> >> I think we can even skip the 619.0 part in the SoC compat string.
> >> So it will be:
> >>
> >> compatible = "qcom,sm4350-adreno", qcom,adreno-619.0", "qcom,adreno";
> >>
> >> In future we can drop the chipid part completely and handle that as a
> >> part of SoC data:
> >>
> >> compatible = "qcom,sm4350-adreno", "qcom,adreno";
> >>
> >> With the driver knowing that sm4350-adreno means ADRENO_ID(6,1,9,0)
> >>
> >
> > I don't think we can do that, there are cases where the same SoC had
> > multiple revisions of adreno.
>
> Is that the case for the production versions of the SoC? In other
> subsystems what we usually do is that we add support only for the latest
> SoC revision (which would probably mean the latest GPU patch revision).
> Previous GPU revisions can be added in the following way (pure example):
>
> qcom,sm4350-adreno -> 6,1,9,1 // assuming v2.0 or v1.1 is the commercial
> sample
> qcom,sm4350-v1-adreno -> 6,1,9,0
>
My recollection was that nexus4 shipped with an early version of 8064
which needed userspace workarounds that later 8064 did not. Not sure
if that is the only such example, but it is one that userspace needed
to be aware of.
Anyways, future things, it sounds like we'll be able to read the id
from the hw/fw. I'm not really a fan of breaking dtb fwd/bk compat,
so I don't want to change any of the existing compat strings.
BR,
-R
> > We could possibly do that with future
> > things where we can read the chip-id from fw.
> >
> > What we _could_ do at the expense of making the compatible parsing a
> > tiny bit more complex is something like:
> >
> > compatible = "qcom,sm4350-adreno-619.0", "qcom,adreno"
> >
> > BR,
> > -R
> >
> >>>
> >>> BR,
> >>> -R
> >>>
> >>>> -Akhil
> >>>>
> >>>>>>
> >>>>>> Signed-off-by: Rob Clark <robdclark@chromium.org>
> >>>>>> ---
> >>>>>> drivers/gpu/drm/msm/adreno/adreno_device.c | 34 +++++++++++++++++++---
> >>>>>> drivers/gpu/drm/msm/adreno/adreno_gpu.h | 1 +
> >>>>>> 2 files changed, 31 insertions(+), 4 deletions(-)
> >>>>>>
> >>>>>> diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c
> >>>>>> index 3c531da417b9..e62bc895a31f 100644
> >>>>>> --- a/drivers/gpu/drm/msm/adreno/adreno_device.c
> >>>>>> +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c
> >>>>>> @@ -258,6 +258,32 @@ static const struct adreno_info gpulist[] = {
> >>>>>> .inactive_period = DRM_MSM_INACTIVE_PERIOD,
> >>>>>> .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT,
> >>>>>> .init = a6xx_gpu_init,
> >>>>>> + }, {
> >>>>>> + .machine = "qcom,sm4350",
> >>>>>> + .rev = ADRENO_REV(6, 1, 9, ANY_ID),
> >>>>>> + .revn = 619,
> >>>>>> + .fw = {
> >>>>>> + [ADRENO_FW_SQE] = "a630_sqe.fw",
> >>>>>> + [ADRENO_FW_GMU] = "a619_gmu.bin",
> >>>>>> + },
> >>>>>> + .gmem = SZ_512K,
> >>>>>> + .inactive_period = DRM_MSM_INACTIVE_PERIOD,
> >>>>>> + .init = a6xx_gpu_init,
> >>>>>> + .zapfw = "a615_zap.mdt",
> >>>>>> + .hwcg = a615_hwcg,
> >>>>>> + }, {
> >>>>>> + .machine = "qcom,sm6375",
> >>>>>> + .rev = ADRENO_REV(6, 1, 9, ANY_ID),
> >>>>>> + .revn = 619,
> >>>>>> + .fw = {
> >>>>>> + [ADRENO_FW_SQE] = "a630_sqe.fw",
> >>>>>> + [ADRENO_FW_GMU] = "a619_gmu.bin",
> >>>>>> + },
> >>>>>> + .gmem = SZ_512K,
> >>>>>> + .inactive_period = DRM_MSM_INACTIVE_PERIOD,
> >>>>>> + .init = a6xx_gpu_init,
> >>>>>> + .zapfw = "a615_zap.mdt",
> >>>>>> + .hwcg = a615_hwcg,
> >>>>>> }, {
> >>>>>> .rev = ADRENO_REV(6, 1, 9, ANY_ID),
> >>>>>> .revn = 619,
> >>>>>> @@ -409,6 +435,8 @@ const struct adreno_info *adreno_info(struct adreno_rev rev)
> >>>>>> /* identify gpu: */
> >>>>>> for (i = 0; i < ARRAY_SIZE(gpulist); i++) {
> >>>>>> const struct adreno_info *info = &gpulist[i];
> >>>>>> + if (info->machine && !of_machine_is_compatible(info->machine))
> >>>>>> + continue;
> >>>>>> if (adreno_cmp_rev(info->rev, rev))
> >>>>>> return info;
> >>>>>> }
> >>>>>> @@ -563,6 +591,8 @@ static int adreno_bind(struct device *dev, struct device *master, void *data)
> >>>>>> config.rev.minor, config.rev.patchid);
> >>>>>> priv->is_a2xx = config.rev.core == 2;
> >>>>>> + priv->has_cached_coherent =
> >>>>>> + !!(info->quirks & ADRENO_QUIRK_HAS_CACHED_COHERENT);
> >>>>>> gpu = info->init(drm);
> >>>>>> if (IS_ERR(gpu)) {
> >>>>>> @@ -574,10 +604,6 @@ static int adreno_bind(struct device *dev, struct device *master, void *data)
> >>>>>> if (ret)
> >>>>>> return ret;
> >>>>>> - priv->has_cached_coherent =
> >>>>>> - !!(info->quirks & ADRENO_QUIRK_HAS_CACHED_COHERENT) &&
> >>>>>> - !adreno_has_gmu_wrapper(to_adreno_gpu(gpu));
> >>>>>> -
> >>>>>> return 0;
> >>>>>> }
> >>>>>> diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> >>>>>> index e08d41337169..d5335b99c64c 100644
> >>>>>> --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> >>>>>> +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> >>>>>> @@ -61,6 +61,7 @@ extern const struct adreno_reglist a612_hwcg[], a615_hwcg[], a630_hwcg[], a640_h
> >>>>>> extern const struct adreno_reglist a660_hwcg[], a690_hwcg[];
> >>>>>> struct adreno_info {
> >>>>>> + const char *machine;
> >>>>>> struct adreno_rev rev;
> >>>>>> uint32_t revn;
> >>>>>> const char *fw[ADRENO_FW_MAX];
> >>>>>
> >>>>> --
> >>>>> With best wishes
> >>>>> Dmitry
> >>>>>
> >>
> >>
> >>
> >> --
> >> With best wishes
> >> Dmitry
>
> --
> With best wishes
> Dmitry
>
^ permalink raw reply [flat|nested] 73+ messages in thread
* Re: [Freedreno] [PATCH 06/12] drm/msm/adreno: Allow SoC specific gpu device table entries
2023-07-26 22:03 ` Rob Clark
@ 2023-07-26 22:33 ` Dmitry Baryshkov
2023-07-26 22:53 ` Rob Clark
2023-07-27 21:13 ` Rob Clark
0 siblings, 2 replies; 73+ messages in thread
From: Dmitry Baryshkov @ 2023-07-26 22:33 UTC (permalink / raw)
To: Rob Clark
Cc: Rob Clark, Akhil P Oommen, linux-arm-msm, dri-devel,
Konrad Dybcio, freedreno
On Thu, 27 Jul 2023 at 01:04, Rob Clark <robdclark@gmail.com> wrote:
>
> On Wed, Jul 26, 2023 at 2:43 PM Dmitry Baryshkov
> <dmitry.baryshkov@linaro.org> wrote:
> >
> > On 26/07/2023 23:11, Rob Clark wrote:
> > > On Wed, Jul 26, 2023 at 1:00 PM Dmitry Baryshkov
> > > <dmitry.baryshkov@linaro.org> wrote:
> > >>
> > >> On Wed, 26 Jul 2023 at 21:28, Rob Clark <robdclark@gmail.com> wrote:
> > >>>
> > >>> On Thu, Jul 13, 2023 at 1:26 PM Akhil P Oommen <quic_akhilpo@quicinc.com> wrote:
> > >>>>
> > >>>> On Fri, Jul 07, 2023 at 05:34:04AM +0300, Dmitry Baryshkov wrote:
> > >>>>>
> > >>>>> On 07/07/2023 00:10, Rob Clark wrote:
> > >>>>>> From: Rob Clark <robdclark@chromium.org>
> > >>>>>>
> > >>>>>> There are cases where there are differences due to SoC integration.
> > >>>>>> Such as cache-coherency support, and (in the next patch) e-fuse to
> > >>>>>> speedbin mappings.
> > >>>>>
> > >>>>> I have the feeling that we are trying to circumvent the way DT works. I'd
> > >>>>> suggest adding explicit SoC-compatible strings to Adreno bindings and then
> > >>>>> using of_device_id::data and then of_device_get_match_data().
> > >>>>>
> > >>>> Just thinking, then how about a unique compatible string which we match
> > >>>> to identify gpu->info and drop chip-id check completely here?
> > >>>
> > >>> Ok, I think we could do this, so something like:
> > >>>
> > >>> compatible = "qcom,sm4350-adreno-619.0", qcom,adreno-619.0", "qcom,adreno"
> > >>>
> > >>> ?
> > >>>
> > >>> It looks like we don't have gpu dt bits upstream yet for either sm4350
> > >>> or sm6375, so I suppose we could get away with this change
> > >>
> > >> I think we can even skip the 619.0 part in the SoC compat string.
> > >> So it will be:
> > >>
> > >> compatible = "qcom,sm4350-adreno", qcom,adreno-619.0", "qcom,adreno";
> > >>
> > >> In future we can drop the chipid part completely and handle that as a
> > >> part of SoC data:
> > >>
> > >> compatible = "qcom,sm4350-adreno", "qcom,adreno";
> > >>
> > >> With the driver knowing that sm4350-adreno means ADRENO_ID(6,1,9,0)
> > >>
> > >
> > > I don't think we can do that, there are cases where the same SoC had
> > > multiple revisions of adreno.
> >
> > Is that the case for the production versions of the SoC? In other
> > subsystems what we usually do is that we add support only for the latest
> > SoC revision (which would probably mean the latest GPU patch revision).
> > Previous GPU revisions can be added in the following way (pure example):
> >
> > qcom,sm4350-adreno -> 6,1,9,1 // assuming v2.0 or v1.1 is the commercial
> > sample
> > qcom,sm4350-v1-adreno -> 6,1,9,0
> >
>
> My recollection was that nexus4 shipped with an early version of 8064
> which needed userspace workarounds that later 8064 did not. Not sure
> if that is the only such example, but it is one that userspace needed
> to be aware of.
Good question. I don't have nexus4, and both nexus7 and ifc6410 work fine.
And this is a perfect use case for "qcom,apq8064-v1.1-adreno" compat string.
>
> Anyways, future things, it sounds like we'll be able to read the id
> from the hw/fw. I'm not really a fan of breaking dtb fwd/bk compat,
> so I don't want to change any of the existing compat strings.
I think so too. Current compat strings should stay.
>
> BR,
> -R
>
> > > We could possibly do that with future
> > > things where we can read the chip-id from fw.
> > >
> > > What we _could_ do at the expense of making the compatible parsing a
> > > tiny bit more complex is something like:
> > >
> > > compatible = "qcom,sm4350-adreno-619.0", "qcom,adreno"
> > >
> > > BR,
> > > -R
> > >
> > >>>
> > >>> BR,
> > >>> -R
> > >>>
> > >>>> -Akhil
> > >>>>
> > >>>>>>
> > >>>>>> Signed-off-by: Rob Clark <robdclark@chromium.org>
> > >>>>>> ---
> > >>>>>> drivers/gpu/drm/msm/adreno/adreno_device.c | 34 +++++++++++++++++++---
> > >>>>>> drivers/gpu/drm/msm/adreno/adreno_gpu.h | 1 +
> > >>>>>> 2 files changed, 31 insertions(+), 4 deletions(-)
> > >>>>>>
> > >>>>>> diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c
> > >>>>>> index 3c531da417b9..e62bc895a31f 100644
> > >>>>>> --- a/drivers/gpu/drm/msm/adreno/adreno_device.c
> > >>>>>> +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c
> > >>>>>> @@ -258,6 +258,32 @@ static const struct adreno_info gpulist[] = {
> > >>>>>> .inactive_period = DRM_MSM_INACTIVE_PERIOD,
> > >>>>>> .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT,
> > >>>>>> .init = a6xx_gpu_init,
> > >>>>>> + }, {
> > >>>>>> + .machine = "qcom,sm4350",
> > >>>>>> + .rev = ADRENO_REV(6, 1, 9, ANY_ID),
> > >>>>>> + .revn = 619,
> > >>>>>> + .fw = {
> > >>>>>> + [ADRENO_FW_SQE] = "a630_sqe.fw",
> > >>>>>> + [ADRENO_FW_GMU] = "a619_gmu.bin",
> > >>>>>> + },
> > >>>>>> + .gmem = SZ_512K,
> > >>>>>> + .inactive_period = DRM_MSM_INACTIVE_PERIOD,
> > >>>>>> + .init = a6xx_gpu_init,
> > >>>>>> + .zapfw = "a615_zap.mdt",
> > >>>>>> + .hwcg = a615_hwcg,
> > >>>>>> + }, {
> > >>>>>> + .machine = "qcom,sm6375",
> > >>>>>> + .rev = ADRENO_REV(6, 1, 9, ANY_ID),
> > >>>>>> + .revn = 619,
> > >>>>>> + .fw = {
> > >>>>>> + [ADRENO_FW_SQE] = "a630_sqe.fw",
> > >>>>>> + [ADRENO_FW_GMU] = "a619_gmu.bin",
> > >>>>>> + },
> > >>>>>> + .gmem = SZ_512K,
> > >>>>>> + .inactive_period = DRM_MSM_INACTIVE_PERIOD,
> > >>>>>> + .init = a6xx_gpu_init,
> > >>>>>> + .zapfw = "a615_zap.mdt",
> > >>>>>> + .hwcg = a615_hwcg,
> > >>>>>> }, {
> > >>>>>> .rev = ADRENO_REV(6, 1, 9, ANY_ID),
> > >>>>>> .revn = 619,
> > >>>>>> @@ -409,6 +435,8 @@ const struct adreno_info *adreno_info(struct adreno_rev rev)
> > >>>>>> /* identify gpu: */
> > >>>>>> for (i = 0; i < ARRAY_SIZE(gpulist); i++) {
> > >>>>>> const struct adreno_info *info = &gpulist[i];
> > >>>>>> + if (info->machine && !of_machine_is_compatible(info->machine))
> > >>>>>> + continue;
> > >>>>>> if (adreno_cmp_rev(info->rev, rev))
> > >>>>>> return info;
> > >>>>>> }
> > >>>>>> @@ -563,6 +591,8 @@ static int adreno_bind(struct device *dev, struct device *master, void *data)
> > >>>>>> config.rev.minor, config.rev.patchid);
> > >>>>>> priv->is_a2xx = config.rev.core == 2;
> > >>>>>> + priv->has_cached_coherent =
> > >>>>>> + !!(info->quirks & ADRENO_QUIRK_HAS_CACHED_COHERENT);
> > >>>>>> gpu = info->init(drm);
> > >>>>>> if (IS_ERR(gpu)) {
> > >>>>>> @@ -574,10 +604,6 @@ static int adreno_bind(struct device *dev, struct device *master, void *data)
> > >>>>>> if (ret)
> > >>>>>> return ret;
> > >>>>>> - priv->has_cached_coherent =
> > >>>>>> - !!(info->quirks & ADRENO_QUIRK_HAS_CACHED_COHERENT) &&
> > >>>>>> - !adreno_has_gmu_wrapper(to_adreno_gpu(gpu));
> > >>>>>> -
> > >>>>>> return 0;
> > >>>>>> }
> > >>>>>> diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> > >>>>>> index e08d41337169..d5335b99c64c 100644
> > >>>>>> --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> > >>>>>> +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> > >>>>>> @@ -61,6 +61,7 @@ extern const struct adreno_reglist a612_hwcg[], a615_hwcg[], a630_hwcg[], a640_h
> > >>>>>> extern const struct adreno_reglist a660_hwcg[], a690_hwcg[];
> > >>>>>> struct adreno_info {
> > >>>>>> + const char *machine;
> > >>>>>> struct adreno_rev rev;
> > >>>>>> uint32_t revn;
> > >>>>>> const char *fw[ADRENO_FW_MAX];
> > >>>>>
> > >>>>> --
> > >>>>> With best wishes
> > >>>>> Dmitry
> > >>>>>
> > >>
> > >>
> > >>
> > >> --
> > >> With best wishes
> > >> Dmitry
> >
> > --
> > With best wishes
> > Dmitry
> >
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 73+ messages in thread
* Re: [Freedreno] [PATCH 06/12] drm/msm/adreno: Allow SoC specific gpu device table entries
2023-07-26 22:33 ` Dmitry Baryshkov
@ 2023-07-26 22:53 ` Rob Clark
2023-07-27 7:51 ` Konrad Dybcio
2023-07-27 21:13 ` Rob Clark
1 sibling, 1 reply; 73+ messages in thread
From: Rob Clark @ 2023-07-26 22:53 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Rob Clark, Akhil P Oommen, linux-arm-msm, dri-devel,
Konrad Dybcio, freedreno
On Wed, Jul 26, 2023 at 3:33 PM Dmitry Baryshkov
<dmitry.baryshkov@linaro.org> wrote:
>
> On Thu, 27 Jul 2023 at 01:04, Rob Clark <robdclark@gmail.com> wrote:
> >
> > On Wed, Jul 26, 2023 at 2:43 PM Dmitry Baryshkov
> > <dmitry.baryshkov@linaro.org> wrote:
> > >
> > > On 26/07/2023 23:11, Rob Clark wrote:
> > > > On Wed, Jul 26, 2023 at 1:00 PM Dmitry Baryshkov
> > > > <dmitry.baryshkov@linaro.org> wrote:
> > > >>
> > > >> On Wed, 26 Jul 2023 at 21:28, Rob Clark <robdclark@gmail.com> wrote:
> > > >>>
> > > >>> On Thu, Jul 13, 2023 at 1:26 PM Akhil P Oommen <quic_akhilpo@quicinc.com> wrote:
> > > >>>>
> > > >>>> On Fri, Jul 07, 2023 at 05:34:04AM +0300, Dmitry Baryshkov wrote:
> > > >>>>>
> > > >>>>> On 07/07/2023 00:10, Rob Clark wrote:
> > > >>>>>> From: Rob Clark <robdclark@chromium.org>
> > > >>>>>>
> > > >>>>>> There are cases where there are differences due to SoC integration.
> > > >>>>>> Such as cache-coherency support, and (in the next patch) e-fuse to
> > > >>>>>> speedbin mappings.
> > > >>>>>
> > > >>>>> I have the feeling that we are trying to circumvent the way DT works. I'd
> > > >>>>> suggest adding explicit SoC-compatible strings to Adreno bindings and then
> > > >>>>> using of_device_id::data and then of_device_get_match_data().
> > > >>>>>
> > > >>>> Just thinking, then how about a unique compatible string which we match
> > > >>>> to identify gpu->info and drop chip-id check completely here?
> > > >>>
> > > >>> Ok, I think we could do this, so something like:
> > > >>>
> > > >>> compatible = "qcom,sm4350-adreno-619.0", qcom,adreno-619.0", "qcom,adreno"
> > > >>>
> > > >>> ?
> > > >>>
> > > >>> It looks like we don't have gpu dt bits upstream yet for either sm4350
> > > >>> or sm6375, so I suppose we could get away with this change
> > > >>
> > > >> I think we can even skip the 619.0 part in the SoC compat string.
> > > >> So it will be:
> > > >>
> > > >> compatible = "qcom,sm4350-adreno", qcom,adreno-619.0", "qcom,adreno";
> > > >>
> > > >> In future we can drop the chipid part completely and handle that as a
> > > >> part of SoC data:
> > > >>
> > > >> compatible = "qcom,sm4350-adreno", "qcom,adreno";
> > > >>
> > > >> With the driver knowing that sm4350-adreno means ADRENO_ID(6,1,9,0)
> > > >>
> > > >
> > > > I don't think we can do that, there are cases where the same SoC had
> > > > multiple revisions of adreno.
> > >
> > > Is that the case for the production versions of the SoC? In other
> > > subsystems what we usually do is that we add support only for the latest
> > > SoC revision (which would probably mean the latest GPU patch revision).
> > > Previous GPU revisions can be added in the following way (pure example):
> > >
> > > qcom,sm4350-adreno -> 6,1,9,1 // assuming v2.0 or v1.1 is the commercial
> > > sample
> > > qcom,sm4350-v1-adreno -> 6,1,9,0
> > >
> >
> > My recollection was that nexus4 shipped with an early version of 8064
> > which needed userspace workarounds that later 8064 did not. Not sure
> > if that is the only such example, but it is one that userspace needed
> > to be aware of.
>
> Good question. I don't have nexus4, and both nexus7 and ifc6410 work fine.
>
> And this is a perfect use case for "qcom,apq8064-v1.1-adreno" compat string.
I no longer have a n4 that boots.. but if I did both it and the later
ones should work properly if they expose the appropriate chip id
I do still prefer parsing the chip-id out of the compatible. It
avoids needing separate table entries just to have a different
chip-id. Maybe the scheme that is used elsewhere makes sense when it
is only the kernel that needs to be aware of the device-id. And maybe
we could just done matching based on compat-id in userspace as well,
but (a) msm and freedreno pre-date dt, and (b) that ship has already
sailed.
BR,
-R
> >
> > Anyways, future things, it sounds like we'll be able to read the id
> > from the hw/fw. I'm not really a fan of breaking dtb fwd/bk compat,
> > so I don't want to change any of the existing compat strings.
>
> I think so too. Current compat strings should stay.
>
> >
> > BR,
> > -R
> >
> > > > We could possibly do that with future
> > > > things where we can read the chip-id from fw.
> > > >
> > > > What we _could_ do at the expense of making the compatible parsing a
> > > > tiny bit more complex is something like:
> > > >
> > > > compatible = "qcom,sm4350-adreno-619.0", "qcom,adreno"
> > > >
> > > > BR,
> > > > -R
> > > >
> > > >>>
> > > >>> BR,
> > > >>> -R
> > > >>>
> > > >>>> -Akhil
> > > >>>>
> > > >>>>>>
> > > >>>>>> Signed-off-by: Rob Clark <robdclark@chromium.org>
> > > >>>>>> ---
> > > >>>>>> drivers/gpu/drm/msm/adreno/adreno_device.c | 34 +++++++++++++++++++---
> > > >>>>>> drivers/gpu/drm/msm/adreno/adreno_gpu.h | 1 +
> > > >>>>>> 2 files changed, 31 insertions(+), 4 deletions(-)
> > > >>>>>>
> > > >>>>>> diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c
> > > >>>>>> index 3c531da417b9..e62bc895a31f 100644
> > > >>>>>> --- a/drivers/gpu/drm/msm/adreno/adreno_device.c
> > > >>>>>> +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c
> > > >>>>>> @@ -258,6 +258,32 @@ static const struct adreno_info gpulist[] = {
> > > >>>>>> .inactive_period = DRM_MSM_INACTIVE_PERIOD,
> > > >>>>>> .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT,
> > > >>>>>> .init = a6xx_gpu_init,
> > > >>>>>> + }, {
> > > >>>>>> + .machine = "qcom,sm4350",
> > > >>>>>> + .rev = ADRENO_REV(6, 1, 9, ANY_ID),
> > > >>>>>> + .revn = 619,
> > > >>>>>> + .fw = {
> > > >>>>>> + [ADRENO_FW_SQE] = "a630_sqe.fw",
> > > >>>>>> + [ADRENO_FW_GMU] = "a619_gmu.bin",
> > > >>>>>> + },
> > > >>>>>> + .gmem = SZ_512K,
> > > >>>>>> + .inactive_period = DRM_MSM_INACTIVE_PERIOD,
> > > >>>>>> + .init = a6xx_gpu_init,
> > > >>>>>> + .zapfw = "a615_zap.mdt",
> > > >>>>>> + .hwcg = a615_hwcg,
> > > >>>>>> + }, {
> > > >>>>>> + .machine = "qcom,sm6375",
> > > >>>>>> + .rev = ADRENO_REV(6, 1, 9, ANY_ID),
> > > >>>>>> + .revn = 619,
> > > >>>>>> + .fw = {
> > > >>>>>> + [ADRENO_FW_SQE] = "a630_sqe.fw",
> > > >>>>>> + [ADRENO_FW_GMU] = "a619_gmu.bin",
> > > >>>>>> + },
> > > >>>>>> + .gmem = SZ_512K,
> > > >>>>>> + .inactive_period = DRM_MSM_INACTIVE_PERIOD,
> > > >>>>>> + .init = a6xx_gpu_init,
> > > >>>>>> + .zapfw = "a615_zap.mdt",
> > > >>>>>> + .hwcg = a615_hwcg,
> > > >>>>>> }, {
> > > >>>>>> .rev = ADRENO_REV(6, 1, 9, ANY_ID),
> > > >>>>>> .revn = 619,
> > > >>>>>> @@ -409,6 +435,8 @@ const struct adreno_info *adreno_info(struct adreno_rev rev)
> > > >>>>>> /* identify gpu: */
> > > >>>>>> for (i = 0; i < ARRAY_SIZE(gpulist); i++) {
> > > >>>>>> const struct adreno_info *info = &gpulist[i];
> > > >>>>>> + if (info->machine && !of_machine_is_compatible(info->machine))
> > > >>>>>> + continue;
> > > >>>>>> if (adreno_cmp_rev(info->rev, rev))
> > > >>>>>> return info;
> > > >>>>>> }
> > > >>>>>> @@ -563,6 +591,8 @@ static int adreno_bind(struct device *dev, struct device *master, void *data)
> > > >>>>>> config.rev.minor, config.rev.patchid);
> > > >>>>>> priv->is_a2xx = config.rev.core == 2;
> > > >>>>>> + priv->has_cached_coherent =
> > > >>>>>> + !!(info->quirks & ADRENO_QUIRK_HAS_CACHED_COHERENT);
> > > >>>>>> gpu = info->init(drm);
> > > >>>>>> if (IS_ERR(gpu)) {
> > > >>>>>> @@ -574,10 +604,6 @@ static int adreno_bind(struct device *dev, struct device *master, void *data)
> > > >>>>>> if (ret)
> > > >>>>>> return ret;
> > > >>>>>> - priv->has_cached_coherent =
> > > >>>>>> - !!(info->quirks & ADRENO_QUIRK_HAS_CACHED_COHERENT) &&
> > > >>>>>> - !adreno_has_gmu_wrapper(to_adreno_gpu(gpu));
> > > >>>>>> -
> > > >>>>>> return 0;
> > > >>>>>> }
> > > >>>>>> diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> > > >>>>>> index e08d41337169..d5335b99c64c 100644
> > > >>>>>> --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> > > >>>>>> +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> > > >>>>>> @@ -61,6 +61,7 @@ extern const struct adreno_reglist a612_hwcg[], a615_hwcg[], a630_hwcg[], a640_h
> > > >>>>>> extern const struct adreno_reglist a660_hwcg[], a690_hwcg[];
> > > >>>>>> struct adreno_info {
> > > >>>>>> + const char *machine;
> > > >>>>>> struct adreno_rev rev;
> > > >>>>>> uint32_t revn;
> > > >>>>>> const char *fw[ADRENO_FW_MAX];
> > > >>>>>
> > > >>>>> --
> > > >>>>> With best wishes
> > > >>>>> Dmitry
> > > >>>>>
> > > >>
> > > >>
> > > >>
> > > >> --
> > > >> With best wishes
> > > >> Dmitry
> > >
> > > --
> > > With best wishes
> > > Dmitry
> > >
>
>
>
> --
> With best wishes
> Dmitry
^ permalink raw reply [flat|nested] 73+ messages in thread
* Re: [Freedreno] [PATCH 06/12] drm/msm/adreno: Allow SoC specific gpu device table entries
2023-07-26 22:53 ` Rob Clark
@ 2023-07-27 7:51 ` Konrad Dybcio
2023-07-27 14:52 ` Rob Clark
0 siblings, 1 reply; 73+ messages in thread
From: Konrad Dybcio @ 2023-07-27 7:51 UTC (permalink / raw)
To: Rob Clark, Dmitry Baryshkov
Cc: Akhil P Oommen, linux-arm-msm, Rob Clark, freedreno, dri-devel
On 27.07.2023 00:53, Rob Clark wrote:
> On Wed, Jul 26, 2023 at 3:33 PM Dmitry Baryshkov
> <dmitry.baryshkov@linaro.org> wrote:
>>
>> On Thu, 27 Jul 2023 at 01:04, Rob Clark <robdclark@gmail.com> wrote:
>>>
>>> On Wed, Jul 26, 2023 at 2:43 PM Dmitry Baryshkov
>>> <dmitry.baryshkov@linaro.org> wrote:
>>>>
>>>> On 26/07/2023 23:11, Rob Clark wrote:
>>>>> On Wed, Jul 26, 2023 at 1:00 PM Dmitry Baryshkov
>>>>> <dmitry.baryshkov@linaro.org> wrote:
>>>>>>
>>>>>> On Wed, 26 Jul 2023 at 21:28, Rob Clark <robdclark@gmail.com> wrote:
>>>>>>>
>>>>>>> On Thu, Jul 13, 2023 at 1:26 PM Akhil P Oommen <quic_akhilpo@quicinc.com> wrote:
>>>>>>>>
>>>>>>>> On Fri, Jul 07, 2023 at 05:34:04AM +0300, Dmitry Baryshkov wrote:
>>>>>>>>>
>>>>>>>>> On 07/07/2023 00:10, Rob Clark wrote:
>>>>>>>>>> From: Rob Clark <robdclark@chromium.org>
>>>>>>>>>>
>>>>>>>>>> There are cases where there are differences due to SoC integration.
>>>>>>>>>> Such as cache-coherency support, and (in the next patch) e-fuse to
>>>>>>>>>> speedbin mappings.
>>>>>>>>>
>>>>>>>>> I have the feeling that we are trying to circumvent the way DT works. I'd
>>>>>>>>> suggest adding explicit SoC-compatible strings to Adreno bindings and then
>>>>>>>>> using of_device_id::data and then of_device_get_match_data().
>>>>>>>>>
>>>>>>>> Just thinking, then how about a unique compatible string which we match
>>>>>>>> to identify gpu->info and drop chip-id check completely here?
>>>>>>>
>>>>>>> Ok, I think we could do this, so something like:
>>>>>>>
>>>>>>> compatible = "qcom,sm4350-adreno-619.0", qcom,adreno-619.0", "qcom,adreno"
>>>>>>>
>>>>>>> ?
>>>>>>>
>>>>>>> It looks like we don't have gpu dt bits upstream yet for either sm4350
>>>>>>> or sm6375, so I suppose we could get away with this change
>>>>>>
>>>>>> I think we can even skip the 619.0 part in the SoC compat string.
>>>>>> So it will be:
>>>>>>
>>>>>> compatible = "qcom,sm4350-adreno", qcom,adreno-619.0", "qcom,adreno";
>>>>>>
>>>>>> In future we can drop the chipid part completely and handle that as a
>>>>>> part of SoC data:
>>>>>>
>>>>>> compatible = "qcom,sm4350-adreno", "qcom,adreno";
>>>>>>
>>>>>> With the driver knowing that sm4350-adreno means ADRENO_ID(6,1,9,0)
>>>>>>
>>>>>
>>>>> I don't think we can do that, there are cases where the same SoC had
>>>>> multiple revisions of adreno.
>>>>
>>>> Is that the case for the production versions of the SoC? In other
>>>> subsystems what we usually do is that we add support only for the latest
>>>> SoC revision (which would probably mean the latest GPU patch revision).
>>>> Previous GPU revisions can be added in the following way (pure example):
>>>>
>>>> qcom,sm4350-adreno -> 6,1,9,1 // assuming v2.0 or v1.1 is the commercial
>>>> sample
>>>> qcom,sm4350-v1-adreno -> 6,1,9,0
>>>>
>>>
>>> My recollection was that nexus4 shipped with an early version of 8064
>>> which needed userspace workarounds that later 8064 did not. Not sure
>>> if that is the only such example, but it is one that userspace needed
>>> to be aware of.
>>
>> Good question. I don't have nexus4, and both nexus7 and ifc6410 work fine.
>>
>> And this is a perfect use case for "qcom,apq8064-v1.1-adreno" compat string.
>
> I no longer have a n4 that boots.. but if I did both it and the later
> ones should work properly if they expose the appropriate chip id
>
> I do still prefer parsing the chip-id out of the compatible. It
> avoids needing separate table entries just to have a different
> chip-id. Maybe the scheme that is used elsewhere makes sense when it
> is only the kernel that needs to be aware of the device-id. And maybe
> we could just done matching based on compat-id in userspace as well,
> but (a) msm and freedreno pre-date dt, and (b) that ship has already
> sailed.
I think a per-soc dt would be the better approach..
We could probably solve the revision issue with a socid readout of
the silicon revision and override based on that?
Konrad
^ permalink raw reply [flat|nested] 73+ messages in thread
* Re: [Freedreno] [PATCH 06/12] drm/msm/adreno: Allow SoC specific gpu device table entries
2023-07-27 7:51 ` Konrad Dybcio
@ 2023-07-27 14:52 ` Rob Clark
0 siblings, 0 replies; 73+ messages in thread
From: Rob Clark @ 2023-07-27 14:52 UTC (permalink / raw)
To: Konrad Dybcio
Cc: Rob Clark, Akhil P Oommen, linux-arm-msm, dri-devel,
Dmitry Baryshkov, freedreno
On Thu, Jul 27, 2023 at 12:51 AM Konrad Dybcio <konrad.dybcio@linaro.org> wrote:
>
> On 27.07.2023 00:53, Rob Clark wrote:
> > On Wed, Jul 26, 2023 at 3:33 PM Dmitry Baryshkov
> > <dmitry.baryshkov@linaro.org> wrote:
> >>
> >> On Thu, 27 Jul 2023 at 01:04, Rob Clark <robdclark@gmail.com> wrote:
> >>>
> >>> On Wed, Jul 26, 2023 at 2:43 PM Dmitry Baryshkov
> >>> <dmitry.baryshkov@linaro.org> wrote:
> >>>>
> >>>> On 26/07/2023 23:11, Rob Clark wrote:
> >>>>> On Wed, Jul 26, 2023 at 1:00 PM Dmitry Baryshkov
> >>>>> <dmitry.baryshkov@linaro.org> wrote:
> >>>>>>
> >>>>>> On Wed, 26 Jul 2023 at 21:28, Rob Clark <robdclark@gmail.com> wrote:
> >>>>>>>
> >>>>>>> On Thu, Jul 13, 2023 at 1:26 PM Akhil P Oommen <quic_akhilpo@quicinc.com> wrote:
> >>>>>>>>
> >>>>>>>> On Fri, Jul 07, 2023 at 05:34:04AM +0300, Dmitry Baryshkov wrote:
> >>>>>>>>>
> >>>>>>>>> On 07/07/2023 00:10, Rob Clark wrote:
> >>>>>>>>>> From: Rob Clark <robdclark@chromium.org>
> >>>>>>>>>>
> >>>>>>>>>> There are cases where there are differences due to SoC integration.
> >>>>>>>>>> Such as cache-coherency support, and (in the next patch) e-fuse to
> >>>>>>>>>> speedbin mappings.
> >>>>>>>>>
> >>>>>>>>> I have the feeling that we are trying to circumvent the way DT works. I'd
> >>>>>>>>> suggest adding explicit SoC-compatible strings to Adreno bindings and then
> >>>>>>>>> using of_device_id::data and then of_device_get_match_data().
> >>>>>>>>>
> >>>>>>>> Just thinking, then how about a unique compatible string which we match
> >>>>>>>> to identify gpu->info and drop chip-id check completely here?
> >>>>>>>
> >>>>>>> Ok, I think we could do this, so something like:
> >>>>>>>
> >>>>>>> compatible = "qcom,sm4350-adreno-619.0", qcom,adreno-619.0", "qcom,adreno"
> >>>>>>>
> >>>>>>> ?
> >>>>>>>
> >>>>>>> It looks like we don't have gpu dt bits upstream yet for either sm4350
> >>>>>>> or sm6375, so I suppose we could get away with this change
> >>>>>>
> >>>>>> I think we can even skip the 619.0 part in the SoC compat string.
> >>>>>> So it will be:
> >>>>>>
> >>>>>> compatible = "qcom,sm4350-adreno", qcom,adreno-619.0", "qcom,adreno";
> >>>>>>
> >>>>>> In future we can drop the chipid part completely and handle that as a
> >>>>>> part of SoC data:
> >>>>>>
> >>>>>> compatible = "qcom,sm4350-adreno", "qcom,adreno";
> >>>>>>
> >>>>>> With the driver knowing that sm4350-adreno means ADRENO_ID(6,1,9,0)
> >>>>>>
> >>>>>
> >>>>> I don't think we can do that, there are cases where the same SoC had
> >>>>> multiple revisions of adreno.
> >>>>
> >>>> Is that the case for the production versions of the SoC? In other
> >>>> subsystems what we usually do is that we add support only for the latest
> >>>> SoC revision (which would probably mean the latest GPU patch revision).
> >>>> Previous GPU revisions can be added in the following way (pure example):
> >>>>
> >>>> qcom,sm4350-adreno -> 6,1,9,1 // assuming v2.0 or v1.1 is the commercial
> >>>> sample
> >>>> qcom,sm4350-v1-adreno -> 6,1,9,0
> >>>>
> >>>
> >>> My recollection was that nexus4 shipped with an early version of 8064
> >>> which needed userspace workarounds that later 8064 did not. Not sure
> >>> if that is the only such example, but it is one that userspace needed
> >>> to be aware of.
> >>
> >> Good question. I don't have nexus4, and both nexus7 and ifc6410 work fine.
> >>
> >> And this is a perfect use case for "qcom,apq8064-v1.1-adreno" compat string.
> >
> > I no longer have a n4 that boots.. but if I did both it and the later
> > ones should work properly if they expose the appropriate chip id
> >
> > I do still prefer parsing the chip-id out of the compatible. It
> > avoids needing separate table entries just to have a different
> > chip-id. Maybe the scheme that is used elsewhere makes sense when it
> > is only the kernel that needs to be aware of the device-id. And maybe
> > we could just done matching based on compat-id in userspace as well,
> > but (a) msm and freedreno pre-date dt, and (b) that ship has already
> > sailed.
> I think a per-soc dt would be the better approach..
The newer rev of apq8064 would need its own dt w/ compatible override
in either case. But if we continue with the current scheme parsing
the compatible, we don't need an extra gpu table entry for it.
BR,
-R
> We could probably solve the revision issue with a socid readout of
> the silicon revision and override based on that?
>
> Konrad
>
^ permalink raw reply [flat|nested] 73+ messages in thread
* Re: [Freedreno] [PATCH 06/12] drm/msm/adreno: Allow SoC specific gpu device table entries
2023-07-26 22:33 ` Dmitry Baryshkov
2023-07-26 22:53 ` Rob Clark
@ 2023-07-27 21:13 ` Rob Clark
2023-07-27 22:02 ` Dmitry Baryshkov
1 sibling, 1 reply; 73+ messages in thread
From: Rob Clark @ 2023-07-27 21:13 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Rob Clark, Akhil P Oommen, linux-arm-msm, dri-devel,
Konrad Dybcio, freedreno
On Wed, Jul 26, 2023 at 3:33 PM Dmitry Baryshkov
<dmitry.baryshkov@linaro.org> wrote:
>
> On Thu, 27 Jul 2023 at 01:04, Rob Clark <robdclark@gmail.com> wrote:
> >
> > On Wed, Jul 26, 2023 at 2:43 PM Dmitry Baryshkov
> > <dmitry.baryshkov@linaro.org> wrote:
> > >
> > > On 26/07/2023 23:11, Rob Clark wrote:
> > > > On Wed, Jul 26, 2023 at 1:00 PM Dmitry Baryshkov
> > > > <dmitry.baryshkov@linaro.org> wrote:
> > > >>
> > > >> On Wed, 26 Jul 2023 at 21:28, Rob Clark <robdclark@gmail.com> wrote:
> > > >>>
> > > >>> On Thu, Jul 13, 2023 at 1:26 PM Akhil P Oommen <quic_akhilpo@quicinc.com> wrote:
> > > >>>>
> > > >>>> On Fri, Jul 07, 2023 at 05:34:04AM +0300, Dmitry Baryshkov wrote:
> > > >>>>>
> > > >>>>> On 07/07/2023 00:10, Rob Clark wrote:
> > > >>>>>> From: Rob Clark <robdclark@chromium.org>
> > > >>>>>>
> > > >>>>>> There are cases where there are differences due to SoC integration.
> > > >>>>>> Such as cache-coherency support, and (in the next patch) e-fuse to
> > > >>>>>> speedbin mappings.
> > > >>>>>
> > > >>>>> I have the feeling that we are trying to circumvent the way DT works. I'd
> > > >>>>> suggest adding explicit SoC-compatible strings to Adreno bindings and then
> > > >>>>> using of_device_id::data and then of_device_get_match_data().
> > > >>>>>
> > > >>>> Just thinking, then how about a unique compatible string which we match
> > > >>>> to identify gpu->info and drop chip-id check completely here?
> > > >>>
> > > >>> Ok, I think we could do this, so something like:
> > > >>>
> > > >>> compatible = "qcom,sm4350-adreno-619.0", qcom,adreno-619.0", "qcom,adreno"
> > > >>>
> > > >>> ?
> > > >>>
> > > >>> It looks like we don't have gpu dt bits upstream yet for either sm4350
> > > >>> or sm6375, so I suppose we could get away with this change
> > > >>
> > > >> I think we can even skip the 619.0 part in the SoC compat string.
> > > >> So it will be:
> > > >>
> > > >> compatible = "qcom,sm4350-adreno", qcom,adreno-619.0", "qcom,adreno";
> > > >>
> > > >> In future we can drop the chipid part completely and handle that as a
> > > >> part of SoC data:
> > > >>
> > > >> compatible = "qcom,sm4350-adreno", "qcom,adreno";
> > > >>
> > > >> With the driver knowing that sm4350-adreno means ADRENO_ID(6,1,9,0)
> > > >>
> > > >
> > > > I don't think we can do that, there are cases where the same SoC had
> > > > multiple revisions of adreno.
> > >
> > > Is that the case for the production versions of the SoC? In other
> > > subsystems what we usually do is that we add support only for the latest
> > > SoC revision (which would probably mean the latest GPU patch revision).
> > > Previous GPU revisions can be added in the following way (pure example):
> > >
> > > qcom,sm4350-adreno -> 6,1,9,1 // assuming v2.0 or v1.1 is the commercial
> > > sample
> > > qcom,sm4350-v1-adreno -> 6,1,9,0
> > >
> >
> > My recollection was that nexus4 shipped with an early version of 8064
> > which needed userspace workarounds that later 8064 did not. Not sure
> > if that is the only such example, but it is one that userspace needed
> > to be aware of.
>
> Good question. I don't have nexus4, and both nexus7 and ifc6410 work fine.
>
> And this is a perfect use case for "qcom,apq8064-v1.1-adreno" compat string.
At this point, I'm failing to see why my original solution of just
checking of_machine_is_compatible() is worse ;-)
I mean what is the difference between checking
"qcom,apq8064-v1.1-adreno" and "qcom,apq8064-v1.1". I wouldn't really
want to use of_match_node() in either case.
BR,
-R
> >
> > Anyways, future things, it sounds like we'll be able to read the id
> > from the hw/fw. I'm not really a fan of breaking dtb fwd/bk compat,
> > so I don't want to change any of the existing compat strings.
>
> I think so too. Current compat strings should stay.
>
> >
> > BR,
> > -R
> >
> > > > We could possibly do that with future
> > > > things where we can read the chip-id from fw.
> > > >
> > > > What we _could_ do at the expense of making the compatible parsing a
> > > > tiny bit more complex is something like:
> > > >
> > > > compatible = "qcom,sm4350-adreno-619.0", "qcom,adreno"
> > > >
> > > > BR,
> > > > -R
> > > >
> > > >>>
> > > >>> BR,
> > > >>> -R
> > > >>>
> > > >>>> -Akhil
> > > >>>>
> > > >>>>>>
> > > >>>>>> Signed-off-by: Rob Clark <robdclark@chromium.org>
> > > >>>>>> ---
> > > >>>>>> drivers/gpu/drm/msm/adreno/adreno_device.c | 34 +++++++++++++++++++---
> > > >>>>>> drivers/gpu/drm/msm/adreno/adreno_gpu.h | 1 +
> > > >>>>>> 2 files changed, 31 insertions(+), 4 deletions(-)
> > > >>>>>>
> > > >>>>>> diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c
> > > >>>>>> index 3c531da417b9..e62bc895a31f 100644
> > > >>>>>> --- a/drivers/gpu/drm/msm/adreno/adreno_device.c
> > > >>>>>> +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c
> > > >>>>>> @@ -258,6 +258,32 @@ static const struct adreno_info gpulist[] = {
> > > >>>>>> .inactive_period = DRM_MSM_INACTIVE_PERIOD,
> > > >>>>>> .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT,
> > > >>>>>> .init = a6xx_gpu_init,
> > > >>>>>> + }, {
> > > >>>>>> + .machine = "qcom,sm4350",
> > > >>>>>> + .rev = ADRENO_REV(6, 1, 9, ANY_ID),
> > > >>>>>> + .revn = 619,
> > > >>>>>> + .fw = {
> > > >>>>>> + [ADRENO_FW_SQE] = "a630_sqe.fw",
> > > >>>>>> + [ADRENO_FW_GMU] = "a619_gmu.bin",
> > > >>>>>> + },
> > > >>>>>> + .gmem = SZ_512K,
> > > >>>>>> + .inactive_period = DRM_MSM_INACTIVE_PERIOD,
> > > >>>>>> + .init = a6xx_gpu_init,
> > > >>>>>> + .zapfw = "a615_zap.mdt",
> > > >>>>>> + .hwcg = a615_hwcg,
> > > >>>>>> + }, {
> > > >>>>>> + .machine = "qcom,sm6375",
> > > >>>>>> + .rev = ADRENO_REV(6, 1, 9, ANY_ID),
> > > >>>>>> + .revn = 619,
> > > >>>>>> + .fw = {
> > > >>>>>> + [ADRENO_FW_SQE] = "a630_sqe.fw",
> > > >>>>>> + [ADRENO_FW_GMU] = "a619_gmu.bin",
> > > >>>>>> + },
> > > >>>>>> + .gmem = SZ_512K,
> > > >>>>>> + .inactive_period = DRM_MSM_INACTIVE_PERIOD,
> > > >>>>>> + .init = a6xx_gpu_init,
> > > >>>>>> + .zapfw = "a615_zap.mdt",
> > > >>>>>> + .hwcg = a615_hwcg,
> > > >>>>>> }, {
> > > >>>>>> .rev = ADRENO_REV(6, 1, 9, ANY_ID),
> > > >>>>>> .revn = 619,
> > > >>>>>> @@ -409,6 +435,8 @@ const struct adreno_info *adreno_info(struct adreno_rev rev)
> > > >>>>>> /* identify gpu: */
> > > >>>>>> for (i = 0; i < ARRAY_SIZE(gpulist); i++) {
> > > >>>>>> const struct adreno_info *info = &gpulist[i];
> > > >>>>>> + if (info->machine && !of_machine_is_compatible(info->machine))
> > > >>>>>> + continue;
> > > >>>>>> if (adreno_cmp_rev(info->rev, rev))
> > > >>>>>> return info;
> > > >>>>>> }
> > > >>>>>> @@ -563,6 +591,8 @@ static int adreno_bind(struct device *dev, struct device *master, void *data)
> > > >>>>>> config.rev.minor, config.rev.patchid);
> > > >>>>>> priv->is_a2xx = config.rev.core == 2;
> > > >>>>>> + priv->has_cached_coherent =
> > > >>>>>> + !!(info->quirks & ADRENO_QUIRK_HAS_CACHED_COHERENT);
> > > >>>>>> gpu = info->init(drm);
> > > >>>>>> if (IS_ERR(gpu)) {
> > > >>>>>> @@ -574,10 +604,6 @@ static int adreno_bind(struct device *dev, struct device *master, void *data)
> > > >>>>>> if (ret)
> > > >>>>>> return ret;
> > > >>>>>> - priv->has_cached_coherent =
> > > >>>>>> - !!(info->quirks & ADRENO_QUIRK_HAS_CACHED_COHERENT) &&
> > > >>>>>> - !adreno_has_gmu_wrapper(to_adreno_gpu(gpu));
> > > >>>>>> -
> > > >>>>>> return 0;
> > > >>>>>> }
> > > >>>>>> diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> > > >>>>>> index e08d41337169..d5335b99c64c 100644
> > > >>>>>> --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> > > >>>>>> +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> > > >>>>>> @@ -61,6 +61,7 @@ extern const struct adreno_reglist a612_hwcg[], a615_hwcg[], a630_hwcg[], a640_h
> > > >>>>>> extern const struct adreno_reglist a660_hwcg[], a690_hwcg[];
> > > >>>>>> struct adreno_info {
> > > >>>>>> + const char *machine;
> > > >>>>>> struct adreno_rev rev;
> > > >>>>>> uint32_t revn;
> > > >>>>>> const char *fw[ADRENO_FW_MAX];
> > > >>>>>
> > > >>>>> --
> > > >>>>> With best wishes
> > > >>>>> Dmitry
> > > >>>>>
> > > >>
> > > >>
> > > >>
> > > >> --
> > > >> With best wishes
> > > >> Dmitry
> > >
> > > --
> > > With best wishes
> > > Dmitry
> > >
>
>
>
> --
> With best wishes
> Dmitry
^ permalink raw reply [flat|nested] 73+ messages in thread
* Re: [Freedreno] [PATCH 06/12] drm/msm/adreno: Allow SoC specific gpu device table entries
2023-07-27 21:13 ` Rob Clark
@ 2023-07-27 22:02 ` Dmitry Baryshkov
2023-07-28 14:43 ` Rob Clark
0 siblings, 1 reply; 73+ messages in thread
From: Dmitry Baryshkov @ 2023-07-27 22:02 UTC (permalink / raw)
To: Rob Clark
Cc: Rob Clark, Akhil P Oommen, linux-arm-msm, dri-devel,
Konrad Dybcio, freedreno
On Fri, 28 Jul 2023 at 00:13, Rob Clark <robdclark@gmail.com> wrote:
>
> On Wed, Jul 26, 2023 at 3:33 PM Dmitry Baryshkov
> <dmitry.baryshkov@linaro.org> wrote:
> >
> > On Thu, 27 Jul 2023 at 01:04, Rob Clark <robdclark@gmail.com> wrote:
> > >
> > > On Wed, Jul 26, 2023 at 2:43 PM Dmitry Baryshkov
> > > <dmitry.baryshkov@linaro.org> wrote:
> > > >
> > > > On 26/07/2023 23:11, Rob Clark wrote:
> > > > > On Wed, Jul 26, 2023 at 1:00 PM Dmitry Baryshkov
> > > > > <dmitry.baryshkov@linaro.org> wrote:
> > > > >>
> > > > >> On Wed, 26 Jul 2023 at 21:28, Rob Clark <robdclark@gmail.com> wrote:
> > > > >>>
> > > > >>> On Thu, Jul 13, 2023 at 1:26 PM Akhil P Oommen <quic_akhilpo@quicinc.com> wrote:
> > > > >>>>
> > > > >>>> On Fri, Jul 07, 2023 at 05:34:04AM +0300, Dmitry Baryshkov wrote:
> > > > >>>>>
> > > > >>>>> On 07/07/2023 00:10, Rob Clark wrote:
> > > > >>>>>> From: Rob Clark <robdclark@chromium.org>
> > > > >>>>>>
> > > > >>>>>> There are cases where there are differences due to SoC integration.
> > > > >>>>>> Such as cache-coherency support, and (in the next patch) e-fuse to
> > > > >>>>>> speedbin mappings.
> > > > >>>>>
> > > > >>>>> I have the feeling that we are trying to circumvent the way DT works. I'd
> > > > >>>>> suggest adding explicit SoC-compatible strings to Adreno bindings and then
> > > > >>>>> using of_device_id::data and then of_device_get_match_data().
> > > > >>>>>
> > > > >>>> Just thinking, then how about a unique compatible string which we match
> > > > >>>> to identify gpu->info and drop chip-id check completely here?
> > > > >>>
> > > > >>> Ok, I think we could do this, so something like:
> > > > >>>
> > > > >>> compatible = "qcom,sm4350-adreno-619.0", qcom,adreno-619.0", "qcom,adreno"
> > > > >>>
> > > > >>> ?
> > > > >>>
> > > > >>> It looks like we don't have gpu dt bits upstream yet for either sm4350
> > > > >>> or sm6375, so I suppose we could get away with this change
> > > > >>
> > > > >> I think we can even skip the 619.0 part in the SoC compat string.
> > > > >> So it will be:
> > > > >>
> > > > >> compatible = "qcom,sm4350-adreno", qcom,adreno-619.0", "qcom,adreno";
> > > > >>
> > > > >> In future we can drop the chipid part completely and handle that as a
> > > > >> part of SoC data:
> > > > >>
> > > > >> compatible = "qcom,sm4350-adreno", "qcom,adreno";
> > > > >>
> > > > >> With the driver knowing that sm4350-adreno means ADRENO_ID(6,1,9,0)
> > > > >>
> > > > >
> > > > > I don't think we can do that, there are cases where the same SoC had
> > > > > multiple revisions of adreno.
> > > >
> > > > Is that the case for the production versions of the SoC? In other
> > > > subsystems what we usually do is that we add support only for the latest
> > > > SoC revision (which would probably mean the latest GPU patch revision).
> > > > Previous GPU revisions can be added in the following way (pure example):
> > > >
> > > > qcom,sm4350-adreno -> 6,1,9,1 // assuming v2.0 or v1.1 is the commercial
> > > > sample
> > > > qcom,sm4350-v1-adreno -> 6,1,9,0
> > > >
> > >
> > > My recollection was that nexus4 shipped with an early version of 8064
> > > which needed userspace workarounds that later 8064 did not. Not sure
> > > if that is the only such example, but it is one that userspace needed
> > > to be aware of.
> >
> > Good question. I don't have nexus4, and both nexus7 and ifc6410 work fine.
> >
> > And this is a perfect use case for "qcom,apq8064-v1.1-adreno" compat string.
>
> At this point, I'm failing to see why my original solution of just
> checking of_machine_is_compatible() is worse ;-)
>
> I mean what is the difference between checking
> "qcom,apq8064-v1.1-adreno" and "qcom,apq8064-v1.1". I wouldn't really
> want to use of_match_node() in either case.
I have been proposing to use of_device_get_match_data().
>
> BR,
> -R
>
> > >
> > > Anyways, future things, it sounds like we'll be able to read the id
> > > from the hw/fw. I'm not really a fan of breaking dtb fwd/bk compat,
> > > so I don't want to change any of the existing compat strings.
> >
> > I think so too. Current compat strings should stay.
> >
> > >
> > > BR,
> > > -R
> > >
> > > > > We could possibly do that with future
> > > > > things where we can read the chip-id from fw.
> > > > >
> > > > > What we _could_ do at the expense of making the compatible parsing a
> > > > > tiny bit more complex is something like:
> > > > >
> > > > > compatible = "qcom,sm4350-adreno-619.0", "qcom,adreno"
> > > > >
> > > > > BR,
> > > > > -R
> > > > >
> > > > >>>
> > > > >>> BR,
> > > > >>> -R
> > > > >>>
> > > > >>>> -Akhil
> > > > >>>>
> > > > >>>>>>
> > > > >>>>>> Signed-off-by: Rob Clark <robdclark@chromium.org>
> > > > >>>>>> ---
> > > > >>>>>> drivers/gpu/drm/msm/adreno/adreno_device.c | 34 +++++++++++++++++++---
> > > > >>>>>> drivers/gpu/drm/msm/adreno/adreno_gpu.h | 1 +
> > > > >>>>>> 2 files changed, 31 insertions(+), 4 deletions(-)
> > > > >>>>>>
> > > > >>>>>> diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c
> > > > >>>>>> index 3c531da417b9..e62bc895a31f 100644
> > > > >>>>>> --- a/drivers/gpu/drm/msm/adreno/adreno_device.c
> > > > >>>>>> +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c
> > > > >>>>>> @@ -258,6 +258,32 @@ static const struct adreno_info gpulist[] = {
> > > > >>>>>> .inactive_period = DRM_MSM_INACTIVE_PERIOD,
> > > > >>>>>> .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT,
> > > > >>>>>> .init = a6xx_gpu_init,
> > > > >>>>>> + }, {
> > > > >>>>>> + .machine = "qcom,sm4350",
> > > > >>>>>> + .rev = ADRENO_REV(6, 1, 9, ANY_ID),
> > > > >>>>>> + .revn = 619,
> > > > >>>>>> + .fw = {
> > > > >>>>>> + [ADRENO_FW_SQE] = "a630_sqe.fw",
> > > > >>>>>> + [ADRENO_FW_GMU] = "a619_gmu.bin",
> > > > >>>>>> + },
> > > > >>>>>> + .gmem = SZ_512K,
> > > > >>>>>> + .inactive_period = DRM_MSM_INACTIVE_PERIOD,
> > > > >>>>>> + .init = a6xx_gpu_init,
> > > > >>>>>> + .zapfw = "a615_zap.mdt",
> > > > >>>>>> + .hwcg = a615_hwcg,
> > > > >>>>>> + }, {
> > > > >>>>>> + .machine = "qcom,sm6375",
> > > > >>>>>> + .rev = ADRENO_REV(6, 1, 9, ANY_ID),
> > > > >>>>>> + .revn = 619,
> > > > >>>>>> + .fw = {
> > > > >>>>>> + [ADRENO_FW_SQE] = "a630_sqe.fw",
> > > > >>>>>> + [ADRENO_FW_GMU] = "a619_gmu.bin",
> > > > >>>>>> + },
> > > > >>>>>> + .gmem = SZ_512K,
> > > > >>>>>> + .inactive_period = DRM_MSM_INACTIVE_PERIOD,
> > > > >>>>>> + .init = a6xx_gpu_init,
> > > > >>>>>> + .zapfw = "a615_zap.mdt",
> > > > >>>>>> + .hwcg = a615_hwcg,
> > > > >>>>>> }, {
> > > > >>>>>> .rev = ADRENO_REV(6, 1, 9, ANY_ID),
> > > > >>>>>> .revn = 619,
> > > > >>>>>> @@ -409,6 +435,8 @@ const struct adreno_info *adreno_info(struct adreno_rev rev)
> > > > >>>>>> /* identify gpu: */
> > > > >>>>>> for (i = 0; i < ARRAY_SIZE(gpulist); i++) {
> > > > >>>>>> const struct adreno_info *info = &gpulist[i];
> > > > >>>>>> + if (info->machine && !of_machine_is_compatible(info->machine))
> > > > >>>>>> + continue;
> > > > >>>>>> if (adreno_cmp_rev(info->rev, rev))
> > > > >>>>>> return info;
> > > > >>>>>> }
> > > > >>>>>> @@ -563,6 +591,8 @@ static int adreno_bind(struct device *dev, struct device *master, void *data)
> > > > >>>>>> config.rev.minor, config.rev.patchid);
> > > > >>>>>> priv->is_a2xx = config.rev.core == 2;
> > > > >>>>>> + priv->has_cached_coherent =
> > > > >>>>>> + !!(info->quirks & ADRENO_QUIRK_HAS_CACHED_COHERENT);
> > > > >>>>>> gpu = info->init(drm);
> > > > >>>>>> if (IS_ERR(gpu)) {
> > > > >>>>>> @@ -574,10 +604,6 @@ static int adreno_bind(struct device *dev, struct device *master, void *data)
> > > > >>>>>> if (ret)
> > > > >>>>>> return ret;
> > > > >>>>>> - priv->has_cached_coherent =
> > > > >>>>>> - !!(info->quirks & ADRENO_QUIRK_HAS_CACHED_COHERENT) &&
> > > > >>>>>> - !adreno_has_gmu_wrapper(to_adreno_gpu(gpu));
> > > > >>>>>> -
> > > > >>>>>> return 0;
> > > > >>>>>> }
> > > > >>>>>> diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> > > > >>>>>> index e08d41337169..d5335b99c64c 100644
> > > > >>>>>> --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> > > > >>>>>> +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> > > > >>>>>> @@ -61,6 +61,7 @@ extern const struct adreno_reglist a612_hwcg[], a615_hwcg[], a630_hwcg[], a640_h
> > > > >>>>>> extern const struct adreno_reglist a660_hwcg[], a690_hwcg[];
> > > > >>>>>> struct adreno_info {
> > > > >>>>>> + const char *machine;
> > > > >>>>>> struct adreno_rev rev;
> > > > >>>>>> uint32_t revn;
> > > > >>>>>> const char *fw[ADRENO_FW_MAX];
> > > > >>>>>
> > > > >>>>> --
> > > > >>>>> With best wishes
> > > > >>>>> Dmitry
> > > > >>>>>
> > > > >>
> > > > >>
> > > > >>
> > > > >> --
> > > > >> With best wishes
> > > > >> Dmitry
> > > >
> > > > --
> > > > With best wishes
> > > > Dmitry
> > > >
> >
> >
> >
> > --
> > With best wishes
> > Dmitry
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 73+ messages in thread
* Re: [Freedreno] [PATCH 06/12] drm/msm/adreno: Allow SoC specific gpu device table entries
2023-07-27 22:02 ` Dmitry Baryshkov
@ 2023-07-28 14:43 ` Rob Clark
2023-07-28 14:51 ` Dmitry Baryshkov
0 siblings, 1 reply; 73+ messages in thread
From: Rob Clark @ 2023-07-28 14:43 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Rob Clark, Akhil P Oommen, linux-arm-msm, dri-devel,
Konrad Dybcio, freedreno
On Thu, Jul 27, 2023 at 3:02 PM Dmitry Baryshkov
<dmitry.baryshkov@linaro.org> wrote:
>
> On Fri, 28 Jul 2023 at 00:13, Rob Clark <robdclark@gmail.com> wrote:
> >
> > On Wed, Jul 26, 2023 at 3:33 PM Dmitry Baryshkov
> > <dmitry.baryshkov@linaro.org> wrote:
> > >
> > > On Thu, 27 Jul 2023 at 01:04, Rob Clark <robdclark@gmail.com> wrote:
> > > >
> > > > On Wed, Jul 26, 2023 at 2:43 PM Dmitry Baryshkov
> > > > <dmitry.baryshkov@linaro.org> wrote:
> > > > >
> > > > > On 26/07/2023 23:11, Rob Clark wrote:
> > > > > > On Wed, Jul 26, 2023 at 1:00 PM Dmitry Baryshkov
> > > > > > <dmitry.baryshkov@linaro.org> wrote:
> > > > > >>
> > > > > >> On Wed, 26 Jul 2023 at 21:28, Rob Clark <robdclark@gmail.com> wrote:
> > > > > >>>
> > > > > >>> On Thu, Jul 13, 2023 at 1:26 PM Akhil P Oommen <quic_akhilpo@quicinc.com> wrote:
> > > > > >>>>
> > > > > >>>> On Fri, Jul 07, 2023 at 05:34:04AM +0300, Dmitry Baryshkov wrote:
> > > > > >>>>>
> > > > > >>>>> On 07/07/2023 00:10, Rob Clark wrote:
> > > > > >>>>>> From: Rob Clark <robdclark@chromium.org>
> > > > > >>>>>>
> > > > > >>>>>> There are cases where there are differences due to SoC integration.
> > > > > >>>>>> Such as cache-coherency support, and (in the next patch) e-fuse to
> > > > > >>>>>> speedbin mappings.
> > > > > >>>>>
> > > > > >>>>> I have the feeling that we are trying to circumvent the way DT works. I'd
> > > > > >>>>> suggest adding explicit SoC-compatible strings to Adreno bindings and then
> > > > > >>>>> using of_device_id::data and then of_device_get_match_data().
> > > > > >>>>>
> > > > > >>>> Just thinking, then how about a unique compatible string which we match
> > > > > >>>> to identify gpu->info and drop chip-id check completely here?
> > > > > >>>
> > > > > >>> Ok, I think we could do this, so something like:
> > > > > >>>
> > > > > >>> compatible = "qcom,sm4350-adreno-619.0", qcom,adreno-619.0", "qcom,adreno"
> > > > > >>>
> > > > > >>> ?
> > > > > >>>
> > > > > >>> It looks like we don't have gpu dt bits upstream yet for either sm4350
> > > > > >>> or sm6375, so I suppose we could get away with this change
> > > > > >>
> > > > > >> I think we can even skip the 619.0 part in the SoC compat string.
> > > > > >> So it will be:
> > > > > >>
> > > > > >> compatible = "qcom,sm4350-adreno", qcom,adreno-619.0", "qcom,adreno";
> > > > > >>
> > > > > >> In future we can drop the chipid part completely and handle that as a
> > > > > >> part of SoC data:
> > > > > >>
> > > > > >> compatible = "qcom,sm4350-adreno", "qcom,adreno";
> > > > > >>
> > > > > >> With the driver knowing that sm4350-adreno means ADRENO_ID(6,1,9,0)
> > > > > >>
> > > > > >
> > > > > > I don't think we can do that, there are cases where the same SoC had
> > > > > > multiple revisions of adreno.
> > > > >
> > > > > Is that the case for the production versions of the SoC? In other
> > > > > subsystems what we usually do is that we add support only for the latest
> > > > > SoC revision (which would probably mean the latest GPU patch revision).
> > > > > Previous GPU revisions can be added in the following way (pure example):
> > > > >
> > > > > qcom,sm4350-adreno -> 6,1,9,1 // assuming v2.0 or v1.1 is the commercial
> > > > > sample
> > > > > qcom,sm4350-v1-adreno -> 6,1,9,0
> > > > >
> > > >
> > > > My recollection was that nexus4 shipped with an early version of 8064
> > > > which needed userspace workarounds that later 8064 did not. Not sure
> > > > if that is the only such example, but it is one that userspace needed
> > > > to be aware of.
> > >
> > > Good question. I don't have nexus4, and both nexus7 and ifc6410 work fine.
> > >
> > > And this is a perfect use case for "qcom,apq8064-v1.1-adreno" compat string.
> >
> > At this point, I'm failing to see why my original solution of just
> > checking of_machine_is_compatible() is worse ;-)
> >
> > I mean what is the difference between checking
> > "qcom,apq8064-v1.1-adreno" and "qcom,apq8064-v1.1". I wouldn't really
> > want to use of_match_node() in either case.
>
> I have been proposing to use of_device_get_match_data().
That has the same limitation when it comes to our needs.. our current
setup lets us have a single table entry that matches multiple
chip-id's. I don't really see the point of using of_match_node() or
of_device_get_match_data() just for the sake of using them.
BR,
-R
> >
> > BR,
> > -R
> >
> > > >
> > > > Anyways, future things, it sounds like we'll be able to read the id
> > > > from the hw/fw. I'm not really a fan of breaking dtb fwd/bk compat,
> > > > so I don't want to change any of the existing compat strings.
> > >
> > > I think so too. Current compat strings should stay.
> > >
> > > >
> > > > BR,
> > > > -R
> > > >
> > > > > > We could possibly do that with future
> > > > > > things where we can read the chip-id from fw.
> > > > > >
> > > > > > What we _could_ do at the expense of making the compatible parsing a
> > > > > > tiny bit more complex is something like:
> > > > > >
> > > > > > compatible = "qcom,sm4350-adreno-619.0", "qcom,adreno"
> > > > > >
> > > > > > BR,
> > > > > > -R
> > > > > >
> > > > > >>>
> > > > > >>> BR,
> > > > > >>> -R
> > > > > >>>
> > > > > >>>> -Akhil
> > > > > >>>>
> > > > > >>>>>>
> > > > > >>>>>> Signed-off-by: Rob Clark <robdclark@chromium.org>
> > > > > >>>>>> ---
> > > > > >>>>>> drivers/gpu/drm/msm/adreno/adreno_device.c | 34 +++++++++++++++++++---
> > > > > >>>>>> drivers/gpu/drm/msm/adreno/adreno_gpu.h | 1 +
> > > > > >>>>>> 2 files changed, 31 insertions(+), 4 deletions(-)
> > > > > >>>>>>
> > > > > >>>>>> diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c
> > > > > >>>>>> index 3c531da417b9..e62bc895a31f 100644
> > > > > >>>>>> --- a/drivers/gpu/drm/msm/adreno/adreno_device.c
> > > > > >>>>>> +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c
> > > > > >>>>>> @@ -258,6 +258,32 @@ static const struct adreno_info gpulist[] = {
> > > > > >>>>>> .inactive_period = DRM_MSM_INACTIVE_PERIOD,
> > > > > >>>>>> .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT,
> > > > > >>>>>> .init = a6xx_gpu_init,
> > > > > >>>>>> + }, {
> > > > > >>>>>> + .machine = "qcom,sm4350",
> > > > > >>>>>> + .rev = ADRENO_REV(6, 1, 9, ANY_ID),
> > > > > >>>>>> + .revn = 619,
> > > > > >>>>>> + .fw = {
> > > > > >>>>>> + [ADRENO_FW_SQE] = "a630_sqe.fw",
> > > > > >>>>>> + [ADRENO_FW_GMU] = "a619_gmu.bin",
> > > > > >>>>>> + },
> > > > > >>>>>> + .gmem = SZ_512K,
> > > > > >>>>>> + .inactive_period = DRM_MSM_INACTIVE_PERIOD,
> > > > > >>>>>> + .init = a6xx_gpu_init,
> > > > > >>>>>> + .zapfw = "a615_zap.mdt",
> > > > > >>>>>> + .hwcg = a615_hwcg,
> > > > > >>>>>> + }, {
> > > > > >>>>>> + .machine = "qcom,sm6375",
> > > > > >>>>>> + .rev = ADRENO_REV(6, 1, 9, ANY_ID),
> > > > > >>>>>> + .revn = 619,
> > > > > >>>>>> + .fw = {
> > > > > >>>>>> + [ADRENO_FW_SQE] = "a630_sqe.fw",
> > > > > >>>>>> + [ADRENO_FW_GMU] = "a619_gmu.bin",
> > > > > >>>>>> + },
> > > > > >>>>>> + .gmem = SZ_512K,
> > > > > >>>>>> + .inactive_period = DRM_MSM_INACTIVE_PERIOD,
> > > > > >>>>>> + .init = a6xx_gpu_init,
> > > > > >>>>>> + .zapfw = "a615_zap.mdt",
> > > > > >>>>>> + .hwcg = a615_hwcg,
> > > > > >>>>>> }, {
> > > > > >>>>>> .rev = ADRENO_REV(6, 1, 9, ANY_ID),
> > > > > >>>>>> .revn = 619,
> > > > > >>>>>> @@ -409,6 +435,8 @@ const struct adreno_info *adreno_info(struct adreno_rev rev)
> > > > > >>>>>> /* identify gpu: */
> > > > > >>>>>> for (i = 0; i < ARRAY_SIZE(gpulist); i++) {
> > > > > >>>>>> const struct adreno_info *info = &gpulist[i];
> > > > > >>>>>> + if (info->machine && !of_machine_is_compatible(info->machine))
> > > > > >>>>>> + continue;
> > > > > >>>>>> if (adreno_cmp_rev(info->rev, rev))
> > > > > >>>>>> return info;
> > > > > >>>>>> }
> > > > > >>>>>> @@ -563,6 +591,8 @@ static int adreno_bind(struct device *dev, struct device *master, void *data)
> > > > > >>>>>> config.rev.minor, config.rev.patchid);
> > > > > >>>>>> priv->is_a2xx = config.rev.core == 2;
> > > > > >>>>>> + priv->has_cached_coherent =
> > > > > >>>>>> + !!(info->quirks & ADRENO_QUIRK_HAS_CACHED_COHERENT);
> > > > > >>>>>> gpu = info->init(drm);
> > > > > >>>>>> if (IS_ERR(gpu)) {
> > > > > >>>>>> @@ -574,10 +604,6 @@ static int adreno_bind(struct device *dev, struct device *master, void *data)
> > > > > >>>>>> if (ret)
> > > > > >>>>>> return ret;
> > > > > >>>>>> - priv->has_cached_coherent =
> > > > > >>>>>> - !!(info->quirks & ADRENO_QUIRK_HAS_CACHED_COHERENT) &&
> > > > > >>>>>> - !adreno_has_gmu_wrapper(to_adreno_gpu(gpu));
> > > > > >>>>>> -
> > > > > >>>>>> return 0;
> > > > > >>>>>> }
> > > > > >>>>>> diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> > > > > >>>>>> index e08d41337169..d5335b99c64c 100644
> > > > > >>>>>> --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> > > > > >>>>>> +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> > > > > >>>>>> @@ -61,6 +61,7 @@ extern const struct adreno_reglist a612_hwcg[], a615_hwcg[], a630_hwcg[], a640_h
> > > > > >>>>>> extern const struct adreno_reglist a660_hwcg[], a690_hwcg[];
> > > > > >>>>>> struct adreno_info {
> > > > > >>>>>> + const char *machine;
> > > > > >>>>>> struct adreno_rev rev;
> > > > > >>>>>> uint32_t revn;
> > > > > >>>>>> const char *fw[ADRENO_FW_MAX];
> > > > > >>>>>
> > > > > >>>>> --
> > > > > >>>>> With best wishes
> > > > > >>>>> Dmitry
> > > > > >>>>>
> > > > > >>
> > > > > >>
> > > > > >>
> > > > > >> --
> > > > > >> With best wishes
> > > > > >> Dmitry
> > > > >
> > > > > --
> > > > > With best wishes
> > > > > Dmitry
> > > > >
> > >
> > >
> > >
> > > --
> > > With best wishes
> > > Dmitry
>
>
>
> --
> With best wishes
> Dmitry
^ permalink raw reply [flat|nested] 73+ messages in thread
* Re: [Freedreno] [PATCH 06/12] drm/msm/adreno: Allow SoC specific gpu device table entries
2023-07-28 14:43 ` Rob Clark
@ 2023-07-28 14:51 ` Dmitry Baryshkov
0 siblings, 0 replies; 73+ messages in thread
From: Dmitry Baryshkov @ 2023-07-28 14:51 UTC (permalink / raw)
To: Rob Clark
Cc: Rob Clark, Akhil P Oommen, linux-arm-msm, dri-devel,
Konrad Dybcio, freedreno
On Fri, 28 Jul 2023 at 17:43, Rob Clark <robdclark@gmail.com> wrote:
>
> On Thu, Jul 27, 2023 at 3:02 PM Dmitry Baryshkov
> <dmitry.baryshkov@linaro.org> wrote:
> >
> > On Fri, 28 Jul 2023 at 00:13, Rob Clark <robdclark@gmail.com> wrote:
> > >
> > > On Wed, Jul 26, 2023 at 3:33 PM Dmitry Baryshkov
> > > <dmitry.baryshkov@linaro.org> wrote:
> > > >
> > > > On Thu, 27 Jul 2023 at 01:04, Rob Clark <robdclark@gmail.com> wrote:
> > > > >
> > > > > On Wed, Jul 26, 2023 at 2:43 PM Dmitry Baryshkov
> > > > > <dmitry.baryshkov@linaro.org> wrote:
> > > > > >
> > > > > > On 26/07/2023 23:11, Rob Clark wrote:
> > > > > > > On Wed, Jul 26, 2023 at 1:00 PM Dmitry Baryshkov
> > > > > > > <dmitry.baryshkov@linaro.org> wrote:
> > > > > > >>
> > > > > > >> On Wed, 26 Jul 2023 at 21:28, Rob Clark <robdclark@gmail.com> wrote:
> > > > > > >>>
> > > > > > >>> On Thu, Jul 13, 2023 at 1:26 PM Akhil P Oommen <quic_akhilpo@quicinc.com> wrote:
> > > > > > >>>>
> > > > > > >>>> On Fri, Jul 07, 2023 at 05:34:04AM +0300, Dmitry Baryshkov wrote:
> > > > > > >>>>>
> > > > > > >>>>> On 07/07/2023 00:10, Rob Clark wrote:
> > > > > > >>>>>> From: Rob Clark <robdclark@chromium.org>
> > > > > > >>>>>>
> > > > > > >>>>>> There are cases where there are differences due to SoC integration.
> > > > > > >>>>>> Such as cache-coherency support, and (in the next patch) e-fuse to
> > > > > > >>>>>> speedbin mappings.
> > > > > > >>>>>
> > > > > > >>>>> I have the feeling that we are trying to circumvent the way DT works. I'd
> > > > > > >>>>> suggest adding explicit SoC-compatible strings to Adreno bindings and then
> > > > > > >>>>> using of_device_id::data and then of_device_get_match_data().
> > > > > > >>>>>
> > > > > > >>>> Just thinking, then how about a unique compatible string which we match
> > > > > > >>>> to identify gpu->info and drop chip-id check completely here?
> > > > > > >>>
> > > > > > >>> Ok, I think we could do this, so something like:
> > > > > > >>>
> > > > > > >>> compatible = "qcom,sm4350-adreno-619.0", qcom,adreno-619.0", "qcom,adreno"
> > > > > > >>>
> > > > > > >>> ?
> > > > > > >>>
> > > > > > >>> It looks like we don't have gpu dt bits upstream yet for either sm4350
> > > > > > >>> or sm6375, so I suppose we could get away with this change
> > > > > > >>
> > > > > > >> I think we can even skip the 619.0 part in the SoC compat string.
> > > > > > >> So it will be:
> > > > > > >>
> > > > > > >> compatible = "qcom,sm4350-adreno", qcom,adreno-619.0", "qcom,adreno";
> > > > > > >>
> > > > > > >> In future we can drop the chipid part completely and handle that as a
> > > > > > >> part of SoC data:
> > > > > > >>
> > > > > > >> compatible = "qcom,sm4350-adreno", "qcom,adreno";
> > > > > > >>
> > > > > > >> With the driver knowing that sm4350-adreno means ADRENO_ID(6,1,9,0)
> > > > > > >>
> > > > > > >
> > > > > > > I don't think we can do that, there are cases where the same SoC had
> > > > > > > multiple revisions of adreno.
> > > > > >
> > > > > > Is that the case for the production versions of the SoC? In other
> > > > > > subsystems what we usually do is that we add support only for the latest
> > > > > > SoC revision (which would probably mean the latest GPU patch revision).
> > > > > > Previous GPU revisions can be added in the following way (pure example):
> > > > > >
> > > > > > qcom,sm4350-adreno -> 6,1,9,1 // assuming v2.0 or v1.1 is the commercial
> > > > > > sample
> > > > > > qcom,sm4350-v1-adreno -> 6,1,9,0
> > > > > >
> > > > >
> > > > > My recollection was that nexus4 shipped with an early version of 8064
> > > > > which needed userspace workarounds that later 8064 did not. Not sure
> > > > > if that is the only such example, but it is one that userspace needed
> > > > > to be aware of.
> > > >
> > > > Good question. I don't have nexus4, and both nexus7 and ifc6410 work fine.
> > > >
> > > > And this is a perfect use case for "qcom,apq8064-v1.1-adreno" compat string.
> > >
> > > At this point, I'm failing to see why my original solution of just
> > > checking of_machine_is_compatible() is worse ;-)
> > >
> > > I mean what is the difference between checking
> > > "qcom,apq8064-v1.1-adreno" and "qcom,apq8064-v1.1". I wouldn't really
> > > want to use of_match_node() in either case.
> >
> > I have been proposing to use of_device_get_match_data().
>
> That has the same limitation when it comes to our needs.. our current
> setup lets us have a single table entry that matches multiple
> chip-id's. I don't really see the point of using of_match_node() or
> of_device_get_match_data() just for the sake of using them.
My point was to be able to use SoC compat strings as the rest of the
kernel does.
But if you feel that the current approach fits our needs, let it be so.
>
> BR,
> -R
>
> > >
> > > BR,
> > > -R
> > >
> > > > >
> > > > > Anyways, future things, it sounds like we'll be able to read the id
> > > > > from the hw/fw. I'm not really a fan of breaking dtb fwd/bk compat,
> > > > > so I don't want to change any of the existing compat strings.
> > > >
> > > > I think so too. Current compat strings should stay.
> > > >
> > > > >
> > > > > BR,
> > > > > -R
> > > > >
> > > > > > > We could possibly do that with future
> > > > > > > things where we can read the chip-id from fw.
> > > > > > >
> > > > > > > What we _could_ do at the expense of making the compatible parsing a
> > > > > > > tiny bit more complex is something like:
> > > > > > >
> > > > > > > compatible = "qcom,sm4350-adreno-619.0", "qcom,adreno"
> > > > > > >
> > > > > > > BR,
> > > > > > > -R
> > > > > > >
> > > > > > >>>
> > > > > > >>> BR,
> > > > > > >>> -R
> > > > > > >>>
> > > > > > >>>> -Akhil
> > > > > > >>>>
> > > > > > >>>>>>
> > > > > > >>>>>> Signed-off-by: Rob Clark <robdclark@chromium.org>
> > > > > > >>>>>> ---
> > > > > > >>>>>> drivers/gpu/drm/msm/adreno/adreno_device.c | 34 +++++++++++++++++++---
> > > > > > >>>>>> drivers/gpu/drm/msm/adreno/adreno_gpu.h | 1 +
> > > > > > >>>>>> 2 files changed, 31 insertions(+), 4 deletions(-)
> > > > > > >>>>>>
> > > > > > >>>>>> diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c
> > > > > > >>>>>> index 3c531da417b9..e62bc895a31f 100644
> > > > > > >>>>>> --- a/drivers/gpu/drm/msm/adreno/adreno_device.c
> > > > > > >>>>>> +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c
> > > > > > >>>>>> @@ -258,6 +258,32 @@ static const struct adreno_info gpulist[] = {
> > > > > > >>>>>> .inactive_period = DRM_MSM_INACTIVE_PERIOD,
> > > > > > >>>>>> .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT,
> > > > > > >>>>>> .init = a6xx_gpu_init,
> > > > > > >>>>>> + }, {
> > > > > > >>>>>> + .machine = "qcom,sm4350",
> > > > > > >>>>>> + .rev = ADRENO_REV(6, 1, 9, ANY_ID),
> > > > > > >>>>>> + .revn = 619,
> > > > > > >>>>>> + .fw = {
> > > > > > >>>>>> + [ADRENO_FW_SQE] = "a630_sqe.fw",
> > > > > > >>>>>> + [ADRENO_FW_GMU] = "a619_gmu.bin",
> > > > > > >>>>>> + },
> > > > > > >>>>>> + .gmem = SZ_512K,
> > > > > > >>>>>> + .inactive_period = DRM_MSM_INACTIVE_PERIOD,
> > > > > > >>>>>> + .init = a6xx_gpu_init,
> > > > > > >>>>>> + .zapfw = "a615_zap.mdt",
> > > > > > >>>>>> + .hwcg = a615_hwcg,
> > > > > > >>>>>> + }, {
> > > > > > >>>>>> + .machine = "qcom,sm6375",
> > > > > > >>>>>> + .rev = ADRENO_REV(6, 1, 9, ANY_ID),
> > > > > > >>>>>> + .revn = 619,
> > > > > > >>>>>> + .fw = {
> > > > > > >>>>>> + [ADRENO_FW_SQE] = "a630_sqe.fw",
> > > > > > >>>>>> + [ADRENO_FW_GMU] = "a619_gmu.bin",
> > > > > > >>>>>> + },
> > > > > > >>>>>> + .gmem = SZ_512K,
> > > > > > >>>>>> + .inactive_period = DRM_MSM_INACTIVE_PERIOD,
> > > > > > >>>>>> + .init = a6xx_gpu_init,
> > > > > > >>>>>> + .zapfw = "a615_zap.mdt",
> > > > > > >>>>>> + .hwcg = a615_hwcg,
> > > > > > >>>>>> }, {
> > > > > > >>>>>> .rev = ADRENO_REV(6, 1, 9, ANY_ID),
> > > > > > >>>>>> .revn = 619,
> > > > > > >>>>>> @@ -409,6 +435,8 @@ const struct adreno_info *adreno_info(struct adreno_rev rev)
> > > > > > >>>>>> /* identify gpu: */
> > > > > > >>>>>> for (i = 0; i < ARRAY_SIZE(gpulist); i++) {
> > > > > > >>>>>> const struct adreno_info *info = &gpulist[i];
> > > > > > >>>>>> + if (info->machine && !of_machine_is_compatible(info->machine))
> > > > > > >>>>>> + continue;
> > > > > > >>>>>> if (adreno_cmp_rev(info->rev, rev))
> > > > > > >>>>>> return info;
> > > > > > >>>>>> }
> > > > > > >>>>>> @@ -563,6 +591,8 @@ static int adreno_bind(struct device *dev, struct device *master, void *data)
> > > > > > >>>>>> config.rev.minor, config.rev.patchid);
> > > > > > >>>>>> priv->is_a2xx = config.rev.core == 2;
> > > > > > >>>>>> + priv->has_cached_coherent =
> > > > > > >>>>>> + !!(info->quirks & ADRENO_QUIRK_HAS_CACHED_COHERENT);
> > > > > > >>>>>> gpu = info->init(drm);
> > > > > > >>>>>> if (IS_ERR(gpu)) {
> > > > > > >>>>>> @@ -574,10 +604,6 @@ static int adreno_bind(struct device *dev, struct device *master, void *data)
> > > > > > >>>>>> if (ret)
> > > > > > >>>>>> return ret;
> > > > > > >>>>>> - priv->has_cached_coherent =
> > > > > > >>>>>> - !!(info->quirks & ADRENO_QUIRK_HAS_CACHED_COHERENT) &&
> > > > > > >>>>>> - !adreno_has_gmu_wrapper(to_adreno_gpu(gpu));
> > > > > > >>>>>> -
> > > > > > >>>>>> return 0;
> > > > > > >>>>>> }
> > > > > > >>>>>> diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> > > > > > >>>>>> index e08d41337169..d5335b99c64c 100644
> > > > > > >>>>>> --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> > > > > > >>>>>> +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> > > > > > >>>>>> @@ -61,6 +61,7 @@ extern const struct adreno_reglist a612_hwcg[], a615_hwcg[], a630_hwcg[], a640_h
> > > > > > >>>>>> extern const struct adreno_reglist a660_hwcg[], a690_hwcg[];
> > > > > > >>>>>> struct adreno_info {
> > > > > > >>>>>> + const char *machine;
> > > > > > >>>>>> struct adreno_rev rev;
> > > > > > >>>>>> uint32_t revn;
> > > > > > >>>>>> const char *fw[ADRENO_FW_MAX];
> > > > > > >>>>>
> > > > > > >>>>> --
> > > > > > >>>>> With best wishes
> > > > > > >>>>> Dmitry
> > > > > > >>>>>
> > > > > > >>
> > > > > > >>
> > > > > > >>
> > > > > > >> --
> > > > > > >> With best wishes
> > > > > > >> Dmitry
> > > > > >
> > > > > > --
> > > > > > With best wishes
> > > > > > Dmitry
> > > > > >
> > > >
> > > >
> > > >
> > > > --
> > > > With best wishes
> > > > Dmitry
> >
> >
> >
> > --
> > With best wishes
> > Dmitry
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 73+ messages in thread
end of thread, other threads:[~2023-07-28 14:51 UTC | newest]
Thread overview: 73+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-07-06 21:10 [PATCH 00/12] drm/msm/adreno: Move away from legacy revision matching Rob Clark
2023-07-06 21:10 ` [PATCH 01/12] drm/msm/adreno: Remove GPU name Rob Clark
2023-07-06 23:21 ` Konrad Dybcio
2023-07-07 0:04 ` [Freedreno] " Dmitry Baryshkov
2023-07-06 21:10 ` [PATCH 02/12] drm/msm/adreno: Remove redundant gmem size param Rob Clark
2023-07-06 23:22 ` Konrad Dybcio
2023-07-13 19:46 ` Akhil P Oommen
2023-07-07 2:23 ` [Freedreno] " Dmitry Baryshkov
2023-07-06 21:10 ` [PATCH 03/12] drm/msm/adreno: Remove redundant revn param Rob Clark
2023-07-06 23:26 ` Konrad Dybcio
2023-07-07 2:24 ` [Freedreno] " Dmitry Baryshkov
2023-07-06 21:10 ` [PATCH 04/12] drm/msm/adreno: Use quirk identify hw_apriv Rob Clark
2023-07-06 23:27 ` Konrad Dybcio
2023-07-07 2:25 ` [Freedreno] " Dmitry Baryshkov
2023-07-06 21:10 ` [PATCH 05/12] drm/msm/adreno: Use quirk to identify cached-coherent support Rob Clark
2023-07-06 23:29 ` Konrad Dybcio
2023-07-07 2:29 ` [Freedreno] " Dmitry Baryshkov
2023-07-07 15:53 ` Rob Clark
2023-07-13 20:05 ` Akhil P Oommen
2023-07-13 22:25 ` Rob Clark
2023-07-17 22:00 ` Akhil P Oommen
2023-07-06 21:10 ` [PATCH 06/12] drm/msm/adreno: Allow SoC specific gpu device table entries Rob Clark
2023-07-07 0:40 ` Konrad Dybcio
2023-07-13 22:15 ` [Freedreno] " Akhil P Oommen
2023-07-07 2:34 ` Dmitry Baryshkov
2023-07-13 20:26 ` Akhil P Oommen
2023-07-26 18:28 ` Rob Clark
2023-07-26 20:00 ` Dmitry Baryshkov
2023-07-26 20:11 ` Rob Clark
2023-07-26 21:43 ` Dmitry Baryshkov
2023-07-26 22:03 ` Rob Clark
2023-07-26 22:33 ` Dmitry Baryshkov
2023-07-26 22:53 ` Rob Clark
2023-07-27 7:51 ` Konrad Dybcio
2023-07-27 14:52 ` Rob Clark
2023-07-27 21:13 ` Rob Clark
2023-07-27 22:02 ` Dmitry Baryshkov
2023-07-28 14:43 ` Rob Clark
2023-07-28 14:51 ` Dmitry Baryshkov
2023-07-06 21:10 ` [PATCH 07/12] drm/msm/adreno: Move speedbin mapping to device table Rob Clark
2023-07-07 2:54 ` [Freedreno] " Dmitry Baryshkov
2023-07-10 19:56 ` Rob Clark
2023-07-10 20:54 ` Dmitry Baryshkov
2023-07-06 21:10 ` [PATCH 08/12] drm/msm/adreno: Bring the a630 family together Rob Clark
2023-07-06 23:32 ` Konrad Dybcio
2023-07-06 21:10 ` [PATCH 09/12] drm/msm/adreno: Add adreno family Rob Clark
2023-07-06 23:35 ` Konrad Dybcio
2023-07-07 3:16 ` Dmitry Baryshkov
2023-07-07 23:52 ` Rob Clark
2023-07-07 23:54 ` Dmitry Baryshkov
2023-07-07 2:49 ` [Freedreno] " Dmitry Baryshkov
2023-07-06 21:10 ` [PATCH 10/12] drm/msm/adreno: Add helper for formating chip-id Rob Clark
2023-07-06 23:36 ` Konrad Dybcio
2023-07-10 20:21 ` Rob Clark
2023-07-07 2:50 ` [Freedreno] " Dmitry Baryshkov
2023-07-06 21:10 ` [PATCH 11/12] dt-bindings: drm/msm/gpu: Extend bindings for chip-id Rob Clark
2023-07-07 7:26 ` Krzysztof Kozlowski
2023-07-07 13:09 ` Rob Clark
2023-07-06 21:10 ` [PATCH 12/12] drm/msm/adreno: Switch to chip-id for identifying GPU Rob Clark
2023-07-07 0:25 ` Konrad Dybcio
2023-07-07 16:08 ` Rob Clark
2023-07-15 13:38 ` Konrad Dybcio
2023-07-15 14:12 ` Rob Clark
2023-07-26 21:45 ` Rob Clark
2023-07-07 3:45 ` [Freedreno] " Dmitry Baryshkov
2023-07-13 21:39 ` Akhil P Oommen
2023-07-13 22:06 ` Rob Clark
2023-07-13 22:53 ` Dmitry Baryshkov
2023-07-17 22:09 ` Akhil P Oommen
2023-07-26 21:37 ` Rob Clark
2023-07-26 21:38 ` Dmitry Baryshkov
2023-07-26 21:44 ` Rob Clark
2023-07-26 21:45 ` Dmitry Baryshkov
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).