[PATCH 1/2] drm/etnaviv: add HWDB entry for GC7000 r6203

[PATCH 1/2] drm/etnaviv: add HWDB entry for GC7000 r6203

[Lucas Stach]

From: Marco Felsch <m.felsch@pengutronix.de>

The GPU is found on the NXP i.MX8MN SoC. The feature bits are taken from
the NXP downstream kernel driver 6.4.3.p2.

Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
---
 drivers/gpu/drm/etnaviv/etnaviv_hwdb.c | 31 ++++++++++++++++++++++++++
 1 file changed, 31 insertions(+)

diff --git a/drivers/gpu/drm/etnaviv/etnaviv_hwdb.c b/drivers/gpu/drm/etnaviv/etnaviv_hwdb.c
index f2fc645c7956..eaed08a3d281 100644
--- a/drivers/gpu/drm/etnaviv/etnaviv_hwdb.c
+++ b/drivers/gpu/drm/etnaviv/etnaviv_hwdb.c
@@ -68,6 +68,37 @@ static const struct etnaviv_chip_identity etnaviv_chip_identities[] = {
 		.minor_features10 = 0x00004040,
 		.minor_features11 = 0x00000024,
 	},
+	{
+		.model = 0x7000,
+		.revision = 0x6203,
+		.product_id = ~0U,
+		.customer_id = ~0U,
+		.eco_id = ~0U,
+		.stream_count = 16,
+		.register_max = 64,
+		.thread_count = 512,
+		.shader_core_count = 2,
+		.vertex_cache_size = 16,
+		.vertex_output_buffer_size = 1024,
+		.pixel_pipes = 1,
+		.instruction_count = 512,
+		.num_constants = 320,
+		.buffer_size = 0,
+		.varyings_count = 16,
+		.features = 0xe0287c8d,
+		.minor_features0 = 0xc1589eff,
+		.minor_features1 = 0xfefbfad9,
+		.minor_features2 = 0xeb9d4fbf,
+		.minor_features3 = 0xedfffced,
+		.minor_features4 = 0xdb0dafc7,
+		.minor_features5 = 0x3b5ac333,
+		.minor_features6 = 0xfcce6000,
+		.minor_features7 = 0xfffbfa6f,
+		.minor_features8 = 0x00e10ef3,
+		.minor_features9 = 0x00c8003c,
+		.minor_features10 = 0x00004040,
+		.minor_features11 = 0x00000024,
+	},
 	{
 		.model = 0x7000,
 		.revision = 0x6204,
-- 
2.30.2

[PATCH 2/2] drm/etnaviv: disable tx clock gating for GC7000 rev6203

[Lucas Stach]

From: Marco Felsch <m.felsch@pengutronix.de>

The i.MX8MN SoC errata sheet mentions ERR050226: "GPU: Texture L2 Cache
idle signal may incorrectly clock gate the texture engine in GPU".

The workaround is to disable the corresponding clock gatings.

While on it move the clock gating check for rev6202 into the same check
to bundle them.

Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
---
 drivers/gpu/drm/etnaviv/etnaviv_gpu.c | 9 +++++----
 1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/etnaviv/etnaviv_gpu.c b/drivers/gpu/drm/etnaviv/etnaviv_gpu.c
index 37018bc55810..430fcc11d668 100644
--- a/drivers/gpu/drm/etnaviv/etnaviv_gpu.c
+++ b/drivers/gpu/drm/etnaviv/etnaviv_gpu.c
@@ -616,14 +616,15 @@ static void etnaviv_gpu_enable_mlcg(struct etnaviv_gpu *gpu)
 
 	/* Disable TX clock gating on affected core revisions. */
 	if (etnaviv_is_model_rev(gpu, GC4000, 0x5222) ||
-	    etnaviv_is_model_rev(gpu, GC2000, 0x5108))
+	    etnaviv_is_model_rev(gpu, GC2000, 0x5108) ||
+	    etnaviv_is_model_rev(gpu, GC2000, 0x6202) ||
+	    etnaviv_is_model_rev(gpu, GC2000, 0x6203))
 		pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_TX;
 
-	/* Disable SE, RA and TX clock gating on affected core revisions. */
+	/* Disable SE and RA clock gating on affected core revisions. */
 	if (etnaviv_is_model_rev(gpu, GC7000, 0x6202))
 		pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_SE |
-		       VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA |
-		       VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_TX;
+		       VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA;
 
 	pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA_HZ;
 	pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA_EZ;
-- 
2.30.2

Re: [PATCH 1/2] drm/etnaviv: add HWDB entry for GC7000 r6203

[Adam Ford]

On Fri, Aug 26, 2022 at 2:07 PM Lucas Stach <l.stach@pengutronix.de> wrote:
>
> From: Marco Felsch <m.felsch@pengutronix.de>
>
> The GPU is found on the NXP i.MX8MN SoC. The feature bits are taken from
> the NXP downstream kernel driver 6.4.3.p2.
>

This series fixes an issue where I saw:
etnaviv-gpu 38000000.gpu: recover hung GPU!

With mesa-22.2.0-rc3, I am able to run 3D demos.

Tested-by: Adam Ford <aford173@gmail.com> #imx8mn-beacon-kit

> Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>
> Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
> ---
>  drivers/gpu/drm/etnaviv/etnaviv_hwdb.c | 31 ++++++++++++++++++++++++++
>  1 file changed, 31 insertions(+)
>
> diff --git a/drivers/gpu/drm/etnaviv/etnaviv_hwdb.c b/drivers/gpu/drm/etnaviv/etnaviv_hwdb.c
> index f2fc645c7956..eaed08a3d281 100644
> --- a/drivers/gpu/drm/etnaviv/etnaviv_hwdb.c
> +++ b/drivers/gpu/drm/etnaviv/etnaviv_hwdb.c
> @@ -68,6 +68,37 @@ static const struct etnaviv_chip_identity etnaviv_chip_identities[] = {
>                 .minor_features10 = 0x00004040,
>                 .minor_features11 = 0x00000024,
>         },
> +       {
> +               .model = 0x7000,
> +               .revision = 0x6203,
> +               .product_id = ~0U,
> +               .customer_id = ~0U,
> +               .eco_id = ~0U,
> +               .stream_count = 16,
> +               .register_max = 64,
> +               .thread_count = 512,
> +               .shader_core_count = 2,
> +               .vertex_cache_size = 16,
> +               .vertex_output_buffer_size = 1024,
> +               .pixel_pipes = 1,
> +               .instruction_count = 512,
> +               .num_constants = 320,
> +               .buffer_size = 0,
> +               .varyings_count = 16,
> +               .features = 0xe0287c8d,
> +               .minor_features0 = 0xc1589eff,
> +               .minor_features1 = 0xfefbfad9,
> +               .minor_features2 = 0xeb9d4fbf,
> +               .minor_features3 = 0xedfffced,
> +               .minor_features4 = 0xdb0dafc7,
> +               .minor_features5 = 0x3b5ac333,
> +               .minor_features6 = 0xfcce6000,
> +               .minor_features7 = 0xfffbfa6f,
> +               .minor_features8 = 0x00e10ef3,
> +               .minor_features9 = 0x00c8003c,
> +               .minor_features10 = 0x00004040,
> +               .minor_features11 = 0x00000024,
> +       },
>         {
>                 .model = 0x7000,
>                 .revision = 0x6204,
> --
> 2.30.2
>

Re: [PATCH 1/2] drm/etnaviv: add HWDB entry for GC7000 r6203

[Christian Gmeiner]

Hi all

Am Fr., 26. Aug. 2022 um 21:07 Uhr schrieb Lucas Stach <l.stach@pengutronix.de>:
>
> From: Marco Felsch <m.felsch@pengutronix.de>
>
> The GPU is found on the NXP i.MX8MN SoC. The feature bits are taken from
> the NXP downstream kernel driver 6.4.3.p2.
>

Can we stop adding new entries to the kernel hwdb and start to
establish a hwdb in the userspace aka mesa?
The kernel provides all the needed information to the user space so
"all" that's left is to add the mesa side. You might
ask why? It is much simpler to maintain such a database in the user
space (thanks to stable patch releases of mesa) than
forcing users to update their kernels to get this new database entry.

-- 
greets
--
Christian Gmeiner, MSc

https://christian-gmeiner.info/privacypolicy

Re: [PATCH 2/2] drm/etnaviv: disable tx clock gating for GC7000 rev6203

[Christian Gmeiner]

> The i.MX8MN SoC errata sheet mentions ERR050226: "GPU: Texture L2 Cache
> idle signal may incorrectly clock gate the texture engine in GPU".
>
> The workaround is to disable the corresponding clock gatings.
>
> While on it move the clock gating check for rev6202 into the same check
> to bundle them.
>
> Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>
> Signed-off-by: Lucas Stach <l.stach@pengutronix.de>

Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>

> ---
>  drivers/gpu/drm/etnaviv/etnaviv_gpu.c | 9 +++++----
>  1 file changed, 5 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/etnaviv/etnaviv_gpu.c b/drivers/gpu/drm/etnaviv/etnaviv_gpu.c
> index 37018bc55810..430fcc11d668 100644
> --- a/drivers/gpu/drm/etnaviv/etnaviv_gpu.c
> +++ b/drivers/gpu/drm/etnaviv/etnaviv_gpu.c
> @@ -616,14 +616,15 @@ static void etnaviv_gpu_enable_mlcg(struct etnaviv_gpu *gpu)
>
>         /* Disable TX clock gating on affected core revisions. */
>         if (etnaviv_is_model_rev(gpu, GC4000, 0x5222) ||
> -           etnaviv_is_model_rev(gpu, GC2000, 0x5108))
> +           etnaviv_is_model_rev(gpu, GC2000, 0x5108) ||
> +           etnaviv_is_model_rev(gpu, GC2000, 0x6202) ||
> +           etnaviv_is_model_rev(gpu, GC2000, 0x6203))
>                 pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_TX;
>
> -       /* Disable SE, RA and TX clock gating on affected core revisions. */
> +       /* Disable SE and RA clock gating on affected core revisions. */
>         if (etnaviv_is_model_rev(gpu, GC7000, 0x6202))
>                 pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_SE |
> -                      VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA |
> -                      VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_TX;
> +                      VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA;
>
>         pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA_HZ;
>         pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA_EZ;
> --
> 2.30.2
>


-- 
greets
--
Christian Gmeiner, MSc

https://christian-gmeiner.info/privacypolicy

Re: [PATCH 1/2] drm/etnaviv: add HWDB entry for GC7000 r6203

[Lucas Stach]

H Christian,

Am Samstag, dem 03.09.2022 um 13:16 +0200 schrieb Christian Gmeiner:
> Hi all
> 
> Am Fr., 26. Aug. 2022 um 21:07 Uhr schrieb Lucas Stach <l.stach@pengutronix.de>:
> > 
> > From: Marco Felsch <m.felsch@pengutronix.de>
> > 
> > The GPU is found on the NXP i.MX8MN SoC. The feature bits are taken from
> > the NXP downstream kernel driver 6.4.3.p2.
> > 
> 
> Can we stop adding new entries to the kernel hwdb and start to
> establish a hwdb in the userspace aka mesa?
> The kernel provides all the needed information to the user space so
> "all" that's left is to add the mesa side. You might
> ask why? It is much simpler to maintain such a database in the user
> space (thanks to stable patch releases of mesa) than
> forcing users to update their kernels to get this new database entry.
> 
Some of the feature bits are also interesting to the kernel, so you
need to update the kernel anyways if you want a new GPU to work. HWDB
entries, same as PCI ID additions, could be picked up into the stable
kernel releases if anyone cares.

I'm not opposed to userspace having its own HWDB, but at this point we
can not remove the kernel HWDB, even just to keep API compatibility.

Regards,
Lucas

Re: [PATCH 1/2] drm/etnaviv: add HWDB entry for GC7000 r6203

[Lucas Stach]

Hi Stefan,

please keep the CC list intact when replying. I've almost missed this.

Am Montag, dem 29.08.2022 um 13:41 +0200 schrieb Stefan Eschenbacher:
> 
> Product_id, customer_id and eco_id should not be zero. The different
> versions of model 0x7000, revision 0x6203 can differ in stream_count,
> minor_feature5 and minor_features7.
>  
>                 {
>                                .model = 0x7000,
>                                .revision = 0x6203,
>                                .product_id = 0x70003,
>                                .customer_id = 0x4,
>                                .eco_id = 0,
>                                .stream_count = 16,
>                                .register_max = 64,
>                                .thread_count = 512,
>                                .shader_core_count = 2,
>                                .vertex_cache_size = 16,
>                                .vertex_output_buffer_size = 1024,
>                                .pixel_pipes = 1,
>                                .instruction_count = 512,
>                                .num_constants = 320,
>                                .buffer_size = 0,
>                                .varyings_count = 16,
>                                .features = 0xe0287c8d,
>                                .minor_features0 = 0xc1799eff,
>                                .minor_features1 = 0xfefbfad9,
>                                .minor_features2 = 0xeb9d4fbf,
>                                .minor_features3 = 0xedfffced,
>                                .minor_features4 = 0xdb0dafc7,
>                                .minor_features5 = 0x3b5ac333,
>                                .minor_features6 = 0xfcce6000,
>                                .minor_features7 = 0xfffbfa6f,
>                                .minor_features8 = 0x00e10ef3,
>                                .minor_features9 = 0x00c8003c,
>                                .minor_features10 = 0x00004040,
>                                .minor_features11 = 0x00000024,
>                 },
>                 {
>                                .model = 0x7000,
>                                .revision = 0x6203,
>                                .product_id = 0x7000f,
>                                .customer_id = 0x60,
>                                .eco_id = 0,
>                                .stream_count = 8,
>                                .register_max = 64,
>                                .thread_count = 512,
>                                .shader_core_count = 2,
>                                .vertex_cache_size = 16,
>                                .vertex_output_buffer_size = 1024,
>                                .pixel_pipes = 1,
>                                .instruction_count = 512,
>                                .num_constants = 320,
>                                .buffer_size = 0,
>                                .varyings_count = 16,
>                                .features = 0xe0287c8d,
>                                 .minor_features0 = 0xc1799eff,
>                                .minor_features1 = 0xfefbfad9,
>                                .minor_features2 = 0xeb9d4fbf,
>                                .minor_features3 = 0xedfffced,
>                                .minor_features4 = 0xdb0dafc7,
>                                .minor_features5 = 0x7b5ac333,
>                                .minor_features6 = 0xfcce6000,
>                                .minor_features7 = 0x1bfbfa6f,
>                                .minor_features8 = 0x00e10ef0,
>                                .minor_features9 = 0x00c8003c,
>                                .minor_features10 = 0x00004040,
>                                .minor_features11 = 0x00000024,
>                 },
> 
> Take a look in the stm32 hwdb file.

While your comment is correct and we should do a more targeted
matching, could you please point me to the stm32 hwdb file you are
referring to?

Regards,
Lucas