[PATCH 0/4 rev2] Sandybridge suspend/resume fixes

[PATCH 0/4 rev2] Sandybridge suspend/resume fixes

[Zhenyu Wang]

I've done more testing with below patches, eliminated some in first
patch set that doesn't affect suspend issue it seems.

The test was done with one rev9 SNB on two boards DH67GD and DQ67SW
with latest bios. And it both passed over 100 cycles of S3 testing.
Without these, upstream kernel still hang quickly on them.

[PATCH 1/4] drm/i915: clock gating fix for gen5 and gen6

[Zhenyu Wang]

Some bits should only be set when enable FBC.

Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h      |    4 +++-
 drivers/gpu/drm/i915/intel_display.c |   27 ++++++++++++++-------------
 2 files changed, 17 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 2abe240..b0aabe4 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2771,8 +2771,10 @@
 #define  ILK_eDP_A_DISABLE		(1<<24)
 #define  ILK_DESKTOP			(1<<23)
 #define ILK_DSPCLK_GATE		0x42020
-#define  ILK_DPARB_CLK_GATE	(1<<5)
+#define  ILK_DPFC_CLK_GATE	(1<<9)
+#define  ILK_DPFCR_CLK_GATE	(1<<8)
 #define  ILK_DPFD_CLK_GATE	(1<<7)
+#define  ILK_DPARB_CLK_GATE	(1<<5)
 
 /* According to spec this bit 7/8/9 of 0x42020 should be set to enable FBC */
 #define   ILK_CLK_FBC		(1<<7)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 49fb54f..b7d1101 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6452,7 +6452,7 @@ void intel_enable_clock_gating(struct drm_device *dev)
 				   ILK_FBCQ_DIS);
 			I915_WRITE(ILK_DISPLAY_CHICKEN2,
 				   I915_READ(ILK_DISPLAY_CHICKEN2) |
-				   ILK_DPARB_GATE);
+				   ILK_DPARB_GATE | ILK_ELPIN_409_SELECT);
 			I915_WRITE(ILK_DSPCLK_GATE,
 				   I915_READ(ILK_DSPCLK_GATE) |
 				   ILK_DPFC_DIS1 |
@@ -6460,10 +6460,6 @@ void intel_enable_clock_gating(struct drm_device *dev)
 				   ILK_CLK_FBC);
 		}
 
-		I915_WRITE(ILK_DISPLAY_CHICKEN2,
-			   I915_READ(ILK_DISPLAY_CHICKEN2) |
-			   ILK_ELPIN_409_SELECT);
-
 		if (IS_GEN5(dev)) {
 			I915_WRITE(_3D_CHICKEN2,
 				   _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
@@ -6484,16 +6480,21 @@ void intel_enable_clock_gating(struct drm_device *dev)
 			 * The bit14 of 0x70180
 			 * The bit14 of 0x71180
 			 */
-			I915_WRITE(ILK_DISPLAY_CHICKEN1,
-				   I915_READ(ILK_DISPLAY_CHICKEN1) |
-				   ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
+			if (I915_HAS_FBC(dev) && i915_powersave) {
+				I915_WRITE(ILK_DISPLAY_CHICKEN1,
+					   I915_READ(ILK_DISPLAY_CHICKEN1) |
+					   ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
+				I915_WRITE(ILK_DSPCLK_GATE,
+					   I915_READ(ILK_DSPCLK_GATE) |
+					   ILK_DPFC_CLK_GATE | ILK_DPFCR_CLK_GATE);
+			} else
+				I915_WRITE(ILK_DISPLAY_CHICKEN1,
+					   I915_READ(ILK_DISPLAY_CHICKEN1) |
+					   ILK_PABSTRETCH_DIS);
+
 			I915_WRITE(ILK_DISPLAY_CHICKEN2,
 				   I915_READ(ILK_DISPLAY_CHICKEN2) |
-				   ILK_DPARB_GATE | ILK_VSDPFD_FULL);
-			I915_WRITE(ILK_DSPCLK_GATE,
-				   I915_READ(ILK_DSPCLK_GATE) |
-				   ILK_DPARB_CLK_GATE  |
-				   ILK_DPFD_CLK_GATE);
+				   ILK_VSDPFD_FULL | ILK_ELPIN_409_SELECT);
 
 			I915_WRITE(DSPACNTR,
 				   I915_READ(DSPACNTR) |
-- 
1.7.4.1

[PATCH 2/4] drm/i915: save/restore DSPARB only for chips before gen4 but not for G33

[Zhenyu Wang]

DSPARB is reserved on G33 and not available on Gen6.

Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_suspend.c |    6 ++++--
 1 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c
index 0521ecf..8d165c4 100644
--- a/drivers/gpu/drm/i915/i915_suspend.c
+++ b/drivers/gpu/drm/i915/i915_suspend.c
@@ -603,7 +603,8 @@ void i915_save_display(struct drm_device *dev)
 	struct drm_i915_private *dev_priv = dev->dev_private;
 
 	/* Display arbitration control */
-	dev_priv->saveDSPARB = I915_READ(DSPARB);
+	if (dev_priv->info->gen < 4 && !IS_G33(dev))
+		dev_priv->saveDSPARB = I915_READ(DSPARB);
 
 	/* This is only meaningful in non-KMS mode */
 	/* Don't save them in KMS mode */
@@ -695,7 +696,8 @@ void i915_restore_display(struct drm_device *dev)
 	struct drm_i915_private *dev_priv = dev->dev_private;
 
 	/* Display arbitration */
-	I915_WRITE(DSPARB, dev_priv->saveDSPARB);
+	if (dev_priv->info->gen < 4 && !IS_G33(dev))
+		I915_WRITE(DSPARB, dev_priv->saveDSPARB);
 
 	/* Display port ratios (must be done before clock is set) */
 	if (SUPPORTS_INTEGRATED_DP(dev)) {
-- 
1.7.4.1

[PATCH 3/4] drm/i915: save/restore MI_ARB_STATE only before gen6

[Zhenyu Wang]

MI_ARB_STATE address is not available on Gen6.

Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_suspend.c |    6 ++++--
 1 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c
index 8d165c4..bce24d8 100644
--- a/drivers/gpu/drm/i915/i915_suspend.c
+++ b/drivers/gpu/drm/i915/i915_suspend.c
@@ -828,7 +828,8 @@ int i915_save_state(struct drm_device *dev)
 	dev_priv->saveCACHE_MODE_0 = I915_READ(CACHE_MODE_0);
 
 	/* Memory Arbitration state */
-	dev_priv->saveMI_ARB_STATE = I915_READ(MI_ARB_STATE);
+	if (dev_priv->info->gen < 6)
+		dev_priv->saveMI_ARB_STATE = I915_READ(MI_ARB_STATE);
 
 	/* Scratch space */
 	for (i = 0; i < 16; i++) {
@@ -881,7 +882,8 @@ int i915_restore_state(struct drm_device *dev)
 	I915_WRITE (CACHE_MODE_0, dev_priv->saveCACHE_MODE_0 | 0xffff0000);
 
 	/* Memory arbitration state */
-	I915_WRITE (MI_ARB_STATE, dev_priv->saveMI_ARB_STATE | 0xffff0000);
+	if (dev_priv->info->gen < 6)
+		I915_WRITE (MI_ARB_STATE, dev_priv->saveMI_ARB_STATE | 0xffff0000);
 
 	for (i = 0; i < 16; i++) {
 		I915_WRITE(SWF00 + (i << 2), dev_priv->saveSWF0[i]);
-- 
1.7.4.1

[PATCH 4/4] drm/i915: move sandybridge RC6 enable in resume after ring initialization

[Zhenyu Wang]

Move RC6 enable after we reset rings for all regines, if e.g render ring
is disabled when RC6 enable on Sandybridge, hw won't save render context
image if any chance when enter RC6. Also match the order like we do in
driver load.

Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_drv.c     |    3 +++
 drivers/gpu/drm/i915/i915_suspend.c |    3 ---
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 22ec066..e675ba9 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -378,6 +378,9 @@ static int i915_drm_thaw(struct drm_device *dev)
 
 		if (IS_IRONLAKE_M(dev))
 			ironlake_enable_rc6(dev);
+
+		if (IS_GEN6(dev))
+			gen6_enable_rps(dev_priv);
 	}
 
 	intel_opregion_init(dev);
diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c
index bce24d8..08c1d04 100644
--- a/drivers/gpu/drm/i915/i915_suspend.c
+++ b/drivers/gpu/drm/i915/i915_suspend.c
@@ -875,9 +875,6 @@ int i915_restore_state(struct drm_device *dev)
 		intel_init_emon(dev);
 	}
 
-	if (IS_GEN6(dev))
-		gen6_enable_rps(dev_priv);
-
 	/* Cache mode state */
 	I915_WRITE (CACHE_MODE_0, dev_priv->saveCACHE_MODE_0 | 0xffff0000);
 
-- 
1.7.4.1

Re: [PATCH 2/4] drm/i915: save/restore DSPARB only for chips before gen4 but not for G33

[Keith Packard]

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On Wed, 23 Mar 2011 10:21:07 +0800, Zhenyu Wang <zhenyuw@linux.intel.com> wrote:

> DSPARB is reserved on G33 and not available on Gen6.

Does this fix a reported problem? Or just spec compliance?

-- 
keith.packard@intel.com

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Re: [PATCH 2/4] drm/i915: save/restore DSPARB only for chips before gen4 but not for G33

[Zhenyu Wang]

[-- Attachment #1.1: Type: text/plain, Size: 492 bytes --]

On 2011.03.23 12:03:41 +0900, Keith Packard wrote:
> On Wed, 23 Mar 2011 10:21:07 +0800, Zhenyu Wang <zhenyuw@linux.intel.com> wrote:
> 
> > DSPARB is reserved on G33 and not available on Gen6.
> 
> Does this fix a reported problem? Or just spec compliance?
> 

I didn't verify if this one is really related, but save/restore
an arbitrary undefined reg seems wrong to me. ;)

-- 
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Re: [PATCH 0/4 rev2] Sandybridge suspend/resume fixes

[Fu Michael]

On 2011/3/23 10:21, Zhenyu Wang wrote:
> I've done more testing with below patches, eliminated some in first
> patch set that doesn't affect suspend issue it seems.
>
> The test was done with one rev9 SNB on two boards DH67GD and DQ67SW
> with latest bios. And it both passed over 100 cycles of S3 testing.
> Without these, upstream kernel still hang quickly on them.
>

better to raise the bar to 1000...

> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>