From: Chris Wilson <chris@chris-wilson.co.uk>
To: intel-gfx@lists.freedesktop.org
Subject: [PATCH 03/13] drm/i915: Introduce i915_gem_object_finish_gpu()
Date: Thu, 14 Apr 2011 10:03:37 +0100 [thread overview]
Message-ID: <1302771827-26112-4-git-send-email-chris@chris-wilson.co.uk> (raw)
In-Reply-To: <1302771827-26112-1-git-send-email-chris@chris-wilson.co.uk>
... reincarnated from i915_gem_object_flush_gpu(). The semantic
difference is that after calling finish_gpu() the object no longer
resides in any GPU domain, and so will cause the GPU caches to be
invalidated if it is ever used again.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/i915_drv.h | 2 +-
drivers/gpu/drm/i915/i915_gem.c | 29 +++++++++++++++++++----------
drivers/gpu/drm/i915/intel_display.c | 2 +-
3 files changed, 21 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 2536334..4f63d17 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1163,7 +1163,7 @@ void i915_gem_clflush_object(struct drm_i915_gem_object *obj);
int __must_check i915_gem_object_set_domain(struct drm_i915_gem_object *obj,
uint32_t read_domains,
uint32_t write_domain);
-int __must_check i915_gem_object_flush_gpu(struct drm_i915_gem_object *obj);
+int __must_check i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj);
int __must_check i915_gem_init_ringbuffer(struct drm_device *dev);
void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
void i915_gem_do_init(struct drm_device *dev,
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index bf32527..2781b40 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -2167,23 +2167,29 @@ i915_gem_object_unbind(struct drm_i915_gem_object *obj)
return -EINVAL;
}
+ ret = i915_gem_object_finish_gpu(obj);
+ if (ret == -ERESTARTSYS)
+ return ret;
+ /* Continue on if we fail due to EIO, the GPU is hung so we
+ * should be safe and we need to cleanup or else we might
+ * cause memory corruption through use-after-free.
+ */
+
/* blow away mappings if mapped through GTT */
i915_gem_release_mmap(obj);
/* Move the object to the CPU domain to ensure that
* any possible CPU writes while it's not in the GTT
- * are flushed when we go to remap it. This will
- * also ensure that all pending GPU writes are finished
- * before we unbind.
+ * are flushed when we go to remap it.
*/
- ret = i915_gem_object_set_to_cpu_domain(obj, 1);
+ if (ret == 0)
+ ret = i915_gem_object_set_to_cpu_domain(obj, 1);
if (ret == -ERESTARTSYS)
return ret;
- /* Continue on if we fail due to EIO, the GPU is hung so we
- * should be safe and we need to cleanup or else we might
- * cause memory corruption through use-after-free.
- */
if (ret) {
+ /* In the event of a disaster, abandon all caches and
+ * hope for the best.
+ */
i915_gem_clflush_object(obj);
obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU;
}
@@ -3045,11 +3051,11 @@ i915_gem_object_set_to_display_plane(struct drm_i915_gem_object *obj,
}
int
-i915_gem_object_flush_gpu(struct drm_i915_gem_object *obj)
+i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj)
{
int ret;
- if (!obj->active)
+ if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0)
return 0;
if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) {
@@ -3058,6 +3064,9 @@ i915_gem_object_flush_gpu(struct drm_i915_gem_object *obj)
return ret;
}
+ /* Ensure that we invalidate the GPU's caches and TLBs. */
+ obj->base.read_domains &= I915_GEM_GPU_DOMAINS;
+
return i915_gem_object_wait_rendering(obj);
}
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 09b20b1..c1337e4 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1966,7 +1966,7 @@ intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
* This should only fail upon a hung GPU, in which case we
* can safely continue.
*/
- ret = i915_gem_object_flush_gpu(obj);
+ ret = i915_gem_object_finish_gpu(obj);
(void) ret;
}
--
1.7.4.1
next prev parent reply other threads:[~2011-04-14 9:04 UTC|newest]
Thread overview: 42+ messages / expand[flat|nested] mbox.gz Atom feed top
2011-04-14 9:03 i915 llc for -next Chris Wilson
2011-04-14 9:03 ` [PATCH 01/13] drm/i915: Rename agp_type to cache_level Chris Wilson
2011-04-14 12:39 ` Keith Packard
2011-04-14 20:57 ` [PATCH] " Chris Wilson
2011-04-14 9:03 ` [PATCH 02/13] drm/i915: Do not clflush snooped objects Chris Wilson
2011-04-14 9:03 ` Chris Wilson [this message]
2011-04-14 16:01 ` [PATCH 03/13] drm/i915: Introduce i915_gem_object_finish_gpu() Daniel Vetter
2011-04-14 9:03 ` [PATCH 04/13] drm/i915: Introduce i915_gem_object_finish_gtt() Chris Wilson
2011-04-14 16:12 ` Daniel Vetter
2011-04-14 20:20 ` Chris Wilson
2011-05-04 16:47 ` Keith Packard
2011-04-14 9:03 ` [PATCH 05/13] drm/i915/gtt: Split out i915_gem_gtt_rebind_object() Chris Wilson
2011-04-14 16:52 ` Daniel Vetter
2011-04-14 9:03 ` [PATCH 06/13] drm/i915: Add an interface to dynamically change the cache level Chris Wilson
2011-04-14 16:54 ` Daniel Vetter
2011-04-14 9:03 ` [PATCH 07/13] drm/i915: Mark the cursor and the overlay as being part of the display planes Chris Wilson
2011-05-04 17:09 ` Keith Packard
2011-05-04 18:28 ` Chris Wilson
2011-05-04 18:46 ` Keith Packard
2011-05-04 19:47 ` Chris Wilson
2011-04-14 9:03 ` [PATCH 08/13] drm/i915: Pin after setting to the display plane Chris Wilson
2011-04-14 17:34 ` Daniel Vetter
2011-04-14 21:31 ` Chris Wilson
2011-04-15 6:04 ` [PATCH 1/2] drm/i915: Combine pinning " Chris Wilson
2011-04-15 6:04 ` [PATCH 2/2] drm/i915: Use the uncached domain for the display planes Chris Wilson
2011-04-16 10:54 ` Daniel Vetter
2011-04-15 12:11 ` [PATCH 1/2] drm/i915: Combine pinning after setting to the display plane Daniel Vetter
2011-04-16 6:26 ` Chris Wilson
2011-04-16 6:27 ` [PATCH] drm/i915: Combine pinning with " Chris Wilson
2011-04-16 10:52 ` Daniel Vetter
2011-04-16 11:00 ` Chris Wilson
2011-04-14 9:03 ` [PATCH 09/13] drm/i915: Use the uncached domain for the display planes Chris Wilson
2011-04-14 9:03 ` [PATCH 10/13] drm/i915: Use the CPU domain for snooped pwrites Chris Wilson
2011-04-14 17:40 ` Daniel Vetter
2011-04-14 9:03 ` [PATCH 11/13] drm/i915: Prevent mmap access through the GTT of snooped pages Chris Wilson
2011-05-04 17:30 ` Keith Packard
2011-04-14 9:03 ` [PATCH 12/13] drm/i915: Prevent mixing of snooped and tiling modes for old chipsets Chris Wilson
2011-04-14 17:43 ` Daniel Vetter
2011-04-14 20:26 ` Chris Wilson
2011-05-04 17:32 ` Keith Packard
2011-04-14 9:03 ` [PATCH 13/13] drm/i915: Use the LLC mode on gen6 for everything but display Chris Wilson
2011-04-15 6:12 ` i915 llc for -next Chris Wilson
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