From: Matt Roper <matthew.d.roper@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [CI 03/18] drm/i915/dg2: add DG2 platform info
Date: Wed, 21 Jul 2021 15:30:28 -0700 [thread overview]
Message-ID: <20210721223043.834562-4-matthew.d.roper@intel.com> (raw)
In-Reply-To: <20210721223043.834562-1-matthew.d.roper@intel.com>
DG2 has Xe_LPD display (version 13) and Xe_HPG (version 12.55) graphics.
There are two variants (treated as subplatforms in the code): DG2-G10
and DG2-G11 that require independent programming in some areas (e.g.,
workarounds).
Bspec: 44472, 44474, 46197, 48028, 48077
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 27 ++++++++++++++++++++++++
drivers/gpu/drm/i915/i915_pci.c | 16 ++++++++++++++
drivers/gpu/drm/i915/intel_device_info.c | 1 +
drivers/gpu/drm/i915/intel_device_info.h | 5 +++++
drivers/gpu/drm/i915/intel_step.c | 20 +++++++++++++++++-
5 files changed, 68 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 310f272a005f..7c446f958357 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1445,6 +1445,11 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define IS_ALDERLAKE_S(dev_priv) IS_PLATFORM(dev_priv, INTEL_ALDERLAKE_S)
#define IS_ALDERLAKE_P(dev_priv) IS_PLATFORM(dev_priv, INTEL_ALDERLAKE_P)
#define IS_XEHPSDV(dev_priv) IS_PLATFORM(dev_priv, INTEL_XEHPSDV)
+#define IS_DG2(dev_priv) IS_PLATFORM(dev_priv, INTEL_DG2)
+#define IS_DG2_G10(dev_priv) \
+ IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G10)
+#define IS_DG2_G11(dev_priv) \
+ IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G11)
#define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
(INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
#define IS_BDW_ULT(dev_priv) \
@@ -1558,6 +1563,28 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define IS_XEHPSDV_GT_STEP(p, since, until) \
(IS_XEHPSDV(p) && IS_GT_STEP(__i915, since, until))
+/*
+ * DG2 hardware steppings are a bit unusual. The hardware design was forked
+ * to create two variants (G10 and G11) which have distinct workaround sets.
+ * The G11 fork of the DG2 design resets the GT stepping back to "A0" for its
+ * first iteration, even though it's more similar to a G10 B0 stepping in terms
+ * of functionality and workarounds. However the display stepping does not
+ * reset in the same manner --- a specific stepping like "B0" has a consistent
+ * meaning regardless of whether it belongs to a G10 or G11 DG2.
+ *
+ * TLDR: All GT workarounds and stepping-specific logic must be applied in
+ * relation to a specific subplatform (G10 or G11), whereas display workarounds
+ * and stepping-specific logic will be applied with a general DG2-wide stepping
+ * number.
+ */
+#define IS_DG2_GT_STEP(__i915, variant, since, until) \
+ (IS_SUBPLATFORM(__i915, INTEL_DG2, INTEL_SUBPLATFORM_##variant) && \
+ IS_GT_STEP(__i915, since, until))
+
+#define IS_DG2_DISP_STEP(__i915, since, until) \
+ (IS_DG2(__i915) && \
+ IS_DISPLAY_STEP(__i915, since, until))
+
#define IS_LP(dev_priv) (INTEL_INFO(dev_priv)->is_lp)
#define IS_GEN9_LP(dev_priv) (GRAPHICS_VER(dev_priv) == 9 && IS_LP(dev_priv))
#define IS_GEN9_BC(dev_priv) (GRAPHICS_VER(dev_priv) == 9 && !IS_LP(dev_priv))
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 330b98396c7b..ec3f576f4247 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -1038,6 +1038,22 @@ static const struct intel_device_info xehpsdv_info = {
.require_force_probe = 1,
};
+__maybe_unused
+static const struct intel_device_info dg2_info = {
+ XE_HP_FEATURES,
+ XE_HPM_FEATURES,
+ XE_LPD_FEATURES,
+ DGFX_FEATURES,
+ .graphics_rel = 55,
+ .media_rel = 55,
+ PLATFORM(INTEL_DG2),
+ .platform_engine_mask =
+ BIT(RCS0) | BIT(BCS0) |
+ BIT(VECS0) | BIT(VECS1) |
+ BIT(VCS0) | BIT(VCS2),
+ .require_force_probe = 1,
+};
+
#undef PLATFORM
/*
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index 71d679ea5779..d5cf5977938a 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -69,6 +69,7 @@ static const char * const platform_names[] = {
PLATFORM_NAME(ALDERLAKE_S),
PLATFORM_NAME(ALDERLAKE_P),
PLATFORM_NAME(XEHPSDV),
+ PLATFORM_NAME(DG2),
};
#undef PLATFORM_NAME
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index 5db585b78cc7..c09f2dd24617 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -89,6 +89,7 @@ enum intel_platform {
INTEL_ALDERLAKE_S,
INTEL_ALDERLAKE_P,
INTEL_XEHPSDV,
+ INTEL_DG2,
INTEL_MAX_PLATFORMS
};
@@ -107,6 +108,10 @@ enum intel_platform {
/* CNL/ICL */
#define INTEL_SUBPLATFORM_PORTF (0)
+/* DG2 */
+#define INTEL_SUBPLATFORM_G10 0
+#define INTEL_SUBPLATFORM_G11 1
+
enum intel_ppgtt_type {
INTEL_PPGTT_NONE = I915_GEM_PPGTT_NONE,
INTEL_PPGTT_ALIASING = I915_GEM_PPGTT_ALIASING,
diff --git a/drivers/gpu/drm/i915/intel_step.c b/drivers/gpu/drm/i915/intel_step.c
index b99829bcb4f7..12c92e554253 100644
--- a/drivers/gpu/drm/i915/intel_step.c
+++ b/drivers/gpu/drm/i915/intel_step.c
@@ -108,6 +108,18 @@ static const struct intel_step_info xehpsdv_revids[] = {
[0x8] = { .gt_step = STEP_C0 },
};
+static const struct intel_step_info dg2_g10_revid_step_tbl[] = {
+ [0x0] = { .gt_step = STEP_A0, .display_step = STEP_A0 },
+ [0x1] = { .gt_step = STEP_A1, .display_step = STEP_A0 },
+ [0x4] = { .gt_step = STEP_B0, .display_step = STEP_B0 },
+ [0x8] = { .gt_step = STEP_C0, .display_step = STEP_C0 },
+};
+
+static const struct intel_step_info dg2_g11_revid_step_tbl[] = {
+ [0x0] = { .gt_step = STEP_A0, .display_step = STEP_B0 },
+ [0x4] = { .gt_step = STEP_B0, .display_step = STEP_C0 },
+};
+
void intel_step_init(struct drm_i915_private *i915)
{
const struct intel_step_info *revids = NULL;
@@ -115,7 +127,13 @@ void intel_step_init(struct drm_i915_private *i915)
int revid = INTEL_REVID(i915);
struct intel_step_info step = {};
- if (IS_XEHPSDV(i915)) {
+ if (IS_DG2_G10(i915)) {
+ revids = dg2_g10_revid_step_tbl;
+ size = ARRAY_SIZE(dg2_g10_revid_step_tbl);
+ } else if (IS_DG2_G11(i915)) {
+ revids = dg2_g11_revid_step_tbl;
+ size = ARRAY_SIZE(dg2_g11_revid_step_tbl);
+ } else if (IS_XEHPSDV(i915)) {
revids = xehpsdv_revids;
size = ARRAY_SIZE(xehpsdv_revids);
} else if (IS_ALDERLAKE_P(i915)) {
--
2.25.4
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next prev parent reply other threads:[~2021-07-21 22:30 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-07-21 22:30 [Intel-gfx] [CI 00/18] CI pass for reviewed Xe_HP SDV and DG2 patches Matt Roper
2021-07-21 22:30 ` [Intel-gfx] [CI 01/18] drm/i915: Add XE_HP initial definitions Matt Roper
2021-07-21 22:30 ` [Intel-gfx] [CI 02/18] drm/i915/xehpsdv: add initial XeHP SDV definitions Matt Roper
2021-07-21 22:30 ` Matt Roper [this message]
2021-07-21 22:30 ` [Intel-gfx] [CI 04/18] drm/i915: Fork DG1 interrupt handler Matt Roper
2021-07-21 22:30 ` [Intel-gfx] [CI 05/18] drm/i915/xehp: VDBOX/VEBOX fusing registers are enable-based Matt Roper
2021-07-21 22:30 ` [Intel-gfx] [CI 06/18] drm/i915/gen12: Use fuse info to enable SFC Matt Roper
2021-07-21 22:30 ` [Intel-gfx] [CI 07/18] drm/i915/selftests: Allow for larger engine counts Matt Roper
2021-07-21 22:30 ` [Intel-gfx] [CI 08/18] drm/i915/xehp: Handle new device context ID format Matt Roper
2021-07-21 22:30 ` [Intel-gfx] [CI 09/18] drm/i915/xehp: New engine context offsets Matt Roper
2021-07-21 22:30 ` [Intel-gfx] [CI 10/18] drm/i915/dg2: Add fake PCH Matt Roper
2021-07-21 22:30 ` [Intel-gfx] [CI 11/18] drm/i915/dg2: Add cdclk table and reference clock Matt Roper
2021-07-21 22:30 ` [Intel-gfx] [CI 12/18] drm/i915/dg2: Skip shared DPLL handling Matt Roper
2021-07-21 22:30 ` [Intel-gfx] [CI 13/18] drm/i915/dg2: Don't wait for AUX power well enable ACKs Matt Roper
2021-07-21 22:30 ` [Intel-gfx] [CI 14/18] drm/i915/dg2: Setup display outputs Matt Roper
2021-07-21 22:30 ` [Intel-gfx] [CI 15/18] drm/i915/dg2: Add dbuf programming Matt Roper
2021-07-21 22:30 ` [Intel-gfx] [CI 16/18] drm/i915/dg2: Don't program BW_BUDDY registers Matt Roper
2021-07-21 22:30 ` [Intel-gfx] [CI 17/18] drm/i915/dg2: Don't read DRAM info Matt Roper
2021-07-21 22:30 ` [Intel-gfx] [CI 18/18] drm/i915/dg2: DG2 has fixed memory bandwidth Matt Roper
2021-07-22 0:06 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for CI pass for reviewed Xe_HP SDV and DG2 patches Patchwork
2021-07-22 0:08 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-07-22 0:37 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-07-22 7:47 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2021-07-22 16:42 ` Matt Roper
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