From: Pekka Paalanen <ppaalanen@gmail.com>
To: "Shankar, Uma" <uma.shankar@intel.com>
Cc: "intel-gfx@lists.freedesktop.org"
<intel-gfx@lists.freedesktop.org>,
"dri-devel@lists.freedesktop.org"
<dri-devel@lists.freedesktop.org>,
"sebastian@sebastianwick.net" <sebastian@sebastianwick.net>,
Harry Wentland <harry.wentland@amd.com>
Subject: Re: [Intel-gfx] [RFC v2 01/22] drm: RFC for Plane Color Hardware Pipeline
Date: Fri, 26 Nov 2021 10:21:05 +0200 [thread overview]
Message-ID: <20211126102105.567428f2@eldfell> (raw)
In-Reply-To: <062cb4bfe0d94fb9aa34845b413e9021@intel.com>
[-- Attachment #1: Type: text/plain, Size: 5231 bytes --]
On Thu, 25 Nov 2021 20:43:19 +0000
"Shankar, Uma" <uma.shankar@intel.com> wrote:
> > -----Original Message-----
> > From: Harry Wentland <harry.wentland@amd.com>
> > Sent: Tuesday, November 23, 2021 8:35 PM
> > To: Shankar, Uma <uma.shankar@intel.com>; intel-gfx@lists.freedesktop.org; dri-
> > devel@lists.freedesktop.org
> > Cc: ville.syrjala@linux.intel.com; ppaalanen@gmail.com; brian.starkey@arm.com;
> > sebastian@sebastianwick.net; Shashank.Sharma@amd.com
> > Subject: Re: [RFC v2 01/22] drm: RFC for Plane Color Hardware Pipeline
> >
> >
> >
> > On 2021-09-06 17:38, Uma Shankar wrote:
> > > This is a RFC proposal for plane color hardware blocks.
> > > It exposes the property interface to userspace and calls out the
> > > details or interfaces created and the intended purpose.
> > >
> > > Credits: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> > > ---
> > > Documentation/gpu/rfc/drm_color_pipeline.rst | 167
> > > +++++++++++++++++++
> > > 1 file changed, 167 insertions(+)
> > > create mode 100644 Documentation/gpu/rfc/drm_color_pipeline.rst
> > >
> > > diff --git a/Documentation/gpu/rfc/drm_color_pipeline.rst
> > > b/Documentation/gpu/rfc/drm_color_pipeline.rst
> > > new file mode 100644
> > > index 000000000000..0d1ca858783b
> > > --- /dev/null
> > > +++ b/Documentation/gpu/rfc/drm_color_pipeline.rst
> > > @@ -0,0 +1,167 @@
> > > +==================================================
> > > +Display Color Pipeline: Proposed DRM Properties
> > > +==================================================
> > > +
> > > +This is how a typical display color hardware pipeline looks like:
> > > + +-------------------------------------------+
> > > + | RAM |
> > > + | +------+ +---------+ +---------+ |
> > > + | | FB 1 | | FB 2 | | FB N | |
> > > + | +------+ +---------+ +---------+ |
> > > + +-------------------------------------------+
> > > + | Plane Color Hardware Block |
> > > + +--------------------------------------------+
> > > + | +---v-----+ +---v-------+ +---v------+ |
> > > + | | Plane A | | Plane B | | Plane N | |
> > > + | | DeGamma | | Degamma | | Degamma | |
> > > + | +---+-----+ +---+-------+ +---+------+ |
> > > + | | | | |
> > > + | +---v-----+ +---v-------+ +---v------+ |
> > > + | |Plane A | | Plane B | | Plane N | |
> > > + | |CSC/CTM | | CSC/CTM | | CSC/CTM | |
> > > + | +---+-----+ +----+------+ +----+-----+ |
> > > + | | | | |
> > > + | +---v-----+ +----v------+ +----v-----+ |
> > > + | | Plane A | | Plane B | | Plane N | |
> > > + | | Gamma | | Gamma | | Gamma | |
> > > + | +---+-----+ +----+------+ +----+-----+ |
> > > + | | | | |
> > > + +--------------------------------------------+
> > > ++------v--------------v---------------v-------|
> > > +|| ||
> > > +|| Pipe Blender ||
> > > ++--------------------+------------------------+
> > > +| | |
> > > +| +-----------v----------+ |
> > > +| | Pipe DeGamma | |
> > > +| | | |
> > > +| +-----------+----------+ |
> > > +| | Pipe Color |
> > > +| +-----------v----------+ Hardware |
> > > +| | Pipe CSC/CTM | |
> > > +| | | |
> > > +| +-----------+----------+ |
> > > +| | |
> > > +| +-----------v----------+ |
> > > +| | Pipe Gamma | |
> > > +| | | |
> > > +| +-----------+----------+ |
> > > +| | |
> > > ++---------------------------------------------+
> > > + |
> > > + v
> > > + Pipe Output
> > > +
> >
> > This diagram defines what happens before and after the blending space but did
> > where does scaling fit into it? Scaling can look different when performed in linear or
> > non-linear space so I think it is important to define where in the pipeline it sits.
> >
> > In my view scaling would happen between plane degamma and plane CSC.
>
> Yeah we can add scaling as well to make it clear. Scaling ideally should happen after
> Degamma. In intel's case it is after the CSC.
Btw. are you aware that if a plane has an alpha channel which is used
for pixel coverage (i.e. shape anti-aliasing), then non-nearest
sampling and therefore also scaling must operate on alpha
pre-multiplied optical (linear) values?
For the best results, of course.
So after degamma indeed, but you cannot degamma with pre-multiplied
alpha, yet scaling should use pre-multiplied alpha.
Thanks,
pq
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next prev parent reply other threads:[~2021-11-26 8:21 UTC|newest]
Thread overview: 79+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-09-06 21:38 [Intel-gfx] [RFC v2 00/22] Add Support for Plane Color Lut and CSC features Uma Shankar
2021-09-06 21:26 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Add Support for Plane Color Lut and CSC features (rev2) Patchwork
2021-09-06 21:30 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-09-06 21:38 ` [Intel-gfx] [RFC v2 01/22] drm: RFC for Plane Color Hardware Pipeline Uma Shankar
2021-10-12 10:30 ` Pekka Paalanen
2021-10-12 10:35 ` Simon Ser
2021-10-12 12:00 ` Pekka Paalanen
2021-10-12 19:11 ` Shankar, Uma
2021-10-13 7:25 ` Pekka Paalanen
2021-10-14 19:46 ` Shankar, Uma
2021-10-12 20:58 ` Shankar, Uma
2021-10-13 8:30 ` Pekka Paalanen
2021-10-14 19:44 ` Shankar, Uma
2021-10-15 7:42 ` Pekka Paalanen
2021-10-26 15:11 ` Harry Wentland
2021-10-26 15:36 ` Harry Wentland
2021-10-27 8:00 ` Pekka Paalanen
2021-10-27 12:48 ` Harry Wentland
2021-10-26 15:40 ` Harry Wentland
2021-11-23 15:05 ` Harry Wentland
2021-11-25 20:43 ` Shankar, Uma
2021-11-26 8:21 ` Pekka Paalanen [this message]
2021-09-06 21:38 ` [Intel-gfx] [RFC v2 02/22] drm: Add Enhanced Gamma and color lut range attributes Uma Shankar
2021-11-03 15:08 ` Harry Wentland
2021-11-04 8:38 ` Pekka Paalanen
2021-11-04 16:27 ` Harry Wentland
2021-11-05 11:49 ` Ville Syrjälä
2021-11-09 20:22 ` Harry Wentland
2021-11-08 9:54 ` Pekka Paalanen
2021-11-09 20:47 ` Harry Wentland
2021-11-09 22:02 ` Ville Syrjälä
2021-11-10 8:49 ` Pekka Paalanen
2021-11-10 11:55 ` Ville Syrjälä
2021-11-10 15:17 ` Harry Wentland
2021-11-11 8:22 ` Pekka Paalanen
2021-09-06 21:38 ` [Intel-gfx] [RFC v2 03/22] drm: Add Plane Degamma Mode property Uma Shankar
2021-10-12 11:50 ` Pekka Paalanen
2021-10-12 21:02 ` Shankar, Uma
2021-09-06 21:38 ` [Intel-gfx] [RFC v2 04/22] drm: Add Plane Degamma Lut property Uma Shankar
2021-09-06 21:38 ` [Intel-gfx] [RFC v2 05/22] drm/i915/xelpd: Define Degamma Lut range struct for HDR planes Uma Shankar
2021-11-03 15:10 ` Harry Wentland
2021-11-05 12:59 ` Ville Syrjälä
2021-11-09 20:19 ` Harry Wentland
2021-11-09 21:45 ` Ville Syrjälä
2021-11-09 21:56 ` Harry Wentland
2021-11-11 15:17 ` Harry Wentland
2021-11-11 16:42 ` Ville Syrjälä
2021-11-11 20:42 ` Shankar, Uma
2021-11-11 21:10 ` Harry Wentland
2021-11-11 21:58 ` Shankar, Uma
2021-11-12 8:37 ` Pekka Paalanen
2021-11-23 14:40 ` Harry Wentland
2021-11-12 14:54 ` Ville Syrjälä
2021-11-16 8:15 ` Pekka Paalanen
2021-09-06 21:38 ` [Intel-gfx] [RFC v2 06/22] drm/i915/xelpd: Add register definitions for Plane Degamma Uma Shankar
2021-09-06 21:38 ` [Intel-gfx] [RFC v2 07/22] drm/i915/xelpd: Enable plane color features Uma Shankar
2021-09-06 21:38 ` [Intel-gfx] [RFC v2 08/22] drm/i915/xelpd: Add color capabilities of SDR planes Uma Shankar
2021-09-06 21:38 ` [Intel-gfx] [RFC v2 09/22] drm/i915/xelpd: Program Plane Degamma Registers Uma Shankar
2021-09-06 21:38 ` [Intel-gfx] [RFC v2 10/22] drm/i915/xelpd: Add plane color check to glk_plane_color_ctl Uma Shankar
2021-09-06 21:38 ` [Intel-gfx] [RFC v2 11/22] drm/i915/xelpd: Initialize plane color features Uma Shankar
2021-09-06 21:38 ` [Intel-gfx] [RFC v2 12/22] drm/i915/xelpd: Load plane color luts from atomic flip Uma Shankar
2021-09-06 21:38 ` [Intel-gfx] [RFC v2 13/22] drm: Add Plane CTM property Uma Shankar
2021-09-06 21:38 ` [Intel-gfx] [RFC v2 14/22] drm: Add helper to attach Plane ctm property Uma Shankar
2021-09-06 21:38 ` [Intel-gfx] [RFC v2 15/22] drm/i915/xelpd: Define Plane CSC Registers Uma Shankar
2021-09-06 21:38 ` [Intel-gfx] [RFC v2 16/22] drm/i915/xelpd: Enable Plane CSC Uma Shankar
2021-09-06 21:38 ` [Intel-gfx] [RFC v2 17/22] drm: Add Plane Gamma Mode property Uma Shankar
2021-09-06 21:39 ` [Intel-gfx] [RFC v2 18/22] drm: Add Plane Gamma Lut property Uma Shankar
2021-09-06 21:39 ` [Intel-gfx] [RFC v2 19/22] drm/i915/xelpd: Define and Initialize Plane Gamma Lut range Uma Shankar
2021-09-06 21:39 ` [Intel-gfx] [RFC v2 20/22] drm/i915/xelpd: Add register definitions for Plane Gamma Uma Shankar
2021-09-06 21:39 ` [Intel-gfx] [RFC v2 21/22] drm/i915/xelpd: Program Plane Gamma Registers Uma Shankar
2021-09-06 21:39 ` [Intel-gfx] [RFC v2 22/22] drm/i915/xelpd: Enable plane gamma Uma Shankar
2021-09-06 21:57 ` [Intel-gfx] ✓ Fi.CI.BAT: success for Add Support for Plane Color Lut and CSC features (rev2) Patchwork
2021-09-06 23:12 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2021-10-12 11:55 ` [Intel-gfx] [RFC v2 00/22] Add Support for Plane Color Lut and CSC features Pekka Paalanen
2021-10-12 21:01 ` Shankar, Uma
2021-10-26 15:02 ` Harry Wentland
2021-10-27 8:18 ` Pekka Paalanen
2022-02-02 16:11 ` Harry Wentland
2022-02-03 17:22 ` Shankar, Uma
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