* [PATCH v2 0/4] drm/i915: i915_reg.h cleanups
@ 2024-04-26 10:51 Jani Nikula
2024-04-26 10:51 ` [PATCH v2 1/4] drm/i915/audio: move LPE audio regs to intel_audio_regs.h Jani Nikula
` (6 more replies)
0 siblings, 7 replies; 10+ messages in thread
From: Jani Nikula @ 2024-04-26 10:51 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, ville.syrjala
v2 of https://lore.kernel.org/r/cover.1712933479.git.jani.nikula@intel.com
Jani Nikula (4):
drm/i915/audio: move LPE audio regs to intel_audio_regs.h
drm/i915/color: move palette registers to intel_color_regs.h
drm/i915/display: split out intel_fbc_regs.h from i915_reg.h
drm/i915/display: split out intel_sprite_regs.h from i915_reg.h
.../gpu/drm/i915/display/intel_audio_regs.h | 16 +
.../gpu/drm/i915/display/intel_color_regs.h | 30 +-
drivers/gpu/drm/i915/display/intel_fbc.c | 1 +
drivers/gpu/drm/i915/display/intel_fbc_regs.h | 120 +++++
.../gpu/drm/i915/display/intel_lpe_audio.c | 2 +-
drivers/gpu/drm/i915/display/intel_sprite.c | 1 +
.../gpu/drm/i915/display/intel_sprite_regs.h | 348 ++++++++++++
drivers/gpu/drm/i915/gt/intel_workarounds.c | 2 +
drivers/gpu/drm/i915/gvt/cmd_parser.c | 1 +
drivers/gpu/drm/i915/gvt/display.c | 1 +
drivers/gpu/drm/i915/gvt/fb_decoder.c | 5 +-
drivers/gpu/drm/i915/gvt/handlers.c | 1 +
drivers/gpu/drm/i915/i915_reg.h | 509 ------------------
drivers/gpu/drm/i915/intel_clock_gating.c | 1 +
drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 2 +
15 files changed, 528 insertions(+), 512 deletions(-)
create mode 100644 drivers/gpu/drm/i915/display/intel_fbc_regs.h
create mode 100644 drivers/gpu/drm/i915/display/intel_sprite_regs.h
--
2.39.2
^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH v2 1/4] drm/i915/audio: move LPE audio regs to intel_audio_regs.h
2024-04-26 10:51 [PATCH v2 0/4] drm/i915: i915_reg.h cleanups Jani Nikula
@ 2024-04-26 10:51 ` Jani Nikula
2024-04-26 10:51 ` [PATCH v2 2/4] drm/i915/color: move palette registers to intel_color_regs.h Jani Nikula
` (5 subsequent siblings)
6 siblings, 0 replies; 10+ messages in thread
From: Jani Nikula @ 2024-04-26 10:51 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, ville.syrjala
There are too few registers to warrant a dedicated file for LPE audio
regs, but the audio reg file is better than i915_reg.h.
v2: Rebase
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/intel_audio_regs.h | 16 ++++++++++++++++
drivers/gpu/drm/i915/display/intel_lpe_audio.c | 2 +-
drivers/gpu/drm/i915/i915_reg.h | 16 ----------------
3 files changed, 17 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_audio_regs.h b/drivers/gpu/drm/i915/display/intel_audio_regs.h
index 616e7b1275c4..88ea2740365d 100644
--- a/drivers/gpu/drm/i915/display/intel_audio_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_audio_regs.h
@@ -148,4 +148,20 @@
#define HBLANK_START_COUNT_96 4
#define HBLANK_START_COUNT_128 5
+/* LPE Audio */
+#define I915_HDMI_LPE_AUDIO_BASE (VLV_DISPLAY_BASE + 0x65000)
+#define I915_HDMI_LPE_AUDIO_SIZE 0x1000
+
+#define VLV_AUD_CHICKEN_BIT_REG _MMIO(VLV_DISPLAY_BASE + 0x62F38)
+#define VLV_CHICKEN_BIT_DBG_ENABLE (1 << 0)
+
+#define _VLV_AUD_PORT_EN_B_DBG 0x62F20
+#define _VLV_AUD_PORT_EN_C_DBG 0x62F30
+#define _VLV_AUD_PORT_EN_D_DBG 0x62F34
+#define VLV_AUD_PORT_EN_DBG(port) _MMIO_BASE_PORT3(VLV_DISPLAY_BASE, (port) - PORT_B, \
+ _VLV_AUD_PORT_EN_B_DBG, \
+ _VLV_AUD_PORT_EN_C_DBG, \
+ _VLV_AUD_PORT_EN_D_DBG)
+#define VLV_AMP_MUTE (1 << 1)
+
#endif /* __INTEL_AUDIO_REGS_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_lpe_audio.c b/drivers/gpu/drm/i915/display/intel_lpe_audio.c
index 5863763de530..93e6cac9a4ed 100644
--- a/drivers/gpu/drm/i915/display/intel_lpe_audio.c
+++ b/drivers/gpu/drm/i915/display/intel_lpe_audio.c
@@ -72,7 +72,7 @@
#include "i915_drv.h"
#include "i915_irq.h"
-#include "i915_reg.h"
+#include "intel_audio_regs.h"
#include "intel_de.h"
#include "intel_lpe_audio.h"
#include "intel_pci_config.h"
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 4eb37f38d888..4913b9a371c0 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -966,22 +966,6 @@
#define I915_ASLE_INTERRUPT (1 << 0)
#define I915_BSD_USER_INTERRUPT (1 << 25)
-#define I915_HDMI_LPE_AUDIO_BASE (VLV_DISPLAY_BASE + 0x65000)
-#define I915_HDMI_LPE_AUDIO_SIZE 0x1000
-
-/* DisplayPort Audio w/ LPE */
-#define VLV_AUD_CHICKEN_BIT_REG _MMIO(VLV_DISPLAY_BASE + 0x62F38)
-#define VLV_CHICKEN_BIT_DBG_ENABLE (1 << 0)
-
-#define _VLV_AUD_PORT_EN_B_DBG 0x62F20
-#define _VLV_AUD_PORT_EN_C_DBG 0x62F30
-#define _VLV_AUD_PORT_EN_D_DBG 0x62F34
-#define VLV_AUD_PORT_EN_DBG(port) _MMIO_BASE_PORT3(VLV_DISPLAY_BASE, (port) - PORT_B, \
- _VLV_AUD_PORT_EN_B_DBG, \
- _VLV_AUD_PORT_EN_C_DBG, \
- _VLV_AUD_PORT_EN_D_DBG)
-#define VLV_AMP_MUTE (1 << 1)
-
#define GEN6_BSD_RNCID _MMIO(0x12198)
#define GEN7_FF_THREAD_MODE _MMIO(0x20a0)
--
2.39.2
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH v2 2/4] drm/i915/color: move palette registers to intel_color_regs.h
2024-04-26 10:51 [PATCH v2 0/4] drm/i915: i915_reg.h cleanups Jani Nikula
2024-04-26 10:51 ` [PATCH v2 1/4] drm/i915/audio: move LPE audio regs to intel_audio_regs.h Jani Nikula
@ 2024-04-26 10:51 ` Jani Nikula
2024-04-26 10:51 ` [PATCH v2 3/4] drm/i915/display: split out intel_fbc_regs.h from i915_reg.h Jani Nikula
` (4 subsequent siblings)
6 siblings, 0 replies; 10+ messages in thread
From: Jani Nikula @ 2024-04-26 10:51 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, ville.syrjala
For some reason the paletter registers were missed when adding
intel_color_regs.h. Finish the job. Adjust some comments while at it.
v2: Fix comments (Ville)
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
.../gpu/drm/i915/display/intel_color_regs.h | 30 ++++++++++++++++++-
drivers/gpu/drm/i915/i915_reg.h | 30 -------------------
2 files changed, 29 insertions(+), 31 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_color_regs.h b/drivers/gpu/drm/i915/display/intel_color_regs.h
index ec8732401cd8..02033c882d7f 100644
--- a/drivers/gpu/drm/i915/display/intel_color_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_color_regs.h
@@ -8,7 +8,35 @@
#include "intel_display_reg_defs.h"
-/* legacy palette */
+/* GMCH palette */
+#define _PALETTE_A 0xa000
+#define _PALETTE_B 0xa800
+#define _CHV_PALETTE_C 0xc000
+/* 8bit mode / i965+ 10.6 interpolated mode ldw/udw */
+#define PALETTE_RED_MASK REG_GENMASK(23, 16)
+#define PALETTE_GREEN_MASK REG_GENMASK(15, 8)
+#define PALETTE_BLUE_MASK REG_GENMASK(7, 0)
+/* pre-i965 10bit interpolated mode ldw */
+#define PALETTE_10BIT_RED_LDW_MASK REG_GENMASK(23, 16)
+#define PALETTE_10BIT_GREEN_LDW_MASK REG_GENMASK(15, 8)
+#define PALETTE_10BIT_BLUE_LDW_MASK REG_GENMASK(7, 0)
+/* pre-i965 10bit interpolated mode udw */
+#define PALETTE_10BIT_RED_EXP_MASK REG_GENMASK(23, 22)
+#define PALETTE_10BIT_RED_MANT_MASK REG_GENMASK(21, 18)
+#define PALETTE_10BIT_RED_UDW_MASK REG_GENMASK(17, 16)
+#define PALETTE_10BIT_GREEN_EXP_MASK REG_GENMASK(15, 14)
+#define PALETTE_10BIT_GREEN_MANT_MASK REG_GENMASK(13, 10)
+#define PALETTE_10BIT_GREEN_UDW_MASK REG_GENMASK(9, 8)
+#define PALETTE_10BIT_BLUE_EXP_MASK REG_GENMASK(7, 6)
+#define PALETTE_10BIT_BLUE_MANT_MASK REG_GENMASK(5, 2)
+#define PALETTE_10BIT_BLUE_UDW_MASK REG_GENMASK(1, 0)
+#define PALETTE(pipe, i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + \
+ _PICK_EVEN_2RANGES(pipe, 2, \
+ _PALETTE_A, _PALETTE_B, \
+ _CHV_PALETTE_C, _CHV_PALETTE_C) + \
+ (i) * 4)
+
+/* ilk+ palette */
#define _LGC_PALETTE_A 0x4a000
#define _LGC_PALETTE_B 0x4a800
/* see PALETTE_* for the bits */
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 4913b9a371c0..c5ea2ed653b9 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1440,36 +1440,6 @@
#define GMBUSFREQ_VLV _MMIO(VLV_DISPLAY_BASE + 0x6510)
-/*
- * Palette regs
- */
-#define _PALETTE_A 0xa000
-#define _PALETTE_B 0xa800
-#define _CHV_PALETTE_C 0xc000
-/* 8bit mode / i965+ 10.6 interpolated mode ldw/udw */
-#define PALETTE_RED_MASK REG_GENMASK(23, 16)
-#define PALETTE_GREEN_MASK REG_GENMASK(15, 8)
-#define PALETTE_BLUE_MASK REG_GENMASK(7, 0)
-/* pre-i965 10bit interpolated mode ldw */
-#define PALETTE_10BIT_RED_LDW_MASK REG_GENMASK(23, 16)
-#define PALETTE_10BIT_GREEN_LDW_MASK REG_GENMASK(15, 8)
-#define PALETTE_10BIT_BLUE_LDW_MASK REG_GENMASK(7, 0)
-/* pre-i965 10bit interpolated mode udw */
-#define PALETTE_10BIT_RED_EXP_MASK REG_GENMASK(23, 22)
-#define PALETTE_10BIT_RED_MANT_MASK REG_GENMASK(21, 18)
-#define PALETTE_10BIT_RED_UDW_MASK REG_GENMASK(17, 16)
-#define PALETTE_10BIT_GREEN_EXP_MASK REG_GENMASK(15, 14)
-#define PALETTE_10BIT_GREEN_MANT_MASK REG_GENMASK(13, 10)
-#define PALETTE_10BIT_GREEN_UDW_MASK REG_GENMASK(9, 8)
-#define PALETTE_10BIT_BLUE_EXP_MASK REG_GENMASK(7, 6)
-#define PALETTE_10BIT_BLUE_MANT_MASK REG_GENMASK(5, 2)
-#define PALETTE_10BIT_BLUE_UDW_MASK REG_GENMASK(1, 0)
-#define PALETTE(pipe, i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + \
- _PICK_EVEN_2RANGES(pipe, 2, \
- _PALETTE_A, _PALETTE_B, \
- _CHV_PALETTE_C, _CHV_PALETTE_C) + \
- (i) * 4)
-
#define PEG_BAND_GAP_DATA _MMIO(0x14d68)
#define BXT_RP_STATE_CAP _MMIO(0x138170)
--
2.39.2
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH v2 3/4] drm/i915/display: split out intel_fbc_regs.h from i915_reg.h
2024-04-26 10:51 [PATCH v2 0/4] drm/i915: i915_reg.h cleanups Jani Nikula
2024-04-26 10:51 ` [PATCH v2 1/4] drm/i915/audio: move LPE audio regs to intel_audio_regs.h Jani Nikula
2024-04-26 10:51 ` [PATCH v2 2/4] drm/i915/color: move palette registers to intel_color_regs.h Jani Nikula
@ 2024-04-26 10:51 ` Jani Nikula
2024-04-26 15:03 ` Ville Syrjälä
2024-04-26 10:51 ` [PATCH v2 4/4] drm/i915/display: split out intel_sprite_regs.h " Jani Nikula
` (3 subsequent siblings)
6 siblings, 1 reply; 10+ messages in thread
From: Jani Nikula @ 2024-04-26 10:51 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, ville.syrjala
Clean up i915_reg.h.
v2: Drop chicken regs and comments (Ville)
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/intel_fbc.c | 1 +
drivers/gpu/drm/i915/display/intel_fbc_regs.h | 120 +++++++++++++++++
drivers/gpu/drm/i915/gt/intel_workarounds.c | 2 +
drivers/gpu/drm/i915/i915_reg.h | 123 ------------------
drivers/gpu/drm/i915/intel_clock_gating.c | 1 +
drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 1 +
6 files changed, 125 insertions(+), 123 deletions(-)
create mode 100644 drivers/gpu/drm/i915/display/intel_fbc_regs.h
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
index 7c4d2b2bf20b..151dcd0c45b6 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -54,6 +54,7 @@
#include "intel_display_trace.h"
#include "intel_display_types.h"
#include "intel_fbc.h"
+#include "intel_fbc_regs.h"
#include "intel_frontbuffer.h"
#define for_each_fbc_id(__dev_priv, __fbc_id) \
diff --git a/drivers/gpu/drm/i915/display/intel_fbc_regs.h b/drivers/gpu/drm/i915/display/intel_fbc_regs.h
new file mode 100644
index 000000000000..ae0699c3c2fe
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_fbc_regs.h
@@ -0,0 +1,120 @@
+/* SPDX-License-Identifier: MIT */
+/* Copyright © 2024 Intel Corporation */
+
+#ifndef __INTEL_FBC_REGS__
+#define __INTEL_FBC_REGS__
+
+#include "intel_display_reg_defs.h"
+
+#define FBC_CFB_BASE _MMIO(0x3200) /* 4k page aligned */
+#define FBC_LL_BASE _MMIO(0x3204) /* 4k page aligned */
+#define FBC_CONTROL _MMIO(0x3208)
+#define FBC_CTL_EN REG_BIT(31)
+#define FBC_CTL_PERIODIC REG_BIT(30)
+#define FBC_CTL_INTERVAL_MASK REG_GENMASK(29, 16)
+#define FBC_CTL_INTERVAL(x) REG_FIELD_PREP(FBC_CTL_INTERVAL_MASK, (x))
+#define FBC_CTL_STOP_ON_MOD REG_BIT(15)
+#define FBC_CTL_UNCOMPRESSIBLE REG_BIT(14) /* i915+ */
+#define FBC_CTL_C3_IDLE REG_BIT(13) /* i945gm only */
+#define FBC_CTL_STRIDE_MASK REG_GENMASK(12, 5)
+#define FBC_CTL_STRIDE(x) REG_FIELD_PREP(FBC_CTL_STRIDE_MASK, (x))
+#define FBC_CTL_FENCENO_MASK REG_GENMASK(3, 0)
+#define FBC_CTL_FENCENO(x) REG_FIELD_PREP(FBC_CTL_FENCENO_MASK, (x))
+#define FBC_COMMAND _MMIO(0x320c)
+#define FBC_CMD_COMPRESS REG_BIT(0)
+#define FBC_STATUS _MMIO(0x3210)
+#define FBC_STAT_COMPRESSING REG_BIT(31)
+#define FBC_STAT_COMPRESSED REG_BIT(30)
+#define FBC_STAT_MODIFIED REG_BIT(29)
+#define FBC_STAT_CURRENT_LINE_MASK REG_GENMASK(10, 0)
+#define FBC_CONTROL2 _MMIO(0x3214) /* i965gm only */
+#define FBC_CTL_FENCE_DBL REG_BIT(4)
+#define FBC_CTL_IDLE_MASK REG_GENMASK(3, 2)
+#define FBC_CTL_IDLE_IMM REG_FIELD_PREP(FBC_CTL_IDLE_MASK, 0)
+#define FBC_CTL_IDLE_FULL REG_FIELD_PREP(FBC_CTL_IDLE_MASK, 1)
+#define FBC_CTL_IDLE_LINE REG_FIELD_PREP(FBC_CTL_IDLE_MASK, 2)
+#define FBC_CTL_IDLE_DEBUG REG_FIELD_PREP(FBC_CTL_IDLE_MASK, 3)
+#define FBC_CTL_CPU_FENCE_EN REG_BIT(1)
+#define FBC_CTL_PLANE_MASK REG_GENMASK(1, 0)
+#define FBC_CTL_PLANE(i9xx_plane) REG_FIELD_PREP(FBC_CTL_PLANE_MASK, (i9xx_plane))
+#define FBC_FENCE_OFF _MMIO(0x3218) /* i965gm only, BSpec typo has 321Bh */
+#define FBC_MOD_NUM _MMIO(0x3220) /* i965gm only */
+#define FBC_MOD_NUM_MASK REG_GENMASK(31, 1)
+#define FBC_MOD_NUM_VALID REG_BIT(0)
+#define FBC_TAG(i) _MMIO(0x3300 + (i) * 4) /* 49 reisters */
+#define FBC_TAG_MASK REG_GENMASK(1, 0) /* 16 tags per register */
+#define FBC_TAG_MODIFIED REG_FIELD_PREP(FBC_TAG_MASK, 0)
+#define FBC_TAG_UNCOMPRESSED REG_FIELD_PREP(FBC_TAG_MASK, 1)
+#define FBC_TAG_UNCOMPRESSIBLE REG_FIELD_PREP(FBC_TAG_MASK, 2)
+#define FBC_TAG_COMPRESSED REG_FIELD_PREP(FBC_TAG_MASK, 3)
+
+#define FBC_LL_SIZE (1536)
+
+#define DPFC_CB_BASE _MMIO(0x3200)
+#define ILK_DPFC_CB_BASE(fbc_id) _MMIO_PIPE((fbc_id), 0x43200, 0x43240)
+#define DPFC_CONTROL _MMIO(0x3208)
+#define ILK_DPFC_CONTROL(fbc_id) _MMIO_PIPE((fbc_id), 0x43208, 0x43248)
+#define DPFC_CTL_EN REG_BIT(31)
+#define DPFC_CTL_PLANE_MASK_G4X REG_BIT(30) /* g4x-snb */
+#define DPFC_CTL_PLANE_G4X(i9xx_plane) REG_FIELD_PREP(DPFC_CTL_PLANE_MASK_G4X, (i9xx_plane))
+#define DPFC_CTL_FENCE_EN_G4X REG_BIT(29) /* g4x-snb */
+#define DPFC_CTL_PLANE_MASK_IVB REG_GENMASK(30, 29) /* ivb only */
+#define DPFC_CTL_PLANE_IVB(i9xx_plane) REG_FIELD_PREP(DPFC_CTL_PLANE_MASK_IVB, (i9xx_plane))
+#define DPFC_CTL_FENCE_EN_IVB REG_BIT(28) /* ivb+ */
+#define DPFC_CTL_PERSISTENT_MODE REG_BIT(25) /* g4x-snb */
+#define DPFC_CTL_PLANE_BINDING_MASK REG_GENMASK(12, 11) /* lnl+ */
+#define DPFC_CTL_PLANE_BINDING(plane_id) REG_FIELD_PREP(DPFC_CTL_PLANE_BINDING_MASK, (plane_id))
+#define DPFC_CTL_FALSE_COLOR REG_BIT(10) /* ivb+ */
+#define DPFC_CTL_SR_EN REG_BIT(10) /* g4x only */
+#define DPFC_CTL_SR_EXIT_DIS REG_BIT(9) /* g4x only */
+#define DPFC_CTL_LIMIT_MASK REG_GENMASK(7, 6)
+#define DPFC_CTL_LIMIT_1X REG_FIELD_PREP(DPFC_CTL_LIMIT_MASK, 0)
+#define DPFC_CTL_LIMIT_2X REG_FIELD_PREP(DPFC_CTL_LIMIT_MASK, 1)
+#define DPFC_CTL_LIMIT_4X REG_FIELD_PREP(DPFC_CTL_LIMIT_MASK, 2)
+#define DPFC_CTL_FENCENO_MASK REG_GENMASK(3, 0)
+#define DPFC_CTL_FENCENO(fence) REG_FIELD_PREP(DPFC_CTL_FENCENO_MASK, (fence))
+#define DPFC_RECOMP_CTL _MMIO(0x320c)
+#define ILK_DPFC_RECOMP_CTL(fbc_id) _MMIO_PIPE((fbc_id), 0x4320c, 0x4324c)
+#define DPFC_RECOMP_STALL_EN REG_BIT(27)
+#define DPFC_RECOMP_STALL_WM_MASK REG_GENMASK(26, 16)
+#define DPFC_RECOMP_TIMER_COUNT_MASK REG_GENMASK(5, 0)
+#define DPFC_STATUS _MMIO(0x3210)
+#define ILK_DPFC_STATUS(fbc_id) _MMIO_PIPE((fbc_id), 0x43210, 0x43250)
+#define DPFC_INVAL_SEG_MASK REG_GENMASK(26, 16)
+#define DPFC_COMP_SEG_MASK REG_GENMASK(10, 0)
+#define DPFC_STATUS2 _MMIO(0x3214)
+#define ILK_DPFC_STATUS2(fbc_id) _MMIO_PIPE((fbc_id), 0x43214, 0x43254)
+#define DPFC_COMP_SEG_MASK_IVB REG_GENMASK(11, 0)
+#define DPFC_FENCE_YOFF _MMIO(0x3218)
+#define ILK_DPFC_FENCE_YOFF(fbc_id) _MMIO_PIPE((fbc_id), 0x43218, 0x43258)
+#define DPFC_CHICKEN _MMIO(0x3224)
+#define ILK_DPFC_CHICKEN(fbc_id) _MMIO_PIPE((fbc_id), 0x43224, 0x43264)
+#define DPFC_HT_MODIFY REG_BIT(31) /* pre-ivb */
+#define DPFC_NUKE_ON_ANY_MODIFICATION REG_BIT(23) /* bdw+ */
+#define DPFC_CHICKEN_COMP_DUMMY_PIXEL REG_BIT(14) /* glk+ */
+#define DPFC_CHICKEN_FORCE_SLB_INVALIDATION REG_BIT(13) /* icl+ */
+#define DPFC_DISABLE_DUMMY0 REG_BIT(8) /* ivb+ */
+
+#define GLK_FBC_STRIDE(fbc_id) _MMIO_PIPE((fbc_id), 0x43228, 0x43268)
+#define FBC_STRIDE_OVERRIDE REG_BIT(15)
+#define FBC_STRIDE_MASK REG_GENMASK(14, 0)
+#define FBC_STRIDE(x) REG_FIELD_PREP(FBC_STRIDE_MASK, (x))
+
+#define ILK_FBC_RT_BASE _MMIO(0x2128)
+#define ILK_FBC_RT_VALID REG_BIT(0)
+#define SNB_FBC_FRONT_BUFFER REG_BIT(1)
+
+#define SNB_DPFC_CTL_SA _MMIO(0x100100)
+#define SNB_DPFC_FENCE_EN REG_BIT(29)
+#define SNB_DPFC_FENCENO_MASK REG_GENMASK(4, 0)
+#define SNB_DPFC_FENCENO(fence) REG_FIELD_PREP(SNB_DPFC_FENCENO_MASK, (fence))
+#define SNB_DPFC_CPU_FENCE_OFFSET _MMIO(0x100104)
+
+#define IVB_FBC_RT_BASE _MMIO(0x7020)
+#define IVB_FBC_RT_BASE_UPPER _MMIO(0x7024)
+
+#define MSG_FBC_REND_STATE(fbc_id) _MMIO_PIPE((fbc_id), 0x50380, 0x50384)
+#define FBC_REND_NUKE REG_BIT(2)
+#define FBC_REND_CACHE_CLEAN REG_BIT(1)
+
+#endif /* __INTEL_FBC_REGS__ */
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 68b6aa11bcf7..40e79f0dc257 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -17,6 +17,8 @@
#include "intel_ring.h"
#include "intel_workarounds.h"
+#include "display/intel_fbc_regs.h"
+
/**
* DOC: Hardware workarounds
*
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c5ea2ed653b9..5cdf3b17e7d4 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -986,109 +986,6 @@
#define GEN7_FF_DS_SCHED_LOAD_BALANCE (0x1 << 4) /* Default */
#define GEN7_FF_DS_SCHED_HW (0x0 << 4)
-/*
- * Framebuffer compression (915+ only)
- */
-
-#define FBC_CFB_BASE _MMIO(0x3200) /* 4k page aligned */
-#define FBC_LL_BASE _MMIO(0x3204) /* 4k page aligned */
-#define FBC_CONTROL _MMIO(0x3208)
-#define FBC_CTL_EN REG_BIT(31)
-#define FBC_CTL_PERIODIC REG_BIT(30)
-#define FBC_CTL_INTERVAL_MASK REG_GENMASK(29, 16)
-#define FBC_CTL_INTERVAL(x) REG_FIELD_PREP(FBC_CTL_INTERVAL_MASK, (x))
-#define FBC_CTL_STOP_ON_MOD REG_BIT(15)
-#define FBC_CTL_UNCOMPRESSIBLE REG_BIT(14) /* i915+ */
-#define FBC_CTL_C3_IDLE REG_BIT(13) /* i945gm only */
-#define FBC_CTL_STRIDE_MASK REG_GENMASK(12, 5)
-#define FBC_CTL_STRIDE(x) REG_FIELD_PREP(FBC_CTL_STRIDE_MASK, (x))
-#define FBC_CTL_FENCENO_MASK REG_GENMASK(3, 0)
-#define FBC_CTL_FENCENO(x) REG_FIELD_PREP(FBC_CTL_FENCENO_MASK, (x))
-#define FBC_COMMAND _MMIO(0x320c)
-#define FBC_CMD_COMPRESS REG_BIT(0)
-#define FBC_STATUS _MMIO(0x3210)
-#define FBC_STAT_COMPRESSING REG_BIT(31)
-#define FBC_STAT_COMPRESSED REG_BIT(30)
-#define FBC_STAT_MODIFIED REG_BIT(29)
-#define FBC_STAT_CURRENT_LINE_MASK REG_GENMASK(10, 0)
-#define FBC_CONTROL2 _MMIO(0x3214) /* i965gm only */
-#define FBC_CTL_FENCE_DBL REG_BIT(4)
-#define FBC_CTL_IDLE_MASK REG_GENMASK(3, 2)
-#define FBC_CTL_IDLE_IMM REG_FIELD_PREP(FBC_CTL_IDLE_MASK, 0)
-#define FBC_CTL_IDLE_FULL REG_FIELD_PREP(FBC_CTL_IDLE_MASK, 1)
-#define FBC_CTL_IDLE_LINE REG_FIELD_PREP(FBC_CTL_IDLE_MASK, 2)
-#define FBC_CTL_IDLE_DEBUG REG_FIELD_PREP(FBC_CTL_IDLE_MASK, 3)
-#define FBC_CTL_CPU_FENCE_EN REG_BIT(1)
-#define FBC_CTL_PLANE_MASK REG_GENMASK(1, 0)
-#define FBC_CTL_PLANE(i9xx_plane) REG_FIELD_PREP(FBC_CTL_PLANE_MASK, (i9xx_plane))
-#define FBC_FENCE_OFF _MMIO(0x3218) /* i965gm only, BSpec typo has 321Bh */
-#define FBC_MOD_NUM _MMIO(0x3220) /* i965gm only */
-#define FBC_MOD_NUM_MASK REG_GENMASK(31, 1)
-#define FBC_MOD_NUM_VALID REG_BIT(0)
-#define FBC_TAG(i) _MMIO(0x3300 + (i) * 4) /* 49 reisters */
-#define FBC_TAG_MASK REG_GENMASK(1, 0) /* 16 tags per register */
-#define FBC_TAG_MODIFIED REG_FIELD_PREP(FBC_TAG_MASK, 0)
-#define FBC_TAG_UNCOMPRESSED REG_FIELD_PREP(FBC_TAG_MASK, 1)
-#define FBC_TAG_UNCOMPRESSIBLE REG_FIELD_PREP(FBC_TAG_MASK, 2)
-#define FBC_TAG_COMPRESSED REG_FIELD_PREP(FBC_TAG_MASK, 3)
-
-#define FBC_LL_SIZE (1536)
-
-/* Framebuffer compression for GM45+ */
-#define DPFC_CB_BASE _MMIO(0x3200)
-#define ILK_DPFC_CB_BASE(fbc_id) _MMIO_PIPE((fbc_id), 0x43200, 0x43240)
-#define DPFC_CONTROL _MMIO(0x3208)
-#define ILK_DPFC_CONTROL(fbc_id) _MMIO_PIPE((fbc_id), 0x43208, 0x43248)
-#define DPFC_CTL_EN REG_BIT(31)
-#define DPFC_CTL_PLANE_MASK_G4X REG_BIT(30) /* g4x-snb */
-#define DPFC_CTL_PLANE_G4X(i9xx_plane) REG_FIELD_PREP(DPFC_CTL_PLANE_MASK_G4X, (i9xx_plane))
-#define DPFC_CTL_FENCE_EN_G4X REG_BIT(29) /* g4x-snb */
-#define DPFC_CTL_PLANE_MASK_IVB REG_GENMASK(30, 29) /* ivb only */
-#define DPFC_CTL_PLANE_IVB(i9xx_plane) REG_FIELD_PREP(DPFC_CTL_PLANE_MASK_IVB, (i9xx_plane))
-#define DPFC_CTL_FENCE_EN_IVB REG_BIT(28) /* ivb+ */
-#define DPFC_CTL_PERSISTENT_MODE REG_BIT(25) /* g4x-snb */
-#define DPFC_CTL_PLANE_BINDING_MASK REG_GENMASK(12, 11) /* lnl+ */
-#define DPFC_CTL_PLANE_BINDING(plane_id) REG_FIELD_PREP(DPFC_CTL_PLANE_BINDING_MASK, (plane_id))
-#define DPFC_CTL_FALSE_COLOR REG_BIT(10) /* ivb+ */
-#define DPFC_CTL_SR_EN REG_BIT(10) /* g4x only */
-#define DPFC_CTL_SR_EXIT_DIS REG_BIT(9) /* g4x only */
-#define DPFC_CTL_LIMIT_MASK REG_GENMASK(7, 6)
-#define DPFC_CTL_LIMIT_1X REG_FIELD_PREP(DPFC_CTL_LIMIT_MASK, 0)
-#define DPFC_CTL_LIMIT_2X REG_FIELD_PREP(DPFC_CTL_LIMIT_MASK, 1)
-#define DPFC_CTL_LIMIT_4X REG_FIELD_PREP(DPFC_CTL_LIMIT_MASK, 2)
-#define DPFC_CTL_FENCENO_MASK REG_GENMASK(3, 0)
-#define DPFC_CTL_FENCENO(fence) REG_FIELD_PREP(DPFC_CTL_FENCENO_MASK, (fence))
-#define DPFC_RECOMP_CTL _MMIO(0x320c)
-#define ILK_DPFC_RECOMP_CTL(fbc_id) _MMIO_PIPE((fbc_id), 0x4320c, 0x4324c)
-#define DPFC_RECOMP_STALL_EN REG_BIT(27)
-#define DPFC_RECOMP_STALL_WM_MASK REG_GENMASK(26, 16)
-#define DPFC_RECOMP_TIMER_COUNT_MASK REG_GENMASK(5, 0)
-#define DPFC_STATUS _MMIO(0x3210)
-#define ILK_DPFC_STATUS(fbc_id) _MMIO_PIPE((fbc_id), 0x43210, 0x43250)
-#define DPFC_INVAL_SEG_MASK REG_GENMASK(26, 16)
-#define DPFC_COMP_SEG_MASK REG_GENMASK(10, 0)
-#define DPFC_STATUS2 _MMIO(0x3214)
-#define ILK_DPFC_STATUS2(fbc_id) _MMIO_PIPE((fbc_id), 0x43214, 0x43254)
-#define DPFC_COMP_SEG_MASK_IVB REG_GENMASK(11, 0)
-#define DPFC_FENCE_YOFF _MMIO(0x3218)
-#define ILK_DPFC_FENCE_YOFF(fbc_id) _MMIO_PIPE((fbc_id), 0x43218, 0x43258)
-#define DPFC_CHICKEN _MMIO(0x3224)
-#define ILK_DPFC_CHICKEN(fbc_id) _MMIO_PIPE((fbc_id), 0x43224, 0x43264)
-#define DPFC_HT_MODIFY REG_BIT(31) /* pre-ivb */
-#define DPFC_NUKE_ON_ANY_MODIFICATION REG_BIT(23) /* bdw+ */
-#define DPFC_CHICKEN_COMP_DUMMY_PIXEL REG_BIT(14) /* glk+ */
-#define DPFC_CHICKEN_FORCE_SLB_INVALIDATION REG_BIT(13) /* icl+ */
-#define DPFC_DISABLE_DUMMY0 REG_BIT(8) /* ivb+ */
-
-#define GLK_FBC_STRIDE(fbc_id) _MMIO_PIPE((fbc_id), 0x43228, 0x43268)
-#define FBC_STRIDE_OVERRIDE REG_BIT(15)
-#define FBC_STRIDE_MASK REG_GENMASK(14, 0)
-#define FBC_STRIDE(x) REG_FIELD_PREP(FBC_STRIDE_MASK, (x))
-
-#define ILK_FBC_RT_BASE _MMIO(0x2128)
-#define ILK_FBC_RT_VALID REG_BIT(0)
-#define SNB_FBC_FRONT_BUFFER REG_BIT(1)
-
#define ILK_DISPLAY_CHICKEN1 _MMIO(0x42000)
#define ILK_FBCQ_DIS REG_BIT(22)
#define ILK_PABSTRETCH_DIS REG_BIT(21)
@@ -1104,30 +1001,10 @@
#define IVB_SPR_STRETCH_MAX_X2 REG_FIELD_PREP(IVB_SPR_STRETCH_MAX_MASK, 2)
#define IVB_SPR_STRETCH_MAX_X1 REG_FIELD_PREP(IVB_SPR_STRETCH_MAX_MASK, 3)
-
-/*
- * Framebuffer compression for Sandybridge
- *
- * The following two registers are of type GTTMMADR
- */
-#define SNB_DPFC_CTL_SA _MMIO(0x100100)
-#define SNB_DPFC_FENCE_EN REG_BIT(29)
-#define SNB_DPFC_FENCENO_MASK REG_GENMASK(4, 0)
-#define SNB_DPFC_FENCENO(fence) REG_FIELD_PREP(SNB_DPFC_FENCENO_MASK, (fence))
-#define SNB_DPFC_CPU_FENCE_OFFSET _MMIO(0x100104)
-
-/* Framebuffer compression for Ivybridge */
-#define IVB_FBC_RT_BASE _MMIO(0x7020)
-#define IVB_FBC_RT_BASE_UPPER _MMIO(0x7024)
-
#define IPS_CTL _MMIO(0x43408)
#define IPS_ENABLE REG_BIT(31)
#define IPS_FALSE_COLOR REG_BIT(4)
-#define MSG_FBC_REND_STATE(fbc_id) _MMIO_PIPE((fbc_id), 0x50380, 0x50384)
-#define FBC_REND_NUKE REG_BIT(2)
-#define FBC_REND_CACHE_CLEAN REG_BIT(1)
-
/*
* Clock control & power management
*/
diff --git a/drivers/gpu/drm/i915/intel_clock_gating.c b/drivers/gpu/drm/i915/intel_clock_gating.c
index 7e70ee4fbd84..1dc5281b2ade 100644
--- a/drivers/gpu/drm/i915/intel_clock_gating.c
+++ b/drivers/gpu/drm/i915/intel_clock_gating.c
@@ -28,6 +28,7 @@
#include "display/intel_de.h"
#include "display/intel_display.h"
#include "display/intel_display_trace.h"
+#include "display/intel_fbc_regs.h"
#include "display/skl_watermark.h"
#include "gt/intel_engine_regs.h"
diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
index d0f111ff0ada..0d3689203510 100644
--- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
+++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
@@ -11,6 +11,7 @@
#include "display/intel_dmc_regs.h"
#include "display/intel_dp_aux_regs.h"
#include "display/intel_dpio_phy.h"
+#include "display/intel_fbc_regs.h"
#include "display/intel_fdi_regs.h"
#include "display/intel_lvds_regs.h"
#include "display/intel_psr_regs.h"
--
2.39.2
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH v2 4/4] drm/i915/display: split out intel_sprite_regs.h from i915_reg.h
2024-04-26 10:51 [PATCH v2 0/4] drm/i915: i915_reg.h cleanups Jani Nikula
` (2 preceding siblings ...)
2024-04-26 10:51 ` [PATCH v2 3/4] drm/i915/display: split out intel_fbc_regs.h from i915_reg.h Jani Nikula
@ 2024-04-26 10:51 ` Jani Nikula
2024-04-26 11:31 ` ✗ Fi.CI.SPARSE: warning for drm/i915: i915_reg.h cleanups (rev2) Patchwork
` (2 subsequent siblings)
6 siblings, 0 replies; 10+ messages in thread
From: Jani Nikula @ 2024-04-26 10:51 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, ville.syrjala
Clean up i915_reg.h.
v2: Drop a redundant comment (Ville)
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/intel_sprite.c | 1 +
.../gpu/drm/i915/display/intel_sprite_regs.h | 348 ++++++++++++++++++
drivers/gpu/drm/i915/gvt/cmd_parser.c | 1 +
drivers/gpu/drm/i915/gvt/display.c | 1 +
drivers/gpu/drm/i915/gvt/fb_decoder.c | 5 +-
drivers/gpu/drm/i915/gvt/handlers.c | 1 +
drivers/gpu/drm/i915/i915_reg.h | 340 -----------------
drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 1 +
8 files changed, 357 insertions(+), 341 deletions(-)
create mode 100644 drivers/gpu/drm/i915/display/intel_sprite_regs.h
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
index d7b440c8caef..36a253a19c74 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -47,6 +47,7 @@
#include "intel_fb.h"
#include "intel_frontbuffer.h"
#include "intel_sprite.h"
+#include "intel_sprite_regs.h"
static char sprite_name(struct drm_i915_private *i915, enum pipe pipe, int sprite)
{
diff --git a/drivers/gpu/drm/i915/display/intel_sprite_regs.h b/drivers/gpu/drm/i915/display/intel_sprite_regs.h
new file mode 100644
index 000000000000..bb67705652b2
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_sprite_regs.h
@@ -0,0 +1,348 @@
+/* SPDX-License-Identifier: MIT */
+/* Copyright © 2024 Intel Corporation */
+
+#ifndef __INTEL_SPRITE_REGS__
+#define __INTEL_SPRITE_REGS__
+
+#include "intel_display_reg_defs.h"
+
+#define _DVSACNTR 0x72180
+#define DVS_ENABLE REG_BIT(31)
+#define DVS_PIPE_GAMMA_ENABLE REG_BIT(30)
+#define DVS_YUV_RANGE_CORRECTION_DISABLE REG_BIT(27)
+#define DVS_FORMAT_MASK REG_GENMASK(26, 25)
+#define DVS_FORMAT_YUV422 REG_FIELD_PREP(DVS_FORMAT_MASK, 0)
+#define DVS_FORMAT_RGBX101010 REG_FIELD_PREP(DVS_FORMAT_MASK, 1)
+#define DVS_FORMAT_RGBX888 REG_FIELD_PREP(DVS_FORMAT_MASK, 2)
+#define DVS_FORMAT_RGBX161616 REG_FIELD_PREP(DVS_FORMAT_MASK, 3)
+#define DVS_PIPE_CSC_ENABLE REG_BIT(24)
+#define DVS_SOURCE_KEY REG_BIT(22)
+#define DVS_RGB_ORDER_XBGR REG_BIT(20)
+#define DVS_YUV_FORMAT_BT709 REG_BIT(18)
+#define DVS_YUV_ORDER_MASK REG_GENMASK(17, 16)
+#define DVS_YUV_ORDER_YUYV REG_FIELD_PREP(DVS_YUV_ORDER_MASK, 0)
+#define DVS_YUV_ORDER_UYVY REG_FIELD_PREP(DVS_YUV_ORDER_MASK, 1)
+#define DVS_YUV_ORDER_YVYU REG_FIELD_PREP(DVS_YUV_ORDER_MASK, 2)
+#define DVS_YUV_ORDER_VYUY REG_FIELD_PREP(DVS_YUV_ORDER_MASK, 3)
+#define DVS_ROTATE_180 REG_BIT(15)
+#define DVS_TRICKLE_FEED_DISABLE REG_BIT(14)
+#define DVS_TILED REG_BIT(10)
+#define DVS_DEST_KEY REG_BIT(2)
+#define _DVSALINOFF 0x72184
+#define _DVSASTRIDE 0x72188
+#define _DVSAPOS 0x7218c
+#define DVS_POS_Y_MASK REG_GENMASK(31, 16)
+#define DVS_POS_Y(y) REG_FIELD_PREP(DVS_POS_Y_MASK, (y))
+#define DVS_POS_X_MASK REG_GENMASK(15, 0)
+#define DVS_POS_X(x) REG_FIELD_PREP(DVS_POS_X_MASK, (x))
+#define _DVSASIZE 0x72190
+#define DVS_HEIGHT_MASK REG_GENMASK(31, 16)
+#define DVS_HEIGHT(h) REG_FIELD_PREP(DVS_HEIGHT_MASK, (h))
+#define DVS_WIDTH_MASK REG_GENMASK(15, 0)
+#define DVS_WIDTH(w) REG_FIELD_PREP(DVS_WIDTH_MASK, (w))
+#define _DVSAKEYVAL 0x72194
+#define _DVSAKEYMSK 0x72198
+#define _DVSASURF 0x7219c
+#define DVS_ADDR_MASK REG_GENMASK(31, 12)
+#define _DVSAKEYMAXVAL 0x721a0
+#define _DVSATILEOFF 0x721a4
+#define DVS_OFFSET_Y_MASK REG_GENMASK(31, 16)
+#define DVS_OFFSET_Y(y) REG_FIELD_PREP(DVS_OFFSET_Y_MASK, (y))
+#define DVS_OFFSET_X_MASK REG_GENMASK(15, 0)
+#define DVS_OFFSET_X(x) REG_FIELD_PREP(DVS_OFFSET_X_MASK, (x))
+#define _DVSASURFLIVE 0x721ac
+#define _DVSAGAMC_G4X 0x721e0 /* g4x */
+#define _DVSASCALE 0x72204
+#define DVS_SCALE_ENABLE REG_BIT(31)
+#define DVS_FILTER_MASK REG_GENMASK(30, 29)
+#define DVS_FILTER_MEDIUM REG_FIELD_PREP(DVS_FILTER_MASK, 0)
+#define DVS_FILTER_ENHANCING REG_FIELD_PREP(DVS_FILTER_MASK, 1)
+#define DVS_FILTER_SOFTENING REG_FIELD_PREP(DVS_FILTER_MASK, 2)
+#define DVS_VERTICAL_OFFSET_HALF REG_BIT(28) /* must be enabled below */
+#define DVS_VERTICAL_OFFSET_ENABLE REG_BIT(27)
+#define DVS_SRC_WIDTH_MASK REG_GENMASK(26, 16)
+#define DVS_SRC_WIDTH(w) REG_FIELD_PREP(DVS_SRC_WIDTH_MASK, (w))
+#define DVS_SRC_HEIGHT_MASK REG_GENMASK(10, 0)
+#define DVS_SRC_HEIGHT(h) REG_FIELD_PREP(DVS_SRC_HEIGHT_MASK, (h))
+#define _DVSAGAMC_ILK 0x72300 /* ilk/snb */
+#define _DVSAGAMCMAX_ILK 0x72340 /* ilk/snb */
+
+#define _DVSBCNTR 0x73180
+#define _DVSBLINOFF 0x73184
+#define _DVSBSTRIDE 0x73188
+#define _DVSBPOS 0x7318c
+#define _DVSBSIZE 0x73190
+#define _DVSBKEYVAL 0x73194
+#define _DVSBKEYMSK 0x73198
+#define _DVSBSURF 0x7319c
+#define _DVSBKEYMAXVAL 0x731a0
+#define _DVSBTILEOFF 0x731a4
+#define _DVSBSURFLIVE 0x731ac
+#define _DVSBGAMC_G4X 0x731e0 /* g4x */
+#define _DVSBSCALE 0x73204
+#define _DVSBGAMC_ILK 0x73300 /* ilk/snb */
+#define _DVSBGAMCMAX_ILK 0x73340 /* ilk/snb */
+
+#define DVSCNTR(pipe) _MMIO_PIPE(pipe, _DVSACNTR, _DVSBCNTR)
+#define DVSLINOFF(pipe) _MMIO_PIPE(pipe, _DVSALINOFF, _DVSBLINOFF)
+#define DVSSTRIDE(pipe) _MMIO_PIPE(pipe, _DVSASTRIDE, _DVSBSTRIDE)
+#define DVSPOS(pipe) _MMIO_PIPE(pipe, _DVSAPOS, _DVSBPOS)
+#define DVSSURF(pipe) _MMIO_PIPE(pipe, _DVSASURF, _DVSBSURF)
+#define DVSKEYMAX(pipe) _MMIO_PIPE(pipe, _DVSAKEYMAXVAL, _DVSBKEYMAXVAL)
+#define DVSSIZE(pipe) _MMIO_PIPE(pipe, _DVSASIZE, _DVSBSIZE)
+#define DVSSCALE(pipe) _MMIO_PIPE(pipe, _DVSASCALE, _DVSBSCALE)
+#define DVSTILEOFF(pipe) _MMIO_PIPE(pipe, _DVSATILEOFF, _DVSBTILEOFF)
+#define DVSKEYVAL(pipe) _MMIO_PIPE(pipe, _DVSAKEYVAL, _DVSBKEYVAL)
+#define DVSKEYMSK(pipe) _MMIO_PIPE(pipe, _DVSAKEYMSK, _DVSBKEYMSK)
+#define DVSSURFLIVE(pipe) _MMIO_PIPE(pipe, _DVSASURFLIVE, _DVSBSURFLIVE)
+#define DVSGAMC_G4X(pipe, i) _MMIO(_PIPE(pipe, _DVSAGAMC_G4X, _DVSBGAMC_G4X) + (5 - (i)) * 4) /* 6 x u0.8 */
+#define DVSGAMC_ILK(pipe, i) _MMIO(_PIPE(pipe, _DVSAGAMC_ILK, _DVSBGAMC_ILK) + (i) * 4) /* 16 x u0.10 */
+#define DVSGAMCMAX_ILK(pipe, i) _MMIO(_PIPE(pipe, _DVSAGAMCMAX_ILK, _DVSBGAMCMAX_ILK) + (i) * 4) /* 3 x u1.10 */
+
+#define _SPRA_CTL 0x70280
+#define SPRITE_ENABLE REG_BIT(31)
+#define SPRITE_PIPE_GAMMA_ENABLE REG_BIT(30)
+#define SPRITE_YUV_RANGE_CORRECTION_DISABLE REG_BIT(28)
+#define SPRITE_FORMAT_MASK REG_GENMASK(27, 25)
+#define SPRITE_FORMAT_YUV422 REG_FIELD_PREP(SPRITE_FORMAT_MASK, 0)
+#define SPRITE_FORMAT_RGBX101010 REG_FIELD_PREP(SPRITE_FORMAT_MASK, 1)
+#define SPRITE_FORMAT_RGBX888 REG_FIELD_PREP(SPRITE_FORMAT_MASK, 2)
+#define SPRITE_FORMAT_RGBX161616 REG_FIELD_PREP(SPRITE_FORMAT_MASK, 3)
+#define SPRITE_FORMAT_YUV444 REG_FIELD_PREP(SPRITE_FORMAT_MASK, 4)
+#define SPRITE_FORMAT_XR_BGR101010 REG_FIELD_PREP(SPRITE_FORMAT_MASK, 5) /* Extended range */
+#define SPRITE_PIPE_CSC_ENABLE REG_BIT(24)
+#define SPRITE_SOURCE_KEY REG_BIT(22)
+#define SPRITE_RGB_ORDER_RGBX REG_BIT(20) /* only for 888 and 161616 */
+#define SPRITE_YUV_TO_RGB_CSC_DISABLE REG_BIT(19)
+#define SPRITE_YUV_TO_RGB_CSC_FORMAT_BT709 REG_BIT(18) /* 0 is BT601 */
+#define SPRITE_YUV_ORDER_MASK REG_GENMASK(17, 16)
+#define SPRITE_YUV_ORDER_YUYV REG_FIELD_PREP(SPRITE_YUV_ORDER_MASK, 0)
+#define SPRITE_YUV_ORDER_UYVY REG_FIELD_PREP(SPRITE_YUV_ORDER_MASK, 1)
+#define SPRITE_YUV_ORDER_YVYU REG_FIELD_PREP(SPRITE_YUV_ORDER_MASK, 2)
+#define SPRITE_YUV_ORDER_VYUY REG_FIELD_PREP(SPRITE_YUV_ORDER_MASK, 3)
+#define SPRITE_ROTATE_180 REG_BIT(15)
+#define SPRITE_TRICKLE_FEED_DISABLE REG_BIT(14)
+#define SPRITE_PLANE_GAMMA_DISABLE REG_BIT(13)
+#define SPRITE_TILED REG_BIT(10)
+#define SPRITE_DEST_KEY REG_BIT(2)
+#define _SPRA_LINOFF 0x70284
+#define _SPRA_STRIDE 0x70288
+#define _SPRA_POS 0x7028c
+#define SPRITE_POS_Y_MASK REG_GENMASK(31, 16)
+#define SPRITE_POS_Y(y) REG_FIELD_PREP(SPRITE_POS_Y_MASK, (y))
+#define SPRITE_POS_X_MASK REG_GENMASK(15, 0)
+#define SPRITE_POS_X(x) REG_FIELD_PREP(SPRITE_POS_X_MASK, (x))
+#define _SPRA_SIZE 0x70290
+#define SPRITE_HEIGHT_MASK REG_GENMASK(31, 16)
+#define SPRITE_HEIGHT(h) REG_FIELD_PREP(SPRITE_HEIGHT_MASK, (h))
+#define SPRITE_WIDTH_MASK REG_GENMASK(15, 0)
+#define SPRITE_WIDTH(w) REG_FIELD_PREP(SPRITE_WIDTH_MASK, (w))
+#define _SPRA_KEYVAL 0x70294
+#define _SPRA_KEYMSK 0x70298
+#define _SPRA_SURF 0x7029c
+#define SPRITE_ADDR_MASK REG_GENMASK(31, 12)
+#define _SPRA_KEYMAX 0x702a0
+#define _SPRA_TILEOFF 0x702a4
+#define SPRITE_OFFSET_Y_MASK REG_GENMASK(31, 16)
+#define SPRITE_OFFSET_Y(y) REG_FIELD_PREP(SPRITE_OFFSET_Y_MASK, (y))
+#define SPRITE_OFFSET_X_MASK REG_GENMASK(15, 0)
+#define SPRITE_OFFSET_X(x) REG_FIELD_PREP(SPRITE_OFFSET_X_MASK, (x))
+#define _SPRA_OFFSET 0x702a4
+#define _SPRA_SURFLIVE 0x702ac
+#define _SPRA_SCALE 0x70304
+#define SPRITE_SCALE_ENABLE REG_BIT(31)
+#define SPRITE_FILTER_MASK REG_GENMASK(30, 29)
+#define SPRITE_FILTER_MEDIUM REG_FIELD_PREP(SPRITE_FILTER_MASK, 0)
+#define SPRITE_FILTER_ENHANCING REG_FIELD_PREP(SPRITE_FILTER_MASK, 1)
+#define SPRITE_FILTER_SOFTENING REG_FIELD_PREP(SPRITE_FILTER_MASK, 2)
+#define SPRITE_VERTICAL_OFFSET_HALF REG_BIT(28) /* must be enabled below */
+#define SPRITE_VERTICAL_OFFSET_ENABLE REG_BIT(27)
+#define SPRITE_SRC_WIDTH_MASK REG_GENMASK(26, 16)
+#define SPRITE_SRC_WIDTH(w) REG_FIELD_PREP(SPRITE_SRC_WIDTH_MASK, (w))
+#define SPRITE_SRC_HEIGHT_MASK REG_GENMASK(10, 0)
+#define SPRITE_SRC_HEIGHT(h) REG_FIELD_PREP(SPRITE_SRC_HEIGHT_MASK, (h))
+#define _SPRA_GAMC 0x70400
+#define _SPRA_GAMC16 0x70440
+#define _SPRA_GAMC17 0x7044c
+
+#define _SPRB_CTL 0x71280
+#define _SPRB_LINOFF 0x71284
+#define _SPRB_STRIDE 0x71288
+#define _SPRB_POS 0x7128c
+#define _SPRB_SIZE 0x71290
+#define _SPRB_KEYVAL 0x71294
+#define _SPRB_KEYMSK 0x71298
+#define _SPRB_SURF 0x7129c
+#define _SPRB_KEYMAX 0x712a0
+#define _SPRB_TILEOFF 0x712a4
+#define _SPRB_OFFSET 0x712a4
+#define _SPRB_SURFLIVE 0x712ac
+#define _SPRB_SCALE 0x71304
+#define _SPRB_GAMC 0x71400
+#define _SPRB_GAMC16 0x71440
+#define _SPRB_GAMC17 0x7144c
+
+#define SPRCTL(pipe) _MMIO_PIPE(pipe, _SPRA_CTL, _SPRB_CTL)
+#define SPRLINOFF(pipe) _MMIO_PIPE(pipe, _SPRA_LINOFF, _SPRB_LINOFF)
+#define SPRSTRIDE(pipe) _MMIO_PIPE(pipe, _SPRA_STRIDE, _SPRB_STRIDE)
+#define SPRPOS(pipe) _MMIO_PIPE(pipe, _SPRA_POS, _SPRB_POS)
+#define SPRSIZE(pipe) _MMIO_PIPE(pipe, _SPRA_SIZE, _SPRB_SIZE)
+#define SPRKEYVAL(pipe) _MMIO_PIPE(pipe, _SPRA_KEYVAL, _SPRB_KEYVAL)
+#define SPRKEYMSK(pipe) _MMIO_PIPE(pipe, _SPRA_KEYMSK, _SPRB_KEYMSK)
+#define SPRSURF(pipe) _MMIO_PIPE(pipe, _SPRA_SURF, _SPRB_SURF)
+#define SPRKEYMAX(pipe) _MMIO_PIPE(pipe, _SPRA_KEYMAX, _SPRB_KEYMAX)
+#define SPRTILEOFF(pipe) _MMIO_PIPE(pipe, _SPRA_TILEOFF, _SPRB_TILEOFF)
+#define SPROFFSET(pipe) _MMIO_PIPE(pipe, _SPRA_OFFSET, _SPRB_OFFSET)
+#define SPRSCALE(pipe) _MMIO_PIPE(pipe, _SPRA_SCALE, _SPRB_SCALE)
+#define SPRGAMC(pipe, i) _MMIO(_PIPE(pipe, _SPRA_GAMC, _SPRB_GAMC) + (i) * 4) /* 16 x u0.10 */
+#define SPRGAMC16(pipe, i) _MMIO(_PIPE(pipe, _SPRA_GAMC16, _SPRB_GAMC16) + (i) * 4) /* 3 x u1.10 */
+#define SPRGAMC17(pipe, i) _MMIO(_PIPE(pipe, _SPRA_GAMC17, _SPRB_GAMC17) + (i) * 4) /* 3 x u2.10 */
+#define SPRSURFLIVE(pipe) _MMIO_PIPE(pipe, _SPRA_SURFLIVE, _SPRB_SURFLIVE)
+
+#define _SPACNTR (VLV_DISPLAY_BASE + 0x72180)
+#define SP_ENABLE REG_BIT(31)
+#define SP_PIPE_GAMMA_ENABLE REG_BIT(30)
+#define SP_FORMAT_MASK REG_GENMASK(29, 26)
+#define SP_FORMAT_YUV422 REG_FIELD_PREP(SP_FORMAT_MASK, 0)
+#define SP_FORMAT_8BPP REG_FIELD_PREP(SP_FORMAT_MASK, 2)
+#define SP_FORMAT_BGR565 REG_FIELD_PREP(SP_FORMAT_MASK, 5)
+#define SP_FORMAT_BGRX8888 REG_FIELD_PREP(SP_FORMAT_MASK, 6)
+#define SP_FORMAT_BGRA8888 REG_FIELD_PREP(SP_FORMAT_MASK, 7)
+#define SP_FORMAT_RGBX1010102 REG_FIELD_PREP(SP_FORMAT_MASK, 8)
+#define SP_FORMAT_RGBA1010102 REG_FIELD_PREP(SP_FORMAT_MASK, 9)
+#define SP_FORMAT_BGRX1010102 REG_FIELD_PREP(SP_FORMAT_MASK, 10) /* CHV pipe B */
+#define SP_FORMAT_BGRA1010102 REG_FIELD_PREP(SP_FORMAT_MASK, 11) /* CHV pipe B */
+#define SP_FORMAT_RGBX8888 REG_FIELD_PREP(SP_FORMAT_MASK, 14)
+#define SP_FORMAT_RGBA8888 REG_FIELD_PREP(SP_FORMAT_MASK, 15)
+#define SP_ALPHA_PREMULTIPLY REG_BIT(23) /* CHV pipe B */
+#define SP_SOURCE_KEY REG_BIT(22)
+#define SP_YUV_FORMAT_BT709 REG_BIT(18)
+#define SP_YUV_ORDER_MASK REG_GENMASK(17, 16)
+#define SP_YUV_ORDER_YUYV REG_FIELD_PREP(SP_YUV_ORDER_MASK, 0)
+#define SP_YUV_ORDER_UYVY REG_FIELD_PREP(SP_YUV_ORDER_MASK, 1)
+#define SP_YUV_ORDER_YVYU REG_FIELD_PREP(SP_YUV_ORDER_MASK, 2)
+#define SP_YUV_ORDER_VYUY REG_FIELD_PREP(SP_YUV_ORDER_MASK, 3)
+#define SP_ROTATE_180 REG_BIT(15)
+#define SP_TILED REG_BIT(10)
+#define SP_MIRROR REG_BIT(8) /* CHV pipe B */
+#define _SPALINOFF (VLV_DISPLAY_BASE + 0x72184)
+#define _SPASTRIDE (VLV_DISPLAY_BASE + 0x72188)
+#define _SPAPOS (VLV_DISPLAY_BASE + 0x7218c)
+#define SP_POS_Y_MASK REG_GENMASK(31, 16)
+#define SP_POS_Y(y) REG_FIELD_PREP(SP_POS_Y_MASK, (y))
+#define SP_POS_X_MASK REG_GENMASK(15, 0)
+#define SP_POS_X(x) REG_FIELD_PREP(SP_POS_X_MASK, (x))
+#define _SPASIZE (VLV_DISPLAY_BASE + 0x72190)
+#define SP_HEIGHT_MASK REG_GENMASK(31, 16)
+#define SP_HEIGHT(h) REG_FIELD_PREP(SP_HEIGHT_MASK, (h))
+#define SP_WIDTH_MASK REG_GENMASK(15, 0)
+#define SP_WIDTH(w) REG_FIELD_PREP(SP_WIDTH_MASK, (w))
+#define _SPAKEYMINVAL (VLV_DISPLAY_BASE + 0x72194)
+#define _SPAKEYMSK (VLV_DISPLAY_BASE + 0x72198)
+#define _SPASURF (VLV_DISPLAY_BASE + 0x7219c)
+#define SP_ADDR_MASK REG_GENMASK(31, 12)
+#define _SPAKEYMAXVAL (VLV_DISPLAY_BASE + 0x721a0)
+#define _SPATILEOFF (VLV_DISPLAY_BASE + 0x721a4)
+#define SP_OFFSET_Y_MASK REG_GENMASK(31, 16)
+#define SP_OFFSET_Y(y) REG_FIELD_PREP(SP_OFFSET_Y_MASK, (y))
+#define SP_OFFSET_X_MASK REG_GENMASK(15, 0)
+#define SP_OFFSET_X(x) REG_FIELD_PREP(SP_OFFSET_X_MASK, (x))
+#define _SPACONSTALPHA (VLV_DISPLAY_BASE + 0x721a8)
+#define SP_CONST_ALPHA_ENABLE REG_BIT(31)
+#define SP_CONST_ALPHA_MASK REG_GENMASK(7, 0)
+#define SP_CONST_ALPHA(alpha) REG_FIELD_PREP(SP_CONST_ALPHA_MASK, (alpha))
+#define _SPASURFLIVE (VLV_DISPLAY_BASE + 0x721ac)
+#define _SPACLRC0 (VLV_DISPLAY_BASE + 0x721d0)
+#define SP_CONTRAST_MASK REG_GENMASK(26, 18)
+#define SP_CONTRAST(x) REG_FIELD_PREP(SP_CONTRAST_MASK, (x)) /* u3.6 */
+#define SP_BRIGHTNESS_MASK REG_GENMASK(7, 0)
+#define SP_BRIGHTNESS(x) REG_FIELD_PREP(SP_BRIGHTNESS_MASK, (x)) /* s8 */
+#define _SPACLRC1 (VLV_DISPLAY_BASE + 0x721d4)
+#define SP_SH_SIN_MASK REG_GENMASK(26, 16)
+#define SP_SH_SIN(x) REG_FIELD_PREP(SP_SH_SIN_MASK, (x)) /* s4.7 */
+#define SP_SH_COS_MASK REG_GENMASK(9, 0)
+#define SP_SH_COS(x) REG_FIELD_PREP(SP_SH_COS_MASK, (x)) /* u3.7 */
+#define _SPAGAMC (VLV_DISPLAY_BASE + 0x721e0)
+
+#define _SPBCNTR (VLV_DISPLAY_BASE + 0x72280)
+#define _SPBLINOFF (VLV_DISPLAY_BASE + 0x72284)
+#define _SPBSTRIDE (VLV_DISPLAY_BASE + 0x72288)
+#define _SPBPOS (VLV_DISPLAY_BASE + 0x7228c)
+#define _SPBSIZE (VLV_DISPLAY_BASE + 0x72290)
+#define _SPBKEYMINVAL (VLV_DISPLAY_BASE + 0x72294)
+#define _SPBKEYMSK (VLV_DISPLAY_BASE + 0x72298)
+#define _SPBSURF (VLV_DISPLAY_BASE + 0x7229c)
+#define _SPBKEYMAXVAL (VLV_DISPLAY_BASE + 0x722a0)
+#define _SPBTILEOFF (VLV_DISPLAY_BASE + 0x722a4)
+#define _SPBCONSTALPHA (VLV_DISPLAY_BASE + 0x722a8)
+#define _SPBSURFLIVE (VLV_DISPLAY_BASE + 0x722ac)
+#define _SPBCLRC0 (VLV_DISPLAY_BASE + 0x722d0)
+#define _SPBCLRC1 (VLV_DISPLAY_BASE + 0x722d4)
+#define _SPBGAMC (VLV_DISPLAY_BASE + 0x722e0)
+
+#define _VLV_SPR(pipe, plane_id, reg_a, reg_b) \
+ _PIPE((pipe) * 2 + (plane_id) - PLANE_SPRITE0, (reg_a), (reg_b))
+#define _MMIO_VLV_SPR(pipe, plane_id, reg_a, reg_b) \
+ _MMIO(_VLV_SPR((pipe), (plane_id), (reg_a), (reg_b)))
+
+#define SPCNTR(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACNTR, _SPBCNTR)
+#define SPLINOFF(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPALINOFF, _SPBLINOFF)
+#define SPSTRIDE(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASTRIDE, _SPBSTRIDE)
+#define SPPOS(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAPOS, _SPBPOS)
+#define SPSIZE(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASIZE, _SPBSIZE)
+#define SPKEYMINVAL(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMINVAL, _SPBKEYMINVAL)
+#define SPKEYMSK(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMSK, _SPBKEYMSK)
+#define SPSURF(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASURF, _SPBSURF)
+#define SPKEYMAXVAL(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMAXVAL, _SPBKEYMAXVAL)
+#define SPTILEOFF(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPATILEOFF, _SPBTILEOFF)
+#define SPCONSTALPHA(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACONSTALPHA, _SPBCONSTALPHA)
+#define SPSURFLIVE(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASURFLIVE, _SPBSURFLIVE)
+#define SPCLRC0(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACLRC0, _SPBCLRC0)
+#define SPCLRC1(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACLRC1, _SPBCLRC1)
+#define SPGAMC(pipe, plane_id, i) _MMIO(_VLV_SPR((pipe), (plane_id), _SPAGAMC, _SPBGAMC) + (5 - (i)) * 4) /* 6 x u0.10 */
+
+/*
+ * CHV pipe B sprite CSC
+ *
+ * |cr| |c0 c1 c2| |cr + cr_ioff| |cr_ooff|
+ * |yg| = |c3 c4 c5| x |yg + yg_ioff| + |yg_ooff|
+ * |cb| |c6 c7 c8| |cb + cr_ioff| |cb_ooff|
+ */
+#define _MMIO_CHV_SPCSC(plane_id, reg) \
+ _MMIO(VLV_DISPLAY_BASE + ((plane_id) - PLANE_SPRITE0) * 0x1000 + (reg))
+
+#define SPCSCYGOFF(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d900)
+#define SPCSCCBOFF(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d904)
+#define SPCSCCROFF(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d908)
+#define SPCSC_OOFF_MASK REG_GENMASK(26, 16)
+#define SPCSC_OOFF(x) REG_FIELD_PREP(SPCSC_OOFF_MASK, (x) & 0x7ff) /* s11 */
+#define SPCSC_IOFF_MASK REG_GENMASK(10, 0)
+#define SPCSC_IOFF(x) REG_FIELD_PREP(SPCSC_IOFF_MASK, (x) & 0x7ff) /* s11 */
+
+#define SPCSCC01(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d90c)
+#define SPCSCC23(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d910)
+#define SPCSCC45(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d914)
+#define SPCSCC67(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d918)
+#define SPCSCC8(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d91c)
+#define SPCSC_C1_MASK REG_GENMASK(30, 16)
+#define SPCSC_C1(x) REG_FIELD_PREP(SPCSC_C1_MASK, (x) & 0x7fff) /* s3.12 */
+#define SPCSC_C0_MASK REG_GENMASK(14, 0)
+#define SPCSC_C0(x) REG_FIELD_PREP(SPCSC_C0_MASK, (x) & 0x7fff) /* s3.12 */
+
+#define SPCSCYGICLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d920)
+#define SPCSCCBICLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d924)
+#define SPCSCCRICLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d928)
+#define SPCSC_IMAX_MASK REG_GENMASK(26, 16)
+#define SPCSC_IMAX(x) REG_FIELD_PREP(SPCSC_IMAX_MASK, (x) & 0x7ff) /* s11 */
+#define SPCSC_IMIN_MASK REG_GENMASK(10, 0)
+#define SPCSC_IMIN(x) REG_FIELD_PREP(SPCSC_IMIN_MASK, (x) & 0x7ff) /* s11 */
+
+#define SPCSCYGOCLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d92c)
+#define SPCSCCBOCLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d930)
+#define SPCSCCROCLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d934)
+#define SPCSC_OMAX_MASK REG_GENMASK(25, 16)
+#define SPCSC_OMAX(x) REG_FIELD_PREP(SPCSC_OMAX_MASK, (x)) /* u10 */
+#define SPCSC_OMIN_MASK REG_GENMASK(9, 0)
+#define SPCSC_OMIN(x) REG_FIELD_PREP(SPCSC_OMIN_MASK, (x)) /* u10 */
+
+#endif /* __INTEL_SPRITE_REGS__ */
diff --git a/drivers/gpu/drm/i915/gvt/cmd_parser.c b/drivers/gpu/drm/i915/gvt/cmd_parser.c
index d4a3f3e093b0..4be8cb65fb7e 100644
--- a/drivers/gpu/drm/i915/gvt/cmd_parser.c
+++ b/drivers/gpu/drm/i915/gvt/cmd_parser.c
@@ -50,6 +50,7 @@
#include "trace.h"
#include "display/intel_display.h"
+#include "display/intel_sprite_regs.h"
#include "gem/i915_gem_context.h"
#include "gem/i915_gem_pm.h"
#include "gt/intel_context.h"
diff --git a/drivers/gpu/drm/i915/gvt/display.c b/drivers/gpu/drm/i915/gvt/display.c
index a0381fd230c0..2b7df7fcf369 100644
--- a/drivers/gpu/drm/i915/gvt/display.c
+++ b/drivers/gpu/drm/i915/gvt/display.c
@@ -39,6 +39,7 @@
#include "display/bxt_dpio_phy_regs.h"
#include "display/intel_display.h"
#include "display/intel_dpio_phy.h"
+#include "display/intel_sprite_regs.h"
static int get_edp_pipe(struct intel_vgpu *vgpu)
{
diff --git a/drivers/gpu/drm/i915/gvt/fb_decoder.c b/drivers/gpu/drm/i915/gvt/fb_decoder.c
index 313efdabee57..4140da68aabb 100644
--- a/drivers/gpu/drm/i915/gvt/fb_decoder.c
+++ b/drivers/gpu/drm/i915/gvt/fb_decoder.c
@@ -34,11 +34,14 @@
*/
#include <uapi/drm/drm_fourcc.h>
-#include "i915_drv.h"
+
#include "gvt.h"
+#include "i915_drv.h"
#include "i915_pvinfo.h"
#include "i915_reg.h"
+#include "display/intel_sprite_regs.h"
+
#define PRIMARY_FORMAT_NUM 16
struct pixel_format {
int drm_format; /* Pixel format in DRM definition */
diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
index f85bf59cdeaf..102eb354fed6 100644
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -50,6 +50,7 @@
#include "display/intel_fdi_regs.h"
#include "display/intel_pps_regs.h"
#include "display/intel_psr_regs.h"
+#include "display/intel_sprite_regs.h"
#include "display/skl_watermark_regs.h"
#include "display/vlv_dsi_pll_regs.h"
#include "gt/intel_gt_regs.h"
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 5cdf3b17e7d4..beed2b97d4b2 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2824,346 +2824,6 @@
#define _PIPEDSI0CONF 0x7b008
#define _PIPEDSI1CONF 0x7b808
-/* Sprite A control */
-#define _DVSACNTR 0x72180
-#define DVS_ENABLE REG_BIT(31)
-#define DVS_PIPE_GAMMA_ENABLE REG_BIT(30)
-#define DVS_YUV_RANGE_CORRECTION_DISABLE REG_BIT(27)
-#define DVS_FORMAT_MASK REG_GENMASK(26, 25)
-#define DVS_FORMAT_YUV422 REG_FIELD_PREP(DVS_FORMAT_MASK, 0)
-#define DVS_FORMAT_RGBX101010 REG_FIELD_PREP(DVS_FORMAT_MASK, 1)
-#define DVS_FORMAT_RGBX888 REG_FIELD_PREP(DVS_FORMAT_MASK, 2)
-#define DVS_FORMAT_RGBX161616 REG_FIELD_PREP(DVS_FORMAT_MASK, 3)
-#define DVS_PIPE_CSC_ENABLE REG_BIT(24)
-#define DVS_SOURCE_KEY REG_BIT(22)
-#define DVS_RGB_ORDER_XBGR REG_BIT(20)
-#define DVS_YUV_FORMAT_BT709 REG_BIT(18)
-#define DVS_YUV_ORDER_MASK REG_GENMASK(17, 16)
-#define DVS_YUV_ORDER_YUYV REG_FIELD_PREP(DVS_YUV_ORDER_MASK, 0)
-#define DVS_YUV_ORDER_UYVY REG_FIELD_PREP(DVS_YUV_ORDER_MASK, 1)
-#define DVS_YUV_ORDER_YVYU REG_FIELD_PREP(DVS_YUV_ORDER_MASK, 2)
-#define DVS_YUV_ORDER_VYUY REG_FIELD_PREP(DVS_YUV_ORDER_MASK, 3)
-#define DVS_ROTATE_180 REG_BIT(15)
-#define DVS_TRICKLE_FEED_DISABLE REG_BIT(14)
-#define DVS_TILED REG_BIT(10)
-#define DVS_DEST_KEY REG_BIT(2)
-#define _DVSALINOFF 0x72184
-#define _DVSASTRIDE 0x72188
-#define _DVSAPOS 0x7218c
-#define DVS_POS_Y_MASK REG_GENMASK(31, 16)
-#define DVS_POS_Y(y) REG_FIELD_PREP(DVS_POS_Y_MASK, (y))
-#define DVS_POS_X_MASK REG_GENMASK(15, 0)
-#define DVS_POS_X(x) REG_FIELD_PREP(DVS_POS_X_MASK, (x))
-#define _DVSASIZE 0x72190
-#define DVS_HEIGHT_MASK REG_GENMASK(31, 16)
-#define DVS_HEIGHT(h) REG_FIELD_PREP(DVS_HEIGHT_MASK, (h))
-#define DVS_WIDTH_MASK REG_GENMASK(15, 0)
-#define DVS_WIDTH(w) REG_FIELD_PREP(DVS_WIDTH_MASK, (w))
-#define _DVSAKEYVAL 0x72194
-#define _DVSAKEYMSK 0x72198
-#define _DVSASURF 0x7219c
-#define DVS_ADDR_MASK REG_GENMASK(31, 12)
-#define _DVSAKEYMAXVAL 0x721a0
-#define _DVSATILEOFF 0x721a4
-#define DVS_OFFSET_Y_MASK REG_GENMASK(31, 16)
-#define DVS_OFFSET_Y(y) REG_FIELD_PREP(DVS_OFFSET_Y_MASK, (y))
-#define DVS_OFFSET_X_MASK REG_GENMASK(15, 0)
-#define DVS_OFFSET_X(x) REG_FIELD_PREP(DVS_OFFSET_X_MASK, (x))
-#define _DVSASURFLIVE 0x721ac
-#define _DVSAGAMC_G4X 0x721e0 /* g4x */
-#define _DVSASCALE 0x72204
-#define DVS_SCALE_ENABLE REG_BIT(31)
-#define DVS_FILTER_MASK REG_GENMASK(30, 29)
-#define DVS_FILTER_MEDIUM REG_FIELD_PREP(DVS_FILTER_MASK, 0)
-#define DVS_FILTER_ENHANCING REG_FIELD_PREP(DVS_FILTER_MASK, 1)
-#define DVS_FILTER_SOFTENING REG_FIELD_PREP(DVS_FILTER_MASK, 2)
-#define DVS_VERTICAL_OFFSET_HALF REG_BIT(28) /* must be enabled below */
-#define DVS_VERTICAL_OFFSET_ENABLE REG_BIT(27)
-#define DVS_SRC_WIDTH_MASK REG_GENMASK(26, 16)
-#define DVS_SRC_WIDTH(w) REG_FIELD_PREP(DVS_SRC_WIDTH_MASK, (w))
-#define DVS_SRC_HEIGHT_MASK REG_GENMASK(10, 0)
-#define DVS_SRC_HEIGHT(h) REG_FIELD_PREP(DVS_SRC_HEIGHT_MASK, (h))
-#define _DVSAGAMC_ILK 0x72300 /* ilk/snb */
-#define _DVSAGAMCMAX_ILK 0x72340 /* ilk/snb */
-
-#define _DVSBCNTR 0x73180
-#define _DVSBLINOFF 0x73184
-#define _DVSBSTRIDE 0x73188
-#define _DVSBPOS 0x7318c
-#define _DVSBSIZE 0x73190
-#define _DVSBKEYVAL 0x73194
-#define _DVSBKEYMSK 0x73198
-#define _DVSBSURF 0x7319c
-#define _DVSBKEYMAXVAL 0x731a0
-#define _DVSBTILEOFF 0x731a4
-#define _DVSBSURFLIVE 0x731ac
-#define _DVSBGAMC_G4X 0x731e0 /* g4x */
-#define _DVSBSCALE 0x73204
-#define _DVSBGAMC_ILK 0x73300 /* ilk/snb */
-#define _DVSBGAMCMAX_ILK 0x73340 /* ilk/snb */
-
-#define DVSCNTR(pipe) _MMIO_PIPE(pipe, _DVSACNTR, _DVSBCNTR)
-#define DVSLINOFF(pipe) _MMIO_PIPE(pipe, _DVSALINOFF, _DVSBLINOFF)
-#define DVSSTRIDE(pipe) _MMIO_PIPE(pipe, _DVSASTRIDE, _DVSBSTRIDE)
-#define DVSPOS(pipe) _MMIO_PIPE(pipe, _DVSAPOS, _DVSBPOS)
-#define DVSSURF(pipe) _MMIO_PIPE(pipe, _DVSASURF, _DVSBSURF)
-#define DVSKEYMAX(pipe) _MMIO_PIPE(pipe, _DVSAKEYMAXVAL, _DVSBKEYMAXVAL)
-#define DVSSIZE(pipe) _MMIO_PIPE(pipe, _DVSASIZE, _DVSBSIZE)
-#define DVSSCALE(pipe) _MMIO_PIPE(pipe, _DVSASCALE, _DVSBSCALE)
-#define DVSTILEOFF(pipe) _MMIO_PIPE(pipe, _DVSATILEOFF, _DVSBTILEOFF)
-#define DVSKEYVAL(pipe) _MMIO_PIPE(pipe, _DVSAKEYVAL, _DVSBKEYVAL)
-#define DVSKEYMSK(pipe) _MMIO_PIPE(pipe, _DVSAKEYMSK, _DVSBKEYMSK)
-#define DVSSURFLIVE(pipe) _MMIO_PIPE(pipe, _DVSASURFLIVE, _DVSBSURFLIVE)
-#define DVSGAMC_G4X(pipe, i) _MMIO(_PIPE(pipe, _DVSAGAMC_G4X, _DVSBGAMC_G4X) + (5 - (i)) * 4) /* 6 x u0.8 */
-#define DVSGAMC_ILK(pipe, i) _MMIO(_PIPE(pipe, _DVSAGAMC_ILK, _DVSBGAMC_ILK) + (i) * 4) /* 16 x u0.10 */
-#define DVSGAMCMAX_ILK(pipe, i) _MMIO(_PIPE(pipe, _DVSAGAMCMAX_ILK, _DVSBGAMCMAX_ILK) + (i) * 4) /* 3 x u1.10 */
-
-#define _SPRA_CTL 0x70280
-#define SPRITE_ENABLE REG_BIT(31)
-#define SPRITE_PIPE_GAMMA_ENABLE REG_BIT(30)
-#define SPRITE_YUV_RANGE_CORRECTION_DISABLE REG_BIT(28)
-#define SPRITE_FORMAT_MASK REG_GENMASK(27, 25)
-#define SPRITE_FORMAT_YUV422 REG_FIELD_PREP(SPRITE_FORMAT_MASK, 0)
-#define SPRITE_FORMAT_RGBX101010 REG_FIELD_PREP(SPRITE_FORMAT_MASK, 1)
-#define SPRITE_FORMAT_RGBX888 REG_FIELD_PREP(SPRITE_FORMAT_MASK, 2)
-#define SPRITE_FORMAT_RGBX161616 REG_FIELD_PREP(SPRITE_FORMAT_MASK, 3)
-#define SPRITE_FORMAT_YUV444 REG_FIELD_PREP(SPRITE_FORMAT_MASK, 4)
-#define SPRITE_FORMAT_XR_BGR101010 REG_FIELD_PREP(SPRITE_FORMAT_MASK, 5) /* Extended range */
-#define SPRITE_PIPE_CSC_ENABLE REG_BIT(24)
-#define SPRITE_SOURCE_KEY REG_BIT(22)
-#define SPRITE_RGB_ORDER_RGBX REG_BIT(20) /* only for 888 and 161616 */
-#define SPRITE_YUV_TO_RGB_CSC_DISABLE REG_BIT(19)
-#define SPRITE_YUV_TO_RGB_CSC_FORMAT_BT709 REG_BIT(18) /* 0 is BT601 */
-#define SPRITE_YUV_ORDER_MASK REG_GENMASK(17, 16)
-#define SPRITE_YUV_ORDER_YUYV REG_FIELD_PREP(SPRITE_YUV_ORDER_MASK, 0)
-#define SPRITE_YUV_ORDER_UYVY REG_FIELD_PREP(SPRITE_YUV_ORDER_MASK, 1)
-#define SPRITE_YUV_ORDER_YVYU REG_FIELD_PREP(SPRITE_YUV_ORDER_MASK, 2)
-#define SPRITE_YUV_ORDER_VYUY REG_FIELD_PREP(SPRITE_YUV_ORDER_MASK, 3)
-#define SPRITE_ROTATE_180 REG_BIT(15)
-#define SPRITE_TRICKLE_FEED_DISABLE REG_BIT(14)
-#define SPRITE_PLANE_GAMMA_DISABLE REG_BIT(13)
-#define SPRITE_TILED REG_BIT(10)
-#define SPRITE_DEST_KEY REG_BIT(2)
-#define _SPRA_LINOFF 0x70284
-#define _SPRA_STRIDE 0x70288
-#define _SPRA_POS 0x7028c
-#define SPRITE_POS_Y_MASK REG_GENMASK(31, 16)
-#define SPRITE_POS_Y(y) REG_FIELD_PREP(SPRITE_POS_Y_MASK, (y))
-#define SPRITE_POS_X_MASK REG_GENMASK(15, 0)
-#define SPRITE_POS_X(x) REG_FIELD_PREP(SPRITE_POS_X_MASK, (x))
-#define _SPRA_SIZE 0x70290
-#define SPRITE_HEIGHT_MASK REG_GENMASK(31, 16)
-#define SPRITE_HEIGHT(h) REG_FIELD_PREP(SPRITE_HEIGHT_MASK, (h))
-#define SPRITE_WIDTH_MASK REG_GENMASK(15, 0)
-#define SPRITE_WIDTH(w) REG_FIELD_PREP(SPRITE_WIDTH_MASK, (w))
-#define _SPRA_KEYVAL 0x70294
-#define _SPRA_KEYMSK 0x70298
-#define _SPRA_SURF 0x7029c
-#define SPRITE_ADDR_MASK REG_GENMASK(31, 12)
-#define _SPRA_KEYMAX 0x702a0
-#define _SPRA_TILEOFF 0x702a4
-#define SPRITE_OFFSET_Y_MASK REG_GENMASK(31, 16)
-#define SPRITE_OFFSET_Y(y) REG_FIELD_PREP(SPRITE_OFFSET_Y_MASK, (y))
-#define SPRITE_OFFSET_X_MASK REG_GENMASK(15, 0)
-#define SPRITE_OFFSET_X(x) REG_FIELD_PREP(SPRITE_OFFSET_X_MASK, (x))
-#define _SPRA_OFFSET 0x702a4
-#define _SPRA_SURFLIVE 0x702ac
-#define _SPRA_SCALE 0x70304
-#define SPRITE_SCALE_ENABLE REG_BIT(31)
-#define SPRITE_FILTER_MASK REG_GENMASK(30, 29)
-#define SPRITE_FILTER_MEDIUM REG_FIELD_PREP(SPRITE_FILTER_MASK, 0)
-#define SPRITE_FILTER_ENHANCING REG_FIELD_PREP(SPRITE_FILTER_MASK, 1)
-#define SPRITE_FILTER_SOFTENING REG_FIELD_PREP(SPRITE_FILTER_MASK, 2)
-#define SPRITE_VERTICAL_OFFSET_HALF REG_BIT(28) /* must be enabled below */
-#define SPRITE_VERTICAL_OFFSET_ENABLE REG_BIT(27)
-#define SPRITE_SRC_WIDTH_MASK REG_GENMASK(26, 16)
-#define SPRITE_SRC_WIDTH(w) REG_FIELD_PREP(SPRITE_SRC_WIDTH_MASK, (w))
-#define SPRITE_SRC_HEIGHT_MASK REG_GENMASK(10, 0)
-#define SPRITE_SRC_HEIGHT(h) REG_FIELD_PREP(SPRITE_SRC_HEIGHT_MASK, (h))
-#define _SPRA_GAMC 0x70400
-#define _SPRA_GAMC16 0x70440
-#define _SPRA_GAMC17 0x7044c
-
-#define _SPRB_CTL 0x71280
-#define _SPRB_LINOFF 0x71284
-#define _SPRB_STRIDE 0x71288
-#define _SPRB_POS 0x7128c
-#define _SPRB_SIZE 0x71290
-#define _SPRB_KEYVAL 0x71294
-#define _SPRB_KEYMSK 0x71298
-#define _SPRB_SURF 0x7129c
-#define _SPRB_KEYMAX 0x712a0
-#define _SPRB_TILEOFF 0x712a4
-#define _SPRB_OFFSET 0x712a4
-#define _SPRB_SURFLIVE 0x712ac
-#define _SPRB_SCALE 0x71304
-#define _SPRB_GAMC 0x71400
-#define _SPRB_GAMC16 0x71440
-#define _SPRB_GAMC17 0x7144c
-
-#define SPRCTL(pipe) _MMIO_PIPE(pipe, _SPRA_CTL, _SPRB_CTL)
-#define SPRLINOFF(pipe) _MMIO_PIPE(pipe, _SPRA_LINOFF, _SPRB_LINOFF)
-#define SPRSTRIDE(pipe) _MMIO_PIPE(pipe, _SPRA_STRIDE, _SPRB_STRIDE)
-#define SPRPOS(pipe) _MMIO_PIPE(pipe, _SPRA_POS, _SPRB_POS)
-#define SPRSIZE(pipe) _MMIO_PIPE(pipe, _SPRA_SIZE, _SPRB_SIZE)
-#define SPRKEYVAL(pipe) _MMIO_PIPE(pipe, _SPRA_KEYVAL, _SPRB_KEYVAL)
-#define SPRKEYMSK(pipe) _MMIO_PIPE(pipe, _SPRA_KEYMSK, _SPRB_KEYMSK)
-#define SPRSURF(pipe) _MMIO_PIPE(pipe, _SPRA_SURF, _SPRB_SURF)
-#define SPRKEYMAX(pipe) _MMIO_PIPE(pipe, _SPRA_KEYMAX, _SPRB_KEYMAX)
-#define SPRTILEOFF(pipe) _MMIO_PIPE(pipe, _SPRA_TILEOFF, _SPRB_TILEOFF)
-#define SPROFFSET(pipe) _MMIO_PIPE(pipe, _SPRA_OFFSET, _SPRB_OFFSET)
-#define SPRSCALE(pipe) _MMIO_PIPE(pipe, _SPRA_SCALE, _SPRB_SCALE)
-#define SPRGAMC(pipe, i) _MMIO(_PIPE(pipe, _SPRA_GAMC, _SPRB_GAMC) + (i) * 4) /* 16 x u0.10 */
-#define SPRGAMC16(pipe, i) _MMIO(_PIPE(pipe, _SPRA_GAMC16, _SPRB_GAMC16) + (i) * 4) /* 3 x u1.10 */
-#define SPRGAMC17(pipe, i) _MMIO(_PIPE(pipe, _SPRA_GAMC17, _SPRB_GAMC17) + (i) * 4) /* 3 x u2.10 */
-#define SPRSURFLIVE(pipe) _MMIO_PIPE(pipe, _SPRA_SURFLIVE, _SPRB_SURFLIVE)
-
-#define _SPACNTR (VLV_DISPLAY_BASE + 0x72180)
-#define SP_ENABLE REG_BIT(31)
-#define SP_PIPE_GAMMA_ENABLE REG_BIT(30)
-#define SP_FORMAT_MASK REG_GENMASK(29, 26)
-#define SP_FORMAT_YUV422 REG_FIELD_PREP(SP_FORMAT_MASK, 0)
-#define SP_FORMAT_8BPP REG_FIELD_PREP(SP_FORMAT_MASK, 2)
-#define SP_FORMAT_BGR565 REG_FIELD_PREP(SP_FORMAT_MASK, 5)
-#define SP_FORMAT_BGRX8888 REG_FIELD_PREP(SP_FORMAT_MASK, 6)
-#define SP_FORMAT_BGRA8888 REG_FIELD_PREP(SP_FORMAT_MASK, 7)
-#define SP_FORMAT_RGBX1010102 REG_FIELD_PREP(SP_FORMAT_MASK, 8)
-#define SP_FORMAT_RGBA1010102 REG_FIELD_PREP(SP_FORMAT_MASK, 9)
-#define SP_FORMAT_BGRX1010102 REG_FIELD_PREP(SP_FORMAT_MASK, 10) /* CHV pipe B */
-#define SP_FORMAT_BGRA1010102 REG_FIELD_PREP(SP_FORMAT_MASK, 11) /* CHV pipe B */
-#define SP_FORMAT_RGBX8888 REG_FIELD_PREP(SP_FORMAT_MASK, 14)
-#define SP_FORMAT_RGBA8888 REG_FIELD_PREP(SP_FORMAT_MASK, 15)
-#define SP_ALPHA_PREMULTIPLY REG_BIT(23) /* CHV pipe B */
-#define SP_SOURCE_KEY REG_BIT(22)
-#define SP_YUV_FORMAT_BT709 REG_BIT(18)
-#define SP_YUV_ORDER_MASK REG_GENMASK(17, 16)
-#define SP_YUV_ORDER_YUYV REG_FIELD_PREP(SP_YUV_ORDER_MASK, 0)
-#define SP_YUV_ORDER_UYVY REG_FIELD_PREP(SP_YUV_ORDER_MASK, 1)
-#define SP_YUV_ORDER_YVYU REG_FIELD_PREP(SP_YUV_ORDER_MASK, 2)
-#define SP_YUV_ORDER_VYUY REG_FIELD_PREP(SP_YUV_ORDER_MASK, 3)
-#define SP_ROTATE_180 REG_BIT(15)
-#define SP_TILED REG_BIT(10)
-#define SP_MIRROR REG_BIT(8) /* CHV pipe B */
-#define _SPALINOFF (VLV_DISPLAY_BASE + 0x72184)
-#define _SPASTRIDE (VLV_DISPLAY_BASE + 0x72188)
-#define _SPAPOS (VLV_DISPLAY_BASE + 0x7218c)
-#define SP_POS_Y_MASK REG_GENMASK(31, 16)
-#define SP_POS_Y(y) REG_FIELD_PREP(SP_POS_Y_MASK, (y))
-#define SP_POS_X_MASK REG_GENMASK(15, 0)
-#define SP_POS_X(x) REG_FIELD_PREP(SP_POS_X_MASK, (x))
-#define _SPASIZE (VLV_DISPLAY_BASE + 0x72190)
-#define SP_HEIGHT_MASK REG_GENMASK(31, 16)
-#define SP_HEIGHT(h) REG_FIELD_PREP(SP_HEIGHT_MASK, (h))
-#define SP_WIDTH_MASK REG_GENMASK(15, 0)
-#define SP_WIDTH(w) REG_FIELD_PREP(SP_WIDTH_MASK, (w))
-#define _SPAKEYMINVAL (VLV_DISPLAY_BASE + 0x72194)
-#define _SPAKEYMSK (VLV_DISPLAY_BASE + 0x72198)
-#define _SPASURF (VLV_DISPLAY_BASE + 0x7219c)
-#define SP_ADDR_MASK REG_GENMASK(31, 12)
-#define _SPAKEYMAXVAL (VLV_DISPLAY_BASE + 0x721a0)
-#define _SPATILEOFF (VLV_DISPLAY_BASE + 0x721a4)
-#define SP_OFFSET_Y_MASK REG_GENMASK(31, 16)
-#define SP_OFFSET_Y(y) REG_FIELD_PREP(SP_OFFSET_Y_MASK, (y))
-#define SP_OFFSET_X_MASK REG_GENMASK(15, 0)
-#define SP_OFFSET_X(x) REG_FIELD_PREP(SP_OFFSET_X_MASK, (x))
-#define _SPACONSTALPHA (VLV_DISPLAY_BASE + 0x721a8)
-#define SP_CONST_ALPHA_ENABLE REG_BIT(31)
-#define SP_CONST_ALPHA_MASK REG_GENMASK(7, 0)
-#define SP_CONST_ALPHA(alpha) REG_FIELD_PREP(SP_CONST_ALPHA_MASK, (alpha))
-#define _SPASURFLIVE (VLV_DISPLAY_BASE + 0x721ac)
-#define _SPACLRC0 (VLV_DISPLAY_BASE + 0x721d0)
-#define SP_CONTRAST_MASK REG_GENMASK(26, 18)
-#define SP_CONTRAST(x) REG_FIELD_PREP(SP_CONTRAST_MASK, (x)) /* u3.6 */
-#define SP_BRIGHTNESS_MASK REG_GENMASK(7, 0)
-#define SP_BRIGHTNESS(x) REG_FIELD_PREP(SP_BRIGHTNESS_MASK, (x)) /* s8 */
-#define _SPACLRC1 (VLV_DISPLAY_BASE + 0x721d4)
-#define SP_SH_SIN_MASK REG_GENMASK(26, 16)
-#define SP_SH_SIN(x) REG_FIELD_PREP(SP_SH_SIN_MASK, (x)) /* s4.7 */
-#define SP_SH_COS_MASK REG_GENMASK(9, 0)
-#define SP_SH_COS(x) REG_FIELD_PREP(SP_SH_COS_MASK, (x)) /* u3.7 */
-#define _SPAGAMC (VLV_DISPLAY_BASE + 0x721e0)
-
-#define _SPBCNTR (VLV_DISPLAY_BASE + 0x72280)
-#define _SPBLINOFF (VLV_DISPLAY_BASE + 0x72284)
-#define _SPBSTRIDE (VLV_DISPLAY_BASE + 0x72288)
-#define _SPBPOS (VLV_DISPLAY_BASE + 0x7228c)
-#define _SPBSIZE (VLV_DISPLAY_BASE + 0x72290)
-#define _SPBKEYMINVAL (VLV_DISPLAY_BASE + 0x72294)
-#define _SPBKEYMSK (VLV_DISPLAY_BASE + 0x72298)
-#define _SPBSURF (VLV_DISPLAY_BASE + 0x7229c)
-#define _SPBKEYMAXVAL (VLV_DISPLAY_BASE + 0x722a0)
-#define _SPBTILEOFF (VLV_DISPLAY_BASE + 0x722a4)
-#define _SPBCONSTALPHA (VLV_DISPLAY_BASE + 0x722a8)
-#define _SPBSURFLIVE (VLV_DISPLAY_BASE + 0x722ac)
-#define _SPBCLRC0 (VLV_DISPLAY_BASE + 0x722d0)
-#define _SPBCLRC1 (VLV_DISPLAY_BASE + 0x722d4)
-#define _SPBGAMC (VLV_DISPLAY_BASE + 0x722e0)
-
-#define _VLV_SPR(pipe, plane_id, reg_a, reg_b) \
- _PIPE((pipe) * 2 + (plane_id) - PLANE_SPRITE0, (reg_a), (reg_b))
-#define _MMIO_VLV_SPR(pipe, plane_id, reg_a, reg_b) \
- _MMIO(_VLV_SPR((pipe), (plane_id), (reg_a), (reg_b)))
-
-#define SPCNTR(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACNTR, _SPBCNTR)
-#define SPLINOFF(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPALINOFF, _SPBLINOFF)
-#define SPSTRIDE(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASTRIDE, _SPBSTRIDE)
-#define SPPOS(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAPOS, _SPBPOS)
-#define SPSIZE(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASIZE, _SPBSIZE)
-#define SPKEYMINVAL(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMINVAL, _SPBKEYMINVAL)
-#define SPKEYMSK(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMSK, _SPBKEYMSK)
-#define SPSURF(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASURF, _SPBSURF)
-#define SPKEYMAXVAL(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMAXVAL, _SPBKEYMAXVAL)
-#define SPTILEOFF(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPATILEOFF, _SPBTILEOFF)
-#define SPCONSTALPHA(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACONSTALPHA, _SPBCONSTALPHA)
-#define SPSURFLIVE(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASURFLIVE, _SPBSURFLIVE)
-#define SPCLRC0(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACLRC0, _SPBCLRC0)
-#define SPCLRC1(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACLRC1, _SPBCLRC1)
-#define SPGAMC(pipe, plane_id, i) _MMIO(_VLV_SPR((pipe), (plane_id), _SPAGAMC, _SPBGAMC) + (5 - (i)) * 4) /* 6 x u0.10 */
-
-/*
- * CHV pipe B sprite CSC
- *
- * |cr| |c0 c1 c2| |cr + cr_ioff| |cr_ooff|
- * |yg| = |c3 c4 c5| x |yg + yg_ioff| + |yg_ooff|
- * |cb| |c6 c7 c8| |cb + cr_ioff| |cb_ooff|
- */
-#define _MMIO_CHV_SPCSC(plane_id, reg) \
- _MMIO(VLV_DISPLAY_BASE + ((plane_id) - PLANE_SPRITE0) * 0x1000 + (reg))
-
-#define SPCSCYGOFF(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d900)
-#define SPCSCCBOFF(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d904)
-#define SPCSCCROFF(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d908)
-#define SPCSC_OOFF_MASK REG_GENMASK(26, 16)
-#define SPCSC_OOFF(x) REG_FIELD_PREP(SPCSC_OOFF_MASK, (x) & 0x7ff) /* s11 */
-#define SPCSC_IOFF_MASK REG_GENMASK(10, 0)
-#define SPCSC_IOFF(x) REG_FIELD_PREP(SPCSC_IOFF_MASK, (x) & 0x7ff) /* s11 */
-
-#define SPCSCC01(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d90c)
-#define SPCSCC23(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d910)
-#define SPCSCC45(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d914)
-#define SPCSCC67(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d918)
-#define SPCSCC8(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d91c)
-#define SPCSC_C1_MASK REG_GENMASK(30, 16)
-#define SPCSC_C1(x) REG_FIELD_PREP(SPCSC_C1_MASK, (x) & 0x7fff) /* s3.12 */
-#define SPCSC_C0_MASK REG_GENMASK(14, 0)
-#define SPCSC_C0(x) REG_FIELD_PREP(SPCSC_C0_MASK, (x) & 0x7fff) /* s3.12 */
-
-#define SPCSCYGICLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d920)
-#define SPCSCCBICLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d924)
-#define SPCSCCRICLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d928)
-#define SPCSC_IMAX_MASK REG_GENMASK(26, 16)
-#define SPCSC_IMAX(x) REG_FIELD_PREP(SPCSC_IMAX_MASK, (x) & 0x7ff) /* s11 */
-#define SPCSC_IMIN_MASK REG_GENMASK(10, 0)
-#define SPCSC_IMIN(x) REG_FIELD_PREP(SPCSC_IMIN_MASK, (x) & 0x7ff) /* s11 */
-
-#define SPCSCYGOCLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d92c)
-#define SPCSCCBOCLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d930)
-#define SPCSCCROCLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d934)
-#define SPCSC_OMAX_MASK REG_GENMASK(25, 16)
-#define SPCSC_OMAX(x) REG_FIELD_PREP(SPCSC_OMAX_MASK, (x)) /* u10 */
-#define SPCSC_OMIN_MASK REG_GENMASK(9, 0)
-#define SPCSC_OMIN(x) REG_FIELD_PREP(SPCSC_OMIN_MASK, (x)) /* u10 */
-
/* Skylake plane registers */
#define _PLANE_CTL_1_A 0x70180
diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
index 0d3689203510..e1a35f70b544 100644
--- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
+++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
@@ -15,6 +15,7 @@
#include "display/intel_fdi_regs.h"
#include "display/intel_lvds_regs.h"
#include "display/intel_psr_regs.h"
+#include "display/intel_sprite_regs.h"
#include "display/skl_watermark_regs.h"
#include "display/vlv_dsi_pll_regs.h"
#include "gt/intel_engine_regs.h"
--
2.39.2
^ permalink raw reply related [flat|nested] 10+ messages in thread
* ✗ Fi.CI.SPARSE: warning for drm/i915: i915_reg.h cleanups (rev2)
2024-04-26 10:51 [PATCH v2 0/4] drm/i915: i915_reg.h cleanups Jani Nikula
` (3 preceding siblings ...)
2024-04-26 10:51 ` [PATCH v2 4/4] drm/i915/display: split out intel_sprite_regs.h " Jani Nikula
@ 2024-04-26 11:31 ` Patchwork
2024-04-26 11:38 ` ✓ Fi.CI.BAT: success " Patchwork
2024-04-26 17:15 ` ✓ Fi.CI.IGT: " Patchwork
6 siblings, 0 replies; 10+ messages in thread
From: Patchwork @ 2024-04-26 11:31 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: i915_reg.h cleanups (rev2)
URL : https://patchwork.freedesktop.org/series/132381/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:173:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:175:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:179:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:181:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:181:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:185:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:187:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:191:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:194:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:194:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:236:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:238:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:66:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:92:1: warning: unreplaced symbol 'return'
+drivers/gpu/drm/i915/display/intel_de.h:105:15: warning: trying to copy expression type 31
+./include/asm-generic/bitops/generic-non-atomic.h:100:17: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:100:23: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:100:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:105:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:107:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:108:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:109:9: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:111:10: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:111:14: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:111:20: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:112:17: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:112:23: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:112:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:121:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:128:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:166:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:168:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:169:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:170:9: warning: unreplaced symbol 'val'
+./include/asm-generic/bitops/generic-non-atomic.h:172:19: warning: unreplaced symbol 'val'
+./include/asm-generic/bitops/generic-non-atomic.h:172:25: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:172:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:28:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:30:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:31:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:33:10: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:33:16: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:37:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:39:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:40:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:42:10: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:42:16: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:55:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:57:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:58:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:60:10: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:60:15: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:73:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:75:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:76:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:77:9: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:79:10: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:79:14: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:79:20: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:80:17: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:80:23: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:80:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:93:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:95:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:96:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:97:9: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:99:10: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:99:14: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:99:21: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/instrumented-non-atomic.h:100:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/instrumented-non-atomic.h:112:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/instrumented-non-atomic.h:115:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/instrumented-non-atomic.h:127:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/instrumented-non-atomic.h:130:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/instrumented-non-atomic.h:139:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/instrumented-non-atomic.h:142:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/instrumented-non-atomic.h:26:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/instrumented-non-atomic.h:42:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/instrumented-non-atomic.h:58:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/instrumented-non-atomic.h:97:1: warning: unreplaced symbol 'return'
^ permalink raw reply [flat|nested] 10+ messages in thread
* ✓ Fi.CI.BAT: success for drm/i915: i915_reg.h cleanups (rev2)
2024-04-26 10:51 [PATCH v2 0/4] drm/i915: i915_reg.h cleanups Jani Nikula
` (4 preceding siblings ...)
2024-04-26 11:31 ` ✗ Fi.CI.SPARSE: warning for drm/i915: i915_reg.h cleanups (rev2) Patchwork
@ 2024-04-26 11:38 ` Patchwork
2024-04-26 17:15 ` ✓ Fi.CI.IGT: " Patchwork
6 siblings, 0 replies; 10+ messages in thread
From: Patchwork @ 2024-04-26 11:38 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 3045 bytes --]
== Series Details ==
Series: drm/i915: i915_reg.h cleanups (rev2)
URL : https://patchwork.freedesktop.org/series/132381/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_14663 -> Patchwork_132381v2
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/index.html
Participating hosts (40 -> 37)
------------------------------
Additional (1): bat-rpls-4
Missing (4): fi-kbl-8809g bat-jsl-1 fi-apl-guc fi-snb-2520m
Known issues
------------
Here are the changes found in Patchwork_132381v2 that come from known issues:
### IGT changes ###
#### Possible fixes ####
* igt@i915_pm_rpm@module-reload:
- {bat-mtlp-9}: [CRASH][1] ([i915#10911]) -> [PASS][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14663/bat-mtlp-9/igt@i915_pm_rpm@module-reload.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/bat-mtlp-9/igt@i915_pm_rpm@module-reload.html
* igt@i915_selftest@live@client:
- bat-arls-1: [ABORT][3] ([i915#9618]) -> [PASS][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14663/bat-arls-1/igt@i915_selftest@live@client.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/bat-arls-1/igt@i915_selftest@live@client.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#1072]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1072
[i915#10911]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10911
[i915#3282]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3282
[i915#3555]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3555
[i915#3708]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3708
[i915#3840]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3840
[i915#4103]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4103
[i915#4613]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4613
[i915#5354]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5354
[i915#9318]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9318
[i915#9618]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9618
[i915#9732]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9732
[i915#9886]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9886
Build changes
-------------
* Linux: CI_DRM_14663 -> Patchwork_132381v2
CI-20190529: 20190529
CI_DRM_14663: 47c509a8d4944e6276f7b956061c2020323f0a90 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7825: 28b2a1b0be86e33a2fc04a022e04f07bd25b66d9 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_132381v2: 47c509a8d4944e6276f7b956061c2020323f0a90 @ git://anongit.freedesktop.org/gfx-ci/linux
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/index.html
[-- Attachment #2: Type: text/html, Size: 2848 bytes --]
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v2 3/4] drm/i915/display: split out intel_fbc_regs.h from i915_reg.h
2024-04-26 10:51 ` [PATCH v2 3/4] drm/i915/display: split out intel_fbc_regs.h from i915_reg.h Jani Nikula
@ 2024-04-26 15:03 ` Ville Syrjälä
2024-04-29 10:16 ` Jani Nikula
0 siblings, 1 reply; 10+ messages in thread
From: Ville Syrjälä @ 2024-04-26 15:03 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
On Fri, Apr 26, 2024 at 01:51:36PM +0300, Jani Nikula wrote:
> Clean up i915_reg.h.
>
> v2: Drop chicken regs and comments (Ville)
>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_fbc.c | 1 +
> drivers/gpu/drm/i915/display/intel_fbc_regs.h | 120 +++++++++++++++++
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 2 +
> drivers/gpu/drm/i915/i915_reg.h | 123 ------------------
> drivers/gpu/drm/i915/intel_clock_gating.c | 1 +
> drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 1 +
> 6 files changed, 125 insertions(+), 123 deletions(-)
> create mode 100644 drivers/gpu/drm/i915/display/intel_fbc_regs.h
>
> diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
> index 7c4d2b2bf20b..151dcd0c45b6 100644
> --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> @@ -54,6 +54,7 @@
> #include "intel_display_trace.h"
> #include "intel_display_types.h"
> #include "intel_fbc.h"
> +#include "intel_fbc_regs.h"
> #include "intel_frontbuffer.h"
>
> #define for_each_fbc_id(__dev_priv, __fbc_id) \
> diff --git a/drivers/gpu/drm/i915/display/intel_fbc_regs.h b/drivers/gpu/drm/i915/display/intel_fbc_regs.h
> new file mode 100644
> index 000000000000..ae0699c3c2fe
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/display/intel_fbc_regs.h
> @@ -0,0 +1,120 @@
> +/* SPDX-License-Identifier: MIT */
> +/* Copyright © 2024 Intel Corporation */
> +
> +#ifndef __INTEL_FBC_REGS__
> +#define __INTEL_FBC_REGS__
> +
> +#include "intel_display_reg_defs.h"
> +
> +#define FBC_CFB_BASE _MMIO(0x3200) /* 4k page aligned */
> +#define FBC_LL_BASE _MMIO(0x3204) /* 4k page aligned */
> +#define FBC_CONTROL _MMIO(0x3208)
> +#define FBC_CTL_EN REG_BIT(31)
> +#define FBC_CTL_PERIODIC REG_BIT(30)
> +#define FBC_CTL_INTERVAL_MASK REG_GENMASK(29, 16)
> +#define FBC_CTL_INTERVAL(x) REG_FIELD_PREP(FBC_CTL_INTERVAL_MASK, (x))
> +#define FBC_CTL_STOP_ON_MOD REG_BIT(15)
> +#define FBC_CTL_UNCOMPRESSIBLE REG_BIT(14) /* i915+ */
> +#define FBC_CTL_C3_IDLE REG_BIT(13) /* i945gm only */
> +#define FBC_CTL_STRIDE_MASK REG_GENMASK(12, 5)
> +#define FBC_CTL_STRIDE(x) REG_FIELD_PREP(FBC_CTL_STRIDE_MASK, (x))
> +#define FBC_CTL_FENCENO_MASK REG_GENMASK(3, 0)
> +#define FBC_CTL_FENCENO(x) REG_FIELD_PREP(FBC_CTL_FENCENO_MASK, (x))
> +#define FBC_COMMAND _MMIO(0x320c)
> +#define FBC_CMD_COMPRESS REG_BIT(0)
> +#define FBC_STATUS _MMIO(0x3210)
> +#define FBC_STAT_COMPRESSING REG_BIT(31)
> +#define FBC_STAT_COMPRESSED REG_BIT(30)
> +#define FBC_STAT_MODIFIED REG_BIT(29)
> +#define FBC_STAT_CURRENT_LINE_MASK REG_GENMASK(10, 0)
> +#define FBC_CONTROL2 _MMIO(0x3214) /* i965gm only */
> +#define FBC_CTL_FENCE_DBL REG_BIT(4)
> +#define FBC_CTL_IDLE_MASK REG_GENMASK(3, 2)
> +#define FBC_CTL_IDLE_IMM REG_FIELD_PREP(FBC_CTL_IDLE_MASK, 0)
> +#define FBC_CTL_IDLE_FULL REG_FIELD_PREP(FBC_CTL_IDLE_MASK, 1)
> +#define FBC_CTL_IDLE_LINE REG_FIELD_PREP(FBC_CTL_IDLE_MASK, 2)
> +#define FBC_CTL_IDLE_DEBUG REG_FIELD_PREP(FBC_CTL_IDLE_MASK, 3)
> +#define FBC_CTL_CPU_FENCE_EN REG_BIT(1)
> +#define FBC_CTL_PLANE_MASK REG_GENMASK(1, 0)
> +#define FBC_CTL_PLANE(i9xx_plane) REG_FIELD_PREP(FBC_CTL_PLANE_MASK, (i9xx_plane))
> +#define FBC_FENCE_OFF _MMIO(0x3218) /* i965gm only, BSpec typo has 321Bh */
> +#define FBC_MOD_NUM _MMIO(0x3220) /* i965gm only */
> +#define FBC_MOD_NUM_MASK REG_GENMASK(31, 1)
> +#define FBC_MOD_NUM_VALID REG_BIT(0)
> +#define FBC_TAG(i) _MMIO(0x3300 + (i) * 4) /* 49 reisters */
> +#define FBC_TAG_MASK REG_GENMASK(1, 0) /* 16 tags per register */
> +#define FBC_TAG_MODIFIED REG_FIELD_PREP(FBC_TAG_MASK, 0)
> +#define FBC_TAG_UNCOMPRESSED REG_FIELD_PREP(FBC_TAG_MASK, 1)
> +#define FBC_TAG_UNCOMPRESSIBLE REG_FIELD_PREP(FBC_TAG_MASK, 2)
> +#define FBC_TAG_COMPRESSED REG_FIELD_PREP(FBC_TAG_MASK, 3)
> +
> +#define FBC_LL_SIZE (1536)
> +
> +#define DPFC_CB_BASE _MMIO(0x3200)
> +#define ILK_DPFC_CB_BASE(fbc_id) _MMIO_PIPE((fbc_id), 0x43200, 0x43240)
> +#define DPFC_CONTROL _MMIO(0x3208)
> +#define ILK_DPFC_CONTROL(fbc_id) _MMIO_PIPE((fbc_id), 0x43208, 0x43248)
> +#define DPFC_CTL_EN REG_BIT(31)
> +#define DPFC_CTL_PLANE_MASK_G4X REG_BIT(30) /* g4x-snb */
> +#define DPFC_CTL_PLANE_G4X(i9xx_plane) REG_FIELD_PREP(DPFC_CTL_PLANE_MASK_G4X, (i9xx_plane))
> +#define DPFC_CTL_FENCE_EN_G4X REG_BIT(29) /* g4x-snb */
> +#define DPFC_CTL_PLANE_MASK_IVB REG_GENMASK(30, 29) /* ivb only */
> +#define DPFC_CTL_PLANE_IVB(i9xx_plane) REG_FIELD_PREP(DPFC_CTL_PLANE_MASK_IVB, (i9xx_plane))
> +#define DPFC_CTL_FENCE_EN_IVB REG_BIT(28) /* ivb+ */
> +#define DPFC_CTL_PERSISTENT_MODE REG_BIT(25) /* g4x-snb */
> +#define DPFC_CTL_PLANE_BINDING_MASK REG_GENMASK(12, 11) /* lnl+ */
> +#define DPFC_CTL_PLANE_BINDING(plane_id) REG_FIELD_PREP(DPFC_CTL_PLANE_BINDING_MASK, (plane_id))
> +#define DPFC_CTL_FALSE_COLOR REG_BIT(10) /* ivb+ */
> +#define DPFC_CTL_SR_EN REG_BIT(10) /* g4x only */
> +#define DPFC_CTL_SR_EXIT_DIS REG_BIT(9) /* g4x only */
> +#define DPFC_CTL_LIMIT_MASK REG_GENMASK(7, 6)
> +#define DPFC_CTL_LIMIT_1X REG_FIELD_PREP(DPFC_CTL_LIMIT_MASK, 0)
> +#define DPFC_CTL_LIMIT_2X REG_FIELD_PREP(DPFC_CTL_LIMIT_MASK, 1)
> +#define DPFC_CTL_LIMIT_4X REG_FIELD_PREP(DPFC_CTL_LIMIT_MASK, 2)
> +#define DPFC_CTL_FENCENO_MASK REG_GENMASK(3, 0)
> +#define DPFC_CTL_FENCENO(fence) REG_FIELD_PREP(DPFC_CTL_FENCENO_MASK, (fence))
> +#define DPFC_RECOMP_CTL _MMIO(0x320c)
> +#define ILK_DPFC_RECOMP_CTL(fbc_id) _MMIO_PIPE((fbc_id), 0x4320c, 0x4324c)
> +#define DPFC_RECOMP_STALL_EN REG_BIT(27)
> +#define DPFC_RECOMP_STALL_WM_MASK REG_GENMASK(26, 16)
> +#define DPFC_RECOMP_TIMER_COUNT_MASK REG_GENMASK(5, 0)
> +#define DPFC_STATUS _MMIO(0x3210)
> +#define ILK_DPFC_STATUS(fbc_id) _MMIO_PIPE((fbc_id), 0x43210, 0x43250)
> +#define DPFC_INVAL_SEG_MASK REG_GENMASK(26, 16)
> +#define DPFC_COMP_SEG_MASK REG_GENMASK(10, 0)
> +#define DPFC_STATUS2 _MMIO(0x3214)
> +#define ILK_DPFC_STATUS2(fbc_id) _MMIO_PIPE((fbc_id), 0x43214, 0x43254)
> +#define DPFC_COMP_SEG_MASK_IVB REG_GENMASK(11, 0)
> +#define DPFC_FENCE_YOFF _MMIO(0x3218)
> +#define ILK_DPFC_FENCE_YOFF(fbc_id) _MMIO_PIPE((fbc_id), 0x43218, 0x43258)
> +#define DPFC_CHICKEN _MMIO(0x3224)
> +#define ILK_DPFC_CHICKEN(fbc_id) _MMIO_PIPE((fbc_id), 0x43224, 0x43264)
> +#define DPFC_HT_MODIFY REG_BIT(31) /* pre-ivb */
> +#define DPFC_NUKE_ON_ANY_MODIFICATION REG_BIT(23) /* bdw+ */
> +#define DPFC_CHICKEN_COMP_DUMMY_PIXEL REG_BIT(14) /* glk+ */
> +#define DPFC_CHICKEN_FORCE_SLB_INVALIDATION REG_BIT(13) /* icl+ */
> +#define DPFC_DISABLE_DUMMY0 REG_BIT(8) /* ivb+ */
> +
> +#define GLK_FBC_STRIDE(fbc_id) _MMIO_PIPE((fbc_id), 0x43228, 0x43268)
> +#define FBC_STRIDE_OVERRIDE REG_BIT(15)
> +#define FBC_STRIDE_MASK REG_GENMASK(14, 0)
> +#define FBC_STRIDE(x) REG_FIELD_PREP(FBC_STRIDE_MASK, (x))
> +
> +#define ILK_FBC_RT_BASE _MMIO(0x2128)
> +#define ILK_FBC_RT_VALID REG_BIT(0)
> +#define SNB_FBC_FRONT_BUFFER REG_BIT(1)
> +
> +#define SNB_DPFC_CTL_SA _MMIO(0x100100)
> +#define SNB_DPFC_FENCE_EN REG_BIT(29)
> +#define SNB_DPFC_FENCENO_MASK REG_GENMASK(4, 0)
> +#define SNB_DPFC_FENCENO(fence) REG_FIELD_PREP(SNB_DPFC_FENCENO_MASK, (fence))
> +#define SNB_DPFC_CPU_FENCE_OFFSET _MMIO(0x100104)
> +
> +#define IVB_FBC_RT_BASE _MMIO(0x7020)
> +#define IVB_FBC_RT_BASE_UPPER _MMIO(0x7024)
> +
> +#define MSG_FBC_REND_STATE(fbc_id) _MMIO_PIPE((fbc_id), 0x50380, 0x50384)
> +#define FBC_REND_NUKE REG_BIT(2)
> +#define FBC_REND_CACHE_CLEAN REG_BIT(1)
> +
> +#endif /* __INTEL_FBC_REGS__ */
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 68b6aa11bcf7..40e79f0dc257 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -17,6 +17,8 @@
> #include "intel_ring.h"
> #include "intel_workarounds.h"
>
> +#include "display/intel_fbc_regs.h"
> +
> /**
> * DOC: Hardware workarounds
> *
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index c5ea2ed653b9..5cdf3b17e7d4 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -986,109 +986,6 @@
> #define GEN7_FF_DS_SCHED_LOAD_BALANCE (0x1 << 4) /* Default */
> #define GEN7_FF_DS_SCHED_HW (0x0 << 4)
>
> -/*
> - * Framebuffer compression (915+ only)
> - */
> -
> -#define FBC_CFB_BASE _MMIO(0x3200) /* 4k page aligned */
> -#define FBC_LL_BASE _MMIO(0x3204) /* 4k page aligned */
> -#define FBC_CONTROL _MMIO(0x3208)
> -#define FBC_CTL_EN REG_BIT(31)
> -#define FBC_CTL_PERIODIC REG_BIT(30)
> -#define FBC_CTL_INTERVAL_MASK REG_GENMASK(29, 16)
> -#define FBC_CTL_INTERVAL(x) REG_FIELD_PREP(FBC_CTL_INTERVAL_MASK, (x))
> -#define FBC_CTL_STOP_ON_MOD REG_BIT(15)
> -#define FBC_CTL_UNCOMPRESSIBLE REG_BIT(14) /* i915+ */
> -#define FBC_CTL_C3_IDLE REG_BIT(13) /* i945gm only */
> -#define FBC_CTL_STRIDE_MASK REG_GENMASK(12, 5)
> -#define FBC_CTL_STRIDE(x) REG_FIELD_PREP(FBC_CTL_STRIDE_MASK, (x))
> -#define FBC_CTL_FENCENO_MASK REG_GENMASK(3, 0)
> -#define FBC_CTL_FENCENO(x) REG_FIELD_PREP(FBC_CTL_FENCENO_MASK, (x))
> -#define FBC_COMMAND _MMIO(0x320c)
> -#define FBC_CMD_COMPRESS REG_BIT(0)
> -#define FBC_STATUS _MMIO(0x3210)
> -#define FBC_STAT_COMPRESSING REG_BIT(31)
> -#define FBC_STAT_COMPRESSED REG_BIT(30)
> -#define FBC_STAT_MODIFIED REG_BIT(29)
> -#define FBC_STAT_CURRENT_LINE_MASK REG_GENMASK(10, 0)
> -#define FBC_CONTROL2 _MMIO(0x3214) /* i965gm only */
> -#define FBC_CTL_FENCE_DBL REG_BIT(4)
> -#define FBC_CTL_IDLE_MASK REG_GENMASK(3, 2)
> -#define FBC_CTL_IDLE_IMM REG_FIELD_PREP(FBC_CTL_IDLE_MASK, 0)
> -#define FBC_CTL_IDLE_FULL REG_FIELD_PREP(FBC_CTL_IDLE_MASK, 1)
> -#define FBC_CTL_IDLE_LINE REG_FIELD_PREP(FBC_CTL_IDLE_MASK, 2)
> -#define FBC_CTL_IDLE_DEBUG REG_FIELD_PREP(FBC_CTL_IDLE_MASK, 3)
> -#define FBC_CTL_CPU_FENCE_EN REG_BIT(1)
> -#define FBC_CTL_PLANE_MASK REG_GENMASK(1, 0)
> -#define FBC_CTL_PLANE(i9xx_plane) REG_FIELD_PREP(FBC_CTL_PLANE_MASK, (i9xx_plane))
> -#define FBC_FENCE_OFF _MMIO(0x3218) /* i965gm only, BSpec typo has 321Bh */
> -#define FBC_MOD_NUM _MMIO(0x3220) /* i965gm only */
> -#define FBC_MOD_NUM_MASK REG_GENMASK(31, 1)
> -#define FBC_MOD_NUM_VALID REG_BIT(0)
> -#define FBC_TAG(i) _MMIO(0x3300 + (i) * 4) /* 49 reisters */
> -#define FBC_TAG_MASK REG_GENMASK(1, 0) /* 16 tags per register */
> -#define FBC_TAG_MODIFIED REG_FIELD_PREP(FBC_TAG_MASK, 0)
> -#define FBC_TAG_UNCOMPRESSED REG_FIELD_PREP(FBC_TAG_MASK, 1)
> -#define FBC_TAG_UNCOMPRESSIBLE REG_FIELD_PREP(FBC_TAG_MASK, 2)
> -#define FBC_TAG_COMPRESSED REG_FIELD_PREP(FBC_TAG_MASK, 3)
> -
> -#define FBC_LL_SIZE (1536)
> -
> -/* Framebuffer compression for GM45+ */
> -#define DPFC_CB_BASE _MMIO(0x3200)
> -#define ILK_DPFC_CB_BASE(fbc_id) _MMIO_PIPE((fbc_id), 0x43200, 0x43240)
> -#define DPFC_CONTROL _MMIO(0x3208)
> -#define ILK_DPFC_CONTROL(fbc_id) _MMIO_PIPE((fbc_id), 0x43208, 0x43248)
> -#define DPFC_CTL_EN REG_BIT(31)
> -#define DPFC_CTL_PLANE_MASK_G4X REG_BIT(30) /* g4x-snb */
> -#define DPFC_CTL_PLANE_G4X(i9xx_plane) REG_FIELD_PREP(DPFC_CTL_PLANE_MASK_G4X, (i9xx_plane))
> -#define DPFC_CTL_FENCE_EN_G4X REG_BIT(29) /* g4x-snb */
> -#define DPFC_CTL_PLANE_MASK_IVB REG_GENMASK(30, 29) /* ivb only */
> -#define DPFC_CTL_PLANE_IVB(i9xx_plane) REG_FIELD_PREP(DPFC_CTL_PLANE_MASK_IVB, (i9xx_plane))
> -#define DPFC_CTL_FENCE_EN_IVB REG_BIT(28) /* ivb+ */
> -#define DPFC_CTL_PERSISTENT_MODE REG_BIT(25) /* g4x-snb */
> -#define DPFC_CTL_PLANE_BINDING_MASK REG_GENMASK(12, 11) /* lnl+ */
> -#define DPFC_CTL_PLANE_BINDING(plane_id) REG_FIELD_PREP(DPFC_CTL_PLANE_BINDING_MASK, (plane_id))
> -#define DPFC_CTL_FALSE_COLOR REG_BIT(10) /* ivb+ */
> -#define DPFC_CTL_SR_EN REG_BIT(10) /* g4x only */
> -#define DPFC_CTL_SR_EXIT_DIS REG_BIT(9) /* g4x only */
> -#define DPFC_CTL_LIMIT_MASK REG_GENMASK(7, 6)
> -#define DPFC_CTL_LIMIT_1X REG_FIELD_PREP(DPFC_CTL_LIMIT_MASK, 0)
> -#define DPFC_CTL_LIMIT_2X REG_FIELD_PREP(DPFC_CTL_LIMIT_MASK, 1)
> -#define DPFC_CTL_LIMIT_4X REG_FIELD_PREP(DPFC_CTL_LIMIT_MASK, 2)
> -#define DPFC_CTL_FENCENO_MASK REG_GENMASK(3, 0)
> -#define DPFC_CTL_FENCENO(fence) REG_FIELD_PREP(DPFC_CTL_FENCENO_MASK, (fence))
> -#define DPFC_RECOMP_CTL _MMIO(0x320c)
> -#define ILK_DPFC_RECOMP_CTL(fbc_id) _MMIO_PIPE((fbc_id), 0x4320c, 0x4324c)
> -#define DPFC_RECOMP_STALL_EN REG_BIT(27)
> -#define DPFC_RECOMP_STALL_WM_MASK REG_GENMASK(26, 16)
> -#define DPFC_RECOMP_TIMER_COUNT_MASK REG_GENMASK(5, 0)
> -#define DPFC_STATUS _MMIO(0x3210)
> -#define ILK_DPFC_STATUS(fbc_id) _MMIO_PIPE((fbc_id), 0x43210, 0x43250)
> -#define DPFC_INVAL_SEG_MASK REG_GENMASK(26, 16)
> -#define DPFC_COMP_SEG_MASK REG_GENMASK(10, 0)
> -#define DPFC_STATUS2 _MMIO(0x3214)
> -#define ILK_DPFC_STATUS2(fbc_id) _MMIO_PIPE((fbc_id), 0x43214, 0x43254)
> -#define DPFC_COMP_SEG_MASK_IVB REG_GENMASK(11, 0)
> -#define DPFC_FENCE_YOFF _MMIO(0x3218)
> -#define ILK_DPFC_FENCE_YOFF(fbc_id) _MMIO_PIPE((fbc_id), 0x43218, 0x43258)
> -#define DPFC_CHICKEN _MMIO(0x3224)
> -#define ILK_DPFC_CHICKEN(fbc_id) _MMIO_PIPE((fbc_id), 0x43224, 0x43264)
> -#define DPFC_HT_MODIFY REG_BIT(31) /* pre-ivb */
> -#define DPFC_NUKE_ON_ANY_MODIFICATION REG_BIT(23) /* bdw+ */
> -#define DPFC_CHICKEN_COMP_DUMMY_PIXEL REG_BIT(14) /* glk+ */
> -#define DPFC_CHICKEN_FORCE_SLB_INVALIDATION REG_BIT(13) /* icl+ */
> -#define DPFC_DISABLE_DUMMY0 REG_BIT(8) /* ivb+ */
> -
> -#define GLK_FBC_STRIDE(fbc_id) _MMIO_PIPE((fbc_id), 0x43228, 0x43268)
> -#define FBC_STRIDE_OVERRIDE REG_BIT(15)
> -#define FBC_STRIDE_MASK REG_GENMASK(14, 0)
> -#define FBC_STRIDE(x) REG_FIELD_PREP(FBC_STRIDE_MASK, (x))
> -
> -#define ILK_FBC_RT_BASE _MMIO(0x2128)
> -#define ILK_FBC_RT_VALID REG_BIT(0)
> -#define SNB_FBC_FRONT_BUFFER REG_BIT(1)
> -
> #define ILK_DISPLAY_CHICKEN1 _MMIO(0x42000)
> #define ILK_FBCQ_DIS REG_BIT(22)
> #define ILK_PABSTRETCH_DIS REG_BIT(21)
> @@ -1104,30 +1001,10 @@
> #define IVB_SPR_STRETCH_MAX_X2 REG_FIELD_PREP(IVB_SPR_STRETCH_MAX_MASK, 2)
> #define IVB_SPR_STRETCH_MAX_X1 REG_FIELD_PREP(IVB_SPR_STRETCH_MAX_MASK, 3)
>
> -
> -/*
> - * Framebuffer compression for Sandybridge
> - *
> - * The following two registers are of type GTTMMADR
> - */
> -#define SNB_DPFC_CTL_SA _MMIO(0x100100)
> -#define SNB_DPFC_FENCE_EN REG_BIT(29)
> -#define SNB_DPFC_FENCENO_MASK REG_GENMASK(4, 0)
> -#define SNB_DPFC_FENCENO(fence) REG_FIELD_PREP(SNB_DPFC_FENCENO_MASK, (fence))
> -#define SNB_DPFC_CPU_FENCE_OFFSET _MMIO(0x100104)
> -
> -/* Framebuffer compression for Ivybridge */
> -#define IVB_FBC_RT_BASE _MMIO(0x7020)
> -#define IVB_FBC_RT_BASE_UPPER _MMIO(0x7024)
> -
> #define IPS_CTL _MMIO(0x43408)
> #define IPS_ENABLE REG_BIT(31)
> #define IPS_FALSE_COLOR REG_BIT(4)
>
> -#define MSG_FBC_REND_STATE(fbc_id) _MMIO_PIPE((fbc_id), 0x50380, 0x50384)
> -#define FBC_REND_NUKE REG_BIT(2)
> -#define FBC_REND_CACHE_CLEAN REG_BIT(1)
> -
> /*
> * Clock control & power management
> */
> diff --git a/drivers/gpu/drm/i915/intel_clock_gating.c b/drivers/gpu/drm/i915/intel_clock_gating.c
> index 7e70ee4fbd84..1dc5281b2ade 100644
> --- a/drivers/gpu/drm/i915/intel_clock_gating.c
> +++ b/drivers/gpu/drm/i915/intel_clock_gating.c
> @@ -28,6 +28,7 @@
> #include "display/intel_de.h"
> #include "display/intel_display.h"
> #include "display/intel_display_trace.h"
> +#include "display/intel_fbc_regs.h"
> #include "display/skl_watermark.h"
>
> #include "gt/intel_engine_regs.h"
> diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
> index d0f111ff0ada..0d3689203510 100644
> --- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
> +++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
> @@ -11,6 +11,7 @@
> #include "display/intel_dmc_regs.h"
> #include "display/intel_dp_aux_regs.h"
> #include "display/intel_dpio_phy.h"
> +#include "display/intel_fbc_regs.h"
> #include "display/intel_fdi_regs.h"
> #include "display/intel_lvds_regs.h"
> #include "display/intel_psr_regs.h"
> --
> 2.39.2
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 10+ messages in thread
* ✓ Fi.CI.IGT: success for drm/i915: i915_reg.h cleanups (rev2)
2024-04-26 10:51 [PATCH v2 0/4] drm/i915: i915_reg.h cleanups Jani Nikula
` (5 preceding siblings ...)
2024-04-26 11:38 ` ✓ Fi.CI.BAT: success " Patchwork
@ 2024-04-26 17:15 ` Patchwork
6 siblings, 0 replies; 10+ messages in thread
From: Patchwork @ 2024-04-26 17:15 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 76727 bytes --]
== Series Details ==
Series: drm/i915: i915_reg.h cleanups (rev2)
URL : https://patchwork.freedesktop.org/series/132381/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_14663_full -> Patchwork_132381v2_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Participating hosts (9 -> 9)
------------------------------
No changes in participating hosts
Known issues
------------
Here are the changes found in Patchwork_132381v2_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@api_intel_bb@crc32:
- shard-rkl: NOTRUN -> [SKIP][1] ([i915#6230])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-rkl-4/igt@api_intel_bb@crc32.html
* igt@device_reset@cold-reset-bound:
- shard-dg2: NOTRUN -> [SKIP][2] ([i915#7701])
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-dg2-8/igt@device_reset@cold-reset-bound.html
- shard-rkl: NOTRUN -> [SKIP][3] ([i915#7701])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-rkl-1/igt@device_reset@cold-reset-bound.html
* igt@drm_fdinfo@busy-hang@rcs0:
- shard-mtlp: NOTRUN -> [SKIP][4] ([i915#8414]) +5 other tests skip
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-mtlp-3/igt@drm_fdinfo@busy-hang@rcs0.html
* igt@drm_fdinfo@busy-idle-check-all@vcs1:
- shard-dg1: NOTRUN -> [SKIP][5] ([i915#8414]) +10 other tests skip
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-dg1-18/igt@drm_fdinfo@busy-idle-check-all@vcs1.html
* igt@drm_fdinfo@most-busy-check-all@rcs0:
- shard-rkl: [PASS][6] -> [FAIL][7] ([i915#7742])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14663/shard-rkl-2/igt@drm_fdinfo@most-busy-check-all@rcs0.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-rkl-4/igt@drm_fdinfo@most-busy-check-all@rcs0.html
* igt@drm_fdinfo@most-busy-idle-check-all@rcs0:
- shard-rkl: NOTRUN -> [FAIL][8] ([i915#7742])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-rkl-5/igt@drm_fdinfo@most-busy-idle-check-all@rcs0.html
* igt@gem_ccs@ctrl-surf-copy-new-ctx:
- shard-rkl: NOTRUN -> [SKIP][9] ([i915#9323])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-rkl-1/igt@gem_ccs@ctrl-surf-copy-new-ctx.html
* igt@gem_close_race@multigpu-basic-threads:
- shard-dg1: NOTRUN -> [SKIP][10] ([i915#7697])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-dg1-18/igt@gem_close_race@multigpu-basic-threads.html
* igt@gem_create@create-ext-cpu-access-sanity-check:
- shard-rkl: NOTRUN -> [SKIP][11] ([i915#6335])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-rkl-1/igt@gem_create@create-ext-cpu-access-sanity-check.html
* igt@gem_create@create-ext-set-pat:
- shard-dg1: NOTRUN -> [SKIP][12] ([i915#8562])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-dg1-18/igt@gem_create@create-ext-set-pat.html
* igt@gem_ctx_persistence@heartbeat-hostile:
- shard-dg1: NOTRUN -> [SKIP][13] ([i915#8555])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-dg1-16/igt@gem_ctx_persistence@heartbeat-hostile.html
* igt@gem_ctx_sseu@invalid-sseu:
- shard-rkl: NOTRUN -> [SKIP][14] ([i915#280])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-rkl-1/igt@gem_ctx_sseu@invalid-sseu.html
* igt@gem_eio@hibernate:
- shard-rkl: NOTRUN -> [ABORT][15] ([i915#7975] / [i915#8213])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-rkl-5/igt@gem_eio@hibernate.html
* igt@gem_eio@kms:
- shard-tglu: [PASS][16] -> [INCOMPLETE][17] ([i915#10513])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14663/shard-tglu-3/igt@gem_eio@kms.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-tglu-7/igt@gem_eio@kms.html
- shard-dg2: NOTRUN -> [FAIL][18] ([i915#5784])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-dg2-8/igt@gem_eio@kms.html
* igt@gem_eio@reset-stress:
- shard-dg1: NOTRUN -> [FAIL][19] ([i915#5784])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-dg1-16/igt@gem_eio@reset-stress.html
* igt@gem_exec_balancer@hog:
- shard-mtlp: NOTRUN -> [SKIP][20] ([i915#4812])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-mtlp-3/igt@gem_exec_balancer@hog.html
* igt@gem_exec_balancer@parallel-keep-in-fence:
- shard-rkl: NOTRUN -> [SKIP][21] ([i915#4525]) +1 other test skip
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-rkl-5/igt@gem_exec_balancer@parallel-keep-in-fence.html
* igt@gem_exec_capture@capture-invisible@lmem0:
- shard-dg1: NOTRUN -> [SKIP][22] ([i915#6334]) +1 other test skip
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-dg1-18/igt@gem_exec_capture@capture-invisible@lmem0.html
* igt@gem_exec_capture@capture-recoverable:
- shard-rkl: NOTRUN -> [SKIP][23] ([i915#6344])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-rkl-4/igt@gem_exec_capture@capture-recoverable.html
* igt@gem_exec_capture@many-4k-incremental:
- shard-glk: NOTRUN -> [FAIL][24] ([i915#9606]) +1 other test fail
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-glk5/igt@gem_exec_capture@many-4k-incremental.html
* igt@gem_exec_fair@basic-none:
- shard-dg1: NOTRUN -> [SKIP][25] ([i915#3539] / [i915#4852])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-dg1-16/igt@gem_exec_fair@basic-none.html
* igt@gem_exec_fair@basic-none-share:
- shard-dg2: NOTRUN -> [SKIP][26] ([i915#3539] / [i915#4852]) +1 other test skip
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-dg2-8/igt@gem_exec_fair@basic-none-share.html
* igt@gem_exec_fair@basic-none-vip@rcs0:
- shard-glk: NOTRUN -> [FAIL][27] ([i915#2842])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-glk4/igt@gem_exec_fair@basic-none-vip@rcs0.html
* igt@gem_exec_fair@basic-none@bcs0:
- shard-rkl: NOTRUN -> [FAIL][28] ([i915#2842]) +5 other tests fail
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-rkl-5/igt@gem_exec_fair@basic-none@bcs0.html
* igt@gem_exec_fair@basic-throttle:
- shard-dg1: NOTRUN -> [SKIP][29] ([i915#3539])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-dg1-18/igt@gem_exec_fair@basic-throttle.html
* igt@gem_exec_flush@basic-uc-set-default:
- shard-dg2: NOTRUN -> [SKIP][30] ([i915#3539])
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-dg2-8/igt@gem_exec_flush@basic-uc-set-default.html
* igt@gem_exec_reloc@basic-cpu-noreloc:
- shard-dg2: NOTRUN -> [SKIP][31] ([i915#3281]) +2 other tests skip
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-dg2-8/igt@gem_exec_reloc@basic-cpu-noreloc.html
* igt@gem_exec_reloc@basic-gtt:
- shard-dg1: NOTRUN -> [SKIP][32] ([i915#3281]) +1 other test skip
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-dg1-16/igt@gem_exec_reloc@basic-gtt.html
* igt@gem_exec_reloc@basic-wc-read-noreloc:
- shard-rkl: NOTRUN -> [SKIP][33] ([i915#3281]) +12 other tests skip
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-rkl-5/igt@gem_exec_reloc@basic-wc-read-noreloc.html
* igt@gem_exec_reloc@basic-write-read-active:
- shard-mtlp: NOTRUN -> [SKIP][34] ([i915#3281])
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-mtlp-3/igt@gem_exec_reloc@basic-write-read-active.html
* igt@gem_exec_schedule@semaphore-power:
- shard-rkl: NOTRUN -> [SKIP][35] ([i915#7276])
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-rkl-1/igt@gem_exec_schedule@semaphore-power.html
* igt@gem_fenced_exec_thrash@no-spare-fences-busy:
- shard-dg1: NOTRUN -> [SKIP][36] ([i915#4860]) +1 other test skip
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-dg1-16/igt@gem_fenced_exec_thrash@no-spare-fences-busy.html
* igt@gem_fenced_exec_thrash@no-spare-fences-busy-interruptible:
- shard-mtlp: NOTRUN -> [SKIP][37] ([i915#4860])
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-mtlp-3/igt@gem_fenced_exec_thrash@no-spare-fences-busy-interruptible.html
* igt@gem_huc_copy@huc-copy:
- shard-rkl: NOTRUN -> [SKIP][38] ([i915#2190])
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-rkl-5/igt@gem_huc_copy@huc-copy.html
- shard-glk: NOTRUN -> [SKIP][39] ([i915#2190])
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-glk2/igt@gem_huc_copy@huc-copy.html
* igt@gem_lmem_swapping@heavy-random@lmem0:
- shard-dg1: NOTRUN -> [FAIL][40] ([i915#10378])
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-dg1-16/igt@gem_lmem_swapping@heavy-random@lmem0.html
* igt@gem_lmem_swapping@heavy-verify-multi-ccs@lmem0:
- shard-dg2: NOTRUN -> [FAIL][41] ([i915#10446])
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-dg2-8/igt@gem_lmem_swapping@heavy-verify-multi-ccs@lmem0.html
* igt@gem_lmem_swapping@heavy-verify-random:
- shard-mtlp: NOTRUN -> [SKIP][42] ([i915#4613]) +1 other test skip
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-mtlp-3/igt@gem_lmem_swapping@heavy-verify-random.html
* igt@gem_lmem_swapping@heavy-verify-random@lmem0:
- shard-dg2: [PASS][43] -> [FAIL][44] ([i915#10378])
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14663/shard-dg2-11/igt@gem_lmem_swapping@heavy-verify-random@lmem0.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-dg2-4/igt@gem_lmem_swapping@heavy-verify-random@lmem0.html
* igt@gem_lmem_swapping@parallel-random-engines:
- shard-rkl: NOTRUN -> [SKIP][45] ([i915#4613]) +3 other tests skip
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-rkl-4/igt@gem_lmem_swapping@parallel-random-engines.html
* igt@gem_lmem_swapping@verify-ccs:
- shard-glk: NOTRUN -> [SKIP][46] ([i915#4613]) +5 other tests skip
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-glk2/igt@gem_lmem_swapping@verify-ccs.html
* igt@gem_media_vme:
- shard-dg2: NOTRUN -> [SKIP][47] ([i915#284])
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-dg2-8/igt@gem_media_vme.html
- shard-rkl: NOTRUN -> [SKIP][48] ([i915#284])
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-rkl-1/igt@gem_media_vme.html
* igt@gem_mmap@bad-object:
- shard-dg1: NOTRUN -> [SKIP][49] ([i915#4083]) +2 other tests skip
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-dg1-16/igt@gem_mmap@bad-object.html
* igt@gem_mmap_gtt@basic-read-write-distinct:
- shard-mtlp: NOTRUN -> [SKIP][50] ([i915#4077]) +4 other tests skip
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-mtlp-3/igt@gem_mmap_gtt@basic-read-write-distinct.html
* igt@gem_mmap_gtt@cpuset-big-copy-odd:
- shard-dg2: NOTRUN -> [SKIP][51] ([i915#4077])
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-dg2-8/igt@gem_mmap_gtt@cpuset-big-copy-odd.html
* igt@gem_mmap_wc@read-write:
- shard-mtlp: NOTRUN -> [SKIP][52] ([i915#4083]) +2 other tests skip
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-mtlp-3/igt@gem_mmap_wc@read-write.html
* igt@gem_mmap_wc@write-cpu-read-wc-unflushed:
- shard-dg2: NOTRUN -> [SKIP][53] ([i915#4083])
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-dg2-8/igt@gem_mmap_wc@write-cpu-read-wc-unflushed.html
* igt@gem_partial_pwrite_pread@write-snoop:
- shard-dg1: NOTRUN -> [SKIP][54] ([i915#3282])
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-dg1-18/igt@gem_partial_pwrite_pread@write-snoop.html
* igt@gem_pread@exhaustion:
- shard-glk: NOTRUN -> [WARN][55] ([i915#2658])
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-glk4/igt@gem_pread@exhaustion.html
* igt@gem_pread@snoop:
- shard-dg2: NOTRUN -> [SKIP][56] ([i915#3282]) +1 other test skip
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-dg2-8/igt@gem_pread@snoop.html
- shard-rkl: NOTRUN -> [SKIP][57] ([i915#3282]) +8 other tests skip
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-rkl-1/igt@gem_pread@snoop.html
* igt@gem_pwrite_snooped:
- shard-mtlp: NOTRUN -> [SKIP][58] ([i915#3282]) +1 other test skip
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-mtlp-3/igt@gem_pwrite_snooped.html
* igt@gem_pxp@create-valid-protected-context:
- shard-mtlp: NOTRUN -> [SKIP][59] ([i915#4270])
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-mtlp-3/igt@gem_pxp@create-valid-protected-context.html
* igt@gem_pxp@display-protected-crc:
- shard-dg2: NOTRUN -> [SKIP][60] ([i915#4270])
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-dg2-8/igt@gem_pxp@display-protected-crc.html
- shard-rkl: NOTRUN -> [SKIP][61] ([i915#4270]) +6 other tests skip
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-rkl-1/igt@gem_pxp@display-protected-crc.html
* igt@gem_pxp@dmabuf-shared-protected-dst-is-context-refcounted:
- shard-dg1: NOTRUN -> [SKIP][62] ([i915#4270]) +1 other test skip
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-dg1-18/igt@gem_pxp@dmabuf-shared-protected-dst-is-context-refcounted.html
* igt@gem_pxp@verify-pxp-stale-ctx-execution:
- shard-tglu: NOTRUN -> [SKIP][63] ([i915#4270]) +1 other test skip
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-tglu-6/igt@gem_pxp@verify-pxp-stale-ctx-execution.html
* igt@gem_render_copy@y-tiled-to-vebox-y-tiled:
- shard-dg2: NOTRUN -> [SKIP][64] ([i915#5190] / [i915#8428])
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-dg2-8/igt@gem_render_copy@y-tiled-to-vebox-y-tiled.html
* igt@gem_render_copy@yf-tiled-ccs-to-x-tiled:
- shard-mtlp: NOTRUN -> [SKIP][65] ([i915#8428]) +1 other test skip
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-mtlp-3/igt@gem_render_copy@yf-tiled-ccs-to-x-tiled.html
* igt@gem_render_tiled_blits@basic:
- shard-dg2: NOTRUN -> [SKIP][66] ([i915#4079])
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-dg2-8/igt@gem_render_tiled_blits@basic.html
* igt@gem_set_tiling_vs_blt@tiled-to-tiled:
- shard-rkl: NOTRUN -> [SKIP][67] ([i915#8411]) +2 other tests skip
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-rkl-1/igt@gem_set_tiling_vs_blt@tiled-to-tiled.html
* igt@gem_tiled_partial_pwrite_pread@writes-after-reads:
- shard-dg1: NOTRUN -> [SKIP][68] ([i915#4077]) +9 other tests skip
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-dg1-16/igt@gem_tiled_partial_pwrite_pread@writes-after-reads.html
* igt@gem_unfence_active_buffers:
- shard-mtlp: NOTRUN -> [SKIP][69] ([i915#4879])
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-mtlp-3/igt@gem_unfence_active_buffers.html
* igt@gem_userptr_blits@create-destroy-unsync:
- shard-rkl: NOTRUN -> [SKIP][70] ([i915#3297]) +2 other tests skip
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-rkl-5/igt@gem_userptr_blits@create-destroy-unsync.html
- shard-dg1: NOTRUN -> [SKIP][71] ([i915#3297])
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-dg1-16/igt@gem_userptr_blits@create-destroy-unsync.html
* igt@gem_userptr_blits@unsync-unmap-after-close:
- shard-tglu: NOTRUN -> [SKIP][72] ([i915#3297]) +1 other test skip
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-tglu-6/igt@gem_userptr_blits@unsync-unmap-after-close.html
* igt@gen9_exec_parse@bb-chained:
- shard-rkl: NOTRUN -> [SKIP][73] ([i915#2527]) +4 other tests skip
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-rkl-1/igt@gen9_exec_parse@bb-chained.html
- shard-dg2: NOTRUN -> [SKIP][74] ([i915#2856])
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-dg2-8/igt@gen9_exec_parse@bb-chained.html
* igt@gen9_exec_parse@bb-large:
- shard-tglu: NOTRUN -> [SKIP][75] ([i915#2527] / [i915#2856])
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-tglu-6/igt@gen9_exec_parse@bb-large.html
* igt@gen9_exec_parse@secure-batches:
- shard-dg1: NOTRUN -> [SKIP][76] ([i915#2527])
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-dg1-18/igt@gen9_exec_parse@secure-batches.html
* igt@i915_module_load@reload-with-fault-injection:
- shard-mtlp: [PASS][77] -> [ABORT][78] ([i915#10131] / [i915#9820])
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14663/shard-mtlp-3/igt@i915_module_load@reload-with-fault-injection.html
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-mtlp-6/igt@i915_module_load@reload-with-fault-injection.html
* igt@i915_pm_freq_api@freq-reset-multiple:
- shard-rkl: NOTRUN -> [SKIP][79] ([i915#8399])
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-rkl-5/igt@i915_pm_freq_api@freq-reset-multiple.html
* igt@i915_pm_rc6_residency@rc6-idle@gt0-vcs0:
- shard-dg1: [PASS][80] -> [FAIL][81] ([i915#3591]) +2 other tests fail
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14663/shard-dg1-13/igt@i915_pm_rc6_residency@rc6-idle@gt0-vcs0.html
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-dg1-14/igt@i915_pm_rc6_residency@rc6-idle@gt0-vcs0.html
* igt@i915_pm_rpm@system-suspend-devices:
- shard-snb: NOTRUN -> [SKIP][82] +69 other tests skip
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-snb7/igt@i915_pm_rpm@system-suspend-devices.html
* igt@i915_pm_rps@thresholds-idle@gt0:
- shard-mtlp: NOTRUN -> [SKIP][83] ([i915#8925])
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-mtlp-3/igt@i915_pm_rps@thresholds-idle@gt0.html
* igt@i915_pm_rps@thresholds-idle@gt1:
- shard-mtlp: NOTRUN -> [SKIP][84] ([i915#3555] / [i915#8925])
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-mtlp-3/igt@i915_pm_rps@thresholds-idle@gt1.html
* igt@i915_power@sanity:
- shard-rkl: NOTRUN -> [SKIP][85] ([i915#7984])
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-rkl-1/igt@i915_power@sanity.html
* igt@i915_selftest@live@execlists:
- shard-dg1: NOTRUN -> [INCOMPLETE][86] ([i915#10461])
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-dg1-18/igt@i915_selftest@live@execlists.html
* igt@i915_selftest@mock@memory_region:
- shard-snb: NOTRUN -> [DMESG-WARN][87] ([i915#9311])
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-snb7/igt@i915_selftest@mock@memory_region.html
- shard-tglu: NOTRUN -> [DMESG-WARN][88] ([i915#9311])
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-tglu-6/igt@i915_selftest@mock@memory_region.html
* igt@intel_hwmon@hwmon-read:
- shard-rkl: NOTRUN -> [SKIP][89] ([i915#7707])
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-rkl-1/igt@intel_hwmon@hwmon-read.html
* igt@kms_addfb_basic@addfb25-x-tiled-legacy:
- shard-dg1: NOTRUN -> [SKIP][90] ([i915#4212])
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-dg1-16/igt@kms_addfb_basic@addfb25-x-tiled-legacy.html
* igt@kms_async_flips@async-flip-with-page-flip-events@pipe-a-hdmi-a-1-y-rc-ccs-cc:
- shard-rkl: NOTRUN -> [SKIP][91] ([i915#8709]) +3 other tests skip
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-rkl-4/igt@kms_async_flips@async-flip-with-page-flip-events@pipe-a-hdmi-a-1-y-rc-ccs-cc.html
* igt@kms_async_flips@async-flip-with-page-flip-events@pipe-c-hdmi-a-1-4-mc-ccs:
- shard-dg2: NOTRUN -> [SKIP][92] ([i915#8709]) +11 other tests skip
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-dg2-10/igt@kms_async_flips@async-flip-with-page-flip-events@pipe-c-hdmi-a-1-4-mc-ccs.html
* igt@kms_async_flips@invalid-async-flip:
- shard-mtlp: NOTRUN -> [SKIP][93] ([i915#6228])
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-mtlp-3/igt@kms_async_flips@invalid-async-flip.html
* igt@kms_atomic_transition@plane-all-modeset-transition-internal-panels:
- shard-rkl: NOTRUN -> [SKIP][94] ([i915#1769] / [i915#3555])
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-rkl-1/igt@kms_atomic_transition@plane-all-modeset-transition-internal-panels.html
* igt@kms_big_fb@4-tiled-addfb:
- shard-rkl: NOTRUN -> [SKIP][95] ([i915#5286]) +8 other tests skip
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-rkl-3/igt@kms_big_fb@4-tiled-addfb.html
* igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180:
- shard-tglu: NOTRUN -> [SKIP][96] ([i915#5286])
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-tglu-6/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180.html
* igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-async-flip:
- shard-dg1: NOTRUN -> [SKIP][97] ([i915#4538] / [i915#5286]) +2 other tests skip
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-dg1-16/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-async-flip.html
* igt@kms_big_fb@linear-32bpp-rotate-90:
- shard-dg1: NOTRUN -> [SKIP][98] ([i915#3638])
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-dg1-18/igt@kms_big_fb@linear-32bpp-rotate-90.html
* igt@kms_big_fb@linear-64bpp-rotate-270:
- shard-mtlp: NOTRUN -> [SKIP][99] +3 other tests skip
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-mtlp-3/igt@kms_big_fb@linear-64bpp-rotate-270.html
* igt@kms_big_fb@linear-8bpp-rotate-270:
- shard-rkl: NOTRUN -> [SKIP][100] ([i915#3638]) +3 other tests skip
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-rkl-4/igt@kms_big_fb@linear-8bpp-rotate-270.html
* igt@kms_big_fb@y-tiled-8bpp-rotate-0:
- shard-dg2: NOTRUN -> [SKIP][101] ([i915#4538] / [i915#5190]) +1 other test skip
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-dg2-8/igt@kms_big_fb@y-tiled-8bpp-rotate-0.html
* igt@kms_big_fb@y-tiled-addfb-size-offset-overflow:
- shard-mtlp: NOTRUN -> [SKIP][102] ([i915#6187])
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-mtlp-3/igt@kms_big_fb@y-tiled-addfb-size-offset-overflow.html
* igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180-async-flip:
- shard-dg1: NOTRUN -> [SKIP][103] ([i915#4538]) +2 other tests skip
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-dg1-16/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180-async-flip.html
* igt@kms_ccs@bad-aux-stride-y-tiled-gen12-rc-ccs@pipe-d-hdmi-a-1:
- shard-dg2: NOTRUN -> [SKIP][104] ([i915#10307] / [i915#10434] / [i915#6095]) +6 other tests skip
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-dg2-8/igt@kms_ccs@bad-aux-stride-y-tiled-gen12-rc-ccs@pipe-d-hdmi-a-1.html
* igt@kms_ccs@bad-rotation-90-4-tiled-mtl-mc-ccs@pipe-b-hdmi-a-3:
- shard-dg1: NOTRUN -> [SKIP][105] ([i915#6095]) +83 other tests skip
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-dg1-13/igt@kms_ccs@bad-rotation-90-4-tiled-mtl-mc-ccs@pipe-b-hdmi-a-3.html
* igt@kms_ccs@bad-rotation-90-4-tiled-xe2-ccs:
- shard-rkl: NOTRUN -> [SKIP][106] ([i915#10278]) +1 other test skip
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-rkl-3/igt@kms_ccs@bad-rotation-90-4-tiled-xe2-ccs.html
* igt@kms_ccs@ccs-on-another-bo-4-tiled-mtl-rc-ccs-cc@pipe-d-hdmi-a-1:
- shard-tglu: NOTRUN -> [SKIP][107] ([i915#6095]) +15 other tests skip
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-tglu-6/igt@kms_ccs@ccs-on-another-bo-4-tiled-mtl-rc-ccs-cc@pipe-d-hdmi-a-1.html
* igt@kms_ccs@crc-primary-rotation-180-4-tiled-dg2-mc-ccs@pipe-b-hdmi-a-1:
- shard-rkl: NOTRUN -> [SKIP][108] ([i915#6095]) +81 other tests skip
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-rkl-5/igt@kms_ccs@crc-primary-rotation-180-4-tiled-dg2-mc-ccs@pipe-b-hdmi-a-1.html
* igt@kms_ccs@crc-primary-rotation-180-4-tiled-dg2-rc-ccs-cc@pipe-a-edp-1:
- shard-mtlp: NOTRUN -> [SKIP][109] ([i915#6095]) +11 other tests skip
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-mtlp-3/igt@kms_ccs@crc-primary-rotation-180-4-tiled-dg2-rc-ccs-cc@pipe-a-edp-1.html
* igt@kms_ccs@crc-primary-rotation-180-4-tiled-xe2-ccs:
- shard-dg1: NOTRUN -> [SKIP][110] ([i915#10278])
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-dg1-16/igt@kms_ccs@crc-primary-rotation-180-4-tiled-xe2-ccs.html
* igt@kms_ccs@crc-sprite-planes-basic-4-tiled-mtl-mc-ccs@pipe-a-hdmi-a-3:
- shard-dg2: NOTRUN -> [SKIP][111] ([i915#10307] / [i915#6095]) +180 other tests skip
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-dg2-5/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-mtl-mc-ccs@pipe-a-hdmi-a-3.html
* igt@kms_ccs@random-ccs-data-y-tiled-gen12-rc-ccs-cc@pipe-c-hdmi-a-2:
- shard-glk: NOTRUN -> [SKIP][112] +310 other tests skip
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-glk2/igt@kms_ccs@random-ccs-data-y-tiled-gen12-rc-ccs-cc@pipe-c-hdmi-a-2.html
* igt@kms_chamelium_audio@dp-audio-edid:
- shard-dg1: NOTRUN -> [SKIP][113] ([i915#7828]) +5 other tests skip
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-dg1-15/igt@kms_chamelium_audio@dp-audio-edid.html
* igt@kms_chamelium_edid@dp-edid-stress-resolution-4k:
- shard-tglu: NOTRUN -> [SKIP][114] ([i915#7828]) +1 other test skip
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-tglu-6/igt@kms_chamelium_edid@dp-edid-stress-resolution-4k.html
* igt@kms_chamelium_frames@hdmi-crc-single:
- shard-rkl: NOTRUN -> [SKIP][115] ([i915#7828]) +11 other tests skip
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-rkl-3/igt@kms_chamelium_frames@hdmi-crc-single.html
* igt@kms_chamelium_frames@hdmi-frame-dump:
- shard-mtlp: NOTRUN -> [SKIP][116] ([i915#7828]) +1 other test skip
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-mtlp-3/igt@kms_chamelium_frames@hdmi-frame-dump.html
* igt@kms_chamelium_hpd@dp-hpd-fast:
- shard-dg2: NOTRUN -> [SKIP][117] ([i915#7828]) +1 other test skip
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-dg2-8/igt@kms_chamelium_hpd@dp-hpd-fast.html
* igt@kms_content_protection@lic-type-1:
- shard-tglu: NOTRUN -> [SKIP][118] ([i915#6944] / [i915#9424])
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-tglu-6/igt@kms_content_protection@lic-type-1.html
* igt@kms_content_protection@type1:
- shard-tglu: NOTRUN -> [SKIP][119] ([i915#6944] / [i915#7116] / [i915#7118] / [i915#9424])
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-tglu-6/igt@kms_content_protection@type1.html
* igt@kms_cursor_crc@cursor-onscreen-512x512:
- shard-tglu: NOTRUN -> [SKIP][120] ([i915#3359])
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-tglu-6/igt@kms_cursor_crc@cursor-onscreen-512x512.html
* igt@kms_cursor_crc@cursor-onscreen-max-size:
- shard-mtlp: NOTRUN -> [SKIP][121] ([i915#3555] / [i915#8814])
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-mtlp-3/igt@kms_cursor_crc@cursor-onscreen-max-size.html
* igt@kms_cursor_crc@cursor-random-512x170:
- shard-rkl: NOTRUN -> [SKIP][122] ([i915#3359]) +2 other tests skip
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-rkl-5/igt@kms_cursor_crc@cursor-random-512x170.html
- shard-dg1: NOTRUN -> [SKIP][123] ([i915#3359])
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-dg1-16/igt@kms_cursor_crc@cursor-random-512x170.html
* igt@kms_cursor_crc@cursor-rapid-movement-max-size:
- shard-tglu: NOTRUN -> [SKIP][124] ([i915#3555]) +4 other tests skip
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-tglu-6/igt@kms_cursor_crc@cursor-rapid-movement-max-size.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- shard-tglu: NOTRUN -> [SKIP][125] ([i915#4103])
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-tglu-6/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-varying-size:
- shard-rkl: NOTRUN -> [SKIP][126] ([i915#4103]) +1 other test skip
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-rkl-5/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-varying-size.html
- shard-dg1: NOTRUN -> [SKIP][127] ([i915#4103] / [i915#4213])
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-dg1-16/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-varying-size.html
* igt@kms_cursor_legacy@cursora-vs-flipb-varying-size:
- shard-mtlp: NOTRUN -> [SKIP][128] ([i915#9809])
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-mtlp-3/igt@kms_cursor_legacy@cursora-vs-flipb-varying-size.html
* igt@kms_display_modes@mst-extended-mode-negative:
- shard-rkl: NOTRUN -> [SKIP][129] ([i915#8588])
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-rkl-3/igt@kms_display_modes@mst-extended-mode-negative.html
* igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-1:
- shard-rkl: NOTRUN -> [SKIP][130] ([i915#3804])
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-rkl-4/igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-1.html
* igt@kms_dsc@dsc-with-bpc:
- shard-rkl: NOTRUN -> [SKIP][131] ([i915#3555] / [i915#3840])
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-rkl-1/igt@kms_dsc@dsc-with-bpc.html
* igt@kms_feature_discovery@chamelium:
- shard-mtlp: NOTRUN -> [SKIP][132] ([i915#4854])
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-mtlp-3/igt@kms_feature_discovery@chamelium.html
* igt@kms_feature_discovery@dp-mst:
- shard-tglu: NOTRUN -> [SKIP][133] ([i915#9337])
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-tglu-4/igt@kms_feature_discovery@dp-mst.html
* igt@kms_fence_pin_leak:
- shard-dg1: NOTRUN -> [SKIP][134] ([i915#4881])
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-dg1-16/igt@kms_fence_pin_leak.html
* igt@kms_flip@2x-flip-vs-dpms-off-vs-modeset-interruptible:
- shard-tglu: NOTRUN -> [SKIP][135] ([i915#3637] / [i915#3966])
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-tglu-6/igt@kms_flip@2x-flip-vs-dpms-off-vs-modeset-interruptible.html
* igt@kms_flip@2x-flip-vs-expired-vblank:
- shard-tglu: NOTRUN -> [SKIP][136] ([i915#3637])
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-tglu-4/igt@kms_flip@2x-flip-vs-expired-vblank.html
* igt@kms_flip@2x-flip-vs-expired-vblank@ab-hdmi-a1-hdmi-a2:
- shard-glk: NOTRUN -> [FAIL][137] ([i915#79])
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-glk2/igt@kms_flip@2x-flip-vs-expired-vblank@ab-hdmi-a1-hdmi-a2.html
* igt@kms_flip@2x-flip-vs-panning-interruptible:
- shard-dg2: NOTRUN -> [SKIP][138] +5 other tests skip
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-dg2-8/igt@kms_flip@2x-flip-vs-panning-interruptible.html
* igt@kms_flip@2x-flip-vs-rmfb:
- shard-mtlp: NOTRUN -> [SKIP][139] ([i915#3637]) +2 other tests skip
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-mtlp-3/igt@kms_flip@2x-flip-vs-rmfb.html
* igt@kms_flip@2x-modeset-vs-vblank-race:
- shard-dg1: NOTRUN -> [SKIP][140] ([i915#9934]) +1 other test skip
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-dg1-18/igt@kms_flip@2x-modeset-vs-vblank-race.html
* igt@kms_flip@2x-plain-flip:
- shard-rkl: NOTRUN -> [SKIP][141] +58 other tests skip
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-rkl-4/igt@kms_flip@2x-plain-flip.html
* igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling@pipe-a-default-mode:
- shard-mtlp: NOTRUN -> [SKIP][142] ([i915#2672])
[142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-mtlp-3/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling@pipe-a-default-mode.html
* igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-32bpp-yftileccs-downscaling@pipe-a-valid-mode:
- shard-tglu: NOTRUN -> [SKIP][143] ([i915#2587] / [i915#2672])
[143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-tglu-6/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-32bpp-yftileccs-downscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-downscaling@pipe-a-valid-mode:
- shard-dg2: NOTRUN -> [SKIP][144] ([i915#2672])
[144]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-dg2-8/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-downscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling@pipe-a-valid-mode:
- shard-dg1: NOTRUN -> [SKIP][145] ([i915#2587] / [i915#2672])
[145]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-dg1-16/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling@pipe-a-valid-mode:
- shard-rkl: NOTRUN -> [SKIP][146] ([i915#2672]) +4 other tests skip
[146]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-rkl-4/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling@pipe-a-valid-mode.html
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-mmap-wc:
- shard-rkl: NOTRUN -> [SKIP][147] ([i915#1825]) +44 other tests skip
[147]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-rkl-5/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-mmap-wc.html
- shard-dg1: NOTRUN -> [SKIP][148] ([i915#8708]) +10 other tests skip
[148]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-dg1-16/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-shrfb-pgflip-blt:
- shard-snb: [PASS][149] -> [SKIP][150] +5 other tests skip
[149]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14663/shard-snb7/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-shrfb-pgflip-blt.html
[150]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-snb6/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-shrfb-pgflip-blt.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-indfb-draw-pwrite:
- shard-dg1: NOTRUN -> [SKIP][151] +19 other tests skip
[151]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-dg1-16/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-indfb-draw-pwrite.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-shrfb-msflip-blt:
- shard-mtlp: NOTRUN -> [SKIP][152] ([i915#1825]) +5 other tests skip
[152]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-mtlp-3/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-shrfb-msflip-blt.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-shrfb-plflip-blt:
- shard-dg2: NOTRUN -> [SKIP][153] ([i915#5354]) +7 other tests skip
[153]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-dg2-8/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-shrfb-plflip-blt.html
* igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-render:
- shard-dg1: NOTRUN -> [SKIP][154] ([i915#3458]) +9 other tests skip
[154]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-dg1-16/igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-render.html
* igt@kms_frontbuffer_tracking@fbcpsr-tiling-y:
- shard-dg2: NOTRUN -> [SKIP][155] ([i915#10055])
[155]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-dg2-8/igt@kms_frontbuffer_tracking@fbcpsr-tiling-y.html
* igt@kms_frontbuffer_tracking@pipe-fbc-rte:
- shard-rkl: NOTRUN -> [SKIP][156] ([i915#9766])
[156]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-rkl-5/igt@kms_frontbuffer_tracking@pipe-fbc-rte.html
- shard-dg1: NOTRUN -> [SKIP][157] ([i915#9766])
[157]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-dg1-16/igt@kms_frontbuffer_tracking@pipe-fbc-rte.html
* igt@kms_frontbuffer_tracking@plane-fbc-rte:
- shard-rkl: NOTRUN -> [SKIP][158] ([i915#10070])
[158]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-rkl-3/igt@kms_frontbuffer_tracking@plane-fbc-rte.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-plflip-blt:
- shard-rkl: NOTRUN -> [SKIP][159] ([i915#3023]) +33 other tests skip
[159]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-rkl-4/igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-plflip-blt.html
* igt@kms_frontbuffer_tracking@psr-1p-rte:
- shard-dg2: NOTRUN -> [SKIP][160] ([i915#3458]) +3 other tests skip
[160]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-dg2-8/igt@kms_frontbuffer_tracking@psr-1p-rte.html
* igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-shrfb-draw-mmap-gtt:
- shard-dg2: NOTRUN -> [SKIP][161] ([i915#8708]) +5 other tests skip
[161]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-dg2-8/igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-shrfb-draw-mmap-gtt.html
* igt@kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-draw-render:
- shard-tglu: NOTRUN -> [SKIP][162] +26 other tests skip
[162]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-tglu-4/igt@kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-draw-render.html
* igt@kms_hdr@bpc-switch:
- shard-tglu: NOTRUN -> [SKIP][163] ([i915#3555] / [i915#8228])
[163]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-tglu-6/igt@kms_hdr@bpc-switch.html
* igt@kms_hdr@invalid-metadata-sizes:
- shard-dg2: NOTRUN -> [SKIP][164] ([i915#3555] / [i915#8228])
[164]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-dg2-2/igt@kms_hdr@invalid-metadata-sizes.html
- shard-rkl: NOTRUN -> [SKIP][165] ([i915#3555] / [i915#8228]) +1 other test skip
[165]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-rkl-1/igt@kms_hdr@invalid-metadata-sizes.html
* igt@kms_multipipe_modeset@basic-max-pipe-crc-check:
- shard-dg1: NOTRUN -> [SKIP][166] ([i915#1839]) +1 other test skip
[166]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-dg1-18/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html
* igt@kms_plane_multiple@tiling-yf:
- shard-rkl: NOTRUN -> [SKIP][167] ([i915#3555]) +7 other tests skip
[167]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-rkl-5/igt@kms_plane_multiple@tiling-yf.html
* igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-2:
- shard-rkl: NOTRUN -> [FAIL][168] ([i915#8292])
[168]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-rkl-1/igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-2.html
* igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-3:
- shard-dg1: NOTRUN -> [FAIL][169] ([i915#8292])
[169]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-dg1-13/igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-3.html
* igt@kms_plane_scaling@plane-downscale-factor-0-25-with-pixel-format@pipe-a-dp-4:
- shard-dg2: NOTRUN -> [SKIP][170] ([i915#9423]) +3 other tests skip
[170]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-dg2-11/igt@kms_plane_scaling@plane-downscale-factor-0-25-with-pixel-format@pipe-a-dp-4.html
* igt@kms_plane_scaling@plane-downscale-factor-0-5-with-rotation@pipe-a-hdmi-a-4:
- shard-dg1: NOTRUN -> [SKIP][171] ([i915#9423]) +7 other tests skip
[171]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-dg1-14/igt@kms_plane_scaling@plane-downscale-factor-0-5-with-rotation@pipe-a-hdmi-a-4.html
* igt@kms_plane_scaling@plane-downscale-factor-0-75-with-rotation@pipe-d-hdmi-a-1:
- shard-tglu: NOTRUN -> [SKIP][172] ([i915#9423]) +3 other tests skip
[172]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-tglu-6/igt@kms_plane_scaling@plane-downscale-factor-0-75-with-rotation@pipe-d-hdmi-a-1.html
* igt@kms_plane_scaling@plane-scaler-unity-scaling-with-rotation@pipe-a-hdmi-a-2:
- shard-rkl: NOTRUN -> [SKIP][173] ([i915#9423]) +7 other tests skip
[173]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-rkl-3/igt@kms_plane_scaling@plane-scaler-unity-scaling-with-rotation@pipe-a-hdmi-a-2.html
* igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-factor-0-25@pipe-b-hdmi-a-2:
- shard-rkl: NOTRUN -> [SKIP][174] ([i915#5235]) +5 other tests skip
[174]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-rkl-3/igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-factor-0-25@pipe-b-hdmi-a-2.html
* igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-factor-0-25@pipe-d-dp-4:
- shard-dg2: NOTRUN -> [SKIP][175] ([i915#5235] / [i915#9423]) +19 other tests skip
[175]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-dg2-11/igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-factor-0-25@pipe-d-dp-4.html
* igt@kms_plane_scaling@planes-downscale-factor-0-25@pipe-c-hdmi-a-3:
- shard-dg1: NOTRUN -> [SKIP][176] ([i915#5235]) +7 other tests skip
[176]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-dg1-13/igt@kms_plane_scaling@planes-downscale-factor-0-25@pipe-c-hdmi-a-3.html
* igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25@pipe-a-hdmi-a-1:
- shard-tglu: NOTRUN -> [SKIP][177] ([i915#5235]) +3 other tests skip
[177]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-tglu-6/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25@pipe-a-hdmi-a-1.html
* igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-75@pipe-a-edp-1:
- shard-mtlp: NOTRUN -> [SKIP][178] ([i915#5235]) +2 other tests skip
[178]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-mtlp-3/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-75@pipe-a-edp-1.html
* igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-75@pipe-d-edp-1:
- shard-mtlp: NOTRUN -> [SKIP][179] ([i915#3555] / [i915#5235])
[179]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-mtlp-3/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-75@pipe-d-edp-1.html
* igt@kms_pm_backlight@bad-brightness:
- shard-rkl: NOTRUN -> [SKIP][180] ([i915#5354]) +1 other test skip
[180]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-rkl-1/igt@kms_pm_backlight@bad-brightness.html
* igt@kms_pm_backlight@fade-with-suspend:
- shard-tglu: NOTRUN -> [SKIP][181] ([i915#9812])
[181]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-tglu-6/igt@kms_pm_backlight@fade-with-suspend.html
* igt@kms_pm_dc@dc6-psr:
- shard-dg1: NOTRUN -> [SKIP][182] ([i915#9685])
[182]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-dg1-16/igt@kms_pm_dc@dc6-psr.html
* igt@kms_pm_lpsp@screens-disabled:
- shard-rkl: NOTRUN -> [SKIP][183] ([i915#8430])
[183]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-rkl-1/igt@kms_pm_lpsp@screens-disabled.html
- shard-dg2: NOTRUN -> [SKIP][184] ([i915#8430])
[184]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-dg2-8/igt@kms_pm_lpsp@screens-disabled.html
* igt@kms_pm_rpm@modeset-lpsp-stress:
- shard-dg2: [PASS][185] -> [SKIP][186] ([i915#9519]) +1 other test skip
[185]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14663/shard-dg2-4/igt@kms_pm_rpm@modeset-lpsp-stress.html
[186]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-dg2-6/igt@kms_pm_rpm@modeset-lpsp-stress.html
* igt@kms_psr2_su@page_flip-p010:
- shard-rkl: NOTRUN -> [SKIP][187] ([i915#9683])
[187]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-rkl-5/igt@kms_psr2_su@page_flip-p010.html
- shard-dg1: NOTRUN -> [SKIP][188] ([i915#9683])
[188]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-dg1-16/igt@kms_psr2_su@page_flip-p010.html
* igt@kms_psr@fbc-pr-dpms:
- shard-mtlp: NOTRUN -> [SKIP][189] ([i915#9688]) +2 other tests skip
[189]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-mtlp-3/igt@kms_psr@fbc-pr-dpms.html
* igt@kms_psr@fbc-psr-cursor-blt:
- shard-dg2: NOTRUN -> [SKIP][190] ([i915#1072] / [i915#9732]) +4 other tests skip
[190]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-dg2-8/igt@kms_psr@fbc-psr-cursor-blt.html
* igt@kms_psr@fbc-psr2-cursor-mmap-cpu:
- shard-tglu: NOTRUN -> [SKIP][191] ([i915#9732]) +6 other tests skip
[191]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-tglu-4/igt@kms_psr@fbc-psr2-cursor-mmap-cpu.html
* igt@kms_psr@fbc-psr2-sprite-render:
- shard-rkl: NOTRUN -> [SKIP][192] ([i915#1072] / [i915#9732]) +26 other tests skip
[192]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-rkl-5/igt@kms_psr@fbc-psr2-sprite-render.html
* igt@kms_psr@psr-cursor-plane-onoff:
- shard-dg1: NOTRUN -> [SKIP][193] ([i915#1072] / [i915#9732]) +9 other tests skip
[193]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-dg1-18/igt@kms_psr@psr-cursor-plane-onoff.html
* igt@kms_psr@psr2-sprite-mmap-gtt@edp-1:
- shard-mtlp: NOTRUN -> [SKIP][194] ([i915#4077] / [i915#9688])
[194]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-mtlp-3/igt@kms_psr@psr2-sprite-mmap-gtt@edp-1.html
* igt@kms_psr_stress_test@flip-primary-invalidate-overlay:
- shard-rkl: NOTRUN -> [SKIP][195] ([i915#9685]) +1 other test skip
[195]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-rkl-1/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html
* igt@kms_rotation_crc@primary-yf-tiled-reflect-x-270:
- shard-rkl: NOTRUN -> [SKIP][196] ([i915#5289]) +2 other tests skip
[196]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-rkl-5/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-270.html
- shard-dg1: NOTRUN -> [SKIP][197] ([i915#5289]) +1 other test skip
[197]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-dg1-16/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-270.html
* igt@kms_setmode@basic-clone-single-crtc:
- shard-dg2: NOTRUN -> [SKIP][198] ([i915#3555]) +1 other test skip
[198]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-dg2-8/igt@kms_setmode@basic-clone-single-crtc.html
* igt@kms_setmode@clone-exclusive-crtc:
- shard-dg1: NOTRUN -> [SKIP][199] ([i915#3555]) +2 other tests skip
[199]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-dg1-18/igt@kms_setmode@clone-exclusive-crtc.html
* igt@kms_universal_plane@cursor-fb-leak@pipe-b-hdmi-a-1:
- shard-rkl: NOTRUN -> [FAIL][200] ([i915#9196])
[200]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-rkl-4/igt@kms_universal_plane@cursor-fb-leak@pipe-b-hdmi-a-1.html
* igt@kms_vrr@flip-suspend:
- shard-mtlp: NOTRUN -> [SKIP][201] ([i915#3555] / [i915#8808])
[201]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-mtlp-3/igt@kms_vrr@flip-suspend.html
* igt@kms_writeback@writeback-fb-id-xrgb2101010:
- shard-dg2: NOTRUN -> [SKIP][202] ([i915#2437] / [i915#9412])
[202]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-dg2-8/igt@kms_writeback@writeback-fb-id-xrgb2101010.html
- shard-rkl: NOTRUN -> [SKIP][203] ([i915#2437] / [i915#9412])
[203]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-rkl-1/igt@kms_writeback@writeback-fb-id-xrgb2101010.html
* igt@perf@per-context-mode-unprivileged:
- shard-rkl: NOTRUN -> [SKIP][204] ([i915#2435])
[204]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-rkl-5/igt@perf@per-context-mode-unprivileged.html
- shard-dg1: NOTRUN -> [SKIP][205] ([i915#2433])
[205]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-dg1-16/igt@perf@per-context-mode-unprivileged.html
* igt@perf_pmu@cpu-hotplug:
- shard-tglu: NOTRUN -> [SKIP][206] ([i915#8850])
[206]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-tglu-6/igt@perf_pmu@cpu-hotplug.html
* igt@prime_vgem@fence-flip-hang:
- shard-dg1: NOTRUN -> [SKIP][207] ([i915#3708])
[207]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-dg1-18/igt@prime_vgem@fence-flip-hang.html
* igt@prime_vgem@fence-read-hang:
- shard-rkl: NOTRUN -> [SKIP][208] ([i915#3708])
[208]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-rkl-3/igt@prime_vgem@fence-read-hang.html
* igt@runner@aborted:
- shard-glk: NOTRUN -> [FAIL][209] ([i915#10291])
[209]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-glk1/igt@runner@aborted.html
* igt@sriov_basic@bind-unbind-vf:
- shard-rkl: NOTRUN -> [SKIP][210] ([i915#9917]) +1 other test skip
[210]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-rkl-4/igt@sriov_basic@bind-unbind-vf.html
* igt@v3d/v3d_perfmon@destroy-invalid-perfmon:
- shard-mtlp: NOTRUN -> [SKIP][211] ([i915#2575]) +2 other tests skip
[211]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-mtlp-3/igt@v3d/v3d_perfmon@destroy-invalid-perfmon.html
* igt@v3d/v3d_submit_cl@multisync-out-syncs:
- shard-dg2: NOTRUN -> [SKIP][212] ([i915#2575]) +2 other tests skip
[212]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-dg2-8/igt@v3d/v3d_submit_cl@multisync-out-syncs.html
* igt@v3d/v3d_submit_cl@valid-submission:
- shard-tglu: NOTRUN -> [SKIP][213] ([i915#2575]) +5 other tests skip
[213]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-tglu-6/igt@v3d/v3d_submit_cl@valid-submission.html
* igt@v3d/v3d_wait_bo@used-bo-1ns:
- shard-dg1: NOTRUN -> [SKIP][214] ([i915#2575]) +5 other tests skip
[214]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-dg1-16/igt@v3d/v3d_wait_bo@used-bo-1ns.html
* igt@vc4/vc4_perfmon@create-single-perfmon:
- shard-mtlp: NOTRUN -> [SKIP][215] ([i915#7711]) +1 other test skip
[215]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-mtlp-3/igt@vc4/vc4_perfmon@create-single-perfmon.html
* igt@vc4/vc4_perfmon@create-two-perfmon:
- shard-rkl: NOTRUN -> [SKIP][216] ([i915#7711]) +9 other tests skip
[216]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-rkl-4/igt@vc4/vc4_perfmon@create-two-perfmon.html
* igt@vc4/vc4_wait_bo@bad-bo:
- shard-dg1: NOTRUN -> [SKIP][217] ([i915#7711]) +3 other tests skip
[217]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-dg1-16/igt@vc4/vc4_wait_bo@bad-bo.html
* igt@vc4/vc4_wait_bo@used-bo-0ns:
- shard-dg2: NOTRUN -> [SKIP][218] ([i915#7711]) +1 other test skip
[218]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-dg2-8/igt@vc4/vc4_wait_bo@used-bo-0ns.html
#### Possible fixes ####
* igt@gem_ctx_exec@basic-nohangcheck:
- shard-rkl: [FAIL][219] ([i915#6268]) -> [PASS][220]
[219]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14663/shard-rkl-6/igt@gem_ctx_exec@basic-nohangcheck.html
[220]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-rkl-3/igt@gem_ctx_exec@basic-nohangcheck.html
* igt@gem_eio@hibernate:
- shard-tglu: [ABORT][221] ([i915#10030] / [i915#7975] / [i915#8213]) -> [PASS][222]
[221]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14663/shard-tglu-10/igt@gem_eio@hibernate.html
[222]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-tglu-4/igt@gem_eio@hibernate.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-rkl: [FAIL][223] ([i915#2842]) -> [PASS][224]
[223]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14663/shard-rkl-3/igt@gem_exec_fair@basic-pace-share@rcs0.html
[224]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-rkl-5/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_lmem_swapping@heavy-verify-multi@lmem0:
- shard-dg1: [FAIL][225] ([i915#10378]) -> [PASS][226]
[225]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14663/shard-dg1-16/igt@gem_lmem_swapping@heavy-verify-multi@lmem0.html
[226]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-dg1-17/igt@gem_lmem_swapping@heavy-verify-multi@lmem0.html
* igt@gem_lmem_swapping@smem-oom@lmem0:
- shard-dg2: [TIMEOUT][227] ([i915#5493]) -> [PASS][228]
[227]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14663/shard-dg2-1/igt@gem_lmem_swapping@smem-oom@lmem0.html
[228]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-dg2-2/igt@gem_lmem_swapping@smem-oom@lmem0.html
* igt@i915_module_load@reload-with-fault-injection:
- shard-snb: [INCOMPLETE][229] ([i915#9849]) -> [PASS][230]
[229]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14663/shard-snb2/igt@i915_module_load@reload-with-fault-injection.html
[230]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-snb7/igt@i915_module_load@reload-with-fault-injection.html
- shard-tglu: [INCOMPLETE][231] ([i915#10047] / [i915#10887] / [i915#9820]) -> [PASS][232]
[231]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14663/shard-tglu-4/igt@i915_module_load@reload-with-fault-injection.html
[232]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-tglu-6/igt@i915_module_load@reload-with-fault-injection.html
* igt@i915_pm_rc6_residency@rc6-idle@gt0-rcs0:
- shard-dg1: [FAIL][233] ([i915#3591]) -> [PASS][234]
[233]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14663/shard-dg1-13/igt@i915_pm_rc6_residency@rc6-idle@gt0-rcs0.html
[234]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-dg1-14/igt@i915_pm_rc6_residency@rc6-idle@gt0-rcs0.html
* igt@i915_selftest@live@hangcheck:
- shard-dg1: [INCOMPLETE][235] ([i915#10461]) -> [PASS][236]
[235]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14663/shard-dg1-13/igt@i915_selftest@live@hangcheck.html
[236]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-dg1-18/igt@i915_selftest@live@hangcheck.html
* igt@kms_cursor_legacy@torture-move@pipe-a:
- shard-tglu: [DMESG-WARN][237] ([i915#10166] / [i915#1982]) -> [PASS][238]
[237]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14663/shard-tglu-10/igt@kms_cursor_legacy@torture-move@pipe-a.html
[238]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-tglu-4/igt@kms_cursor_legacy@torture-move@pipe-a.html
* igt@kms_fbcon_fbt@fbc-suspend:
- shard-mtlp: [FAIL][239] ([i915#4767]) -> [PASS][240]
[239]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14663/shard-mtlp-1/igt@kms_fbcon_fbt@fbc-suspend.html
[240]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-mtlp-8/igt@kms_fbcon_fbt@fbc-suspend.html
* igt@kms_flip@2x-blocking-wf_vblank@ab-vga1-hdmi-a1:
- shard-snb: [FAIL][241] ([i915#2122]) -> [PASS][242]
[241]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14663/shard-snb7/igt@kms_flip@2x-blocking-wf_vblank@ab-vga1-hdmi-a1.html
[242]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-snb6/igt@kms_flip@2x-blocking-wf_vblank@ab-vga1-hdmi-a1.html
* igt@kms_flip@flip-vs-blocking-wf-vblank@a-hdmi-a4:
- shard-dg1: [FAIL][243] ([i915#2122]) -> [PASS][244]
[243]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14663/shard-dg1-18/igt@kms_flip@flip-vs-blocking-wf-vblank@a-hdmi-a4.html
[244]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-dg1-16/igt@kms_flip@flip-vs-blocking-wf-vblank@a-hdmi-a4.html
* igt@kms_pm_rpm@dpms-lpsp:
- shard-dg2: [SKIP][245] ([i915#9519]) -> [PASS][246]
[245]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14663/shard-dg2-11/igt@kms_pm_rpm@dpms-lpsp.html
[246]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-dg2-4/igt@kms_pm_rpm@dpms-lpsp.html
* igt@kms_pm_rpm@dpms-mode-unset-non-lpsp:
- shard-rkl: [SKIP][247] ([i915#9519]) -> [PASS][248] +2 other tests pass
[247]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14663/shard-rkl-4/igt@kms_pm_rpm@dpms-mode-unset-non-lpsp.html
[248]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-rkl-3/igt@kms_pm_rpm@dpms-mode-unset-non-lpsp.html
* igt@kms_sysfs_edid_timing:
- shard-dg2: [FAIL][249] ([IGT#2]) -> [PASS][250]
[249]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14663/shard-dg2-4/igt@kms_sysfs_edid_timing.html
[250]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-dg2-11/igt@kms_sysfs_edid_timing.html
* igt@kms_universal_plane@cursor-fb-leak@pipe-b-edp-1:
- shard-mtlp: [FAIL][251] ([i915#9196]) -> [PASS][252]
[251]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14663/shard-mtlp-2/igt@kms_universal_plane@cursor-fb-leak@pipe-b-edp-1.html
[252]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-mtlp-4/igt@kms_universal_plane@cursor-fb-leak@pipe-b-edp-1.html
* igt@kms_universal_plane@cursor-fb-leak@pipe-b-hdmi-a-4:
- shard-dg1: [FAIL][253] ([i915#9196]) -> [PASS][254]
[253]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14663/shard-dg1-18/igt@kms_universal_plane@cursor-fb-leak@pipe-b-hdmi-a-4.html
[254]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-dg1-16/igt@kms_universal_plane@cursor-fb-leak@pipe-b-hdmi-a-4.html
* igt@kms_universal_plane@cursor-fb-leak@pipe-c-hdmi-a-1:
- shard-tglu: [FAIL][255] ([i915#9196]) -> [PASS][256]
[255]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14663/shard-tglu-8/igt@kms_universal_plane@cursor-fb-leak@pipe-c-hdmi-a-1.html
[256]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-tglu-3/igt@kms_universal_plane@cursor-fb-leak@pipe-c-hdmi-a-1.html
#### Warnings ####
* igt@gem_create@create-ext-cpu-access-big:
- shard-dg2: [ABORT][257] ([i915#9846]) -> [INCOMPLETE][258] ([i915#9364])
[257]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14663/shard-dg2-3/igt@gem_create@create-ext-cpu-access-big.html
[258]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-dg2-10/igt@gem_create@create-ext-cpu-access-big.html
* igt@kms_content_protection@mei-interface:
- shard-dg1: [SKIP][259] ([i915#9424]) -> [SKIP][260] ([i915#9433])
[259]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14663/shard-dg1-15/igt@kms_content_protection@mei-interface.html
[260]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-dg1-13/igt@kms_content_protection@mei-interface.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-shrfb-plflip-blt:
- shard-dg2: [SKIP][261] ([i915#3458]) -> [SKIP][262] ([i915#10433] / [i915#3458]) +3 other tests skip
[261]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14663/shard-dg2-3/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-shrfb-plflip-blt.html
[262]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-dg2-4/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-shrfb-plflip-blt.html
* igt@kms_frontbuffer_tracking@psr-rgb565-draw-mmap-cpu:
- shard-dg2: [SKIP][263] ([i915#10433] / [i915#3458]) -> [SKIP][264] ([i915#3458]) +3 other tests skip
[263]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14663/shard-dg2-4/igt@kms_frontbuffer_tracking@psr-rgb565-draw-mmap-cpu.html
[264]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-dg2-6/igt@kms_frontbuffer_tracking@psr-rgb565-draw-mmap-cpu.html
* igt@kms_multipipe_modeset@basic-max-pipe-crc-check:
- shard-rkl: [SKIP][265] ([i915#4816]) -> [SKIP][266] ([i915#4070] / [i915#4816])
[265]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14663/shard-rkl-4/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html
[266]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-rkl-5/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html
* igt@kms_pm_dc@dc6-dpms:
- shard-rkl: [SKIP][267] ([i915#3361]) -> [FAIL][268] ([i915#9295])
[267]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14663/shard-rkl-6/igt@kms_pm_dc@dc6-dpms.html
[268]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-rkl-5/igt@kms_pm_dc@dc6-dpms.html
* igt@kms_psr@fbc-psr-cursor-plane-move:
- shard-dg2: [SKIP][269] ([i915#1072] / [i915#9732]) -> [SKIP][270] ([i915#1072] / [i915#9673] / [i915#9732]) +14 other tests skip
[269]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14663/shard-dg2-4/igt@kms_psr@fbc-psr-cursor-plane-move.html
[270]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-dg2-11/igt@kms_psr@fbc-psr-cursor-plane-move.html
* igt@kms_psr@psr2-cursor-blt:
- shard-dg2: [SKIP][271] ([i915#1072] / [i915#9673] / [i915#9732]) -> [SKIP][272] ([i915#1072] / [i915#9732]) +12 other tests skip
[271]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14663/shard-dg2-11/igt@kms_psr@psr2-cursor-blt.html
[272]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-dg2-5/igt@kms_psr@psr2-cursor-blt.html
* igt@prime_mmap@test_aperture_limit@test_aperture_limit-smem:
- shard-dg2: [INCOMPLETE][273] ([i915#5493]) -> [CRASH][274] ([i915#9351])
[273]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14663/shard-dg2-4/igt@prime_mmap@test_aperture_limit@test_aperture_limit-smem.html
[274]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/shard-dg2-6/igt@prime_mmap@test_aperture_limit@test_aperture_limit-smem.html
[IGT#2]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/2
[i915#10030]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10030
[i915#10047]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10047
[i915#10055]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10055
[i915#10070]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10070
[i915#10131]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10131
[i915#10166]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10166
[i915#10278]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10278
[i915#10291]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10291
[i915#10307]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10307
[i915#10378]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10378
[i915#10433]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10433
[i915#10434]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10434
[i915#10446]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10446
[i915#10461]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10461
[i915#10513]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10513
[i915#1072]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1072
[i915#10887]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10887
[i915#1769]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1769
[i915#1825]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1825
[i915#1839]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1839
[i915#1982]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1982
[i915#2122]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2122
[i915#2190]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2190
[i915#2433]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2433
[i915#2435]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2435
[i915#2437]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2437
[i915#2527]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2527
[i915#2575]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2575
[i915#2587]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2587
[i915#2658]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2658
[i915#2672]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2672
[i915#280]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/280
[i915#284]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/284
[i915#2842]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2842
[i915#2856]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2856
[i915#3023]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3023
[i915#3281]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3281
[i915#3282]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3282
[i915#3297]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3297
[i915#3359]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3359
[i915#3361]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3361
[i915#3458]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3458
[i915#3539]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3539
[i915#3555]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3555
[i915#3591]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3591
[i915#3637]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3637
[i915#3638]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3638
[i915#3708]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3708
[i915#3804]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3804
[i915#3840]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3840
[i915#3966]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3966
[i915#4070]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4070
[i915#4077]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4077
[i915#4079]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4079
[i915#4083]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4083
[i915#4103]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4103
[i915#4212]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4212
[i915#4213]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4213
[i915#4270]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4270
[i915#4525]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4525
[i915#4538]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4538
[i915#4613]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4613
[i915#4767]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4767
[i915#4812]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4812
[i915#4816]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4816
[i915#4852]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4852
[i915#4854]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4854
[i915#4860]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4860
[i915#4879]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4879
[i915#4881]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4881
[i915#5190]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5190
[i915#5235]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5235
[i915#5286]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5286
[i915#5289]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5289
[i915#5354]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5354
[i915#5493]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5493
[i915#5784]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5784
[i915#6095]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6095
[i915#6187]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6187
[i915#6228]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6228
[i915#6230]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6230
[i915#6268]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6268
[i915#6334]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6334
[i915#6335]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6335
[i915#6344]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6344
[i915#6944]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6944
[i915#7116]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7116
[i915#7118]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7118
[i915#7276]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7276
[i915#7697]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7697
[i915#7701]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7701
[i915#7707]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7707
[i915#7711]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7711
[i915#7742]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7742
[i915#7828]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7828
[i915#79]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/79
[i915#7975]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7975
[i915#7984]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7984
[i915#8213]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8213
[i915#8228]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8228
[i915#8292]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8292
[i915#8399]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8399
[i915#8411]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8411
[i915#8414]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8414
[i915#8428]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8428
[i915#8430]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8430
[i915#8555]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8555
[i915#8562]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8562
[i915#8588]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8588
[i915#8708]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8708
[i915#8709]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8709
[i915#8808]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8808
[i915#8814]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8814
[i915#8850]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8850
[i915#8925]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8925
[i915#9196]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9196
[i915#9295]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9295
[i915#9311]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9311
[i915#9323]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9323
[i915#9337]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9337
[i915#9351]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9351
[i915#9364]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9364
[i915#9412]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9412
[i915#9423]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9423
[i915#9424]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9424
[i915#9433]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9433
[i915#9519]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9519
[i915#9606]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9606
[i915#9673]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9673
[i915#9683]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9683
[i915#9685]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9685
[i915#9688]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9688
[i915#9732]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9732
[i915#9766]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9766
[i915#9809]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9809
[i915#9812]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9812
[i915#9820]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9820
[i915#9846]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9846
[i915#9849]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9849
[i915#9917]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9917
[i915#9934]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9934
Build changes
-------------
* Linux: CI_DRM_14663 -> Patchwork_132381v2
CI-20190529: 20190529
CI_DRM_14663: 47c509a8d4944e6276f7b956061c2020323f0a90 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7825: 28b2a1b0be86e33a2fc04a022e04f07bd25b66d9 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_132381v2: 47c509a8d4944e6276f7b956061c2020323f0a90 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v2/index.html
[-- Attachment #2: Type: text/html, Size: 93689 bytes --]
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v2 3/4] drm/i915/display: split out intel_fbc_regs.h from i915_reg.h
2024-04-26 15:03 ` Ville Syrjälä
@ 2024-04-29 10:16 ` Jani Nikula
0 siblings, 0 replies; 10+ messages in thread
From: Jani Nikula @ 2024-04-29 10:16 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
On Fri, 26 Apr 2024, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> On Fri, Apr 26, 2024 at 01:51:36PM +0300, Jani Nikula wrote:
>> Clean up i915_reg.h.
>>
>> v2: Drop chicken regs and comments (Ville)
>>
>> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>
> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Thanks, pushed the lot to din.
BR,
Jani.
--
Jani Nikula, Intel
^ permalink raw reply [flat|nested] 10+ messages in thread
end of thread, other threads:[~2024-04-29 10:16 UTC | newest]
Thread overview: 10+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2024-04-26 10:51 [PATCH v2 0/4] drm/i915: i915_reg.h cleanups Jani Nikula
2024-04-26 10:51 ` [PATCH v2 1/4] drm/i915/audio: move LPE audio regs to intel_audio_regs.h Jani Nikula
2024-04-26 10:51 ` [PATCH v2 2/4] drm/i915/color: move palette registers to intel_color_regs.h Jani Nikula
2024-04-26 10:51 ` [PATCH v2 3/4] drm/i915/display: split out intel_fbc_regs.h from i915_reg.h Jani Nikula
2024-04-26 15:03 ` Ville Syrjälä
2024-04-29 10:16 ` Jani Nikula
2024-04-26 10:51 ` [PATCH v2 4/4] drm/i915/display: split out intel_sprite_regs.h " Jani Nikula
2024-04-26 11:31 ` ✗ Fi.CI.SPARSE: warning for drm/i915: i915_reg.h cleanups (rev2) Patchwork
2024-04-26 11:38 ` ✓ Fi.CI.BAT: success " Patchwork
2024-04-26 17:15 ` ✓ Fi.CI.IGT: " Patchwork
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