* [PATCH 000/123] drm/i915: remove implicit dev_priv local variable use
@ 2024-04-26 13:01 Jani Nikula
2024-04-26 13:01 ` [PATCH 001/123] drm/i915: pass dev_priv explicitly to DPLL Jani Nikula
` (17 more replies)
0 siblings, 18 replies; 21+ messages in thread
From: Jani Nikula @ 2024-04-26 13:01 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: jani.nikula
Hey all, it's time to stop using the implicit dev_priv local variable in
register macros. Yes, this is huge. It's also (almost) completely
scripted.
Thoughts?
BR,
Jani.
Here's the script:
#!/bin/bash
set -e
# Find all the registers implicitly relying on dev_priv
REGS=$(git grep -h "#define.*dev_priv" -- drivers/gpu/drm/i915/i915_reg.h |\
grep -v '#define[ \t]\+[a-zA-Z0-9_]\+(dev_priv' |\
sed 's/#define[ \t]\+\([a-zA-Z0-9_]\+\).*/\1/')
for reg in $REGS; do
echo $reg
FILES=$(git grep -wl $reg -- drivers/gpu/drm/i915)
cocci=$(mktemp)
cat >$cocci <<EOF
@@
identifier reg =~ "^$reg\$";
@@
<...
(
reg(
+ dev_priv,
...)
|
- reg
+ reg(dev_priv)
)
...>
EOF
# already function-like macros
sed -i "s/\(#define *${reg}(\)/\1dev_priv, /" $FILES
# new function-like macros
sed -i "s/\(#define *${reg}\)\([ \t]\)/\1(dev_priv)\2/" $FILES
spatch --sp-file $cocci --in-place --linux-spacing $FILES >/dev/null
rm -f $cocci
git commit -as -F - <<EOF
drm/i915: pass dev_priv explicitly to $reg
Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the $reg register macro.
EOF
done
Jani Nikula (123):
drm/i915: pass dev_priv explicitly to DPLL
drm/i915: pass dev_priv explicitly to DPLL_MD
drm/i915: pass dev_priv explicitly to PALETTE
drm/i915: pass dev_priv explicitly to PIPE_CRC_CTL
drm/i915: pass dev_priv explicitly to PIPE_CRC_RES_1_IVB
drm/i915: pass dev_priv explicitly to PIPE_CRC_RES_2_IVB
drm/i915: pass dev_priv explicitly to PIPE_CRC_RES_3_IVB
drm/i915: pass dev_priv explicitly to PIPE_CRC_RES_4_IVB
drm/i915: pass dev_priv explicitly to PIPE_CRC_RES_5_IVB
drm/i915: pass dev_priv explicitly to PIPE_CRC_RES_RED
drm/i915: pass dev_priv explicitly to PIPE_CRC_RES_GREEN
drm/i915: pass dev_priv explicitly to PIPE_CRC_RES_BLUE
drm/i915: pass dev_priv explicitly to PIPE_CRC_RES_RES1_I915
drm/i915: pass dev_priv explicitly to PIPE_CRC_RES_RES2_G4X
drm/i915: pass dev_priv explicitly to TRANS_HTOTAL
drm/i915: pass dev_priv explicitly to TRANS_HBLANK
drm/i915: pass dev_priv explicitly to TRANS_HSYNC
drm/i915: pass dev_priv explicitly to TRANS_VTOTAL
drm/i915: pass dev_priv explicitly to TRANS_VBLANK
drm/i915: pass dev_priv explicitly to TRANS_VSYNC
drm/i915: pass dev_priv explicitly to BCLRPAT
drm/i915: pass dev_priv explicitly to TRANS_VSYNCSHIFT
drm/i915: pass dev_priv explicitly to PIPESRC
drm/i915: pass dev_priv explicitly to TRANS_MULT
drm/i915: pass dev_priv explicitly to TRANS_VRR_CTL
drm/i915: pass dev_priv explicitly to TRANS_VRR_VMAX
drm/i915: pass dev_priv explicitly to TRANS_VRR_VMIN
drm/i915: pass dev_priv explicitly to TRANS_VRR_VMAXSHIFT
drm/i915: pass dev_priv explicitly to TRANS_VRR_STATUS
drm/i915: pass dev_priv explicitly to TRANS_VRR_VTOTAL_PREV
drm/i915: pass dev_priv explicitly to TRANS_VRR_FLIPLINE
drm/i915: pass dev_priv explicitly to TRANS_VRR_STATUS2
drm/i915: pass dev_priv explicitly to TRANS_PUSH
drm/i915: pass dev_priv explicitly to TRANS_VRR_VSYNC
drm/i915: pass dev_priv explicitly to PORT_HOTPLUG_EN
drm/i915: pass dev_priv explicitly to PORT_HOTPLUG_STAT
drm/i915: pass dev_priv explicitly to PORT_DFT2_G4X
drm/i915: pass dev_priv explicitly to PFIT_CONTROL
drm/i915: pass dev_priv explicitly to PFIT_PGM_RATIOS
drm/i915: pass dev_priv explicitly to PFIT_AUTO_RATIOS
drm/i915: pass dev_priv explicitly to TRANSCONF
drm/i915: pass dev_priv explicitly to PIPEDSL
drm/i915: pass dev_priv explicitly to PIPEFRAME
drm/i915: pass dev_priv explicitly to PIPEFRAMEPIXEL
drm/i915: pass dev_priv explicitly to PIPESTAT
drm/i915: pass dev_priv explicitly to PIPEGCMAX
drm/i915: pass dev_priv explicitly to PIPE_ARB_CTL
drm/i915: pass dev_priv explicitly to ICL_PIPESTATUS
drm/i915: pass dev_priv explicitly to DSPARB
drm/i915: pass dev_priv explicitly to DSPFW1
drm/i915: pass dev_priv explicitly to DSPFW2
drm/i915: pass dev_priv explicitly to DSPFW3
drm/i915: pass dev_priv explicitly to PIPE_FRMCOUNT_G4X
drm/i915: pass dev_priv explicitly to PIPE_FLIPCOUNT_G4X
drm/i915: pass dev_priv explicitly to CURCNTR
drm/i915: pass dev_priv explicitly to CURBASE
drm/i915: pass dev_priv explicitly to CURPOS
drm/i915: pass dev_priv explicitly to CURPOS_ERLY_TPT
drm/i915: pass dev_priv explicitly to CURSIZE
drm/i915: pass dev_priv explicitly to CUR_FBC_CTL
drm/i915: pass dev_priv explicitly to CUR_CHICKEN
drm/i915: pass dev_priv explicitly to CURSURFLIVE
drm/i915: pass dev_priv explicitly to DSPADDR_VLV
drm/i915: pass dev_priv explicitly to DSPCNTR
drm/i915: pass dev_priv explicitly to DSPADDR
drm/i915: pass dev_priv explicitly to DSPSTRIDE
drm/i915: pass dev_priv explicitly to DSPPOS
drm/i915: pass dev_priv explicitly to DSPSIZE
drm/i915: pass dev_priv explicitly to DSPSURF
drm/i915: pass dev_priv explicitly to DSPTILEOFF
drm/i915: pass dev_priv explicitly to DSPOFFSET
drm/i915: pass dev_priv explicitly to DSPSURFLIVE
drm/i915: pass dev_priv explicitly to DSPGAMC
drm/i915: pass dev_priv explicitly to CHV_BLEND
drm/i915: pass dev_priv explicitly to CHV_CANVAS
drm/i915: pass dev_priv explicitly to PRIMPOS
drm/i915: pass dev_priv explicitly to PRIMSIZE
drm/i915: pass dev_priv explicitly to PRIMCNSTALPHA
drm/i915: pass dev_priv explicitly to SWF0
drm/i915: pass dev_priv explicitly to SWF1
drm/i915: pass dev_priv explicitly to SWF3
drm/i915: pass dev_priv explicitly to _PIPEBDSL
drm/i915: pass dev_priv explicitly to _TRANSBCONF
drm/i915: pass dev_priv explicitly to _PIPEBSTAT
drm/i915: pass dev_priv explicitly to _PIPEB_FRMCOUNT_G4X
drm/i915: pass dev_priv explicitly to _PIPEB_FLIPCOUNT_G4X
drm/i915: pass dev_priv explicitly to _DSPBCNTR
drm/i915: pass dev_priv explicitly to _DSPBADDR
drm/i915: pass dev_priv explicitly to _DSPBSTRIDE
drm/i915: pass dev_priv explicitly to _DSPBPOS
drm/i915: pass dev_priv explicitly to _DSPBSIZE
drm/i915: pass dev_priv explicitly to _DSPBSURF
drm/i915: pass dev_priv explicitly to _DSPBTILEOFF
drm/i915: pass dev_priv explicitly to _DSPBOFFSET
drm/i915: pass dev_priv explicitly to _DSPBSURFLIVE
drm/i915: pass dev_priv explicitly to PIPE_DATA_M1
drm/i915: pass dev_priv explicitly to PIPE_DATA_N1
drm/i915: pass dev_priv explicitly to PIPE_DATA_M2
drm/i915: pass dev_priv explicitly to PIPE_DATA_N2
drm/i915: pass dev_priv explicitly to PIPE_LINK_M1
drm/i915: pass dev_priv explicitly to PIPE_LINK_N1
drm/i915: pass dev_priv explicitly to PIPE_LINK_M2
drm/i915: pass dev_priv explicitly to PIPE_LINK_N2
drm/i915: pass dev_priv explicitly to HSW_TVIDEO_DIP_CTL
drm/i915: pass dev_priv explicitly to HSW_TVIDEO_DIP_GCP
drm/i915: pass dev_priv explicitly to HSW_TVIDEO_DIP_AVI_DATA
drm/i915: pass dev_priv explicitly to HSW_TVIDEO_DIP_VS_DATA
drm/i915: pass dev_priv explicitly to HSW_TVIDEO_DIP_SPD_DATA
drm/i915: pass dev_priv explicitly to HSW_TVIDEO_DIP_GMP_DATA
drm/i915: pass dev_priv explicitly to HSW_TVIDEO_DIP_VSC_DATA
drm/i915: pass dev_priv explicitly to GLK_TVIDEO_DIP_DRM_DATA
drm/i915: pass dev_priv explicitly to ICL_VIDEO_DIP_PPS_DATA
drm/i915: pass dev_priv explicitly to ICL_VIDEO_DIP_PPS_ECC
drm/i915: pass dev_priv explicitly to ADL_TVIDEO_DIP_AS_SDP_DATA
drm/i915: pass dev_priv explicitly to HSW_STEREO_3D_CTL
drm/i915: pass dev_priv explicitly to TRANS_DDI_FUNC_CTL
drm/i915: pass dev_priv explicitly to TRANS_DDI_FUNC_CTL2
drm/i915: pass dev_priv explicitly to TGL_DP_TP_CTL
drm/i915: pass dev_priv explicitly to TGL_DP_TP_STATUS
drm/i915: pass dev_priv explicitly to TRANS_MSA_MISC
drm/i915: pass dev_priv explicitly to TRANS_SET_CONTEXT_LATENCY
drm/i915: pass dev_priv explicitly to MTL_CLKGATE_DIS_TRANS
drm/i915: pass dev_priv explicitly to DSPLINOFF
drivers/gpu/drm/i915/display/g4x_dp.c | 2 +-
drivers/gpu/drm/i915/display/i9xx_plane.c | 62 ++--
drivers/gpu/drm/i915/display/i9xx_wm.c | 87 +++---
drivers/gpu/drm/i915/display/icl_dsi.c | 46 +--
drivers/gpu/drm/i915/display/intel_color.c | 44 +--
drivers/gpu/drm/i915/display/intel_crt.c | 50 ++--
drivers/gpu/drm/i915/display/intel_cursor.c | 33 ++-
drivers/gpu/drm/i915/display/intel_ddi.c | 47 ++--
drivers/gpu/drm/i915/display/intel_display.c | 203 ++++++++------
.../drm/i915/display/intel_display_debugfs.c | 2 +-
.../gpu/drm/i915/display/intel_display_irq.c | 41 +--
.../drm/i915/display/intel_display_power.c | 2 +-
.../i915/display/intel_display_power_well.c | 14 +-
drivers/gpu/drm/i915/display/intel_dp.c | 3 +-
drivers/gpu/drm/i915/display/intel_dp_mst.c | 5 +-
drivers/gpu/drm/i915/display/intel_dpll.c | 63 +++--
drivers/gpu/drm/i915/display/intel_drrs.c | 2 +-
drivers/gpu/drm/i915/display/intel_dvo.c | 5 +-
drivers/gpu/drm/i915/display/intel_fbc.c | 8 +-
drivers/gpu/drm/i915/display/intel_fdi.c | 15 +-
.../drm/i915/display/intel_fifo_underrun.c | 13 +-
drivers/gpu/drm/i915/display/intel_hdmi.c | 32 ++-
.../gpu/drm/i915/display/intel_hotplug_irq.c | 12 +-
drivers/gpu/drm/i915/display/intel_lspcon.c | 2 +-
drivers/gpu/drm/i915/display/intel_lvds.c | 2 +-
drivers/gpu/drm/i915/display/intel_overlay.c | 10 +-
.../gpu/drm/i915/display/intel_pch_display.c | 21 +-
drivers/gpu/drm/i915/display/intel_pipe_crc.c | 20 +-
drivers/gpu/drm/i915/display/intel_pps.c | 2 +-
drivers/gpu/drm/i915/display/intel_psr.c | 18 +-
drivers/gpu/drm/i915/display/intel_vblank.c | 14 +-
drivers/gpu/drm/i915/display/intel_vrr.c | 52 ++--
drivers/gpu/drm/i915/display/vlv_dsi.c | 3 +-
drivers/gpu/drm/i915/gvt/cmd_parser.c | 14 +-
drivers/gpu/drm/i915/gvt/display.c | 71 ++---
drivers/gpu/drm/i915/gvt/fb_decoder.c | 20 +-
drivers/gpu/drm/i915/gvt/handlers.c | 40 +--
drivers/gpu/drm/i915/i915_irq.c | 5 +-
drivers/gpu/drm/i915/i915_reg.h | 246 ++++++++--------
drivers/gpu/drm/i915/i915_suspend.c | 48 ++--
drivers/gpu/drm/i915/intel_clock_gating.c | 9 +-
drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 264 +++++++++---------
42 files changed, 906 insertions(+), 746 deletions(-)
--
2.39.2
^ permalink raw reply [flat|nested] 21+ messages in thread
* [PATCH 001/123] drm/i915: pass dev_priv explicitly to DPLL
2024-04-26 13:01 [PATCH 000/123] drm/i915: remove implicit dev_priv local variable use Jani Nikula
@ 2024-04-26 13:01 ` Jani Nikula
2024-04-26 13:01 ` [PATCH 002/123] drm/i915: pass dev_priv explicitly to DPLL_MD Jani Nikula
` (16 subsequent siblings)
17 siblings, 0 replies; 21+ messages in thread
From: Jani Nikula @ 2024-04-26 13:01 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: jani.nikula
Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the DPLL register macro.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 21 ++++-----
.../drm/i915/display/intel_display_power.c | 2 +-
.../i915/display/intel_display_power_well.c | 6 +--
drivers/gpu/drm/i915/display/intel_dpll.c | 45 ++++++++++---------
drivers/gpu/drm/i915/display/intel_dvo.c | 5 ++-
drivers/gpu/drm/i915/display/intel_pps.c | 2 +-
drivers/gpu/drm/i915/i915_reg.h | 2 +-
7 files changed, 43 insertions(+), 40 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index f45e5f02096d..5b6025e2f621 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -376,11 +376,11 @@ void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
fallthrough;
case PORT_B:
port_mask = DPLL_PORTB_READY_MASK;
- dpll_reg = DPLL(0);
+ dpll_reg = DPLL(dev_priv, 0);
break;
case PORT_C:
port_mask = DPLL_PORTC_READY_MASK;
- dpll_reg = DPLL(0);
+ dpll_reg = DPLL(dev_priv, 0);
expected_mask <<= 4;
break;
case PORT_D:
@@ -8185,11 +8185,12 @@ void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
* the P1/P2 dividers. Otherwise the DPLL will keep using the old
* dividers, even though the register value does change.
*/
- intel_de_write(dev_priv, DPLL(pipe), dpll & ~DPLL_VGA_MODE_DIS);
- intel_de_write(dev_priv, DPLL(pipe), dpll);
+ intel_de_write(dev_priv, DPLL(dev_priv, pipe),
+ dpll & ~DPLL_VGA_MODE_DIS);
+ intel_de_write(dev_priv, DPLL(dev_priv, pipe), dpll);
/* Wait for the clocks to stabilize. */
- intel_de_posting_read(dev_priv, DPLL(pipe));
+ intel_de_posting_read(dev_priv, DPLL(dev_priv, pipe));
udelay(150);
/* The pixel multiplier can only be updated once the
@@ -8197,12 +8198,12 @@ void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
*
* So write it again.
*/
- intel_de_write(dev_priv, DPLL(pipe), dpll);
+ intel_de_write(dev_priv, DPLL(dev_priv, pipe), dpll);
/* We do this three times for luck */
for (i = 0; i < 3 ; i++) {
- intel_de_write(dev_priv, DPLL(pipe), dpll);
- intel_de_posting_read(dev_priv, DPLL(pipe));
+ intel_de_write(dev_priv, DPLL(dev_priv, pipe), dpll);
+ intel_de_posting_read(dev_priv, DPLL(dev_priv, pipe));
udelay(150); /* wait for warmup */
}
@@ -8235,8 +8236,8 @@ void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
intel_wait_for_pipe_scanline_stopped(crtc);
- intel_de_write(dev_priv, DPLL(pipe), DPLL_VGA_MODE_DIS);
- intel_de_posting_read(dev_priv, DPLL(pipe));
+ intel_de_write(dev_priv, DPLL(dev_priv, pipe), DPLL_VGA_MODE_DIS);
+ intel_de_posting_read(dev_priv, DPLL(dev_priv, pipe));
}
void intel_hpd_poll_fini(struct drm_i915_private *i915)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 03dc7edcc443..354083128efb 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -1768,7 +1768,7 @@ static void chv_phy_control_init(struct drm_i915_private *dev_priv)
* current lane status.
*/
if (intel_power_well_is_enabled(dev_priv, cmn_bc)) {
- u32 status = intel_de_read(dev_priv, DPLL(PIPE_A));
+ u32 status = intel_de_read(dev_priv, DPLL(dev_priv, PIPE_A));
unsigned int mask;
mask = status & DPLL_PORTB_READY_MASK;
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
index e8a6e53fd551..77b586f9e931 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
@@ -1195,13 +1195,13 @@ static void vlv_display_power_well_init(struct drm_i915_private *dev_priv)
* CHV DPLL B/C have some issues if VGA mode is enabled.
*/
for_each_pipe(dev_priv, pipe) {
- u32 val = intel_de_read(dev_priv, DPLL(pipe));
+ u32 val = intel_de_read(dev_priv, DPLL(dev_priv, pipe));
val |= DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
if (pipe != PIPE_A)
val |= DPLL_INTEGRATED_CRI_CLK_VLV;
- intel_de_write(dev_priv, DPLL(pipe), val);
+ intel_de_write(dev_priv, DPLL(dev_priv, pipe), val);
}
vlv_init_display_clock_gating(dev_priv);
@@ -1354,7 +1354,7 @@ static void assert_chv_phy_status(struct drm_i915_private *dev_priv)
*/
if (BITS_SET(phy_control,
PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1)) &&
- (intel_de_read(dev_priv, DPLL(PIPE_B)) & DPLL_VCO_ENABLE) == 0)
+ (intel_de_read(dev_priv, DPLL(dev_priv, PIPE_B)) & DPLL_VCO_ENABLE) == 0)
phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH1);
if (BITS_SET(phy_control,
diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c
index 49274d632716..ccd299e31e95 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll.c
@@ -402,7 +402,7 @@ void i9xx_dpll_get_hw_state(struct intel_crtc *crtc,
hw_state->dpll_md = tmp;
}
- hw_state->dpll = intel_de_read(dev_priv, DPLL(crtc->pipe));
+ hw_state->dpll = intel_de_read(dev_priv, DPLL(dev_priv, crtc->pipe));
if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
hw_state->fp0 = intel_de_read(dev_priv, FP0(crtc->pipe));
@@ -1840,11 +1840,12 @@ void i9xx_enable_pll(const struct intel_crtc_state *crtc_state)
* the P1/P2 dividers. Otherwise the DPLL will keep using the old
* dividers, even though the register value does change.
*/
- intel_de_write(dev_priv, DPLL(pipe), hw_state->dpll & ~DPLL_VGA_MODE_DIS);
- intel_de_write(dev_priv, DPLL(pipe), hw_state->dpll);
+ intel_de_write(dev_priv, DPLL(dev_priv, pipe),
+ hw_state->dpll & ~DPLL_VGA_MODE_DIS);
+ intel_de_write(dev_priv, DPLL(dev_priv, pipe), hw_state->dpll);
/* Wait for the clocks to stabilize. */
- intel_de_posting_read(dev_priv, DPLL(pipe));
+ intel_de_posting_read(dev_priv, DPLL(dev_priv, pipe));
udelay(150);
if (DISPLAY_VER(dev_priv) >= 4) {
@@ -1855,13 +1856,13 @@ void i9xx_enable_pll(const struct intel_crtc_state *crtc_state)
*
* So write it again.
*/
- intel_de_write(dev_priv, DPLL(pipe), hw_state->dpll);
+ intel_de_write(dev_priv, DPLL(dev_priv, pipe), hw_state->dpll);
}
/* We do this three times for luck */
for (i = 0; i < 3; i++) {
- intel_de_write(dev_priv, DPLL(pipe), hw_state->dpll);
- intel_de_posting_read(dev_priv, DPLL(pipe));
+ intel_de_write(dev_priv, DPLL(dev_priv, pipe), hw_state->dpll);
+ intel_de_posting_read(dev_priv, DPLL(dev_priv, pipe));
udelay(150); /* wait for warmup */
}
}
@@ -1993,11 +1994,11 @@ static void _vlv_enable_pll(const struct intel_crtc_state *crtc_state)
const struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx;
enum pipe pipe = crtc->pipe;
- intel_de_write(dev_priv, DPLL(pipe), hw_state->dpll);
- intel_de_posting_read(dev_priv, DPLL(pipe));
+ intel_de_write(dev_priv, DPLL(dev_priv, pipe), hw_state->dpll);
+ intel_de_posting_read(dev_priv, DPLL(dev_priv, pipe));
udelay(150);
- if (intel_de_wait_for_set(dev_priv, DPLL(pipe), DPLL_LOCK_VLV, 1))
+ if (intel_de_wait_for_set(dev_priv, DPLL(dev_priv, pipe), DPLL_LOCK_VLV, 1))
drm_err(&dev_priv->drm, "DPLL %d failed to lock\n", pipe);
}
@@ -2014,7 +2015,7 @@ void vlv_enable_pll(const struct intel_crtc_state *crtc_state)
assert_pps_unlocked(dev_priv, pipe);
/* Enable Refclk */
- intel_de_write(dev_priv, DPLL(pipe),
+ intel_de_write(dev_priv, DPLL(dev_priv, pipe),
hw_state->dpll & ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV));
if (hw_state->dpll & DPLL_VCO_ENABLE) {
@@ -2146,10 +2147,10 @@ static void _chv_enable_pll(const struct intel_crtc_state *crtc_state)
udelay(1);
/* Enable PLL */
- intel_de_write(dev_priv, DPLL(pipe), hw_state->dpll);
+ intel_de_write(dev_priv, DPLL(dev_priv, pipe), hw_state->dpll);
/* Check PLL is locked */
- if (intel_de_wait_for_set(dev_priv, DPLL(pipe), DPLL_LOCK_VLV, 1))
+ if (intel_de_wait_for_set(dev_priv, DPLL(dev_priv, pipe), DPLL_LOCK_VLV, 1))
drm_err(&dev_priv->drm, "PLL %d failed to lock\n", pipe);
}
@@ -2166,7 +2167,7 @@ void chv_enable_pll(const struct intel_crtc_state *crtc_state)
assert_pps_unlocked(dev_priv, pipe);
/* Enable Refclk and SSC */
- intel_de_write(dev_priv, DPLL(pipe),
+ intel_de_write(dev_priv, DPLL(dev_priv, pipe),
hw_state->dpll & ~DPLL_VCO_ENABLE);
if (hw_state->dpll & DPLL_VCO_ENABLE) {
@@ -2191,7 +2192,7 @@ void chv_enable_pll(const struct intel_crtc_state *crtc_state)
* We should always have it disabled.
*/
drm_WARN_ON(&dev_priv->drm,
- (intel_de_read(dev_priv, DPLL(PIPE_B)) &
+ (intel_de_read(dev_priv, DPLL(dev_priv, PIPE_B)) &
DPLL_VGA_MODE_DIS) == 0);
} else {
intel_de_write(dev_priv, DPLL_MD(pipe), hw_state->dpll_md);
@@ -2249,8 +2250,8 @@ void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
if (pipe != PIPE_A)
val |= DPLL_INTEGRATED_CRI_CLK_VLV;
- intel_de_write(dev_priv, DPLL(pipe), val);
- intel_de_posting_read(dev_priv, DPLL(pipe));
+ intel_de_write(dev_priv, DPLL(dev_priv, pipe), val);
+ intel_de_posting_read(dev_priv, DPLL(dev_priv, pipe));
}
void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
@@ -2267,8 +2268,8 @@ void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
if (pipe != PIPE_A)
val |= DPLL_INTEGRATED_CRI_CLK_VLV;
- intel_de_write(dev_priv, DPLL(pipe), val);
- intel_de_posting_read(dev_priv, DPLL(pipe));
+ intel_de_write(dev_priv, DPLL(dev_priv, pipe), val);
+ intel_de_posting_read(dev_priv, DPLL(dev_priv, pipe));
vlv_dpio_get(dev_priv);
@@ -2293,8 +2294,8 @@ void i9xx_disable_pll(const struct intel_crtc_state *crtc_state)
/* Make sure the pipe isn't still relying on us */
assert_transcoder_disabled(dev_priv, crtc_state->cpu_transcoder);
- intel_de_write(dev_priv, DPLL(pipe), DPLL_VGA_MODE_DIS);
- intel_de_posting_read(dev_priv, DPLL(pipe));
+ intel_de_write(dev_priv, DPLL(dev_priv, pipe), DPLL_VGA_MODE_DIS);
+ intel_de_posting_read(dev_priv, DPLL(dev_priv, pipe));
}
@@ -2320,7 +2321,7 @@ static void assert_pll(struct drm_i915_private *dev_priv,
{
bool cur_state;
- cur_state = intel_de_read(dev_priv, DPLL(pipe)) & DPLL_VCO_ENABLE;
+ cur_state = intel_de_read(dev_priv, DPLL(dev_priv, pipe)) & DPLL_VCO_ENABLE;
I915_STATE_WARN(dev_priv, cur_state != state,
"PLL state assertion failure (expected %s, current %s)\n",
str_on_off(state), str_on_off(cur_state));
diff --git a/drivers/gpu/drm/i915/display/intel_dvo.c b/drivers/gpu/drm/i915/display/intel_dvo.c
index 1840f5b59229..091824334f26 100644
--- a/drivers/gpu/drm/i915/display/intel_dvo.c
+++ b/drivers/gpu/drm/i915/display/intel_dvo.c
@@ -456,13 +456,14 @@ static bool intel_dvo_init_dev(struct drm_i915_private *dev_priv,
* the device.
*/
for_each_pipe(dev_priv, pipe)
- dpll[pipe] = intel_de_rmw(dev_priv, DPLL(pipe), 0, DPLL_DVO_2X_MODE);
+ dpll[pipe] = intel_de_rmw(dev_priv, DPLL(dev_priv, pipe), 0,
+ DPLL_DVO_2X_MODE);
ret = dvo->dev_ops->init(&intel_dvo->dev, i2c);
/* restore the DVO 2x clock state to original */
for_each_pipe(dev_priv, pipe) {
- intel_de_write(dev_priv, DPLL(pipe), dpll[pipe]);
+ intel_de_write(dev_priv, DPLL(dev_priv, pipe), dpll[pipe]);
}
intel_gmbus_force_bit(i2c, false);
diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c
index 0ccbf9a85914..c0208e85e4ad 100644
--- a/drivers/gpu/drm/i915/display/intel_pps.c
+++ b/drivers/gpu/drm/i915/display/intel_pps.c
@@ -119,7 +119,7 @@ vlv_power_sequencer_kick(struct intel_dp *intel_dp)
else
DP |= DP_PIPE_SEL(pipe);
- pll_enabled = intel_de_read(dev_priv, DPLL(pipe)) & DPLL_VCO_ENABLE;
+ pll_enabled = intel_de_read(dev_priv, DPLL(dev_priv, pipe)) & DPLL_VCO_ENABLE;
/*
* The DPLL for the pipe must be enabled for this to work.
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 4eb37f38d888..2f34069b05b0 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1150,7 +1150,7 @@
#define _DPLL_A 0x6014
#define _DPLL_B 0x6018
#define _CHV_DPLL_C 0x6030
-#define DPLL(pipe) _MMIO_BASE_PIPE3(DISPLAY_MMIO_BASE(dev_priv), \
+#define DPLL(dev_priv, pipe) _MMIO_BASE_PIPE3(DISPLAY_MMIO_BASE(dev_priv), \
(pipe), _DPLL_A, _DPLL_B, _CHV_DPLL_C)
#define VGA0 _MMIO(0x6000)
--
2.39.2
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH 002/123] drm/i915: pass dev_priv explicitly to DPLL_MD
2024-04-26 13:01 [PATCH 000/123] drm/i915: remove implicit dev_priv local variable use Jani Nikula
2024-04-26 13:01 ` [PATCH 001/123] drm/i915: pass dev_priv explicitly to DPLL Jani Nikula
@ 2024-04-26 13:01 ` Jani Nikula
2024-04-26 13:01 ` [PATCH 003/123] drm/i915: pass dev_priv explicitly to PALETTE Jani Nikula
` (15 subsequent siblings)
17 siblings, 0 replies; 21+ messages in thread
From: Jani Nikula @ 2024-04-26 13:01 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: jani.nikula
Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the DPLL_MD register macro.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/intel_dpll.c | 18 +++++++++++-------
drivers/gpu/drm/i915/i915_reg.h | 2 +-
2 files changed, 12 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c
index ccd299e31e95..3f29316da5e6 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll.c
@@ -397,7 +397,8 @@ void i9xx_dpll_get_hw_state(struct intel_crtc *crtc,
if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A)
tmp = dev_priv->display.state.chv_dpll_md[crtc->pipe];
else
- tmp = intel_de_read(dev_priv, DPLL_MD(crtc->pipe));
+ tmp = intel_de_read(dev_priv,
+ DPLL_MD(dev_priv, crtc->pipe));
hw_state->dpll_md = tmp;
}
@@ -1849,7 +1850,8 @@ void i9xx_enable_pll(const struct intel_crtc_state *crtc_state)
udelay(150);
if (DISPLAY_VER(dev_priv) >= 4) {
- intel_de_write(dev_priv, DPLL_MD(pipe), hw_state->dpll_md);
+ intel_de_write(dev_priv, DPLL_MD(dev_priv, pipe),
+ hw_state->dpll_md);
} else {
/* The pixel multiplier can only be updated once the
* DPLL is enabled and the clocks are stable.
@@ -2023,8 +2025,8 @@ void vlv_enable_pll(const struct intel_crtc_state *crtc_state)
_vlv_enable_pll(crtc_state);
}
- intel_de_write(dev_priv, DPLL_MD(pipe), hw_state->dpll_md);
- intel_de_posting_read(dev_priv, DPLL_MD(pipe));
+ intel_de_write(dev_priv, DPLL_MD(dev_priv, pipe), hw_state->dpll_md);
+ intel_de_posting_read(dev_priv, DPLL_MD(dev_priv, pipe));
}
static void chv_prepare_pll(const struct intel_crtc_state *crtc_state)
@@ -2183,7 +2185,8 @@ void chv_enable_pll(const struct intel_crtc_state *crtc_state)
* the value from DPLLBMD to either pipe B or C.
*/
intel_de_write(dev_priv, CBR4_VLV, CBR_DPLLBMD_PIPE(pipe));
- intel_de_write(dev_priv, DPLL_MD(PIPE_B), hw_state->dpll_md);
+ intel_de_write(dev_priv, DPLL_MD(dev_priv, PIPE_B),
+ hw_state->dpll_md);
intel_de_write(dev_priv, CBR4_VLV, 0);
dev_priv->display.state.chv_dpll_md[pipe] = hw_state->dpll_md;
@@ -2195,8 +2198,9 @@ void chv_enable_pll(const struct intel_crtc_state *crtc_state)
(intel_de_read(dev_priv, DPLL(dev_priv, PIPE_B)) &
DPLL_VGA_MODE_DIS) == 0);
} else {
- intel_de_write(dev_priv, DPLL_MD(pipe), hw_state->dpll_md);
- intel_de_posting_read(dev_priv, DPLL_MD(pipe));
+ intel_de_write(dev_priv, DPLL_MD(dev_priv, pipe),
+ hw_state->dpll_md);
+ intel_de_posting_read(dev_priv, DPLL_MD(dev_priv, pipe));
}
}
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 2f34069b05b0..744698a9c107 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1250,7 +1250,7 @@
#define _DPLL_A_MD 0x601c
#define _DPLL_B_MD 0x6020
#define _CHV_DPLL_C_MD 0x603c
-#define DPLL_MD(pipe) _MMIO_BASE_PIPE3(DISPLAY_MMIO_BASE(dev_priv), \
+#define DPLL_MD(dev_priv, pipe) _MMIO_BASE_PIPE3(DISPLAY_MMIO_BASE(dev_priv), \
(pipe), _DPLL_A_MD, _DPLL_B_MD, _CHV_DPLL_C_MD)
/*
--
2.39.2
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH 003/123] drm/i915: pass dev_priv explicitly to PALETTE
2024-04-26 13:01 [PATCH 000/123] drm/i915: remove implicit dev_priv local variable use Jani Nikula
2024-04-26 13:01 ` [PATCH 001/123] drm/i915: pass dev_priv explicitly to DPLL Jani Nikula
2024-04-26 13:01 ` [PATCH 002/123] drm/i915: pass dev_priv explicitly to DPLL_MD Jani Nikula
@ 2024-04-26 13:01 ` Jani Nikula
2024-04-26 13:01 ` [PATCH 004/123] drm/i915: pass dev_priv explicitly to PIPE_CRC_CTL Jani Nikula
` (14 subsequent siblings)
17 siblings, 0 replies; 21+ messages in thread
From: Jani Nikula @ 2024-04-26 13:01 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: jani.nikula
Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the PALETTE register macro.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/intel_color.c | 29 ++++++++++++++--------
drivers/gpu/drm/i915/i915_reg.h | 2 +-
2 files changed, 20 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index ca7112b32cb3..edb805fc9c97 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -1227,7 +1227,7 @@ static void i9xx_load_lut_8(struct intel_crtc *crtc,
lut = blob->data;
for (i = 0; i < 256; i++)
- intel_de_write_fw(dev_priv, PALETTE(pipe, i),
+ intel_de_write_fw(dev_priv, PALETTE(dev_priv, pipe, i),
i9xx_lut_8(&lut[i]));
}
@@ -1240,9 +1240,11 @@ static void i9xx_load_lut_10(struct intel_crtc *crtc,
enum pipe pipe = crtc->pipe;
for (i = 0; i < lut_size - 1; i++) {
- intel_de_write_fw(dev_priv, PALETTE(pipe, 2 * i + 0),
+ intel_de_write_fw(dev_priv,
+ PALETTE(dev_priv, pipe, 2 * i + 0),
i9xx_lut_10_ldw(&lut[i]));
- intel_de_write_fw(dev_priv, PALETTE(pipe, 2 * i + 1),
+ intel_de_write_fw(dev_priv,
+ PALETTE(dev_priv, pipe, 2 * i + 1),
i9xx_lut_10_udw(&lut[i]));
}
}
@@ -1274,9 +1276,11 @@ static void i965_load_lut_10p6(struct intel_crtc *crtc,
enum pipe pipe = crtc->pipe;
for (i = 0; i < lut_size - 1; i++) {
- intel_de_write_fw(dev_priv, PALETTE(pipe, 2 * i + 0),
+ intel_de_write_fw(dev_priv,
+ PALETTE(dev_priv, pipe, 2 * i + 0),
i965_lut_10p6_ldw(&lut[i]));
- intel_de_write_fw(dev_priv, PALETTE(pipe, 2 * i + 1),
+ intel_de_write_fw(dev_priv,
+ PALETTE(dev_priv, pipe, 2 * i + 1),
i965_lut_10p6_udw(&lut[i]));
}
@@ -3150,7 +3154,8 @@ static struct drm_property_blob *i9xx_read_lut_8(struct intel_crtc *crtc)
lut = blob->data;
for (i = 0; i < LEGACY_LUT_LENGTH; i++) {
- u32 val = intel_de_read_fw(dev_priv, PALETTE(pipe, i));
+ u32 val = intel_de_read_fw(dev_priv,
+ PALETTE(dev_priv, pipe, i));
i9xx_lut_8_pack(&lut[i], val);
}
@@ -3176,8 +3181,10 @@ static struct drm_property_blob *i9xx_read_lut_10(struct intel_crtc *crtc)
lut = blob->data;
for (i = 0; i < lut_size - 1; i++) {
- ldw = intel_de_read_fw(dev_priv, PALETTE(pipe, 2 * i + 0));
- udw = intel_de_read_fw(dev_priv, PALETTE(pipe, 2 * i + 1));
+ ldw = intel_de_read_fw(dev_priv,
+ PALETTE(dev_priv, pipe, 2 * i + 0));
+ udw = intel_de_read_fw(dev_priv,
+ PALETTE(dev_priv, pipe, 2 * i + 1));
i9xx_lut_10_pack(&lut[i], ldw, udw);
}
@@ -3224,8 +3231,10 @@ static struct drm_property_blob *i965_read_lut_10p6(struct intel_crtc *crtc)
lut = blob->data;
for (i = 0; i < lut_size - 1; i++) {
- u32 ldw = intel_de_read_fw(dev_priv, PALETTE(pipe, 2 * i + 0));
- u32 udw = intel_de_read_fw(dev_priv, PALETTE(pipe, 2 * i + 1));
+ u32 ldw = intel_de_read_fw(dev_priv,
+ PALETTE(dev_priv, pipe, 2 * i + 0));
+ u32 udw = intel_de_read_fw(dev_priv,
+ PALETTE(dev_priv, pipe, 2 * i + 1));
i965_lut_10p6_pack(&lut[i], ldw, udw);
}
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 744698a9c107..5c07b489073d 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1480,7 +1480,7 @@
#define PALETTE_10BIT_BLUE_EXP_MASK REG_GENMASK(7, 6)
#define PALETTE_10BIT_BLUE_MANT_MASK REG_GENMASK(5, 2)
#define PALETTE_10BIT_BLUE_UDW_MASK REG_GENMASK(1, 0)
-#define PALETTE(pipe, i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + \
+#define PALETTE(dev_priv, pipe, i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + \
_PICK_EVEN_2RANGES(pipe, 2, \
_PALETTE_A, _PALETTE_B, \
_CHV_PALETTE_C, _CHV_PALETTE_C) + \
--
2.39.2
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH 004/123] drm/i915: pass dev_priv explicitly to PIPE_CRC_CTL
2024-04-26 13:01 [PATCH 000/123] drm/i915: remove implicit dev_priv local variable use Jani Nikula
` (2 preceding siblings ...)
2024-04-26 13:01 ` [PATCH 003/123] drm/i915: pass dev_priv explicitly to PALETTE Jani Nikula
@ 2024-04-26 13:01 ` Jani Nikula
2024-04-26 13:01 ` [PATCH 005/123] drm/i915: pass dev_priv explicitly to PIPE_CRC_RES_1_IVB Jani Nikula
` (13 subsequent siblings)
17 siblings, 0 replies; 21+ messages in thread
From: Jani Nikula @ 2024-04-26 13:01 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: jani.nikula
Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the PIPE_CRC_CTL register macro.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/intel_pipe_crc.c | 12 ++++++------
drivers/gpu/drm/i915/i915_reg.h | 2 +-
2 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_pipe_crc.c b/drivers/gpu/drm/i915/display/intel_pipe_crc.c
index 5a468ed6e26c..35c3dd1130ce 100644
--- a/drivers/gpu/drm/i915/display/intel_pipe_crc.c
+++ b/drivers/gpu/drm/i915/display/intel_pipe_crc.c
@@ -608,8 +608,8 @@ int intel_crtc_set_crc_source(struct drm_crtc *_crtc, const char *source_name)
goto out;
pipe_crc->source = source;
- intel_de_write(dev_priv, PIPE_CRC_CTL(pipe), val);
- intel_de_posting_read(dev_priv, PIPE_CRC_CTL(pipe));
+ intel_de_write(dev_priv, PIPE_CRC_CTL(dev_priv, pipe), val);
+ intel_de_posting_read(dev_priv, PIPE_CRC_CTL(dev_priv, pipe));
if (!source) {
if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
@@ -643,8 +643,8 @@ void intel_crtc_enable_pipe_crc(struct intel_crtc *crtc)
/* Don't need pipe_crc->lock here, IRQs are not generated. */
pipe_crc->skipped = 0;
- intel_de_write(dev_priv, PIPE_CRC_CTL(pipe), val);
- intel_de_posting_read(dev_priv, PIPE_CRC_CTL(pipe));
+ intel_de_write(dev_priv, PIPE_CRC_CTL(dev_priv, pipe), val);
+ intel_de_posting_read(dev_priv, PIPE_CRC_CTL(dev_priv, pipe));
}
void intel_crtc_disable_pipe_crc(struct intel_crtc *crtc)
@@ -658,7 +658,7 @@ void intel_crtc_disable_pipe_crc(struct intel_crtc *crtc)
pipe_crc->skipped = INT_MIN;
spin_unlock_irq(&pipe_crc->lock);
- intel_de_write(dev_priv, PIPE_CRC_CTL(pipe), 0);
- intel_de_posting_read(dev_priv, PIPE_CRC_CTL(pipe));
+ intel_de_write(dev_priv, PIPE_CRC_CTL(dev_priv, pipe), 0);
+ intel_de_posting_read(dev_priv, PIPE_CRC_CTL(dev_priv, pipe));
intel_synchronize_irq(dev_priv);
}
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 5c07b489073d..7c8a9c5ccd4f 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1649,7 +1649,7 @@
#define _PIPE_CRC_RES_4_B_IVB 0x61070
#define _PIPE_CRC_RES_5_B_IVB 0x61074
-#define PIPE_CRC_CTL(pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_CTL_A)
+#define PIPE_CRC_CTL(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_CTL_A)
#define PIPE_CRC_RES_1_IVB(pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_1_A_IVB)
#define PIPE_CRC_RES_2_IVB(pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_2_A_IVB)
#define PIPE_CRC_RES_3_IVB(pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_3_A_IVB)
--
2.39.2
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH 005/123] drm/i915: pass dev_priv explicitly to PIPE_CRC_RES_1_IVB
2024-04-26 13:01 [PATCH 000/123] drm/i915: remove implicit dev_priv local variable use Jani Nikula
` (3 preceding siblings ...)
2024-04-26 13:01 ` [PATCH 004/123] drm/i915: pass dev_priv explicitly to PIPE_CRC_CTL Jani Nikula
@ 2024-04-26 13:01 ` Jani Nikula
2024-04-26 13:01 ` [PATCH 006/123] drm/i915: pass dev_priv explicitly to PIPE_CRC_RES_2_IVB Jani Nikula
` (12 subsequent siblings)
17 siblings, 0 replies; 21+ messages in thread
From: Jani Nikula @ 2024-04-26 13:01 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: jani.nikula
Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the PIPE_CRC_RES_1_IVB register macro.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/intel_display_irq.c | 4 ++--
drivers/gpu/drm/i915/i915_reg.h | 2 +-
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c
index c337e0597541..45abbc169bf5 100644
--- a/drivers/gpu/drm/i915/display/intel_display_irq.c
+++ b/drivers/gpu/drm/i915/display/intel_display_irq.c
@@ -356,7 +356,7 @@ static void hsw_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
enum pipe pipe)
{
display_pipe_crc_irq_handler(dev_priv, pipe,
- intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_1_IVB(pipe)),
+ intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_1_IVB(dev_priv, pipe)),
0, 0, 0, 0);
}
@@ -364,7 +364,7 @@ static void ivb_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
enum pipe pipe)
{
display_pipe_crc_irq_handler(dev_priv, pipe,
- intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_1_IVB(pipe)),
+ intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_1_IVB(dev_priv, pipe)),
intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_2_IVB(pipe)),
intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_3_IVB(pipe)),
intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_4_IVB(pipe)),
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 7c8a9c5ccd4f..cabc938843b3 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1650,7 +1650,7 @@
#define _PIPE_CRC_RES_5_B_IVB 0x61074
#define PIPE_CRC_CTL(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_CTL_A)
-#define PIPE_CRC_RES_1_IVB(pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_1_A_IVB)
+#define PIPE_CRC_RES_1_IVB(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_1_A_IVB)
#define PIPE_CRC_RES_2_IVB(pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_2_A_IVB)
#define PIPE_CRC_RES_3_IVB(pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_3_A_IVB)
#define PIPE_CRC_RES_4_IVB(pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_4_A_IVB)
--
2.39.2
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH 006/123] drm/i915: pass dev_priv explicitly to PIPE_CRC_RES_2_IVB
2024-04-26 13:01 [PATCH 000/123] drm/i915: remove implicit dev_priv local variable use Jani Nikula
` (4 preceding siblings ...)
2024-04-26 13:01 ` [PATCH 005/123] drm/i915: pass dev_priv explicitly to PIPE_CRC_RES_1_IVB Jani Nikula
@ 2024-04-26 13:01 ` Jani Nikula
2024-04-26 13:01 ` [PATCH 007/123] drm/i915: pass dev_priv explicitly to PIPE_CRC_RES_3_IVB Jani Nikula
` (11 subsequent siblings)
17 siblings, 0 replies; 21+ messages in thread
From: Jani Nikula @ 2024-04-26 13:01 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: jani.nikula
Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the PIPE_CRC_RES_2_IVB register macro.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/intel_display_irq.c | 2 +-
drivers/gpu/drm/i915/i915_reg.h | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c
index 45abbc169bf5..d810a0bab901 100644
--- a/drivers/gpu/drm/i915/display/intel_display_irq.c
+++ b/drivers/gpu/drm/i915/display/intel_display_irq.c
@@ -365,7 +365,7 @@ static void ivb_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
{
display_pipe_crc_irq_handler(dev_priv, pipe,
intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_1_IVB(dev_priv, pipe)),
- intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_2_IVB(pipe)),
+ intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_2_IVB(dev_priv, pipe)),
intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_3_IVB(pipe)),
intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_4_IVB(pipe)),
intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_5_IVB(pipe)));
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index cabc938843b3..7b7b9f73db02 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1651,7 +1651,7 @@
#define PIPE_CRC_CTL(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_CTL_A)
#define PIPE_CRC_RES_1_IVB(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_1_A_IVB)
-#define PIPE_CRC_RES_2_IVB(pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_2_A_IVB)
+#define PIPE_CRC_RES_2_IVB(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_2_A_IVB)
#define PIPE_CRC_RES_3_IVB(pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_3_A_IVB)
#define PIPE_CRC_RES_4_IVB(pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_4_A_IVB)
#define PIPE_CRC_RES_5_IVB(pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_5_A_IVB)
--
2.39.2
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH 007/123] drm/i915: pass dev_priv explicitly to PIPE_CRC_RES_3_IVB
2024-04-26 13:01 [PATCH 000/123] drm/i915: remove implicit dev_priv local variable use Jani Nikula
` (5 preceding siblings ...)
2024-04-26 13:01 ` [PATCH 006/123] drm/i915: pass dev_priv explicitly to PIPE_CRC_RES_2_IVB Jani Nikula
@ 2024-04-26 13:01 ` Jani Nikula
2024-04-26 13:01 ` [PATCH 008/123] drm/i915: pass dev_priv explicitly to PIPE_CRC_RES_4_IVB Jani Nikula
` (10 subsequent siblings)
17 siblings, 0 replies; 21+ messages in thread
From: Jani Nikula @ 2024-04-26 13:01 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: jani.nikula
Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the PIPE_CRC_RES_3_IVB register macro.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/intel_display_irq.c | 2 +-
drivers/gpu/drm/i915/i915_reg.h | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c
index d810a0bab901..a17c258bb219 100644
--- a/drivers/gpu/drm/i915/display/intel_display_irq.c
+++ b/drivers/gpu/drm/i915/display/intel_display_irq.c
@@ -366,7 +366,7 @@ static void ivb_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
display_pipe_crc_irq_handler(dev_priv, pipe,
intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_1_IVB(dev_priv, pipe)),
intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_2_IVB(dev_priv, pipe)),
- intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_3_IVB(pipe)),
+ intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_3_IVB(dev_priv, pipe)),
intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_4_IVB(pipe)),
intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_5_IVB(pipe)));
}
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 7b7b9f73db02..248312e6e06e 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1652,7 +1652,7 @@
#define PIPE_CRC_CTL(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_CTL_A)
#define PIPE_CRC_RES_1_IVB(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_1_A_IVB)
#define PIPE_CRC_RES_2_IVB(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_2_A_IVB)
-#define PIPE_CRC_RES_3_IVB(pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_3_A_IVB)
+#define PIPE_CRC_RES_3_IVB(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_3_A_IVB)
#define PIPE_CRC_RES_4_IVB(pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_4_A_IVB)
#define PIPE_CRC_RES_5_IVB(pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_5_A_IVB)
--
2.39.2
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH 008/123] drm/i915: pass dev_priv explicitly to PIPE_CRC_RES_4_IVB
2024-04-26 13:01 [PATCH 000/123] drm/i915: remove implicit dev_priv local variable use Jani Nikula
` (6 preceding siblings ...)
2024-04-26 13:01 ` [PATCH 007/123] drm/i915: pass dev_priv explicitly to PIPE_CRC_RES_3_IVB Jani Nikula
@ 2024-04-26 13:01 ` Jani Nikula
2024-04-26 13:01 ` [PATCH 009/123] drm/i915: pass dev_priv explicitly to PIPE_CRC_RES_5_IVB Jani Nikula
` (9 subsequent siblings)
17 siblings, 0 replies; 21+ messages in thread
From: Jani Nikula @ 2024-04-26 13:01 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: jani.nikula
Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the PIPE_CRC_RES_4_IVB register macro.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/intel_display_irq.c | 2 +-
drivers/gpu/drm/i915/i915_reg.h | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c
index a17c258bb219..919ff34a7bb1 100644
--- a/drivers/gpu/drm/i915/display/intel_display_irq.c
+++ b/drivers/gpu/drm/i915/display/intel_display_irq.c
@@ -367,7 +367,7 @@ static void ivb_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_1_IVB(dev_priv, pipe)),
intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_2_IVB(dev_priv, pipe)),
intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_3_IVB(dev_priv, pipe)),
- intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_4_IVB(pipe)),
+ intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_4_IVB(dev_priv, pipe)),
intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_5_IVB(pipe)));
}
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 248312e6e06e..2544d2f0220c 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1653,7 +1653,7 @@
#define PIPE_CRC_RES_1_IVB(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_1_A_IVB)
#define PIPE_CRC_RES_2_IVB(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_2_A_IVB)
#define PIPE_CRC_RES_3_IVB(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_3_A_IVB)
-#define PIPE_CRC_RES_4_IVB(pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_4_A_IVB)
+#define PIPE_CRC_RES_4_IVB(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_4_A_IVB)
#define PIPE_CRC_RES_5_IVB(pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_5_A_IVB)
#define PIPE_CRC_RES_RED(pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_RED_A)
--
2.39.2
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH 009/123] drm/i915: pass dev_priv explicitly to PIPE_CRC_RES_5_IVB
2024-04-26 13:01 [PATCH 000/123] drm/i915: remove implicit dev_priv local variable use Jani Nikula
` (7 preceding siblings ...)
2024-04-26 13:01 ` [PATCH 008/123] drm/i915: pass dev_priv explicitly to PIPE_CRC_RES_4_IVB Jani Nikula
@ 2024-04-26 13:01 ` Jani Nikula
2024-04-26 13:01 ` [PATCH 010/123] drm/i915: pass dev_priv explicitly to PIPE_CRC_RES_RED Jani Nikula
` (8 subsequent siblings)
17 siblings, 0 replies; 21+ messages in thread
From: Jani Nikula @ 2024-04-26 13:01 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: jani.nikula
Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the PIPE_CRC_RES_5_IVB register macro.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/intel_display_irq.c | 2 +-
drivers/gpu/drm/i915/i915_reg.h | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c
index 919ff34a7bb1..8bef21f74010 100644
--- a/drivers/gpu/drm/i915/display/intel_display_irq.c
+++ b/drivers/gpu/drm/i915/display/intel_display_irq.c
@@ -368,7 +368,7 @@ static void ivb_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_2_IVB(dev_priv, pipe)),
intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_3_IVB(dev_priv, pipe)),
intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_4_IVB(dev_priv, pipe)),
- intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_5_IVB(pipe)));
+ intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_5_IVB(dev_priv, pipe)));
}
static void i9xx_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 2544d2f0220c..6f85d5b23c2c 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1654,7 +1654,7 @@
#define PIPE_CRC_RES_2_IVB(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_2_A_IVB)
#define PIPE_CRC_RES_3_IVB(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_3_A_IVB)
#define PIPE_CRC_RES_4_IVB(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_4_A_IVB)
-#define PIPE_CRC_RES_5_IVB(pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_5_A_IVB)
+#define PIPE_CRC_RES_5_IVB(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_5_A_IVB)
#define PIPE_CRC_RES_RED(pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_RED_A)
#define PIPE_CRC_RES_GREEN(pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_GREEN_A)
--
2.39.2
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH 010/123] drm/i915: pass dev_priv explicitly to PIPE_CRC_RES_RED
2024-04-26 13:01 [PATCH 000/123] drm/i915: remove implicit dev_priv local variable use Jani Nikula
` (8 preceding siblings ...)
2024-04-26 13:01 ` [PATCH 009/123] drm/i915: pass dev_priv explicitly to PIPE_CRC_RES_5_IVB Jani Nikula
@ 2024-04-26 13:01 ` Jani Nikula
2024-04-26 13:01 ` [PATCH 011/123] drm/i915: pass dev_priv explicitly to PIPE_CRC_RES_GREEN Jani Nikula
` (7 subsequent siblings)
17 siblings, 0 replies; 21+ messages in thread
From: Jani Nikula @ 2024-04-26 13:01 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: jani.nikula
Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the PIPE_CRC_RES_RED register macro.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/intel_display_irq.c | 2 +-
drivers/gpu/drm/i915/i915_reg.h | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c
index 8bef21f74010..4593f5244706 100644
--- a/drivers/gpu/drm/i915/display/intel_display_irq.c
+++ b/drivers/gpu/drm/i915/display/intel_display_irq.c
@@ -387,7 +387,7 @@ static void i9xx_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
res2 = 0;
display_pipe_crc_irq_handler(dev_priv, pipe,
- intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_RED(pipe)),
+ intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_RED(dev_priv, pipe)),
intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_GREEN(pipe)),
intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_BLUE(pipe)),
res1, res2);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 6f85d5b23c2c..87c637039480 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1656,7 +1656,7 @@
#define PIPE_CRC_RES_4_IVB(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_4_A_IVB)
#define PIPE_CRC_RES_5_IVB(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_5_A_IVB)
-#define PIPE_CRC_RES_RED(pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_RED_A)
+#define PIPE_CRC_RES_RED(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_RED_A)
#define PIPE_CRC_RES_GREEN(pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_GREEN_A)
#define PIPE_CRC_RES_BLUE(pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_BLUE_A)
#define PIPE_CRC_RES_RES1_I915(pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_RES1_A_I915)
--
2.39.2
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH 011/123] drm/i915: pass dev_priv explicitly to PIPE_CRC_RES_GREEN
2024-04-26 13:01 [PATCH 000/123] drm/i915: remove implicit dev_priv local variable use Jani Nikula
` (9 preceding siblings ...)
2024-04-26 13:01 ` [PATCH 010/123] drm/i915: pass dev_priv explicitly to PIPE_CRC_RES_RED Jani Nikula
@ 2024-04-26 13:01 ` Jani Nikula
2024-04-26 13:01 ` [PATCH 012/123] drm/i915: pass dev_priv explicitly to PIPE_CRC_RES_BLUE Jani Nikula
` (6 subsequent siblings)
17 siblings, 0 replies; 21+ messages in thread
From: Jani Nikula @ 2024-04-26 13:01 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: jani.nikula
Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the PIPE_CRC_RES_GREEN register macro.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/intel_display_irq.c | 2 +-
drivers/gpu/drm/i915/i915_reg.h | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c
index 4593f5244706..77be9f2029ac 100644
--- a/drivers/gpu/drm/i915/display/intel_display_irq.c
+++ b/drivers/gpu/drm/i915/display/intel_display_irq.c
@@ -388,7 +388,7 @@ static void i9xx_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
display_pipe_crc_irq_handler(dev_priv, pipe,
intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_RED(dev_priv, pipe)),
- intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_GREEN(pipe)),
+ intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_GREEN(dev_priv, pipe)),
intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_BLUE(pipe)),
res1, res2);
}
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 87c637039480..68a2dea9017b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1657,7 +1657,7 @@
#define PIPE_CRC_RES_5_IVB(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_5_A_IVB)
#define PIPE_CRC_RES_RED(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_RED_A)
-#define PIPE_CRC_RES_GREEN(pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_GREEN_A)
+#define PIPE_CRC_RES_GREEN(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_GREEN_A)
#define PIPE_CRC_RES_BLUE(pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_BLUE_A)
#define PIPE_CRC_RES_RES1_I915(pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_RES1_A_I915)
#define PIPE_CRC_RES_RES2_G4X(pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_RES2_A_G4X)
--
2.39.2
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH 012/123] drm/i915: pass dev_priv explicitly to PIPE_CRC_RES_BLUE
2024-04-26 13:01 [PATCH 000/123] drm/i915: remove implicit dev_priv local variable use Jani Nikula
` (10 preceding siblings ...)
2024-04-26 13:01 ` [PATCH 011/123] drm/i915: pass dev_priv explicitly to PIPE_CRC_RES_GREEN Jani Nikula
@ 2024-04-26 13:01 ` Jani Nikula
2024-04-26 13:01 ` [PATCH 013/123] drm/i915: pass dev_priv explicitly to PIPE_CRC_RES_RES1_I915 Jani Nikula
` (5 subsequent siblings)
17 siblings, 0 replies; 21+ messages in thread
From: Jani Nikula @ 2024-04-26 13:01 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: jani.nikula
Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the PIPE_CRC_RES_BLUE register macro.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/intel_display_irq.c | 2 +-
drivers/gpu/drm/i915/i915_reg.h | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c
index 77be9f2029ac..5738e06a773c 100644
--- a/drivers/gpu/drm/i915/display/intel_display_irq.c
+++ b/drivers/gpu/drm/i915/display/intel_display_irq.c
@@ -389,7 +389,7 @@ static void i9xx_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
display_pipe_crc_irq_handler(dev_priv, pipe,
intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_RED(dev_priv, pipe)),
intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_GREEN(dev_priv, pipe)),
- intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_BLUE(pipe)),
+ intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_BLUE(dev_priv, pipe)),
res1, res2);
}
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 68a2dea9017b..b50115d1f1d4 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1658,7 +1658,7 @@
#define PIPE_CRC_RES_RED(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_RED_A)
#define PIPE_CRC_RES_GREEN(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_GREEN_A)
-#define PIPE_CRC_RES_BLUE(pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_BLUE_A)
+#define PIPE_CRC_RES_BLUE(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_BLUE_A)
#define PIPE_CRC_RES_RES1_I915(pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_RES1_A_I915)
#define PIPE_CRC_RES_RES2_G4X(pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_RES2_A_G4X)
--
2.39.2
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH 013/123] drm/i915: pass dev_priv explicitly to PIPE_CRC_RES_RES1_I915
2024-04-26 13:01 [PATCH 000/123] drm/i915: remove implicit dev_priv local variable use Jani Nikula
` (11 preceding siblings ...)
2024-04-26 13:01 ` [PATCH 012/123] drm/i915: pass dev_priv explicitly to PIPE_CRC_RES_BLUE Jani Nikula
@ 2024-04-26 13:01 ` Jani Nikula
2024-04-26 13:01 ` [PATCH 014/123] drm/i915: pass dev_priv explicitly to PIPE_CRC_RES_RES2_G4X Jani Nikula
` (4 subsequent siblings)
17 siblings, 0 replies; 21+ messages in thread
From: Jani Nikula @ 2024-04-26 13:01 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: jani.nikula
Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the PIPE_CRC_RES_RES1_I915 register macro.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/intel_display_irq.c | 3 ++-
drivers/gpu/drm/i915/i915_reg.h | 2 +-
2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c
index 5738e06a773c..b83e4f312f7e 100644
--- a/drivers/gpu/drm/i915/display/intel_display_irq.c
+++ b/drivers/gpu/drm/i915/display/intel_display_irq.c
@@ -377,7 +377,8 @@ static void i9xx_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
u32 res1, res2;
if (DISPLAY_VER(dev_priv) >= 3)
- res1 = intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_RES1_I915(pipe));
+ res1 = intel_uncore_read(&dev_priv->uncore,
+ PIPE_CRC_RES_RES1_I915(dev_priv, pipe));
else
res1 = 0;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index b50115d1f1d4..8c79bfc02714 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1659,7 +1659,7 @@
#define PIPE_CRC_RES_RED(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_RED_A)
#define PIPE_CRC_RES_GREEN(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_GREEN_A)
#define PIPE_CRC_RES_BLUE(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_BLUE_A)
-#define PIPE_CRC_RES_RES1_I915(pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_RES1_A_I915)
+#define PIPE_CRC_RES_RES1_I915(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_RES1_A_I915)
#define PIPE_CRC_RES_RES2_G4X(pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_RES2_A_G4X)
/* Pipe/transcoder A timing regs */
--
2.39.2
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH 014/123] drm/i915: pass dev_priv explicitly to PIPE_CRC_RES_RES2_G4X
2024-04-26 13:01 [PATCH 000/123] drm/i915: remove implicit dev_priv local variable use Jani Nikula
` (12 preceding siblings ...)
2024-04-26 13:01 ` [PATCH 013/123] drm/i915: pass dev_priv explicitly to PIPE_CRC_RES_RES1_I915 Jani Nikula
@ 2024-04-26 13:01 ` Jani Nikula
2024-04-26 13:01 ` [PATCH 015/123] drm/i915: pass dev_priv explicitly to TRANS_HTOTAL Jani Nikula
` (3 subsequent siblings)
17 siblings, 0 replies; 21+ messages in thread
From: Jani Nikula @ 2024-04-26 13:01 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: jani.nikula
Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the PIPE_CRC_RES_RES2_G4X register macro.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/intel_display_irq.c | 3 ++-
drivers/gpu/drm/i915/i915_reg.h | 2 +-
2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c
index b83e4f312f7e..04e867db0878 100644
--- a/drivers/gpu/drm/i915/display/intel_display_irq.c
+++ b/drivers/gpu/drm/i915/display/intel_display_irq.c
@@ -383,7 +383,8 @@ static void i9xx_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
res1 = 0;
if (DISPLAY_VER(dev_priv) >= 5 || IS_G4X(dev_priv))
- res2 = intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_RES2_G4X(pipe));
+ res2 = intel_uncore_read(&dev_priv->uncore,
+ PIPE_CRC_RES_RES2_G4X(dev_priv, pipe));
else
res2 = 0;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 8c79bfc02714..c9bd827eba60 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1660,7 +1660,7 @@
#define PIPE_CRC_RES_GREEN(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_GREEN_A)
#define PIPE_CRC_RES_BLUE(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_BLUE_A)
#define PIPE_CRC_RES_RES1_I915(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_RES1_A_I915)
-#define PIPE_CRC_RES_RES2_G4X(pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_RES2_A_G4X)
+#define PIPE_CRC_RES_RES2_G4X(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_RES2_A_G4X)
/* Pipe/transcoder A timing regs */
#define _TRANS_HTOTAL_A 0x60000
--
2.39.2
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH 015/123] drm/i915: pass dev_priv explicitly to TRANS_HTOTAL
2024-04-26 13:01 [PATCH 000/123] drm/i915: remove implicit dev_priv local variable use Jani Nikula
` (13 preceding siblings ...)
2024-04-26 13:01 ` [PATCH 014/123] drm/i915: pass dev_priv explicitly to PIPE_CRC_RES_RES2_G4X Jani Nikula
@ 2024-04-26 13:01 ` Jani Nikula
2024-04-26 13:01 ` [PATCH 016/123] drm/i915: pass dev_priv explicitly to TRANS_HBLANK Jani Nikula
` (2 subsequent siblings)
17 siblings, 0 replies; 21+ messages in thread
From: Jani Nikula @ 2024-04-26 13:01 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: jani.nikula
Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the TRANS_HTOTAL register macro.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/icl_dsi.c | 2 +-
drivers/gpu/drm/i915/display/intel_display.c | 6 +++---
drivers/gpu/drm/i915/display/intel_pch_display.c | 2 +-
drivers/gpu/drm/i915/gvt/handlers.c | 2 +-
drivers/gpu/drm/i915/i915_reg.h | 2 +-
drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 8 ++++----
6 files changed, 11 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index 79ecfc339430..af0d3159369e 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -915,7 +915,7 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder,
/* program TRANS_HTOTAL register */
for_each_dsi_port(port, intel_dsi->ports) {
dsi_trans = dsi_port_to_transcoder(port);
- intel_de_write(dev_priv, TRANS_HTOTAL(dsi_trans),
+ intel_de_write(dev_priv, TRANS_HTOTAL(dev_priv, dsi_trans),
HACTIVE(hactive - 1) | HTOTAL(htotal - 1));
}
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 5b6025e2f621..d84c5541f3ee 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2705,7 +2705,7 @@ static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_sta
intel_de_write(dev_priv, TRANS_VSYNCSHIFT(cpu_transcoder),
vsyncshift);
- intel_de_write(dev_priv, TRANS_HTOTAL(cpu_transcoder),
+ intel_de_write(dev_priv, TRANS_HTOTAL(dev_priv, cpu_transcoder),
HACTIVE(adjusted_mode->crtc_hdisplay - 1) |
HTOTAL(adjusted_mode->crtc_htotal - 1));
intel_de_write(dev_priv, TRANS_HBLANK(cpu_transcoder),
@@ -2806,7 +2806,7 @@ static void intel_get_transcoder_timings(struct intel_crtc *crtc,
struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
u32 tmp;
- tmp = intel_de_read(dev_priv, TRANS_HTOTAL(cpu_transcoder));
+ tmp = intel_de_read(dev_priv, TRANS_HTOTAL(dev_priv, cpu_transcoder));
adjusted_mode->crtc_hdisplay = REG_FIELD_GET(HACTIVE_MASK, tmp) + 1;
adjusted_mode->crtc_htotal = REG_FIELD_GET(HTOTAL_MASK, tmp) + 1;
@@ -8162,7 +8162,7 @@ void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
PLL_REF_INPUT_DREFCLK |
DPLL_VCO_ENABLE;
- intel_de_write(dev_priv, TRANS_HTOTAL(cpu_transcoder),
+ intel_de_write(dev_priv, TRANS_HTOTAL(dev_priv, cpu_transcoder),
HACTIVE(640 - 1) | HTOTAL(800 - 1));
intel_de_write(dev_priv, TRANS_HBLANK(cpu_transcoder),
HBLANK_START(640 - 1) | HBLANK_END(800 - 1));
diff --git a/drivers/gpu/drm/i915/display/intel_pch_display.c b/drivers/gpu/drm/i915/display/intel_pch_display.c
index 826e38a9e6a4..2bf00d5336e3 100644
--- a/drivers/gpu/drm/i915/display/intel_pch_display.c
+++ b/drivers/gpu/drm/i915/display/intel_pch_display.c
@@ -224,7 +224,7 @@ static void ilk_pch_transcoder_set_timings(const struct intel_crtc_state *crtc_s
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
intel_de_write(dev_priv, PCH_TRANS_HTOTAL(pch_transcoder),
- intel_de_read(dev_priv, TRANS_HTOTAL(cpu_transcoder)));
+ intel_de_read(dev_priv, TRANS_HTOTAL(dev_priv, cpu_transcoder)));
intel_de_write(dev_priv, PCH_TRANS_HBLANK(pch_transcoder),
intel_de_read(dev_priv, TRANS_HBLANK(cpu_transcoder)));
intel_de_write(dev_priv, PCH_TRANS_HSYNC(pch_transcoder),
diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
index f85bf59cdeaf..63a8dfbe4cb3 100644
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -672,7 +672,7 @@ static void vgpu_update_refresh_rate(struct intel_vgpu *vgpu)
link_n = vgpu_vreg_t(vgpu, PIPE_LINK_N1(TRANSCODER_A));
/* Get H/V total from transcoder timing */
- htotal = (vgpu_vreg_t(vgpu, TRANS_HTOTAL(TRANSCODER_A)) >> TRANS_HTOTAL_SHIFT);
+ htotal = (vgpu_vreg_t(vgpu, TRANS_HTOTAL(dev_priv, TRANSCODER_A)) >> TRANS_HTOTAL_SHIFT);
vtotal = (vgpu_vreg_t(vgpu, TRANS_VTOTAL(TRANSCODER_A)) >> TRANS_VTOTAL_SHIFT);
if (dp_br && link_n && htotal && vtotal) {
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c9bd827eba60..3ab39bbd1d2d 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1729,7 +1729,7 @@
#define _TRANS_VSYNC_DSI1 0x6b814
#define _TRANS_VSYNCSHIFT_DSI1 0x6b828
-#define TRANS_HTOTAL(trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_HTOTAL_A)
+#define TRANS_HTOTAL(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_HTOTAL_A)
#define TRANS_HBLANK(trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_HBLANK_A)
#define TRANS_HSYNC(trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_HSYNC_A)
#define TRANS_VTOTAL(trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_VTOTAL_A)
diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
index d0f111ff0ada..09db1d7a777d 100644
--- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
+++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
@@ -226,7 +226,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
MMIO_D(SPRSCALE(PIPE_C));
MMIO_D(SPRSURFLIVE(PIPE_C));
MMIO_D(REG_50080(PIPE_C, PLANE_SPRITE0));
- MMIO_D(TRANS_HTOTAL(TRANSCODER_A));
+ MMIO_D(TRANS_HTOTAL(dev_priv, TRANSCODER_A));
MMIO_D(TRANS_HBLANK(TRANSCODER_A));
MMIO_D(TRANS_HSYNC(TRANSCODER_A));
MMIO_D(TRANS_VTOTAL(TRANSCODER_A));
@@ -235,7 +235,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
MMIO_D(BCLRPAT(TRANSCODER_A));
MMIO_D(TRANS_VSYNCSHIFT(TRANSCODER_A));
MMIO_D(PIPESRC(TRANSCODER_A));
- MMIO_D(TRANS_HTOTAL(TRANSCODER_B));
+ MMIO_D(TRANS_HTOTAL(dev_priv, TRANSCODER_B));
MMIO_D(TRANS_HBLANK(TRANSCODER_B));
MMIO_D(TRANS_HSYNC(TRANSCODER_B));
MMIO_D(TRANS_VTOTAL(TRANSCODER_B));
@@ -244,7 +244,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
MMIO_D(BCLRPAT(TRANSCODER_B));
MMIO_D(TRANS_VSYNCSHIFT(TRANSCODER_B));
MMIO_D(PIPESRC(TRANSCODER_B));
- MMIO_D(TRANS_HTOTAL(TRANSCODER_C));
+ MMIO_D(TRANS_HTOTAL(dev_priv, TRANSCODER_C));
MMIO_D(TRANS_HBLANK(TRANSCODER_C));
MMIO_D(TRANS_HSYNC(TRANSCODER_C));
MMIO_D(TRANS_VTOTAL(TRANSCODER_C));
@@ -253,7 +253,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
MMIO_D(BCLRPAT(TRANSCODER_C));
MMIO_D(TRANS_VSYNCSHIFT(TRANSCODER_C));
MMIO_D(PIPESRC(TRANSCODER_C));
- MMIO_D(TRANS_HTOTAL(TRANSCODER_EDP));
+ MMIO_D(TRANS_HTOTAL(dev_priv, TRANSCODER_EDP));
MMIO_D(TRANS_HBLANK(TRANSCODER_EDP));
MMIO_D(TRANS_HSYNC(TRANSCODER_EDP));
MMIO_D(TRANS_VTOTAL(TRANSCODER_EDP));
--
2.39.2
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH 016/123] drm/i915: pass dev_priv explicitly to TRANS_HBLANK
2024-04-26 13:01 [PATCH 000/123] drm/i915: remove implicit dev_priv local variable use Jani Nikula
` (14 preceding siblings ...)
2024-04-26 13:01 ` [PATCH 015/123] drm/i915: pass dev_priv explicitly to TRANS_HTOTAL Jani Nikula
@ 2024-04-26 13:01 ` Jani Nikula
2024-04-26 13:01 ` [PATCH 017/123] drm/i915: pass dev_priv explicitly to TRANS_HSYNC Jani Nikula
2024-04-26 13:09 ` [PATCH 000/123] drm/i915: remove implicit dev_priv local variable use Jani Nikula
17 siblings, 0 replies; 21+ messages in thread
From: Jani Nikula @ 2024-04-26 13:01 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: jani.nikula
Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the TRANS_HBLANK register macro.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 7 ++++---
drivers/gpu/drm/i915/display/intel_pch_display.c | 2 +-
drivers/gpu/drm/i915/i915_reg.h | 2 +-
drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 8 ++++----
4 files changed, 10 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index d84c5541f3ee..b9da3605b6aa 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2708,7 +2708,7 @@ static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_sta
intel_de_write(dev_priv, TRANS_HTOTAL(dev_priv, cpu_transcoder),
HACTIVE(adjusted_mode->crtc_hdisplay - 1) |
HTOTAL(adjusted_mode->crtc_htotal - 1));
- intel_de_write(dev_priv, TRANS_HBLANK(cpu_transcoder),
+ intel_de_write(dev_priv, TRANS_HBLANK(dev_priv, cpu_transcoder),
HBLANK_START(adjusted_mode->crtc_hblank_start - 1) |
HBLANK_END(adjusted_mode->crtc_hblank_end - 1));
intel_de_write(dev_priv, TRANS_HSYNC(cpu_transcoder),
@@ -2811,7 +2811,8 @@ static void intel_get_transcoder_timings(struct intel_crtc *crtc,
adjusted_mode->crtc_htotal = REG_FIELD_GET(HTOTAL_MASK, tmp) + 1;
if (!transcoder_is_dsi(cpu_transcoder)) {
- tmp = intel_de_read(dev_priv, TRANS_HBLANK(cpu_transcoder));
+ tmp = intel_de_read(dev_priv,
+ TRANS_HBLANK(dev_priv, cpu_transcoder));
adjusted_mode->crtc_hblank_start = REG_FIELD_GET(HBLANK_START_MASK, tmp) + 1;
adjusted_mode->crtc_hblank_end = REG_FIELD_GET(HBLANK_END_MASK, tmp) + 1;
}
@@ -8164,7 +8165,7 @@ void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
intel_de_write(dev_priv, TRANS_HTOTAL(dev_priv, cpu_transcoder),
HACTIVE(640 - 1) | HTOTAL(800 - 1));
- intel_de_write(dev_priv, TRANS_HBLANK(cpu_transcoder),
+ intel_de_write(dev_priv, TRANS_HBLANK(dev_priv, cpu_transcoder),
HBLANK_START(640 - 1) | HBLANK_END(800 - 1));
intel_de_write(dev_priv, TRANS_HSYNC(cpu_transcoder),
HSYNC_START(656 - 1) | HSYNC_END(752 - 1));
diff --git a/drivers/gpu/drm/i915/display/intel_pch_display.c b/drivers/gpu/drm/i915/display/intel_pch_display.c
index 2bf00d5336e3..625b1fedd54c 100644
--- a/drivers/gpu/drm/i915/display/intel_pch_display.c
+++ b/drivers/gpu/drm/i915/display/intel_pch_display.c
@@ -226,7 +226,7 @@ static void ilk_pch_transcoder_set_timings(const struct intel_crtc_state *crtc_s
intel_de_write(dev_priv, PCH_TRANS_HTOTAL(pch_transcoder),
intel_de_read(dev_priv, TRANS_HTOTAL(dev_priv, cpu_transcoder)));
intel_de_write(dev_priv, PCH_TRANS_HBLANK(pch_transcoder),
- intel_de_read(dev_priv, TRANS_HBLANK(cpu_transcoder)));
+ intel_de_read(dev_priv, TRANS_HBLANK(dev_priv, cpu_transcoder)));
intel_de_write(dev_priv, PCH_TRANS_HSYNC(pch_transcoder),
intel_de_read(dev_priv, TRANS_HSYNC(cpu_transcoder)));
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 3ab39bbd1d2d..f5ddcb6d9127 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1730,7 +1730,7 @@
#define _TRANS_VSYNCSHIFT_DSI1 0x6b828
#define TRANS_HTOTAL(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_HTOTAL_A)
-#define TRANS_HBLANK(trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_HBLANK_A)
+#define TRANS_HBLANK(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_HBLANK_A)
#define TRANS_HSYNC(trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_HSYNC_A)
#define TRANS_VTOTAL(trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_VTOTAL_A)
#define TRANS_VBLANK(trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_VBLANK_A)
diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
index 09db1d7a777d..7243b36b2a4e 100644
--- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
+++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
@@ -227,7 +227,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
MMIO_D(SPRSURFLIVE(PIPE_C));
MMIO_D(REG_50080(PIPE_C, PLANE_SPRITE0));
MMIO_D(TRANS_HTOTAL(dev_priv, TRANSCODER_A));
- MMIO_D(TRANS_HBLANK(TRANSCODER_A));
+ MMIO_D(TRANS_HBLANK(dev_priv, TRANSCODER_A));
MMIO_D(TRANS_HSYNC(TRANSCODER_A));
MMIO_D(TRANS_VTOTAL(TRANSCODER_A));
MMIO_D(TRANS_VBLANK(TRANSCODER_A));
@@ -236,7 +236,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
MMIO_D(TRANS_VSYNCSHIFT(TRANSCODER_A));
MMIO_D(PIPESRC(TRANSCODER_A));
MMIO_D(TRANS_HTOTAL(dev_priv, TRANSCODER_B));
- MMIO_D(TRANS_HBLANK(TRANSCODER_B));
+ MMIO_D(TRANS_HBLANK(dev_priv, TRANSCODER_B));
MMIO_D(TRANS_HSYNC(TRANSCODER_B));
MMIO_D(TRANS_VTOTAL(TRANSCODER_B));
MMIO_D(TRANS_VBLANK(TRANSCODER_B));
@@ -245,7 +245,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
MMIO_D(TRANS_VSYNCSHIFT(TRANSCODER_B));
MMIO_D(PIPESRC(TRANSCODER_B));
MMIO_D(TRANS_HTOTAL(dev_priv, TRANSCODER_C));
- MMIO_D(TRANS_HBLANK(TRANSCODER_C));
+ MMIO_D(TRANS_HBLANK(dev_priv, TRANSCODER_C));
MMIO_D(TRANS_HSYNC(TRANSCODER_C));
MMIO_D(TRANS_VTOTAL(TRANSCODER_C));
MMIO_D(TRANS_VBLANK(TRANSCODER_C));
@@ -254,7 +254,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
MMIO_D(TRANS_VSYNCSHIFT(TRANSCODER_C));
MMIO_D(PIPESRC(TRANSCODER_C));
MMIO_D(TRANS_HTOTAL(dev_priv, TRANSCODER_EDP));
- MMIO_D(TRANS_HBLANK(TRANSCODER_EDP));
+ MMIO_D(TRANS_HBLANK(dev_priv, TRANSCODER_EDP));
MMIO_D(TRANS_HSYNC(TRANSCODER_EDP));
MMIO_D(TRANS_VTOTAL(TRANSCODER_EDP));
MMIO_D(TRANS_VBLANK(TRANSCODER_EDP));
--
2.39.2
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH 017/123] drm/i915: pass dev_priv explicitly to TRANS_HSYNC
2024-04-26 13:01 [PATCH 000/123] drm/i915: remove implicit dev_priv local variable use Jani Nikula
` (15 preceding siblings ...)
2024-04-26 13:01 ` [PATCH 016/123] drm/i915: pass dev_priv explicitly to TRANS_HBLANK Jani Nikula
@ 2024-04-26 13:01 ` Jani Nikula
2024-04-26 13:09 ` [PATCH 000/123] drm/i915: remove implicit dev_priv local variable use Jani Nikula
17 siblings, 0 replies; 21+ messages in thread
From: Jani Nikula @ 2024-04-26 13:01 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: jani.nikula
Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the TRANS_HSYNC register macro.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/icl_dsi.c | 3 ++-
drivers/gpu/drm/i915/display/intel_display.c | 6 +++---
drivers/gpu/drm/i915/display/intel_pch_display.c | 2 +-
drivers/gpu/drm/i915/i915_reg.h | 2 +-
drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 8 ++++----
5 files changed, 11 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index af0d3159369e..f87a2170ac91 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -938,7 +938,8 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder,
for_each_dsi_port(port, intel_dsi->ports) {
dsi_trans = dsi_port_to_transcoder(port);
- intel_de_write(dev_priv, TRANS_HSYNC(dsi_trans),
+ intel_de_write(dev_priv,
+ TRANS_HSYNC(dev_priv, dsi_trans),
HSYNC_START(hsync_start - 1) | HSYNC_END(hsync_end - 1));
}
}
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index b9da3605b6aa..49c63b8855b3 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2711,7 +2711,7 @@ static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_sta
intel_de_write(dev_priv, TRANS_HBLANK(dev_priv, cpu_transcoder),
HBLANK_START(adjusted_mode->crtc_hblank_start - 1) |
HBLANK_END(adjusted_mode->crtc_hblank_end - 1));
- intel_de_write(dev_priv, TRANS_HSYNC(cpu_transcoder),
+ intel_de_write(dev_priv, TRANS_HSYNC(dev_priv, cpu_transcoder),
HSYNC_START(adjusted_mode->crtc_hsync_start - 1) |
HSYNC_END(adjusted_mode->crtc_hsync_end - 1));
@@ -2817,7 +2817,7 @@ static void intel_get_transcoder_timings(struct intel_crtc *crtc,
adjusted_mode->crtc_hblank_end = REG_FIELD_GET(HBLANK_END_MASK, tmp) + 1;
}
- tmp = intel_de_read(dev_priv, TRANS_HSYNC(cpu_transcoder));
+ tmp = intel_de_read(dev_priv, TRANS_HSYNC(dev_priv, cpu_transcoder));
adjusted_mode->crtc_hsync_start = REG_FIELD_GET(HSYNC_START_MASK, tmp) + 1;
adjusted_mode->crtc_hsync_end = REG_FIELD_GET(HSYNC_END_MASK, tmp) + 1;
@@ -8167,7 +8167,7 @@ void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
HACTIVE(640 - 1) | HTOTAL(800 - 1));
intel_de_write(dev_priv, TRANS_HBLANK(dev_priv, cpu_transcoder),
HBLANK_START(640 - 1) | HBLANK_END(800 - 1));
- intel_de_write(dev_priv, TRANS_HSYNC(cpu_transcoder),
+ intel_de_write(dev_priv, TRANS_HSYNC(dev_priv, cpu_transcoder),
HSYNC_START(656 - 1) | HSYNC_END(752 - 1));
intel_de_write(dev_priv, TRANS_VTOTAL(cpu_transcoder),
VACTIVE(480 - 1) | VTOTAL(525 - 1));
diff --git a/drivers/gpu/drm/i915/display/intel_pch_display.c b/drivers/gpu/drm/i915/display/intel_pch_display.c
index 625b1fedd54c..480c0e09434d 100644
--- a/drivers/gpu/drm/i915/display/intel_pch_display.c
+++ b/drivers/gpu/drm/i915/display/intel_pch_display.c
@@ -228,7 +228,7 @@ static void ilk_pch_transcoder_set_timings(const struct intel_crtc_state *crtc_s
intel_de_write(dev_priv, PCH_TRANS_HBLANK(pch_transcoder),
intel_de_read(dev_priv, TRANS_HBLANK(dev_priv, cpu_transcoder)));
intel_de_write(dev_priv, PCH_TRANS_HSYNC(pch_transcoder),
- intel_de_read(dev_priv, TRANS_HSYNC(cpu_transcoder)));
+ intel_de_read(dev_priv, TRANS_HSYNC(dev_priv, cpu_transcoder)));
intel_de_write(dev_priv, PCH_TRANS_VTOTAL(pch_transcoder),
intel_de_read(dev_priv, TRANS_VTOTAL(cpu_transcoder)));
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index f5ddcb6d9127..57a195c5b698 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1731,7 +1731,7 @@
#define TRANS_HTOTAL(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_HTOTAL_A)
#define TRANS_HBLANK(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_HBLANK_A)
-#define TRANS_HSYNC(trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_HSYNC_A)
+#define TRANS_HSYNC(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_HSYNC_A)
#define TRANS_VTOTAL(trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_VTOTAL_A)
#define TRANS_VBLANK(trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_VBLANK_A)
#define TRANS_VSYNC(trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_VSYNC_A)
diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
index 7243b36b2a4e..8c614543b79f 100644
--- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
+++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
@@ -228,7 +228,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
MMIO_D(REG_50080(PIPE_C, PLANE_SPRITE0));
MMIO_D(TRANS_HTOTAL(dev_priv, TRANSCODER_A));
MMIO_D(TRANS_HBLANK(dev_priv, TRANSCODER_A));
- MMIO_D(TRANS_HSYNC(TRANSCODER_A));
+ MMIO_D(TRANS_HSYNC(dev_priv, TRANSCODER_A));
MMIO_D(TRANS_VTOTAL(TRANSCODER_A));
MMIO_D(TRANS_VBLANK(TRANSCODER_A));
MMIO_D(TRANS_VSYNC(TRANSCODER_A));
@@ -237,7 +237,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
MMIO_D(PIPESRC(TRANSCODER_A));
MMIO_D(TRANS_HTOTAL(dev_priv, TRANSCODER_B));
MMIO_D(TRANS_HBLANK(dev_priv, TRANSCODER_B));
- MMIO_D(TRANS_HSYNC(TRANSCODER_B));
+ MMIO_D(TRANS_HSYNC(dev_priv, TRANSCODER_B));
MMIO_D(TRANS_VTOTAL(TRANSCODER_B));
MMIO_D(TRANS_VBLANK(TRANSCODER_B));
MMIO_D(TRANS_VSYNC(TRANSCODER_B));
@@ -246,7 +246,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
MMIO_D(PIPESRC(TRANSCODER_B));
MMIO_D(TRANS_HTOTAL(dev_priv, TRANSCODER_C));
MMIO_D(TRANS_HBLANK(dev_priv, TRANSCODER_C));
- MMIO_D(TRANS_HSYNC(TRANSCODER_C));
+ MMIO_D(TRANS_HSYNC(dev_priv, TRANSCODER_C));
MMIO_D(TRANS_VTOTAL(TRANSCODER_C));
MMIO_D(TRANS_VBLANK(TRANSCODER_C));
MMIO_D(TRANS_VSYNC(TRANSCODER_C));
@@ -255,7 +255,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
MMIO_D(PIPESRC(TRANSCODER_C));
MMIO_D(TRANS_HTOTAL(dev_priv, TRANSCODER_EDP));
MMIO_D(TRANS_HBLANK(dev_priv, TRANSCODER_EDP));
- MMIO_D(TRANS_HSYNC(TRANSCODER_EDP));
+ MMIO_D(TRANS_HSYNC(dev_priv, TRANSCODER_EDP));
MMIO_D(TRANS_VTOTAL(TRANSCODER_EDP));
MMIO_D(TRANS_VBLANK(TRANSCODER_EDP));
MMIO_D(TRANS_VSYNC(TRANSCODER_EDP));
--
2.39.2
^ permalink raw reply related [flat|nested] 21+ messages in thread
* Re: [PATCH 000/123] drm/i915: remove implicit dev_priv local variable use
2024-04-26 13:01 [PATCH 000/123] drm/i915: remove implicit dev_priv local variable use Jani Nikula
` (16 preceding siblings ...)
2024-04-26 13:01 ` [PATCH 017/123] drm/i915: pass dev_priv explicitly to TRANS_HSYNC Jani Nikula
@ 2024-04-26 13:09 ` Jani Nikula
2024-04-29 12:43 ` Rodrigo Vivi
17 siblings, 1 reply; 21+ messages in thread
From: Jani Nikula @ 2024-04-26 13:09 UTC (permalink / raw)
To: intel-gfx, intel-xe
On Fri, 26 Apr 2024, Jani Nikula <jani.nikula@intel.com> wrote:
> Hey all, it's time to stop using the implicit dev_priv local variable in
> register macros. Yes, this is huge. It's also (almost) completely
> scripted.
Okay, I was first going to send the entire series, but chickened out and
hit ^C when git send-email was going though the patches. You get the
idea with what's here. It's just more of the same. Plus I pushed the lot
to [1].
I think we'll need to do this. The question is how to handle this
churn. Do we want this many patches? If not, how much to squash?
BR,
Jani.
[1] https://gitlab.freedesktop.org/jani/linux/-/commits/regs-mass-dev-priv-removal/?ref_type=heads
--
Jani Nikula, Intel
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH 000/123] drm/i915: remove implicit dev_priv local variable use
2024-04-26 13:09 ` [PATCH 000/123] drm/i915: remove implicit dev_priv local variable use Jani Nikula
@ 2024-04-29 12:43 ` Rodrigo Vivi
2024-04-29 14:08 ` Jani Nikula
0 siblings, 1 reply; 21+ messages in thread
From: Rodrigo Vivi @ 2024-04-29 12:43 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx, intel-xe
On Fri, Apr 26, 2024 at 04:09:45PM +0300, Jani Nikula wrote:
> On Fri, 26 Apr 2024, Jani Nikula <jani.nikula@intel.com> wrote:
> > Hey all, it's time to stop using the implicit dev_priv local variable in
> > register macros. Yes, this is huge. It's also (almost) completely
> > scripted.
>
> Okay, I was first going to send the entire series, but chickened out and
> hit ^C when git send-email was going though the patches. You get the
> idea with what's here. It's just more of the same. Plus I pushed the lot
> to [1].
now it makes sense. I was wondering why I was only seeing a few patches
when the series was telling over a hundred.
>
> I think we'll need to do this.
Agreed. Let's do this.
> The question is how to handle this
> churn. Do we want this many patches? If not, how much to squash?
From a glance on these initial patches, it sounds really organized in
individual patches and easy to review.
Perhaps if we take this path we might just split the series in blocks
and merge these initial 17, and we continue over the next weeks.
However, if this is automated like you mentioned in the cover letter,
perhaps we can do one patch per directory? (display vs gvt vs gem? vs drm/i915/{.c,.h})
>
>
> BR,
> Jani.
>
>
> [1] https://gitlab.freedesktop.org/jani/linux/-/commits/regs-mass-dev-priv-removal/?ref_type=heads
>
>
> --
> Jani Nikula, Intel
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH 000/123] drm/i915: remove implicit dev_priv local variable use
2024-04-29 12:43 ` Rodrigo Vivi
@ 2024-04-29 14:08 ` Jani Nikula
0 siblings, 0 replies; 21+ messages in thread
From: Jani Nikula @ 2024-04-29 14:08 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: intel-gfx, intel-xe
On Mon, 29 Apr 2024, Rodrigo Vivi <rodrigo.vivi@intel.com> wrote:
> From a glance on these initial patches, it sounds really organized in
> individual patches and easy to review.
> Perhaps if we take this path we might just split the series in blocks
> and merge these initial 17, and we continue over the next weeks.
Ack.
> However, if this is automated like you mentioned in the cover letter,
> perhaps we can do one patch per directory? (display vs gvt vs gem? vs drm/i915/{.c,.h})
I'll look into it. The first natural batch came about when I moved some
color regs, so I sent them [1].
BR,
Jani.
[1] https://lore.kernel.org/r/cover.1714399071.git.jani.nikula@intel.com
--
Jani Nikula, Intel
^ permalink raw reply [flat|nested] 21+ messages in thread
end of thread, other threads:[~2024-04-29 14:09 UTC | newest]
Thread overview: 21+ messages (download: mbox.gz / follow: Atom feed)
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2024-04-26 13:01 ` [PATCH 010/123] drm/i915: pass dev_priv explicitly to PIPE_CRC_RES_RED Jani Nikula
2024-04-26 13:01 ` [PATCH 011/123] drm/i915: pass dev_priv explicitly to PIPE_CRC_RES_GREEN Jani Nikula
2024-04-26 13:01 ` [PATCH 012/123] drm/i915: pass dev_priv explicitly to PIPE_CRC_RES_BLUE Jani Nikula
2024-04-26 13:01 ` [PATCH 013/123] drm/i915: pass dev_priv explicitly to PIPE_CRC_RES_RES1_I915 Jani Nikula
2024-04-26 13:01 ` [PATCH 014/123] drm/i915: pass dev_priv explicitly to PIPE_CRC_RES_RES2_G4X Jani Nikula
2024-04-26 13:01 ` [PATCH 015/123] drm/i915: pass dev_priv explicitly to TRANS_HTOTAL Jani Nikula
2024-04-26 13:01 ` [PATCH 016/123] drm/i915: pass dev_priv explicitly to TRANS_HBLANK Jani Nikula
2024-04-26 13:01 ` [PATCH 017/123] drm/i915: pass dev_priv explicitly to TRANS_HSYNC Jani Nikula
2024-04-26 13:09 ` [PATCH 000/123] drm/i915: remove implicit dev_priv local variable use Jani Nikula
2024-04-29 12:43 ` Rodrigo Vivi
2024-04-29 14:08 ` Jani Nikula
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