[PATCH v1 0/3] PEBS virtualization enabling via DS in Qemu

[PATCH v1 0/3] PEBS virtualization enabling via DS in Qemu

[Luwei Kang]

The PEBS virtualization will be first supported on ICELAKE server.
This patchset introduce a new CPU parameter "pebs"(e.g.
"-cpu Icelake-Server,pmu=true,pebs=true") that use for enable PEBS
feature in KVM guest, and add the support for save/load PEBS MSRs.

Luwei Kang (3):
  i386: Add "pebs" parameter to enable PEBS feature
  i386: Add support for save/load PEBS MSRs
  i386: Add support for save/load IA32_PEBS_DATA_CFG MSR

 hw/i386/pc.c          |  1 +
 target/i386/cpu.c     | 14 ++++++++++++++
 target/i386/cpu.h     | 15 +++++++++++++++
 target/i386/kvm.c     | 43 +++++++++++++++++++++++++++++++++++++++++++
 target/i386/machine.c | 49 +++++++++++++++++++++++++++++++++++++++++++++++++
 5 files changed, 122 insertions(+)

-- 
1.8.3.1

[PATCH v1 1/3] i386: Add "pebs" parameter to enable PEBS feature

[Luwei Kang]

The PEBS virtualization enabling in KVM guest will be supported start from
IceLake hardware. This patch introduce a new CPU parameter "pebs" to enable
PEBS feature. The paramter of "pebs" is false by default.

PDCM,DTES64,DTS are needed by PEBS feature. Expose these feature bits to
KVM guest when the KVM support PEBS virtualization and the "pebs" parameter
is true.

Signed-off-by: Luwei Kang <luwei.kang@intel.com>
---
 hw/i386/pc.c      |  1 +
 target/i386/cpu.c | 14 ++++++++++++++
 target/i386/cpu.h |  7 +++++++
 3 files changed, 22 insertions(+)

diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index 96715f8..aeb9fb9 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -316,6 +316,7 @@ GlobalProperty pc_compat_1_5[] = {
     { "Nehalem-" TYPE_X86_CPU, "min-level", "2" },
     { "virtio-net-pci", "any_layout", "off" },
     { TYPE_X86_CPU, "pmu", "on" },
+    { TYPE_X86_CPU, "pebs", "on" },
     { "i440FX-pcihost", "short_root_bus", "0" },
     { "q35-pcihost", "short_root_bus", "0" },
 };
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index cc586dc..1ca56de 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -3306,6 +3306,7 @@ static void max_x86_cpu_initfn(Object *obj)
     }
 
     object_property_set_bool(OBJECT(cpu), true, "pmu", &error_abort);
+    object_property_set_bool(OBJECT(cpu), true, "pebs", &error_abort);
 }
 
 static const TypeInfo max_x86_cpu_type_info = {
@@ -4511,11 +4512,23 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
         if ((*ecx & CPUID_EXT_XSAVE) && (env->cr[4] & CR4_OSXSAVE_MASK)) {
             *ecx |= CPUID_EXT_OSXSAVE;
         }
+        if (kvm_enabled() && cpu->enable_pmu && cpu->enable_pebs) {
+            *ecx |= kvm_arch_get_supported_cpuid(cs->kvm_state, 0x1, 0, R_ECX) &
+                                            (CPUID_EXT_PDCM | CPUID_EXT_DTES64);
+        } else {
+            *ecx &= ~(CPUID_EXT_PDCM | CPUID_EXT_DTES64);
+        }
         *edx = env->features[FEAT_1_EDX];
         if (cs->nr_cores * cs->nr_threads > 1) {
             *ebx |= (cs->nr_cores * cs->nr_threads) << 16;
             *edx |= CPUID_HT;
         }
+        if (kvm_enabled() && cpu->enable_pmu && cpu->enable_pebs) {
+            *edx |= kvm_arch_get_supported_cpuid(cs->kvm_state, 0x1, 0, R_EDX) &
+                                            CPUID_DTS;
+        } else {
+            *edx &= ~CPUID_DTS;
+        }
         break;
     case 2:
         /* cache info: needed for Pentium Pro compatibility */
@@ -6129,6 +6142,7 @@ static Property x86_cpu_properties[] = {
 #endif
     DEFINE_PROP_INT32("node-id", X86CPU, node_id, CPU_UNSET_NUMA_NODE_ID),
     DEFINE_PROP_BOOL("pmu", X86CPU, enable_pmu, false),
+    DEFINE_PROP_BOOL("pebs", X86CPU, enable_pebs, false),
 
     DEFINE_PROP_UINT32("hv-spinlocks", X86CPU, hyperv_spinlock_attempts,
                        HYPERV_SPINLOCK_NEVER_RETRY),
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index 5352c9f..398810f 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -1664,6 +1664,13 @@ struct X86CPU {
      */
     bool enable_pmu;
 
+    /* Enable PEBS CPUID bits. This can't be enabled by default yet because
+     * it doesn't have ABI stability guarantees, as it passes all PEBS CPUID
+     * bits returned by GET_SUPPORTED_CPUID (that depend on host CPU and kernel
+     * capabilities) directly to the guest.
+     */
+    bool enable_pebs;
+
     /* LMCE support can be enabled/disabled via cpu option 'lmce=on/off'. It is
      * disabled by default to avoid breaking migration between QEMU with
      * different LMCE configurations.
-- 
1.8.3.1

[PATCH v1 2/3] i386: Add support for save/load PEBS MSRs

[Luwei Kang]

PEBS feature virtualization required IA32_PEBS_ENABLE and
DS_AREA MSRs. This patch is to add the support of these MSRs
saved/loaded in guest.

Signed-off-by: Luwei Kang <luwei.kang@intel.com>
---
 target/i386/cpu.h     |  6 ++++++
 target/i386/kvm.c     | 29 +++++++++++++++++++++++++++++
 target/i386/machine.c | 25 +++++++++++++++++++++++++
 3 files changed, 60 insertions(+)

diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index 398810f..872a495 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -412,6 +412,9 @@ typedef enum X86Seg {
 #define MSR_CORE_PERF_GLOBAL_CTRL       0x38f
 #define MSR_CORE_PERF_GLOBAL_OVF_CTRL   0x390
 
+#define MSR_IA32_PEBS_ENABLE            0x3f1
+#define MSR_IA32_DS_AREA                0x600
+
 #define MSR_MC0_CTL                     0x400
 #define MSR_MC0_STATUS                  0x401
 #define MSR_MC0_ADDR                    0x402
@@ -1444,6 +1447,9 @@ typedef struct CPUX86State {
     uint64_t msr_gp_counters[MAX_GP_COUNTERS];
     uint64_t msr_gp_evtsel[MAX_GP_COUNTERS];
 
+    uint64_t msr_pebs_enable;
+    uint64_t msr_ds_area;
+
     uint64_t pat;
     uint32_t smbase;
     uint64_t msr_smi_count;
diff --git a/target/i386/kvm.c b/target/i386/kvm.c
index bfd09bd..1043961 100644
--- a/target/i386/kvm.c
+++ b/target/i386/kvm.c
@@ -102,6 +102,8 @@ static bool has_msr_smi_count;
 static bool has_msr_arch_capabs;
 static bool has_msr_core_capabs;
 static bool has_msr_vmx_vmfunc;
+static bool has_msr_pebs_enable;
+static bool has_msr_ds_area;
 
 static uint32_t has_architectural_pmu_version;
 static uint32_t num_architectural_pmu_gp_counters;
@@ -2048,6 +2050,12 @@ static int kvm_get_supported_msrs(KVMState *s)
             case MSR_IA32_VMX_VMFUNC:
                 has_msr_vmx_vmfunc = true;
                 break;
+            case MSR_IA32_PEBS_ENABLE:
+                has_msr_pebs_enable = true;
+                break;
+            case MSR_IA32_DS_AREA:
+                has_msr_ds_area = true;
+                break;
             }
         }
     }
@@ -2770,7 +2778,16 @@ static int kvm_put_msrs(X86CPU *cpu, int level)
                 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL,
                                   env->msr_global_ctrl);
             }
+            if (has_msr_pebs_enable) {
+                kvm_msr_entry_add(cpu, MSR_IA32_PEBS_ENABLE,
+                                  env->msr_pebs_enable);
+            }
+            if (has_msr_ds_area) {
+                kvm_msr_entry_add(cpu, MSR_IA32_DS_AREA,
+                                  env->msr_ds_area);
+            }
         }
+
         /*
          * Hyper-V partition-wide MSRs: to avoid clearing them on cpu hot-add,
          * only sync them to KVM on the first cpu
@@ -3154,6 +3171,12 @@ static int kvm_get_msrs(X86CPU *cpu)
             kvm_msr_entry_add(cpu, MSR_P6_PERFCTR0 + i, 0);
             kvm_msr_entry_add(cpu, MSR_P6_EVNTSEL0 + i, 0);
         }
+        if (has_msr_pebs_enable) {
+            kvm_msr_entry_add(cpu, MSR_IA32_PEBS_ENABLE, 0);
+        }
+        if (has_msr_ds_area) {
+            kvm_msr_entry_add(cpu, MSR_IA32_DS_AREA, 0);
+        }
     }
 
     if (env->mcg_cap) {
@@ -3402,6 +3425,12 @@ static int kvm_get_msrs(X86CPU *cpu)
         case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL0 + MAX_GP_COUNTERS - 1:
             env->msr_gp_evtsel[index - MSR_P6_EVNTSEL0] = msrs[i].data;
             break;
+        case MSR_IA32_PEBS_ENABLE:
+            env->msr_pebs_enable = msrs[i].data;
+            break;
+        case MSR_IA32_DS_AREA:
+            env->msr_ds_area = msrs[i].data;
+            break;
         case HV_X64_MSR_HYPERCALL:
             env->msr_hv_hypercall = msrs[i].data;
             break;
diff --git a/target/i386/machine.c b/target/i386/machine.c
index 6481f84..82a2101 100644
--- a/target/i386/machine.c
+++ b/target/i386/machine.c
@@ -646,6 +646,30 @@ static const VMStateDescription vmstate_msr_architectural_pmu = {
     }
 };
 
+static bool pebs_via_ds_needed(void *opaque)
+{
+    X86CPU *cpu = opaque;
+    CPUX86State *env = &cpu->env;
+
+    if (env->msr_pebs_enable || env->msr_ds_area) {
+        return true;
+    }
+
+    return false;
+}
+
+static const VMStateDescription vmstate_msr_pebs_via_ds = {
+    .name = "cpu/msr_pebs_via_ds",
+    .version_id = 1,
+    .minimum_version_id = 1,
+    .needed = pebs_via_ds_needed,
+    .fields = (VMStateField[]) {
+        VMSTATE_UINT64(env.msr_pebs_enable, X86CPU),
+        VMSTATE_UINT64(env.msr_ds_area, X86CPU),
+        VMSTATE_END_OF_LIST()
+    }
+};
+
 static bool mpx_needed(void *opaque)
 {
     X86CPU *cpu = opaque;
@@ -1399,6 +1423,7 @@ VMStateDescription vmstate_x86_cpu = {
         &vmstate_msr_ia32_misc_enable,
         &vmstate_msr_ia32_feature_control,
         &vmstate_msr_architectural_pmu,
+        &vmstate_msr_pebs_via_ds,
         &vmstate_mpx,
         &vmstate_msr_hypercall_hypercall,
         &vmstate_msr_hyperv_vapic,
-- 
1.8.3.1

[PATCH v1 3/3] i386: Add support for save/load IA32_PEBS_DATA_CFG MSR

[Luwei Kang]

Add support for save/load PEBS baseline feature
IA32_PEBS_DATA_CFG MSR.

Signed-off-by: Luwei Kang <luwei.kang@intel.com>
---
 target/i386/cpu.h     |  2 ++
 target/i386/kvm.c     | 14 ++++++++++++++
 target/i386/machine.c | 24 ++++++++++++++++++++++++
 3 files changed, 40 insertions(+)

diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index 872a495..a9a7b3f 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -413,6 +413,7 @@ typedef enum X86Seg {
 #define MSR_CORE_PERF_GLOBAL_OVF_CTRL   0x390
 
 #define MSR_IA32_PEBS_ENABLE            0x3f1
+#define MSR_IA32_PEBS_DATA_CFG          0x3f2
 #define MSR_IA32_DS_AREA                0x600
 
 #define MSR_MC0_CTL                     0x400
@@ -1449,6 +1450,7 @@ typedef struct CPUX86State {
 
     uint64_t msr_pebs_enable;
     uint64_t msr_ds_area;
+    uint64_t msr_pebs_data_cfg;
 
     uint64_t pat;
     uint32_t smbase;
diff --git a/target/i386/kvm.c b/target/i386/kvm.c
index 1043961..ab4e7bb 100644
--- a/target/i386/kvm.c
+++ b/target/i386/kvm.c
@@ -104,6 +104,7 @@ static bool has_msr_core_capabs;
 static bool has_msr_vmx_vmfunc;
 static bool has_msr_pebs_enable;
 static bool has_msr_ds_area;
+static bool has_msr_pebs_data_cfg;
 
 static uint32_t has_architectural_pmu_version;
 static uint32_t num_architectural_pmu_gp_counters;
@@ -2056,6 +2057,9 @@ static int kvm_get_supported_msrs(KVMState *s)
             case MSR_IA32_DS_AREA:
                 has_msr_ds_area = true;
                 break;
+            case MSR_IA32_PEBS_DATA_CFG:
+                has_msr_pebs_data_cfg = true;
+                break;
             }
         }
     }
@@ -2786,6 +2790,10 @@ static int kvm_put_msrs(X86CPU *cpu, int level)
                 kvm_msr_entry_add(cpu, MSR_IA32_DS_AREA,
                                   env->msr_ds_area);
             }
+            if (has_msr_pebs_data_cfg) {
+                kvm_msr_entry_add(cpu, MSR_IA32_PEBS_DATA_CFG,
+                                  env->msr_pebs_data_cfg);
+            }
         }
 
         /*
@@ -3177,6 +3185,9 @@ static int kvm_get_msrs(X86CPU *cpu)
         if (has_msr_ds_area) {
             kvm_msr_entry_add(cpu, MSR_IA32_DS_AREA, 0);
         }
+        if (has_msr_pebs_data_cfg) {
+            kvm_msr_entry_add(cpu, MSR_IA32_PEBS_DATA_CFG, 0);
+        }
     }
 
     if (env->mcg_cap) {
@@ -3431,6 +3442,9 @@ static int kvm_get_msrs(X86CPU *cpu)
         case MSR_IA32_DS_AREA:
             env->msr_ds_area = msrs[i].data;
             break;
+        case MSR_IA32_PEBS_DATA_CFG:
+            env->msr_pebs_data_cfg = msrs[i].data;
+            break;
         case HV_X64_MSR_HYPERCALL:
             env->msr_hv_hypercall = msrs[i].data;
             break;
diff --git a/target/i386/machine.c b/target/i386/machine.c
index 82a2101..58b786d 100644
--- a/target/i386/machine.c
+++ b/target/i386/machine.c
@@ -670,6 +670,29 @@ static const VMStateDescription vmstate_msr_pebs_via_ds = {
     }
 };
 
+static bool pebs_baseline_needed(void *opaque)
+{
+    X86CPU *cpu = opaque;
+    CPUX86State *env = &cpu->env;
+
+    if (env->msr_pebs_data_cfg) {
+        return true;
+    }
+
+    return false;
+}
+
+static const VMStateDescription vmstate_msr_pebs_baseline = {
+    .name = "cpu/msr_pebs_baseline",
+    .version_id = 1,
+    .minimum_version_id = 1,
+    .needed = pebs_baseline_needed,
+    .fields = (VMStateField[]) {
+        VMSTATE_UINT64(env.msr_pebs_data_cfg, X86CPU),
+        VMSTATE_END_OF_LIST()
+    }
+};
+
 static bool mpx_needed(void *opaque)
 {
     X86CPU *cpu = opaque;
@@ -1424,6 +1447,7 @@ VMStateDescription vmstate_x86_cpu = {
         &vmstate_msr_ia32_feature_control,
         &vmstate_msr_architectural_pmu,
         &vmstate_msr_pebs_via_ds,
+        &vmstate_msr_pebs_baseline,
         &vmstate_mpx,
         &vmstate_msr_hypercall_hypercall,
         &vmstate_msr_hyperv_vapic,
-- 
1.8.3.1