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* [kvm-unit-tests PATCH v2 0/2] x86: SPEC_CTRL tests
@ 2021-01-29  0:36 Babu Moger
  2021-01-29  0:36 ` [kvm-unit-tests PATCH v2 1/2] x86: Add SPEC CTRL detection tests Babu Moger
  2021-01-29  0:36 ` [kvm-unit-tests PATCH v2 2/2] x86: svm: Add SPEC_CTRL feature test Babu Moger
  0 siblings, 2 replies; 3+ messages in thread
From: Babu Moger @ 2021-01-29  0:36 UTC (permalink / raw)
  Cc: kvm

Add SPEC_CTRL detection and verification tests.
---
v2:
   Added svm SPEC_CTRL verification tests.
   Changed few texts.

v1: https://lore.kernel.org/kvm/160865324865.19910.5159218511905134908.stgit@bmoger-ubuntu/

Babu Moger (2):
      x86: Add SPEC CTRL detection tests
      x86: svm: Add SPEC_CTRL feature test


 lib/x86/processor.h |    5 +++++
 x86/Makefile.x86_64 |    1 +
 x86/spec_ctrl.c     |   30 +++++++++++++++++++++++++++++
 x86/svm_tests.c     |   52 +++++++++++++++++++++++++++++++++++++++++++++++++++
 x86/unittests.cfg   |    5 +++++
 5 files changed, 93 insertions(+)
 create mode 100644 x86/spec_ctrl.c

--

^ permalink raw reply	[flat|nested] 3+ messages in thread

* [kvm-unit-tests PATCH v2 1/2] x86: Add SPEC CTRL detection tests
  2021-01-29  0:36 [kvm-unit-tests PATCH v2 0/2] x86: SPEC_CTRL tests Babu Moger
@ 2021-01-29  0:36 ` Babu Moger
  2021-01-29  0:36 ` [kvm-unit-tests PATCH v2 2/2] x86: svm: Add SPEC_CTRL feature test Babu Moger
  1 sibling, 0 replies; 3+ messages in thread
From: Babu Moger @ 2021-01-29  0:36 UTC (permalink / raw)
  Cc: kvm

Detect the available SPEC CTRL settings on the host.

Signed-off-by: Babu Moger <babu.moger@amd.com>
---
 lib/x86/processor.h |    5 +++++
 x86/Makefile.x86_64 |    1 +
 x86/spec_ctrl.c     |   30 ++++++++++++++++++++++++++++++
 x86/unittests.cfg   |    5 +++++
 4 files changed, 41 insertions(+)
 create mode 100644 x86/spec_ctrl.c

diff --git a/lib/x86/processor.h b/lib/x86/processor.h
index 87112bd..40caac1 100644
--- a/lib/x86/processor.h
+++ b/lib/x86/processor.h
@@ -159,7 +159,9 @@ static inline u8 cpuid_maxphyaddr(void)
 #define	X86_FEATURE_LA57		(CPUID(0x7, 0, ECX, 16))
 #define	X86_FEATURE_RDPID		(CPUID(0x7, 0, ECX, 22))
 #define	X86_FEATURE_SPEC_CTRL		(CPUID(0x7, 0, EDX, 26))
+#define X86_FEATURE_STIBP		(CPUID(0x7, 0, EDX, 27))
 #define	X86_FEATURE_ARCH_CAPABILITIES	(CPUID(0x7, 0, EDX, 29))
+#define X86_FEATURE_SSBD		(CPUID(0x7, 0, EDX, 31))
 #define	X86_FEATURE_PKS			(CPUID(0x7, 0, ECX, 31))
 #define	X86_FEATURE_NX			(CPUID(0x80000001, 0, EDX, 20))
 #define	X86_FEATURE_RDPRU		(CPUID(0x80000008, 0, EBX, 4))
@@ -170,6 +172,9 @@ static inline u8 cpuid_maxphyaddr(void)
 #define	X86_FEATURE_SVM			(CPUID(0x80000001, 0, ECX, 2))
 #define	X86_FEATURE_RDTSCP		(CPUID(0x80000001, 0, EDX, 27))
 #define	X86_FEATURE_AMD_IBPB		(CPUID(0x80000008, 0, EBX, 12))
+#define	X86_FEATURE_AMD_IBRS		(CPUID(0x80000008, 0, EBX, 14))
+#define	X86_FEATURE_AMD_STIBP		(CPUID(0x80000008, 0, EBX, 15))
+#define	X86_FEATURE_AMD_SSBD		(CPUID(0x80000008, 0, EBX, 24))
 #define	X86_FEATURE_NPT			(CPUID(0x8000000A, 0, EDX, 0))
 #define	X86_FEATURE_NRIPS		(CPUID(0x8000000A, 0, EDX, 3))
 
diff --git a/x86/Makefile.x86_64 b/x86/Makefile.x86_64
index 3a353df..79e4586 100644
--- a/x86/Makefile.x86_64
+++ b/x86/Makefile.x86_64
@@ -21,6 +21,7 @@ tests += $(TEST_DIR)/intel-iommu.flat
 tests += $(TEST_DIR)/vmware_backdoors.flat
 tests += $(TEST_DIR)/rdpru.flat
 tests += $(TEST_DIR)/pks.flat
+tests += $(TEST_DIR)/spec_ctrl.flat
 
 include $(SRCDIR)/$(TEST_DIR)/Makefile.common
 
diff --git a/x86/spec_ctrl.c b/x86/spec_ctrl.c
new file mode 100644
index 0000000..7359a9d
--- /dev/null
+++ b/x86/spec_ctrl.c
@@ -0,0 +1,30 @@
+/* SPEC CTRL Tests */
+
+#include "libcflat.h"
+#include "processor.h"
+
+int main(int ac, char **av)
+{
+	if (this_cpu_has(X86_FEATURE_AMD_IBPB))
+		report(true, "X86_FEATURE_AMD_IBPB detected");
+
+	if (this_cpu_has(X86_FEATURE_AMD_IBRS))
+		report(true, "X86_FEATURE_AMD_IBRS detected");
+
+	if (this_cpu_has(X86_FEATURE_AMD_STIBP))
+		report(true, "X86_FEATURE_AMD_STIBP detected");
+
+	if (this_cpu_has(X86_FEATURE_AMD_SSBD))
+		report(true, "X86_FEATURE_AMD_SSBD detected");
+
+	if (this_cpu_has(X86_FEATURE_SPEC_CTRL))
+		report(true, "X86_FEATURE_SPEC_CTRL(IBRS and IBPB) detected");
+
+	if (this_cpu_has(X86_FEATURE_STIBP))
+		report(true, "X86_FEATURE_STIBP detected");
+
+	if (this_cpu_has(X86_FEATURE_SSBD))
+		report(true, "X86_FEATURE_SSBD detected");
+
+	return report_summary();
+}
diff --git a/x86/unittests.cfg b/x86/unittests.cfg
index 90e370f..b3c5320 100644
--- a/x86/unittests.cfg
+++ b/x86/unittests.cfg
@@ -251,6 +251,11 @@ file = rdpru.flat
 extra_params = -cpu max
 arch = x86_64
 
+[spec_ctrl]
+file = spec_ctrl.flat
+extra_params = -cpu host
+arch = x86_64
+
 [umip]
 file = umip.flat
 extra_params = -cpu qemu64,+umip


^ permalink raw reply related	[flat|nested] 3+ messages in thread

* [kvm-unit-tests PATCH v2 2/2] x86: svm: Add SPEC_CTRL feature test
  2021-01-29  0:36 [kvm-unit-tests PATCH v2 0/2] x86: SPEC_CTRL tests Babu Moger
  2021-01-29  0:36 ` [kvm-unit-tests PATCH v2 1/2] x86: Add SPEC CTRL detection tests Babu Moger
@ 2021-01-29  0:36 ` Babu Moger
  1 sibling, 0 replies; 3+ messages in thread
From: Babu Moger @ 2021-01-29  0:36 UTC (permalink / raw)
  Cc: kvm

Add the SPEC_CTRL tests for SVM and make sure the settings on L2
guests does not overwrite the L1 guest's SPEC_CTRL settings.

Test Method.
1. Save the L1 guests SPEC_CTRL settings(rdmsr). Normally 0.
2. Start the L2 guest
3. Change the L2 guests SPEC_CTRL settings.
4. Exit the L2 guest.
5. Verify if the settings from step #1 still holds.

Signed-off-by: Babu Moger <babu.moger@amd.com>
---
 x86/svm_tests.c |   52 ++++++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 52 insertions(+)

diff --git a/x86/svm_tests.c b/x86/svm_tests.c
index 29a0b59..2867337 100644
--- a/x86/svm_tests.c
+++ b/x86/svm_tests.c
@@ -2002,6 +2002,55 @@ static bool init_intercept_check(struct svm_test *test)
     return init_intercept;
 }
 
+/* Indirect Branch Restricted Speculation(bit 0) */
+#define SPEC_CTRL_IBRS        1
+/* Single Thread Indirect Branch Predictor (STIBP)(bit 1) */
+#define SPEC_CTRL_STIBP       2
+/* Speculative Store Bypass Disable (bit 2) */
+#define SPEC_CTRL_SSBD        4
+
+static bool spec_ctrl_supported(void)
+{
+    return this_cpu_has(X86_FEATURE_AMD_SSBD) ||
+           this_cpu_has(X86_FEATURE_AMD_STIBP) ||
+           this_cpu_has(X86_FEATURE_AMD_IBRS);
+}
+
+static void spec_ctrl_prepare(struct svm_test *test)
+{
+    vmcb_ident(vmcb);
+    test->scratch = rdmsr(MSR_IA32_SPEC_CTRL);
+}
+
+/*
+ * Write it twice to bypass the interception. The first write to
+ * SPEC_CTRL is intercepted in older kernels.
+ */
+static void spec_ctrl_test(struct svm_test *test)
+{
+    int spec_ctrl = 0;
+
+    if (this_cpu_has(X86_FEATURE_AMD_SSBD))
+        spec_ctrl |= SPEC_CTRL_SSBD;
+    if (this_cpu_has(X86_FEATURE_AMD_STIBP))
+        spec_ctrl |= SPEC_CTRL_STIBP;
+    if (this_cpu_has(X86_FEATURE_AMD_IBRS))
+        spec_ctrl |= SPEC_CTRL_IBRS;
+
+    wrmsr(MSR_IA32_SPEC_CTRL, spec_ctrl);
+    wrmsr(MSR_IA32_SPEC_CTRL, spec_ctrl);
+}
+
+static bool spec_ctrl_finished(struct svm_test *test)
+{
+    return vmcb->control.exit_code == SVM_EXIT_VMMCALL;
+}
+
+static bool spec_ctrl_check(struct svm_test *test)
+{
+    return test->scratch == rdmsr(MSR_IA32_SPEC_CTRL);
+}
+
 #define TEST(name) { #name, .v2 = name }
 
 /*
@@ -2492,6 +2541,9 @@ struct svm_test svm_tests[] = {
     { "svm_init_intercept_test", smp_supported, init_intercept_prepare,
       default_prepare_gif_clear, init_intercept_test,
       init_intercept_finished, init_intercept_check, .on_vcpu = 2 },
+    { "SPEC_CTRL", spec_ctrl_supported, spec_ctrl_prepare,
+      default_prepare_gif_clear, spec_ctrl_test,
+      spec_ctrl_finished, spec_ctrl_check },
     TEST(svm_cr4_osxsave_test),
     TEST(svm_guest_state_test),
     TEST(svm_vmrun_errata_test),


^ permalink raw reply related	[flat|nested] 3+ messages in thread

end of thread, other threads:[~2021-01-29  0:39 UTC | newest]

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