From: Eric Auger <eric.auger@redhat.com>
To: eric.auger.pro@gmail.com, eric.auger@redhat.com, maz@kernel.org,
kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org,
qemu-devel@nongnu.org, qemu-arm@nongnu.org
Cc: andrew.murray@arm.com, andre.przywara@arm.com
Subject: [kvm-unit-tests PATCH v2 6/9] arm: pmu: Test chained counter
Date: Thu, 30 Jan 2020 12:25:07 +0100 [thread overview]
Message-ID: <20200130112510.15154-7-eric.auger@redhat.com> (raw)
In-Reply-To: <20200130112510.15154-1-eric.auger@redhat.com>
Add 2 tests exercising chained counters. The first one uses
CPU_CYCLES and the second one uses SW_INCR.
Signed-off-by: Eric Auger <eric.auger@redhat.com>
---
arm/pmu.c | 128 ++++++++++++++++++++++++++++++++++++++++++++++
arm/unittests.cfg | 12 +++++
2 files changed, 140 insertions(+)
diff --git a/arm/pmu.c b/arm/pmu.c
index 1b0101f..538fbeb 100644
--- a/arm/pmu.c
+++ b/arm/pmu.c
@@ -113,6 +113,8 @@ static void test_event_introspection(void) {}
static void test_event_counter_config(void) {}
static void test_basic_event_count(void) {}
static void test_mem_access(void) {}
+static void test_chained_counters(void) {}
+static void test_chained_sw_incr(void) {}
#elif defined(__aarch64__)
#define ID_AA64DFR0_PERFMON_SHIFT 8
@@ -458,6 +460,126 @@ static void test_mem_access(void)
read_sysreg(pmovsclr_el0));
}
+static void test_chained_counters(void)
+{
+ uint32_t events[] = { 0x11 /* CPU_CYCLES */, 0x1E /* CHAIN */};
+
+ if (!satisfy_prerequisites(events, ARRAY_SIZE(events)))
+ return;
+
+ pmu_reset();
+
+ write_regn(pmevtyper, 0, events[0] | PMEVTYPER_EXCLUDE_EL0);
+ write_regn(pmevtyper, 1, events[1] | PMEVTYPER_EXCLUDE_EL0);
+ /* enable counters #0 and #1 */
+ write_sysreg_s(0x3, PMCNTENSET_EL0);
+ /* preset counter #0 at 0xFFFFFFF0 */
+ write_regn(pmevcntr, 0, 0xFFFFFFF0);
+
+ precise_instrs_loop(22, pmu.pmcr_ro | PMU_PMCR_E);
+
+ report(read_regn(pmevcntr, 1) == 1, "CHAIN counter #1 incremented");
+ report(!read_sysreg(pmovsclr_el0), "check no overflow is recorded");
+
+ /* test 64b overflow */
+
+ pmu_reset();
+ write_sysreg_s(0x3, PMCNTENSET_EL0);
+
+ write_regn(pmevcntr, 0, 0xFFFFFFF0);
+ write_regn(pmevcntr, 1, 0x1);
+ precise_instrs_loop(22, pmu.pmcr_ro | PMU_PMCR_E);
+ report_info("overflow reg = 0x%lx", read_sysreg(pmovsclr_el0));
+ report(read_regn(pmevcntr, 1) == 2, "CHAIN counter #1 incremented");
+ report(!read_sysreg(pmovsclr_el0), "check no overflow is recorded");
+
+ write_regn(pmevcntr, 0, 0xFFFFFFF0);
+ write_regn(pmevcntr, 1, 0xFFFFFFFF);
+
+ precise_instrs_loop(22, pmu.pmcr_ro | PMU_PMCR_E);
+ report_info("overflow reg = 0x%lx", read_sysreg(pmovsclr_el0));
+ report(!read_regn(pmevcntr, 1), "CHAIN counter #1 wrapped");
+ report(read_sysreg(pmovsclr_el0) == 0x2,
+ "check no overflow is recorded");
+}
+
+static void test_chained_sw_incr(void)
+{
+ uint32_t events[] = { 0x0 /* SW_INCR */, 0x0 /* SW_INCR */};
+ int i;
+
+ if (!satisfy_prerequisites(events, ARRAY_SIZE(events)))
+ return;
+
+ pmu_reset();
+
+ write_regn(pmevtyper, 0, events[0] | PMEVTYPER_EXCLUDE_EL0);
+ write_regn(pmevtyper, 1, events[1] | PMEVTYPER_EXCLUDE_EL0);
+ /* enable counters #0 and #1 */
+ write_sysreg_s(0x3, PMCNTENSET_EL0);
+
+ /* preset counter #0 at 0xFFFFFFF0 */
+ write_regn(pmevcntr, 0, 0xFFFFFFF0);
+
+ for (i = 0; i < 100; i++)
+ write_sysreg(0x1, pmswinc_el0);
+
+ report_info("SW_INCR counter #0 has value %ld", read_regn(pmevcntr, 0));
+ report(read_regn(pmevcntr, 0) == 0xFFFFFFF0,
+ "PWSYNC does not increment if PMCR.E is unset");
+
+ pmu_reset();
+
+ write_regn(pmevcntr, 0, 0xFFFFFFF0);
+ write_sysreg_s(0x3, PMCNTENSET_EL0);
+ set_pmcr(pmu.pmcr_ro | PMU_PMCR_E);
+
+ for (i = 0; i < 100; i++)
+ write_sysreg(0x3, pmswinc_el0);
+
+ report(read_regn(pmevcntr, 0) == 84, "counter #1 after + 100 SW_INCR");
+ report(read_regn(pmevcntr, 1) == 100,
+ "counter #0 after + 100 SW_INCR");
+ report_info("counter values after 100 SW_INCR #0=%ld #1=%ld",
+ read_regn(pmevcntr, 0), read_regn(pmevcntr, 1));
+ report(read_sysreg(pmovsclr_el0) == 0x1,
+ "overflow reg after 100 SW_INCR");
+
+ /* 64b SW_INCR */
+ pmu_reset();
+
+ events[1] = 0x1E /* CHAIN */;
+ write_regn(pmevtyper, 1, events[1] | PMEVTYPER_EXCLUDE_EL0);
+ write_regn(pmevcntr, 0, 0xFFFFFFF0);
+ write_sysreg_s(0x3, PMCNTENSET_EL0);
+ set_pmcr(pmu.pmcr_ro | PMU_PMCR_E);
+ for (i = 0; i < 100; i++)
+ write_sysreg(0x3, pmswinc_el0);
+
+ report(!read_sysreg(pmovsclr_el0) && (read_regn(pmevcntr, 1) == 1),
+ "overflow reg after 100 SW_INCR/CHAIN");
+ report_info("overflow=0x%lx, #0=%ld #1=%ld", read_sysreg(pmovsclr_el0),
+ read_regn(pmevcntr, 0), read_regn(pmevcntr, 1));
+
+ /* 64b SW_INCR and overflow on CHAIN counter*/
+ pmu_reset();
+
+ write_regn(pmevtyper, 1, events[1] | PMEVTYPER_EXCLUDE_EL0);
+ write_regn(pmevcntr, 0, 0xFFFFFFF0);
+ write_regn(pmevcntr, 1, 0xFFFFFFFF);
+ write_sysreg_s(0x3, PMCNTENSET_EL0);
+ set_pmcr(pmu.pmcr_ro | PMU_PMCR_E);
+ for (i = 0; i < 100; i++)
+ write_sysreg(0x3, pmswinc_el0);
+
+ report((read_sysreg(pmovsclr_el0) == 0x2) &&
+ (read_regn(pmevcntr, 1) == 0) &&
+ (read_regn(pmevcntr, 0) == 84),
+ "overflow reg after 100 SW_INCR/CHAIN");
+ report_info("overflow=0x%lx, #0=%ld #1=%ld", read_sysreg(pmovsclr_el0),
+ read_regn(pmevcntr, 0), read_regn(pmevcntr, 1));
+}
+
#endif
/*
@@ -657,6 +779,12 @@ int main(int argc, char *argv[])
} else if (strcmp(argv[1], "mem-access") == 0) {
report_prefix_push(argv[1]);
test_mem_access();
+ } else if (strcmp(argv[1], "chained-counters") == 0) {
+ report_prefix_push(argv[1]);
+ test_chained_counters();
+ } else if (strcmp(argv[1], "chained-sw-incr") == 0) {
+ report_prefix_push(argv[1]);
+ test_chained_sw_incr();
} else {
report_abort("Unknown sub-test '%s'", argv[1]);
}
diff --git a/arm/unittests.cfg b/arm/unittests.cfg
index 7a59403..1bd4319 100644
--- a/arm/unittests.cfg
+++ b/arm/unittests.cfg
@@ -90,6 +90,18 @@ groups = pmu
arch = arm64
extra_params = -append 'mem-access'
+[pmu-chained-counters]
+file = pmu.flat
+groups = pmu
+arch = arm64
+extra_params = -append 'chained-counters'
+
+[pmu-chained-sw-incr]
+file = pmu.flat
+groups = pmu
+arch = arm64
+extra_params = -append 'chained-sw-incr'
+
# Test PMU support (TCG) with -icount IPC=1
#[pmu-tcg-icount-1]
#file = pmu.flat
--
2.20.1
_______________________________________________
kvmarm mailing list
kvmarm@lists.cs.columbia.edu
https://lists.cs.columbia.edu/mailman/listinfo/kvmarm
next prev parent reply other threads:[~2020-01-30 11:26 UTC|newest]
Thread overview: 38+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-01-30 11:25 [kvm-unit-tests PATCH v2 0/9] KVM: arm64: PMUv3 Event Counter Tests Eric Auger
2020-01-30 11:25 ` [kvm-unit-tests PATCH v2 1/9] arm64: Provide read/write_sysreg_s Eric Auger
2020-01-30 11:25 ` [kvm-unit-tests PATCH v2 2/9] arm: pmu: Let pmu tests take a sub-test parameter Eric Auger
2020-03-04 18:01 ` Andre Przywara
2020-03-05 8:44 ` Andrew Jones
2020-01-30 11:25 ` [kvm-unit-tests PATCH v2 3/9] arm: pmu: Add a pmu struct Eric Auger
2020-03-04 18:02 ` Andre Przywara
2020-03-04 18:21 ` Auger Eric
2020-03-05 8:53 ` Andrew Jones
2020-01-30 11:25 ` [kvm-unit-tests PATCH v2 4/9] arm: pmu: Check Required Event Support Eric Auger
2020-02-11 15:33 ` Peter Maydell
2020-02-11 18:08 ` Auger Eric
2020-02-11 16:28 ` Peter Maydell
2020-02-11 18:32 ` Auger Eric
2020-03-04 18:02 ` Andre Przywara
2020-03-05 9:04 ` Andrew Jones
2020-01-30 11:25 ` [kvm-unit-tests PATCH v2 5/9] arm: pmu: Basic event counter Tests Eric Auger
2020-02-11 16:27 ` Peter Maydell
2020-02-11 18:31 ` Auger Eric
2020-03-04 18:03 ` Andre Przywara
2020-03-05 9:33 ` Andrew Jones
2020-03-12 11:19 ` Auger Eric
2020-03-05 9:42 ` Andrew Jones
2020-03-12 11:16 ` Auger Eric
2020-01-30 11:25 ` Eric Auger [this message]
2020-02-11 16:24 ` [kvm-unit-tests PATCH v2 6/9] arm: pmu: Test chained counter Peter Maydell
2020-02-11 18:30 ` Auger Eric
2020-03-05 9:37 ` Andrew Jones
2020-01-30 11:25 ` [kvm-unit-tests PATCH v2 7/9] arm: pmu: test 32-bit <-> 64-bit transitions Eric Auger
2020-03-05 9:50 ` Andrew Jones
2020-01-30 11:25 ` [kvm-unit-tests PATCH v2 8/9] arm: gic: Provide per-IRQ helper functions Eric Auger
2020-03-05 9:55 ` Andrew Jones
2020-03-05 11:10 ` Alexandru Elisei
2020-01-30 11:25 ` [kvm-unit-tests PATCH v2 9/9] arm: pmu: Test overflow interrupts Eric Auger
2020-03-05 10:17 ` Andrew Jones
2020-02-11 15:42 ` [kvm-unit-tests PATCH v2 0/9] KVM: arm64: PMUv3 Event Counter Tests Peter Maydell
2020-02-11 16:07 ` Andrew Jones
2020-02-11 18:23 ` Auger Eric
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20200130112510.15154-7-eric.auger@redhat.com \
--to=eric.auger@redhat.com \
--cc=andre.przywara@arm.com \
--cc=andrew.murray@arm.com \
--cc=eric.auger.pro@gmail.com \
--cc=kvm@vger.kernel.org \
--cc=kvmarm@lists.cs.columbia.edu \
--cc=maz@kernel.org \
--cc=qemu-arm@nongnu.org \
--cc=qemu-devel@nongnu.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).