From: Jeremy Linton <jeremy.linton@arm.com>
To: Sudeep Holla <sudeep.holla@arm.com>
Cc: linux-arm-kernel@lists.infradead.org, linux-acpi@vger.kernel.org,
catalin.marinas@arm.com, will.deacon@arm.com, rjw@rjwysocki.net,
lenb@kernel.org, mark.rutland@arm.com, lorenzo.pieralisi@arm.com,
linuxarm@huawei.com, john.garry@huawei.com
Subject: Re: [PATCH v3 4/5] arm_pmu: acpi: spe: Add initial MADT/SPE probing
Date: Fri, 7 Jun 2019 08:28:04 -0500 [thread overview]
Message-ID: <b4d7d954-5667-c32d-80ae-c45678d3f0e3@arm.com> (raw)
In-Reply-To: <20190607095729.GD2429@e107155-lin>
Hi,
On 6/7/19 4:57 AM, Sudeep Holla wrote:
> On Fri, May 03, 2019 at 06:24:06PM -0500, Jeremy Linton wrote:
>> ACPI 6.3 adds additional fields to the MADT GICC
>> structure to describe SPE PPI's. We pick these out
>> of the cached reference to the madt_gicc structure
>> similarly to the core PMU code. We then create a platform
>> device referring to the IRQ and let the user/module loader
>> decide whether to load the SPE driver.
>>
>> Signed-off-by: Jeremy Linton <jeremy.linton@arm.com>
>> ---
>> arch/arm64/include/asm/acpi.h | 3 ++
>> drivers/perf/Kconfig | 5 +++
>> drivers/perf/arm_pmu_acpi.c | 76 +++++++++++++++++++++++++++++++++++
>> include/linux/perf/arm_pmu.h | 2 +
>> 4 files changed, 86 insertions(+)
>>
>> diff --git a/arch/arm64/include/asm/acpi.h b/arch/arm64/include/asm/acpi.h
>> index 7628efbe6c12..d10399b9f998 100644
>> --- a/arch/arm64/include/asm/acpi.h
>> +++ b/arch/arm64/include/asm/acpi.h
>> @@ -41,6 +41,9 @@
>> (!(entry) || (entry)->header.length < ACPI_MADT_GICC_MIN_LENGTH || \
>> (unsigned long)(entry) + (entry)->header.length > (end))
>>
>> +#define ACPI_MADT_GICC_SPE (ACPI_OFFSET(struct acpi_madt_generic_interrupt, \
>> + spe_interrupt) + sizeof(u16))
>> +
>> /* Basic configuration for ACPI */
>> #ifdef CONFIG_ACPI
>> pgprot_t __acpi_get_mem_attribute(phys_addr_t addr);
>> diff --git a/drivers/perf/Kconfig b/drivers/perf/Kconfig
>> index af9bc178495d..bc2647c64c9d 100644
>> --- a/drivers/perf/Kconfig
>> +++ b/drivers/perf/Kconfig
>> @@ -52,6 +52,11 @@ config ARM_PMU_ACPI
>> depends on ARM_PMU && ACPI
>> def_bool y
>>
>> +config ARM_SPE_ACPI
>> + depends on ARM_PMU_ACPI && ARM_SPE_PMU
>> + def_bool y
>> +
>> +
>> config ARM_DSU_PMU
>> tristate "ARM DynamIQ Shared Unit (DSU) PMU"
>> depends on ARM64
>> diff --git a/drivers/perf/arm_pmu_acpi.c b/drivers/perf/arm_pmu_acpi.c
>> index 0f197516d708..b0244e1e8c91 100644
>> --- a/drivers/perf/arm_pmu_acpi.c
>> +++ b/drivers/perf/arm_pmu_acpi.c
>> @@ -74,6 +74,80 @@ static void arm_pmu_acpi_unregister_irq(int cpu)
>> acpi_unregister_gsi(gsi);
>> }
>>
>> +#ifdef CONFIG_ARM_SPE_ACPI
>> +static struct resource spe_resources[] = {
>> + {
>> + /* irq */
>> + .flags = IORESOURCE_IRQ,
>> + }
>> +};
>> +
>> +static struct platform_device spe_dev = {
>> + .name = ARMV8_SPE_PDEV_NAME,
>> + .id = -1,
>> + .resource = spe_resources,
>> + .num_resources = ARRAY_SIZE(spe_resources)
>> +};
>> +
>> +/*
>> + * For lack of a better place, hook the normal PMU MADT walk
>> + * and create a SPE device if we detect a recent MADT with
>> + * a homogeneous PPI mapping.
>> + */
>> +static int arm_spe_acpi_register_device(void)
>> +{
>> + int cpu, ret, irq;
>> + int hetid;
>> + u16 gsi = 0;
>> + bool first = true;
>> +
>> + struct acpi_madt_generic_interrupt *gicc;
>> +
>> + /*
>> + * sanity check all the GICC tables for the same interrupt number
>> + * for now we only support homogeneous ACPI/SPE machines.
>> + */
>> + for_each_possible_cpu(cpu) {
>> + gicc = acpi_cpu_get_madt_gicc(cpu);
>> +
>> + if (gicc->header.length < ACPI_MADT_GICC_SPE)
>> + return -ENODEV;
>> + if (first) {
>> + gsi = gicc->spe_interrupt;
>> + if (!gsi)
>> + return -ENODEV;
>> + hetid = find_acpi_cpu_topology_hetero_id(cpu);
>> + first = false;
>> + } else if ((gsi != gicc->spe_interrupt) ||
>> + (hetid != find_acpi_cpu_topology_hetero_id(cpu))) {
>
> Sorry, I should have noticed this in patch 2 itself. Won't this break for
> multi-socket system ? The hetid in that case will be package id, no ?
Your assuming a PPTT with multiple trees, one for each socket? Yes it
breaks in that case, and is what I was complaining about in the cover
letter because there won't be a common node with the IDENTICAL flag set.
OTOH, I think it works fine for multi-socket given a single tree where
the root has IDENTICAL set (I did some very light testing on such a
machine).
I don't think there is a solution to this problem that won't break in
the case of a heterogeneous machine with multiple sockets populated with
differing cores.
>
> Otherwise the patch looks good.
>
> --
> Regards,
> Sudeep
>
next prev parent reply other threads:[~2019-06-07 13:28 UTC|newest]
Thread overview: 40+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-05-03 23:24 [PATCH v3 0/5] arm64: SPE ACPI enablement Jeremy Linton
2019-05-03 23:24 ` Jeremy Linton
2019-05-03 23:24 ` [PATCH v3 1/5] ACPI/PPTT: Trivial, change the capitalization of CPU Jeremy Linton
2019-05-03 23:24 ` Jeremy Linton
2019-05-07 18:12 ` Jeremy Linton
2019-05-07 18:12 ` Jeremy Linton
2019-05-03 23:24 ` [PATCH v3 2/5] ACPI/PPTT: Add function to return ACPI 6.3 Identical tokens Jeremy Linton
2019-05-03 23:24 ` Jeremy Linton
2019-05-05 7:09 ` Kefeng Wang
2019-05-05 7:09 ` Kefeng Wang
2019-05-07 18:26 ` Jeremy Linton
2019-05-07 18:26 ` Jeremy Linton
2019-06-07 9:49 ` Sudeep Holla
2019-05-03 23:24 ` [PATCH v3 3/5] ACPI/PPTT: Modify node flag detection to find last IDENTICAL Jeremy Linton
2019-05-03 23:24 ` Jeremy Linton
2019-06-07 9:53 ` Sudeep Holla
2019-06-07 13:15 ` Jeremy Linton
2019-06-07 13:47 ` Sudeep Holla
2019-05-03 23:24 ` [PATCH v3 4/5] arm_pmu: acpi: spe: Add initial MADT/SPE probing Jeremy Linton
2019-05-03 23:24 ` Jeremy Linton
2019-05-08 11:18 ` John Garry
2019-05-08 20:04 ` Jeremy Linton
2019-06-07 9:57 ` Sudeep Holla
2019-06-07 13:28 ` Jeremy Linton [this message]
2019-06-07 13:37 ` Sudeep Holla
2019-05-03 23:24 ` [PATCH v3 5/5] perf: arm_spe: Enable ACPI/Platform automatic module loading Jeremy Linton
2019-05-03 23:24 ` Jeremy Linton
2019-05-04 11:06 ` [PATCH v3 0/5] arm64: SPE ACPI enablement Hanjun Guo
2019-05-04 11:06 ` Hanjun Guo
2019-05-07 17:58 ` Jeremy Linton
2019-05-07 17:58 ` Jeremy Linton
2019-05-08 9:35 ` Hanjun Guo
2019-05-08 16:51 ` Sudeep Holla
2019-05-09 9:28 ` Will Deacon
2019-05-09 10:35 ` Sudeep Holla
2019-05-09 14:13 ` Sudeep Holla
2019-05-13 10:56 ` Will Deacon
2019-05-13 11:31 ` Sudeep Holla
2019-05-13 11:10 ` Hanjun Guo
2019-05-08 16:45 ` Sudeep Holla
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=b4d7d954-5667-c32d-80ae-c45678d3f0e3@arm.com \
--to=jeremy.linton@arm.com \
--cc=catalin.marinas@arm.com \
--cc=john.garry@huawei.com \
--cc=lenb@kernel.org \
--cc=linux-acpi@vger.kernel.org \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linuxarm@huawei.com \
--cc=lorenzo.pieralisi@arm.com \
--cc=mark.rutland@arm.com \
--cc=rjw@rjwysocki.net \
--cc=sudeep.holla@arm.com \
--cc=will.deacon@arm.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).