[QUESTION] Convert axg-audio-clkc to YAML format

[QUESTION] Convert axg-audio-clkc to YAML format

[Jan Dakinevich]

Previously we discussed how to implement dt-schema for audio clock controller in
Amlogic SoC [1]. Also, there was an earlier attempt to convert to yaml [2].

Let me remind you that the problem is that only "pclk" clock of this controller.
Other clocks are optional and they are allowed to be not routed.

I can suggest two approaches how to deal with this. Could you please tell me
which of them is more correct?

Approach 1: use 'additionalItems' to declare optional clocks.
Pros: 
 - it is short and simple;
 - no need to modify existing DTSIs.
Cons:
 - checking works but 'additionalItems' doesn't expect no-boolean value [3]
 - there is reasoning that all clocks should be specified ragardless if they are
   used or not [3][4].

Approach 2: assume that all clocks are mandatory and declare all of them.
Pros:
 - it is more common and compatible with existing meta-schemas;
 - may be architecturally it is more correct.
Cons:
 - boilerplate in schema and in DTSIs;
 - requires modification of existing DTSIs.

Links:
[1] https://lore.kernel.org/lkml/20240419125812.983409-5-jan.dakinevich@salutedevices.com/
[2] https://lore.kernel.org/linux-devicetree/20230808194811.113087-1-alexander.stein@mailbox.org/
[3] https://lore.kernel.org/lkml/20240419210949.GA3979121-robh@kernel.org/
[4] https://lore.kernel.org/lkml/07b1ca57-49a0-4151-99bf-caac053eaa01@kernel.org/

-- 
2.34.1


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[APPROACH 1 1/1] dt-bindings: clock: meson: Convert axg-audio-clkc to YAML format

[Jan Dakinevich]

From: Alexander Stein <alexander.stein@mailbox.org>

Convert Amlogic AXG Audio Clock Controller binding to yaml.

Signed-off-by: Alexander Stein <alexander.stein@mailbox.org>
Signed-off-by: Jan Dakinevich <jan.dakinevich@salutedevices.com>
---
 .../bindings/clock/amlogic,axg-audio-clkc.txt |  59 ---------
 .../clock/amlogic,axg-audio-clkc.yaml         | 115 ++++++++++++++++++
 2 files changed, 115 insertions(+), 59 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.txt
 create mode 100644 Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.yaml

diff --git a/Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.txt b/Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.txt
deleted file mode 100644
index 3a8948c04bc9..000000000000
--- a/Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.txt
+++ /dev/null
@@ -1,59 +0,0 @@
-* Amlogic AXG Audio Clock Controllers
-
-The Amlogic AXG audio clock controller generates and supplies clock to the
-other elements of the audio subsystem, such as fifos, i2s, spdif and pdm
-devices.
-
-Required Properties:
-
-- compatible	: should be "amlogic,axg-audio-clkc" for the A113X and A113D,
-		  "amlogic,g12a-audio-clkc" for G12A,
-		  "amlogic,sm1-audio-clkc" for S905X3.
-- reg		: physical base address of the clock controller and length of
-		  memory mapped region.
-- clocks	: a list of phandle + clock-specifier pairs for the clocks listed
-		  in clock-names.
-- clock-names	: must contain the following:
-		  * "pclk" - Main peripheral bus clock
-		  may contain the following:
-		  * "mst_in[0-7]" - 8 input plls to generate clock signals
-		  * "slv_sclk[0-9]" - 10 slave bit clocks provided by external
-				      components.
-		  * "slv_lrclk[0-9]" - 10 slave sample clocks provided by external
-				       components.
-- resets	: phandle of the internal reset line
-- #clock-cells	: should be 1.
-- #reset-cells  : should be 1 on the g12a (and following) soc family
-
-Each clock is assigned an identifier and client nodes can use this identifier
-to specify the clock which they consume. All available clocks are defined as
-preprocessor macros in the dt-bindings/clock/axg-audio-clkc.h header and can be
-used in device tree sources.
-
-Example:
-
-clkc_audio: clock-controller@0 {
-	compatible = "amlogic,axg-audio-clkc";
-	reg = <0x0 0x0 0x0 0xb4>;
-	#clock-cells = <1>;
-
-	clocks = <&clkc CLKID_AUDIO>,
-		 <&clkc CLKID_MPLL0>,
-		 <&clkc CLKID_MPLL1>,
-		 <&clkc CLKID_MPLL2>,
-		 <&clkc CLKID_MPLL3>,
-		 <&clkc CLKID_HIFI_PLL>,
-		 <&clkc CLKID_FCLK_DIV3>,
-		 <&clkc CLKID_FCLK_DIV4>,
-		 <&clkc CLKID_GP0_PLL>;
-	clock-names = "pclk",
-		      "mst_in0",
-		      "mst_in1",
-		      "mst_in2",
-		      "mst_in3",
-		      "mst_in4",
-		      "mst_in5",
-		      "mst_in6",
-		      "mst_in7";
-	resets = <&reset RESET_AUDIO>;
-};
diff --git a/Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.yaml b/Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.yaml
new file mode 100644
index 000000000000..b683896e950a
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.yaml
@@ -0,0 +1,115 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/amlogic,axg-audio-clkc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Amlogic AXG Audio Clock Controller
+
+maintainers:
+  - Neil Armstrong <neil.armstrong@linaro.org>
+  - Jerome Brunet <jbrunet@baylibre.com>
+
+description:
+  The Amlogic AXG audio clock controller generates and supplies clock to the
+  other elements of the audio subsystem, such as fifos, i2s, spdif and pdm
+  devices.
+
+properties:
+  compatible:
+    enum:
+      - amlogic,axg-audio-clkc
+      - amlogic,g12a-audio-clkc
+      - amlogic,sm1-audio-clkc
+
+  '#clock-cells':
+    const: 1
+
+  '#reset-cells':
+    const: 1
+
+  reg:
+    maxItems: 1
+
+  clocks:
+    maxItems: 28
+    items:
+      - description: main peripheral bus clock
+    additionalItems:
+      oneOf:
+        - description: mst_in[0-7] - input plls to generate clock signals
+        - description: slv_sclk[0-9] - slave bit clocks provided by external components
+        - description: slv_lrclk[0-9]- slave sample clocks provided by external components
+
+  clock-names:
+    maxItems: 28
+    items:
+      - const: pclk
+    additionalItems:
+      oneOf:
+        - pattern: "^mst_in[0-7]$"
+        - pattern: "^slv_sclk[0-9]$"
+        - pattern: "^slv_lrclk[0-9]$"
+
+  resets:
+    description: internal reset line
+
+required:
+  - compatible
+  - '#clock-cells'
+  - reg
+  - clocks
+  - clock-names
+  - resets
+
+allOf:
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - amlogic,g12a-audio-clkc
+              - amlogic,sm1-audio-clkc
+    then:
+      required:
+        - '#reset-cells'
+    else:
+      properties:
+        '#reset-cells': false
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/axg-clkc.h>
+    #include <dt-bindings/reset/amlogic,meson-axg-reset.h>
+    apb {
+        #address-cells = <2>;
+        #size-cells = <2>;
+
+        clkc_audio: clock-controller@0 {
+            compatible = "amlogic,axg-audio-clkc";
+            reg = <0x0 0x0 0x0 0xb4>;
+            #clock-cells = <1>;
+
+            clocks = <&clkc CLKID_AUDIO>,
+                     <&clkc CLKID_MPLL0>,
+                     <&clkc CLKID_MPLL1>,
+                     <&clkc CLKID_MPLL2>,
+                     <&clkc CLKID_MPLL3>,
+                     <&clkc CLKID_HIFI_PLL>,
+                     <&clkc CLKID_FCLK_DIV3>,
+                     <&clkc CLKID_FCLK_DIV4>,
+                     <&clkc CLKID_GP0_PLL>;
+            clock-names = "pclk",
+                          "mst_in0",
+                          "mst_in1",
+                          "mst_in2",
+                          "mst_in3",
+                          "mst_in4",
+                          "mst_in5",
+                          "mst_in6",
+                          "mst_in7";
+            resets = <&reset RESET_AUDIO>;
+        };
+    };
-- 
2.34.1


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[APPROACH 2 1/2] arm64: dts: amlogic: list all slave clocks for audio clock controller

[Jan Dakinevich]

Signed-off-by: Jan Dakinevich <jan.dakinevich@salutedevices.com>
---
 arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 27 ++++++++++++++++++++--
 arch/arm64/boot/dts/amlogic/meson-g12.dtsi | 26 +++++++++++++++++++--
 arch/arm64/boot/dts/amlogic/meson-sm1.dtsi | 26 +++++++++++++++++++--
 3 files changed, 73 insertions(+), 6 deletions(-)

diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
index 6d12b760b90f..28f4ec5f39b0 100644
--- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
@@ -1342,7 +1342,9 @@ clkc_audio: clock-controller@0 {
 					 <&clkc CLKID_HIFI_PLL>,
 					 <&clkc CLKID_FCLK_DIV3>,
 					 <&clkc CLKID_FCLK_DIV4>,
-					 <&clkc CLKID_GP0_PLL>;
+					 <&clkc CLKID_GP0_PLL>,
+					 <0>, <0>, <0>, <0>, <0>, <0>, <0>, <0>, <0>, <0>,
+					 <0>, <0>, <0>, <0>, <0>, <0>, <0>, <0>, <0>, <0>;
 				clock-names = "pclk",
 					      "mst_in0",
 					      "mst_in1",
@@ -1351,7 +1353,28 @@ clkc_audio: clock-controller@0 {
 					      "mst_in4",
 					      "mst_in5",
 					      "mst_in6",
-					      "mst_in7";
+					      "mst_in7",
+					      "slv_sclk0",
+					      "slv_sclk1",
+					      "slv_sclk2",
+					      "slv_sclk3",
+					      "slv_sclk4",
+					      "slv_sclk5",
+					      "slv_sclk6",
+					      "slv_sclk7",
+					      "slv_sclk8",
+					      "slv_sclk9",
+					      "slv_lrclk0",
+					      "slv_lrclk1",
+					      "slv_lrclk2",
+					      "slv_lrclk3",
+					      "slv_lrclk4",
+					      "slv_lrclk5",
+					      "slv_lrclk6",
+					      "slv_lrclk7",
+					      "slv_lrclk8",
+					      "slv_lrclk9";
+
 
 				resets = <&reset RESET_AUDIO>;
 			};
diff --git a/arch/arm64/boot/dts/amlogic/meson-g12.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12.dtsi
index e732df3f3114..af99781f3c4e 100644
--- a/arch/arm64/boot/dts/amlogic/meson-g12.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-g12.dtsi
@@ -82,7 +82,9 @@ clkc_audio: clock-controller@0 {
 				 <&clkc CLKID_HIFI_PLL>,
 				 <&clkc CLKID_FCLK_DIV3>,
 				 <&clkc CLKID_FCLK_DIV4>,
-				 <&clkc CLKID_GP0_PLL>;
+				 <&clkc CLKID_GP0_PLL>,
+				 <0>, <0>, <0>, <0>, <0>, <0>, <0>, <0>, <0>, <0>,
+				 <0>, <0>, <0>, <0>, <0>, <0>, <0>, <0>, <0>, <0>;
 			clock-names = "pclk",
 				      "mst_in0",
 				      "mst_in1",
@@ -91,7 +93,27 @@ clkc_audio: clock-controller@0 {
 				      "mst_in4",
 				      "mst_in5",
 				      "mst_in6",
-				      "mst_in7";
+				      "mst_in7",
+				      "slv_sclk0",
+				      "slv_sclk1",
+				      "slv_sclk2",
+				      "slv_sclk3",
+				      "slv_sclk4",
+				      "slv_sclk5",
+				      "slv_sclk6",
+				      "slv_sclk7",
+				      "slv_sclk8",
+				      "slv_sclk9",
+				      "slv_lrclk0",
+				      "slv_lrclk1",
+				      "slv_lrclk2",
+				      "slv_lrclk3",
+				      "slv_lrclk4",
+				      "slv_lrclk5",
+				      "slv_lrclk6",
+				      "slv_lrclk7",
+				      "slv_lrclk8",
+				      "slv_lrclk9";
 
 			resets = <&reset RESET_AUDIO>;
 		};
diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi b/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi
index 643f94d9d08e..24e520c3e2a6 100644
--- a/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi
@@ -162,7 +162,9 @@ clkc_audio: clock-controller@0 {
 				 <&clkc CLKID_HIFI_PLL>,
 				 <&clkc CLKID_FCLK_DIV3>,
 				 <&clkc CLKID_FCLK_DIV4>,
-				 <&clkc CLKID_FCLK_DIV5>;
+				 <&clkc CLKID_FCLK_DIV5>,
+				 <0>, <0>, <0>, <0>, <0>, <0>, <0>, <0>, <0>, <0>,
+				 <0>, <0>, <0>, <0>, <0>, <0>, <0>, <0>, <0>, <0>;
 			clock-names = "pclk",
 				      "mst_in0",
 				      "mst_in1",
@@ -171,7 +173,27 @@ clkc_audio: clock-controller@0 {
 				      "mst_in4",
 				      "mst_in5",
 				      "mst_in6",
-				      "mst_in7";
+				      "mst_in7",
+				      "slv_sclk0",
+				      "slv_sclk1",
+				      "slv_sclk2",
+				      "slv_sclk3",
+				      "slv_sclk4",
+				      "slv_sclk5",
+				      "slv_sclk6",
+				      "slv_sclk7",
+				      "slv_sclk8",
+				      "slv_sclk9",
+				      "slv_lrclk0",
+				      "slv_lrclk1",
+				      "slv_lrclk2",
+				      "slv_lrclk3",
+				      "slv_lrclk4",
+				      "slv_lrclk5",
+				      "slv_lrclk6",
+				      "slv_lrclk7",
+				      "slv_lrclk8",
+				      "slv_lrclk9";
 
 			resets = <&reset RESET_AUDIO>;
 		};
-- 
2.34.1


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[APPROACH 2 2/2] dt-bindings: clock: meson: Convert axg-audio-clkc to YAML format

[Jan Dakinevich]

Convert Amlogic AXG Audio Clock Controller binding to yaml.

Signed-off-by: Alexander Stein <alexander.stein@mailbox.org>
Signed-off-by: Jan Dakinevich <jan.dakinevich@salutedevices.com>
---
 .../bindings/clock/amlogic,axg-audio-clkc.txt |  59 ------
 .../clock/amlogic,axg-audio-clkc.yaml         | 181 ++++++++++++++++++
 2 files changed, 181 insertions(+), 59 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.txt
 create mode 100644 Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.yaml

diff --git a/Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.txt b/Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.txt
deleted file mode 100644
index 3a8948c04bc9..000000000000
--- a/Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.txt
+++ /dev/null
@@ -1,59 +0,0 @@
-* Amlogic AXG Audio Clock Controllers
-
-The Amlogic AXG audio clock controller generates and supplies clock to the
-other elements of the audio subsystem, such as fifos, i2s, spdif and pdm
-devices.
-
-Required Properties:
-
-- compatible	: should be "amlogic,axg-audio-clkc" for the A113X and A113D,
-		  "amlogic,g12a-audio-clkc" for G12A,
-		  "amlogic,sm1-audio-clkc" for S905X3.
-- reg		: physical base address of the clock controller and length of
-		  memory mapped region.
-- clocks	: a list of phandle + clock-specifier pairs for the clocks listed
-		  in clock-names.
-- clock-names	: must contain the following:
-		  * "pclk" - Main peripheral bus clock
-		  may contain the following:
-		  * "mst_in[0-7]" - 8 input plls to generate clock signals
-		  * "slv_sclk[0-9]" - 10 slave bit clocks provided by external
-				      components.
-		  * "slv_lrclk[0-9]" - 10 slave sample clocks provided by external
-				       components.
-- resets	: phandle of the internal reset line
-- #clock-cells	: should be 1.
-- #reset-cells  : should be 1 on the g12a (and following) soc family
-
-Each clock is assigned an identifier and client nodes can use this identifier
-to specify the clock which they consume. All available clocks are defined as
-preprocessor macros in the dt-bindings/clock/axg-audio-clkc.h header and can be
-used in device tree sources.
-
-Example:
-
-clkc_audio: clock-controller@0 {
-	compatible = "amlogic,axg-audio-clkc";
-	reg = <0x0 0x0 0x0 0xb4>;
-	#clock-cells = <1>;
-
-	clocks = <&clkc CLKID_AUDIO>,
-		 <&clkc CLKID_MPLL0>,
-		 <&clkc CLKID_MPLL1>,
-		 <&clkc CLKID_MPLL2>,
-		 <&clkc CLKID_MPLL3>,
-		 <&clkc CLKID_HIFI_PLL>,
-		 <&clkc CLKID_FCLK_DIV3>,
-		 <&clkc CLKID_FCLK_DIV4>,
-		 <&clkc CLKID_GP0_PLL>;
-	clock-names = "pclk",
-		      "mst_in0",
-		      "mst_in1",
-		      "mst_in2",
-		      "mst_in3",
-		      "mst_in4",
-		      "mst_in5",
-		      "mst_in6",
-		      "mst_in7";
-	resets = <&reset RESET_AUDIO>;
-};
diff --git a/Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.yaml b/Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.yaml
new file mode 100644
index 000000000000..9704bb78fca2
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.yaml
@@ -0,0 +1,181 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/amlogic,axg-audio-clkc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Amlogic AXG Audio Clock Controller
+
+maintainers:
+  - Neil Armstrong <neil.armstrong@linaro.org>
+  - Jerome Brunet <jbrunet@baylibre.com>
+
+description:
+  The Amlogic AXG audio clock controller generates and supplies clock to the
+  other elements of the audio subsystem, such as fifos, i2s, spdif and pdm
+  devices.
+
+properties:
+  compatible:
+    enum:
+      - amlogic,axg-audio-clkc
+      - amlogic,g12a-audio-clkc
+      - amlogic,sm1-audio-clkc
+
+  '#clock-cells':
+    const: 1
+
+  '#reset-cells':
+    const: 1
+
+  reg:
+    maxItems: 1
+
+  clocks:
+    items:
+      - description: main peripheral bus clock
+      - description: input plls to generate clock signals N0
+      - description: input plls to generate clock signals N1
+      - description: input plls to generate clock signals N2
+      - description: input plls to generate clock signals N3
+      - description: input plls to generate clock signals N4
+      - description: input plls to generate clock signals N5
+      - description: input plls to generate clock signals N6
+      - description: input plls to generate clock signals N7
+      - description: slave bit clock N0 provided by external components
+      - description: slave bit clock N1 provided by external components
+      - description: slave bit clock N2 provided by external components
+      - description: slave bit clock N3 provided by external components
+      - description: slave bit clock N4 provided by external components
+      - description: slave bit clock N5 provided by external components
+      - description: slave bit clock N6 provided by external components
+      - description: slave bit clock N7 provided by external components
+      - description: slave bit clock N8 provided by external components
+      - description: slave bit clock N9 provided by external components
+      - description: slave sample clock N0 provided by external components
+      - description: slave sample clock N1 provided by external components
+      - description: slave sample clock N2 provided by external components
+      - description: slave sample clock N3 provided by external components
+      - description: slave sample clock N4 provided by external components
+      - description: slave sample clock N5 provided by external components
+      - description: slave sample clock N6 provided by external components
+      - description: slave sample clock N7 provided by external components
+      - description: slave sample clock N8 provided by external components
+      - description: slave sample clock N9 provided by external components
+
+  clock-names:
+    items:
+      - const: pclk
+      - const: mst_in0
+      - const: mst_in1
+      - const: mst_in2
+      - const: mst_in3
+      - const: mst_in4
+      - const: mst_in5
+      - const: mst_in6
+      - const: mst_in7
+      - const: slv_sclk0
+      - const: slv_sclk1
+      - const: slv_sclk2
+      - const: slv_sclk3
+      - const: slv_sclk4
+      - const: slv_sclk5
+      - const: slv_sclk6
+      - const: slv_sclk7
+      - const: slv_sclk8
+      - const: slv_sclk9
+      - const: slv_lrclk0
+      - const: slv_lrclk1
+      - const: slv_lrclk2
+      - const: slv_lrclk3
+      - const: slv_lrclk4
+      - const: slv_lrclk5
+      - const: slv_lrclk6
+      - const: slv_lrclk7
+      - const: slv_lrclk8
+      - const: slv_lrclk9
+
+  resets:
+    description: internal reset line
+
+required:
+  - compatible
+  - '#clock-cells'
+  - reg
+  - clocks
+  - clock-names
+  - resets
+
+allOf:
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - amlogic,g12a-audio-clkc
+              - amlogic,sm1-audio-clkc
+    then:
+      required:
+        - '#reset-cells'
+    else:
+      properties:
+        '#reset-cells': false
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/axg-clkc.h>
+    #include <dt-bindings/reset/amlogic,meson-axg-reset.h>
+    apb {
+        #address-cells = <2>;
+        #size-cells = <2>;
+
+        clkc_audio: clock-controller@0 {
+            compatible = "amlogic,axg-audio-clkc";
+            reg = <0x0 0x0 0x0 0xb4>;
+            #clock-cells = <1>;
+
+            clocks = <&clkc CLKID_AUDIO>,
+                     <&clkc CLKID_MPLL0>,
+                     <&clkc CLKID_MPLL1>,
+                     <&clkc CLKID_MPLL2>,
+                     <&clkc CLKID_MPLL3>,
+                     <&clkc CLKID_HIFI_PLL>,
+                     <&clkc CLKID_FCLK_DIV3>,
+                     <&clkc CLKID_FCLK_DIV4>,
+                     <&clkc CLKID_GP0_PLL>,
+                     <0>, <0>, <0>, <0>, <0>, <0>, <0>, <0>, <0>, <0>,
+                     <0>, <0>, <0>, <0>, <0>, <0>, <0>, <0>, <0>, <0>;
+            clock-names = "pclk",
+                          "mst_in0",
+                          "mst_in1",
+                          "mst_in2",
+                          "mst_in3",
+                          "mst_in4",
+                          "mst_in5",
+                          "mst_in6",
+                          "mst_in7",
+                          "slv_sclk0",
+                          "slv_sclk1",
+                          "slv_sclk2",
+                          "slv_sclk3",
+                          "slv_sclk4",
+                          "slv_sclk5",
+                          "slv_sclk6",
+                          "slv_sclk7",
+                          "slv_sclk8",
+                          "slv_sclk9",
+                          "slv_lrclk0",
+                          "slv_lrclk1",
+                          "slv_lrclk2",
+                          "slv_lrclk3",
+                          "slv_lrclk4",
+                          "slv_lrclk5",
+                          "slv_lrclk6",
+                          "slv_lrclk7",
+                          "slv_lrclk8",
+                          "slv_lrclk9";
+            resets = <&reset RESET_AUDIO>;
+        };
+    };
-- 
2.34.1


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Re: [APPROACH 2 2/2] dt-bindings: clock: meson: Convert axg-audio-clkc to YAML format

[Rob Herring (Arm)]

On Wed, 08 May 2024 17:42:59 +0300, Jan Dakinevich wrote:
> Convert Amlogic AXG Audio Clock Controller binding to yaml.
> 
> Signed-off-by: Alexander Stein <alexander.stein@mailbox.org>
> Signed-off-by: Jan Dakinevich <jan.dakinevich@salutedevices.com>
> ---
>  .../bindings/clock/amlogic,axg-audio-clkc.txt |  59 ------
>  .../clock/amlogic,axg-audio-clkc.yaml         | 181 ++++++++++++++++++
>  2 files changed, 181 insertions(+), 59 deletions(-)
>  delete mode 100644 Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.txt
>  create mode 100644 Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.yaml
> 

My bot found errors running 'make dt_binding_check' on your patch:

yamllint warnings/errors:

dtschema/dtc warnings/errors:
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.example.dtb: clock-controller@0: clocks: [[4294967295, 35], [4294967295, 11], [4294967295, 12], [4294967295, 13], [4294967295, 14], [4294967295, 69], [4294967295, 3], [4294967295, 4], [4294967295, 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0]] is too short
	from schema $id: http://devicetree.org/schemas/clock/amlogic,axg-audio-clkc.yaml#

doc reference errors (make refcheckdocs):

See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20240508144259.191843-4-jan.dakinevich@salutedevices.com

The base for the series is generally the latest rc1. A different dependency
should be noted in *this* patch.

If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:

pip3 install dtschema --upgrade

Please check and re-submit after running the above command yourself. Note
that DT_SCHEMA_FILES can be set to your schema file to speed up checking
your schema. However, it must be unset to test all examples with your schema.


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Re: [APPROACH 2 1/2] arm64: dts: amlogic: list all slave clocks for audio clock controller

[Rob Herring]

On Wed, May 08, 2024 at 05:42:58PM +0300, Jan Dakinevich wrote:
> Signed-off-by: Jan Dakinevich <jan.dakinevich@salutedevices.com>
> ---
>  arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 27 ++++++++++++++++++++--
>  arch/arm64/boot/dts/amlogic/meson-g12.dtsi | 26 +++++++++++++++++++--
>  arch/arm64/boot/dts/amlogic/meson-sm1.dtsi | 26 +++++++++++++++++++--
>  3 files changed, 73 insertions(+), 6 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
> index 6d12b760b90f..28f4ec5f39b0 100644
> --- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
> +++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
> @@ -1342,7 +1342,9 @@ clkc_audio: clock-controller@0 {
>  					 <&clkc CLKID_HIFI_PLL>,
>  					 <&clkc CLKID_FCLK_DIV3>,
>  					 <&clkc CLKID_FCLK_DIV4>,
> -					 <&clkc CLKID_GP0_PLL>;
> +					 <&clkc CLKID_GP0_PLL>,
> +					 <0>, <0>, <0>, <0>, <0>, <0>, <0>, <0>, <0>, <0>,
> +					 <0>, <0>, <0>, <0>, <0>, <0>, <0>, <0>, <0>, <0>;

All 3 cases are just unused clocks on the end. I suppose that's not 
always the case. You could just set 'minItems' in the binding to 
avoid needing to pad the end and the dts changes.

Rob

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Re: [APPROACH 2 1/2] arm64: dts: amlogic: list all slave clocks for audio clock controller

[Jan Dakinevich]

On 5/8/24 20:50, Rob Herring wrote:
> On Wed, May 08, 2024 at 05:42:58PM +0300, Jan Dakinevich wrote:
>> Signed-off-by: Jan Dakinevich <jan.dakinevich@salutedevices.com>
>> ---
>>  arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 27 ++++++++++++++++++++--
>>  arch/arm64/boot/dts/amlogic/meson-g12.dtsi | 26 +++++++++++++++++++--
>>  arch/arm64/boot/dts/amlogic/meson-sm1.dtsi | 26 +++++++++++++++++++--
>>  3 files changed, 73 insertions(+), 6 deletions(-)
>>
>> diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
>> index 6d12b760b90f..28f4ec5f39b0 100644
>> --- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
>> +++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
>> @@ -1342,7 +1342,9 @@ clkc_audio: clock-controller@0 {
>>  					 <&clkc CLKID_HIFI_PLL>,
>>  					 <&clkc CLKID_FCLK_DIV3>,
>>  					 <&clkc CLKID_FCLK_DIV4>,
>> -					 <&clkc CLKID_GP0_PLL>;
>> +					 <&clkc CLKID_GP0_PLL>,
>> +					 <0>, <0>, <0>, <0>, <0>, <0>, <0>, <0>, <0>, <0>,
>> +					 <0>, <0>, <0>, <0>, <0>, <0>, <0>, <0>, <0>, <0>;
> 
> All 3 cases are just unused clocks on the end. I suppose that's not 
> always the case. You could just set 'minItems' in the binding to 
> avoid needing to pad the end and the dts changes.
> 

You are right. I mistakenly thought that 'minItems' can not be
redefined. But not, it is allowed to redefine it and it works. Thus,
this patch is not needed for this approach.

Anyway, what do you think about first approach? As for me, it is more
simple and readable.

> Rob

-- 
Best regards
Jan Dakinevich

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Re: [APPROACH 2 1/2] arm64: dts: amlogic: list all slave clocks for audio clock controller

[Rob Herring]

On Sun, May 12, 2024 at 10:06:23PM +0300, Jan Dakinevich wrote:
> 
> 
> On 5/8/24 20:50, Rob Herring wrote:
> > On Wed, May 08, 2024 at 05:42:58PM +0300, Jan Dakinevich wrote:
> >> Signed-off-by: Jan Dakinevich <jan.dakinevich@salutedevices.com>
> >> ---
> >>  arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 27 ++++++++++++++++++++--
> >>  arch/arm64/boot/dts/amlogic/meson-g12.dtsi | 26 +++++++++++++++++++--
> >>  arch/arm64/boot/dts/amlogic/meson-sm1.dtsi | 26 +++++++++++++++++++--
> >>  3 files changed, 73 insertions(+), 6 deletions(-)
> >>
> >> diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
> >> index 6d12b760b90f..28f4ec5f39b0 100644
> >> --- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
> >> +++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
> >> @@ -1342,7 +1342,9 @@ clkc_audio: clock-controller@0 {
> >>  					 <&clkc CLKID_HIFI_PLL>,
> >>  					 <&clkc CLKID_FCLK_DIV3>,
> >>  					 <&clkc CLKID_FCLK_DIV4>,
> >> -					 <&clkc CLKID_GP0_PLL>;
> >> +					 <&clkc CLKID_GP0_PLL>,
> >> +					 <0>, <0>, <0>, <0>, <0>, <0>, <0>, <0>, <0>, <0>,
> >> +					 <0>, <0>, <0>, <0>, <0>, <0>, <0>, <0>, <0>, <0>;
> > 
> > All 3 cases are just unused clocks on the end. I suppose that's not 
> > always the case. You could just set 'minItems' in the binding to 
> > avoid needing to pad the end and the dts changes.
> > 
> 
> You are right. I mistakenly thought that 'minItems' can not be
> redefined. But not, it is allowed to redefine it and it works. Thus,
> this patch is not needed for this approach.
> 
> Anyway, what do you think about first approach? As for me, it is more
> simple and readable.

I prefer this one as it enforces the order.

Rob

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