From: Jianxin Pan <jianxin.pan@amlogic.com>
To: Jerome Brunet <jbrunet@baylibre.com>,
Kevin Hilman <khilman@baylibre.com>,
<linux-amlogic@lists.infradead.org>
Cc: devicetree@vger.kernel.org, Hanjie Lin <hanjie.lin@amlogic.com>,
Victor Wan <victor.wan@amlogic.com>,
Neil Armstrong <narmstrong@baylibre.com>,
Martin Blumenstingl <martin.blumenstingl@googlemail.com>,
linux-kernel@vger.kernel.org,
Qiufang Dai <qiufang.dai@amlogic.com>,
Rob Herring <robh+dt@kernel.org>, Jian Hu <jian.hu@amlogic.com>,
Xingyu Chen <xingyu.chen@amlogic.com>,
Carlo Caione <carlo@caione.org>, Tao Zeng <tao.zeng@amlogic.com>,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH 4/4] arm64: dts: add support for A1 based Amlogic AD401
Date: Tue, 3 Sep 2019 16:00:15 +0800 [thread overview]
Message-ID: <de374b4a-be2e-0b85-ff3f-f7cdc785c26a@amlogic.com> (raw)
In-Reply-To: <1jef0xrg5d.fsf@starbuckisacylon.baylibre.com>
Hi Jerome,
Thanks for your suggestion.
I will fix them in the next version.
On 2019/9/3 15:30, Jerome Brunet wrote:
> On Tue 03 Sep 2019 at 02:51, Jianxin Pan <jianxin.pan@amlogic.com> wrote:
>
>> Add basic support for the Amlogic A1 based Amlogic AD401 board:
>> which describe components as follows: Reserve Memory, CPU, GIC, IRQ,
>> Timer, UART. It's capable of booting up into the serial console.
>>
>> Signed-off-by: Jianxin Pan <jianxin.pan@amlogic.com>
>> ---
>> arch/arm64/boot/dts/amlogic/Makefile | 1 +
>> arch/arm64/boot/dts/amlogic/meson-a1-ad401.dts | 30 ++++++
>> arch/arm64/boot/dts/amlogic/meson-a1.dtsi | 121 +++++++++++++++++++++++++
>> 3 files changed, 152 insertions(+)
>> create mode 100644 arch/arm64/boot/dts/amlogic/meson-a1-ad401.dts
>> create mode 100644 arch/arm64/boot/dts/amlogic/meson-a1.dtsi
>>
>> diff --git a/arch/arm64/boot/dts/amlogic/Makefile b/arch/arm64/boot/dts/amlogic/Makefile
>> index edbf128..1720c45 100644
>> --- a/arch/arm64/boot/dts/amlogic/Makefile
>> +++ b/arch/arm64/boot/dts/amlogic/Makefile
>> @@ -36,3 +36,4 @@ dtb-$(CONFIG_ARCH_MESON) += meson-gxm-rbox-pro.dtb
>> dtb-$(CONFIG_ARCH_MESON) += meson-gxm-vega-s96.dtb
>> dtb-$(CONFIG_ARCH_MESON) += meson-sm1-sei610.dtb
>> dtb-$(CONFIG_ARCH_MESON) += meson-sm1-khadas-vim3l.dtb
>> +dtb-$(CONFIG_ARCH_MESON) += meson-a1-ad401.dtb
>> diff --git a/arch/arm64/boot/dts/amlogic/meson-a1-ad401.dts b/arch/arm64/boot/dts/amlogic/meson-a1-ad401.dts
>> new file mode 100644
>> index 00000000..3c05cc0
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/amlogic/meson-a1-ad401.dts
>> @@ -0,0 +1,30 @@
>> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
>> +/*
>> + * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
>> + */
>> +
>> +/dts-v1/;
>> +
>> +#include "meson-a1.dtsi"
>> +
>> +/ {
>> + compatible = "amlogic,ad401", "amlogic,a1";
>> + model = "Amlogic Meson A1 AD401 Development Board";
>> +
>> + aliases {
>> + serial0 = &uart_AO_B;
>> + };
>
> Newline here please
>
>> + chosen {
>> + stdout-path = "serial0:115200n8";
>> + };
>
> same
>
>> + memory@0 {
>> + device_type = "memory";
>> + linux,usable-memory = <0x0 0x0 0x0 0x8000000>;
>> + };
>> +};
>> +
>> +&uart_AO_B {
>> + status = "okay";
>> + /*pinctrl-0 = <&uart_ao_a_pins>;*/
>> + /*pinctrl-names = "default";*/
>
> Remove the commented code please
>
>> +};
>> diff --git a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
>> new file mode 100644
>> index 00000000..b98d648
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
>> @@ -0,0 +1,121 @@
>> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
>> +/*
>> + * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
>> + */
>> +
>> +#include <dt-bindings/interrupt-controller/irq.h>
>> +#include <dt-bindings/interrupt-controller/arm-gic.h>
>> +
>> +/ {
>> + compatible = "amlogic,a1";
>> +
>> + interrupt-parent = <&gic>;
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>> +
>> + cpus {
>> + #address-cells = <0x2>;
>> + #size-cells = <0x0>;
>> +
>> + cpu0: cpu@0 {
>> + device_type = "cpu";
>> + compatible = "arm,cortex-a35";
>> + reg = <0x0 0x0>;
>> + enable-method = "psci";
>> + next-level-cache = <&l2>;
>> + };
>> +
>> + cpu1: cpu@1 {
>> + device_type = "cpu";
>> + compatible = "arm,cortex-a35";
>> + reg = <0x0 0x1>;
>> + enable-method = "psci";
>> + next-level-cache = <&l2>;
>> + };
>> +
>> + l2: l2-cache0 {
>> + compatible = "cache";
>> + };
>> + };
>
> New line here please
>
> With this minor comments adressed, looks good.
>
> Reviewed-by: Jerome Brunet <jbrunet@baylibre.com>
>
>> + psci {
>> + compatible = "arm,psci-1.0";
>> + method = "smc";
>> + };
>> +
>> + reserved-memory {
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>> + ranges;
>> +
>> + linux,cma {
>> + compatible = "shared-dma-pool";
>> + reusable;
>> + size = <0x0 0x800000>;
>> + alignment = <0x0 0x400000>;
>> + linux,cma-default;
>> + };
>> + };
>> +
>> + sm: secure-monitor {
>> + compatible = "amlogic,meson-gxbb-sm";
>> + };
>> +
>> + soc {
>> + compatible = "simple-bus";
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>> + ranges;
>> +
>> + uart_AO: serial@fe001c00 {
>> + compatible = "amlogic,meson-gx-uart",
>> + "amlogic,meson-ao-uart";
>> + reg = <0x0 0xfe001c00 0x0 0x18>;
>> + interrupts = <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>;
>> + clocks = <&xtal>, <&xtal>, <&xtal>;
>> + clock-names = "xtal", "pclk", "baud";
>> + status = "disabled";
>> + };
>> +
>> + uart_AO_B: serial@fe002000 {
>> + compatible = "amlogic,meson-gx-uart",
>> + "amlogic,meson-ao-uart";
>> + reg = <0x0 0xfe002000 0x0 0x18>;
>> + interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
>> + clocks = <&xtal>, <&xtal>, <&xtal>;
>> + clock-names = "xtal", "pclk", "baud";
>> + status = "disabled";
>> + };
>> +
>> + gic: interrupt-controller@ff901000 {
>> + compatible = "arm,gic-400";
>> + reg = <0x0 0xff901000 0x0 0x1000>,
>> + <0x0 0xff902000 0x0 0x2000>,
>> + <0x0 0xff904000 0x0 0x2000>,
>> + <0x0 0xff906000 0x0 0x2000>;
>> + interrupt-controller;
>> + interrupts = <GIC_PPI 9
>> + (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
>> + #interrupt-cells = <3>;
>> + #address-cells = <0>;
>> + };
>> + };
>> +
>> + timer {
>> + compatible = "arm,armv8-timer";
>> + interrupts = <GIC_PPI 13
>> + (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
>> + <GIC_PPI 14
>> + (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
>> + <GIC_PPI 11
>> + (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
>> + <GIC_PPI 10
>> + (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
>> + };
>> +
>> + xtal: xtal-clk {
>> + compatible = "fixed-clock";
>> + clock-frequency = <24000000>;
>> + clock-output-names = "xtal";
>> + #clock-cells = <0>;
>> + };
>> +};
>> --
>> 2.7.4
>
> .
>
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next prev parent reply other threads:[~2019-09-03 8:00 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-09-03 6:51 [PATCH 0/4] arm64: Add basic support for Amlogic A1 SoC Family Jianxin Pan
2019-09-03 6:51 ` [PATCH 1/4] soc: amlogic: meson-gx-socinfo: Add A1 and A113L IDs Jianxin Pan
2019-09-03 7:12 ` Neil Armstrong
2019-09-03 6:51 ` [PATCH 2/4] dt-bindings: arm: amlogic: add A1 bindings Jianxin Pan
2019-09-03 17:38 ` Rob Herring
2019-09-03 6:51 ` [PATCH 3/4] dt-bindings: arm: amlogic: add Amlogic AD401 bindings Jianxin Pan
2019-09-03 17:38 ` Rob Herring
2019-09-03 6:51 ` [PATCH 4/4] arm64: dts: add support for A1 based Amlogic AD401 Jianxin Pan
2019-09-03 7:30 ` Jerome Brunet
2019-09-03 8:00 ` Jianxin Pan [this message]
2019-09-03 7:42 ` Neil Armstrong
2019-09-03 8:16 ` Jianxin Pan
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