From: "Wu, Hao" <hao.wu@intel.com>
To: Alan Tull <atull@kernel.org>
Cc: Moritz Fischer <mdf@kernel.org>,
"linux-fpga@vger.kernel.org" <linux-fpga@vger.kernel.org>,
linux-kernel <linux-kernel@vger.kernel.org>,
"linux-api@vger.kernel.org" <linux-api@vger.kernel.org>,
"Kang, Luwei" <luwei.kang@intel.com>,
"Zhang, Yi Z" <yi.z.zhang@intel.com>,
Xiao Guangrong <guangrong.xiao@linux.intel.com>,
"Whisonant, Tim" <tim.whisonant@intel.com>,
"Luebbers, Enno" <enno.luebbers@intel.com>,
"Rao, Shiva" <shiva.rao@intel.com>,
"Rauer, Christopher" <christopher.rauer@intel.com>
Subject: RE: [PATCH v2 07/22] fpga: intel: pcie: parse feature list and create platform device for features.
Date: Tue, 18 Jul 2017 02:29:57 +0000 [thread overview]
Message-ID: <BE8371DA886269458E0220A16DC1F8277E0583A8@SHSMSX104.ccr.corp.intel.com> (raw)
In-Reply-To: <CANk1AXR3p16it2E0aVSnYG7FB2hrp-++98cBTMB1YzMUdeUmGQ@mail.gmail.com>
> On Sun, Jun 25, 2017 at 8:52 PM, Wu Hao <hao.wu@intel.com> wrote:
> > From: Xiao Guangrong <guangrong.xiao@linux.intel.com>
> >
> > Device Feature List structure creates a link list of feature headers
> > within the MMIO space to provide an extensible way of adding features.
> >
> > The Intel FPGA PCIe driver walks through the feature headers to enumerate
> > feature devices, FPGA Management Engine (FME) and FPGA Port for
> Accelerated
> > Function Unit (AFU), and their private sub features. For feature devices,
> > it creates the platform devices and linked the private sub features into
> > their platform data.
> >
> > Signed-off-by: Tim Whisonant <tim.whisonant@intel.com>
> > Signed-off-by: Enno Luebbers <enno.luebbers@intel.com>
> > Signed-off-by: Shiva Rao <shiva.rao@intel.com>
> > Signed-off-by: Christopher Rauer <christopher.rauer@intel.com>
> > Signed-off-by: Kang Luwei <luwei.kang@intel.com>
> > Signed-off-by: Zhang Yi <yi.z.zhang@intel.com>
> > Signed-off-by: Xiao Guangrong <guangrong.xiao@linux.intel.com>
> > Signed-off-by: Wu Hao <hao.wu@intel.com>
> > ---
> > v2: moved the code to drivers/fpga folder as suggested by Alan Tull.
> > switched to GPLv2 license.
> > fixed comments from Moritz Fischer.
> > fixed kbuild warning, typos and clean up the code.
> > ---
> > drivers/fpga/Makefile | 2 +-
> > drivers/fpga/intel-feature-dev.c | 130 ++++++
> > drivers/fpga/intel-feature-dev.h | 341 ++++++++++++++++
> > drivers/fpga/intel-pcie.c | 841
> ++++++++++++++++++++++++++++++++++++++-
> > 4 files changed, 1311 insertions(+), 3 deletions(-)
> > create mode 100644 drivers/fpga/intel-feature-dev.c
> > create mode 100644 drivers/fpga/intel-feature-dev.h
> >
> > diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile
> > index 5613133..ad24b3d 100644
> > --- a/drivers/fpga/Makefile
> > +++ b/drivers/fpga/Makefile
> > @@ -31,4 +31,4 @@ obj-$(CONFIG_OF_FPGA_REGION) += of-fpga-
> region.o
> > # Intel FPGA Support
> > obj-$(CONFIG_INTEL_FPGA_PCI) += intel-fpga-pci.o
> >
> > -intel-fpga-pci-objs := intel-pcie.o
> > +intel-fpga-pci-objs := intel-pcie.o intel-feature-dev.o
> > diff --git a/drivers/fpga/intel-feature-dev.c b/drivers/fpga/intel-feature-dev.c
> > new file mode 100644
> > index 0000000..68f9cba
> > --- /dev/null
> > +++ b/drivers/fpga/intel-feature-dev.c
> > @@ -0,0 +1,130 @@
> > +/*
> > + * Intel FPGA Feature Device Driver
> > + *
> > + * Copyright (C) 2017 Intel Corporation, Inc.
> > + *
> > + * Authors:
> > + * Kang Luwei <luwei.kang@intel.com>
> > + * Zhang Yi <yi.z.zhang@intel.com>
> > + * Wu Hao <hao.wu@intel.com>
> > + * Xiao Guangrong <guangrong.xiao@linux.intel.com>
> > + *
> > + * This work is licensed under the terms of the GNU GPL version 2. See
> > + * the COPYING file in the top-level directory.
> > + */
> > +
> > +#include "intel-feature-dev.h"
> > +
> > +void feature_platform_data_add(struct feature_platform_data *pdata,
> > + int index, const char *name,
> > + int resource_index, void __iomem *ioaddr)
> > +{
> > + WARN_ON(index >= pdata->num);
> > +
> > + pdata->features[index].name = name;
> > + pdata->features[index].resource_index = resource_index;
> > + pdata->features[index].ioaddr = ioaddr;
> > +}
> > +
> > +struct feature_platform_data *
> > +feature_platform_data_alloc_and_init(struct platform_device *dev, int num)
> > +{
> > + struct feature_platform_data *pdata;
> > +
> > + pdata = kzalloc(feature_platform_data_size(num), GFP_KERNEL);
> > + if (pdata) {
> > + pdata->dev = dev;
> > + pdata->num = num;
> > + mutex_init(&pdata->lock);
> > + }
> > +
> > + return pdata;
> > +}
> > +
> > +int fme_feature_num(void)
> > +{
> > + return FME_FEATURE_ID_MAX;
> > +}
> > +
> > +int port_feature_num(void)
> > +{
> > + return PORT_FEATURE_ID_MAX;
> > +}
> > +
> > +int fpga_port_id(struct platform_device *pdev)
> > +{
> > + struct feature_port_header *port_hdr;
> > + struct feature_port_capability capability;
> > +
> > + port_hdr = get_feature_ioaddr_by_index(&pdev->dev,
> > + PORT_FEATURE_ID_HEADER);
> > + WARN_ON(!port_hdr);
> > +
> > + capability.csr = readq(&port_hdr->capability);
> > + return capability.port_number;
> > +}
> > +EXPORT_SYMBOL_GPL(fpga_port_id);
> > +
> > +/*
> > + * Enable Port by clear the port soft reset bit, which is set by default.
> > + * The User AFU is unable to respond to any MMIO access while in reset.
> > + * __fpga_port_enable function should only be used after
> __fpga_port_disable
> > + * function.
> > + */
> > +void __fpga_port_enable(struct platform_device *pdev)
> > +{
> > + struct feature_platform_data *pdata = dev_get_platdata(&pdev->dev);
> > + struct feature_port_header *port_hdr;
> > + struct feature_port_control control;
> > +
> > + WARN_ON(!pdata->disable_count);
> > +
> > + if (--pdata->disable_count != 0)
> > + return;
> > +
> > + port_hdr = get_feature_ioaddr_by_index(&pdev->dev,
> > + PORT_FEATURE_ID_HEADER);
> > + WARN_ON(!port_hdr);
> > +
> > + control.csr = readq(&port_hdr->control);
> > + control.port_sftrst = 0x0;
> > + writeq(control.csr, &port_hdr->control);
> > +}
> > +EXPORT_SYMBOL_GPL(__fpga_port_enable);
> > +
> > +#define RST_POLL_INVL 10 /* us */
> > +#define RST_POLL_TIMEOUT 1000 /* us */
> > +
> > +int __fpga_port_disable(struct platform_device *pdev)
> > +{
> > + struct feature_platform_data *pdata = dev_get_platdata(&pdev->dev);
> > + struct feature_port_header *port_hdr;
> > + struct feature_port_control control;
> > +
> > + if (pdata->disable_count++ != 0)
> > + return 0;
> > +
> > + port_hdr = get_feature_ioaddr_by_index(&pdev->dev,
> > + PORT_FEATURE_ID_HEADER);
> > + WARN_ON(!port_hdr);
> > +
> > + /* Set port soft reset */
> > + control.csr = readq(&port_hdr->control);
> > + control.port_sftrst = 0x1;
> > + writeq(control.csr, &port_hdr->control);
> > +
> > + /*
> > + * HW sets ack bit to 1 when all outstanding requests have been drained
> > + * on this port and minimum soft reset pulse width has elapsed.
> > + * Driver polls port_soft_reset_ack to determine if reset done by HW.
> > + */
> > + if (readq_poll_timeout(&port_hdr->control, control.csr,
> > + (control.port_sftrst_ack == 1),
> > + RST_POLL_INVL, RST_POLL_TIMEOUT)) {
> > + dev_err(&pdev->dev, "timeout, fail to reset device\n");
> > + return -ETIMEDOUT;
> > + }
> > +
> > + return 0;
> > +}
> > +EXPORT_SYMBOL_GPL(__fpga_port_disable);
> > diff --git a/drivers/fpga/intel-feature-dev.h b/drivers/fpga/intel-feature-dev.h
> > new file mode 100644
> > index 0000000..f67784a
> > --- /dev/null
> > +++ b/drivers/fpga/intel-feature-dev.h
> > @@ -0,0 +1,341 @@
> > +/*
> > + * Intel FPGA Feature Device Driver Header File
> > + *
> > + * Copyright (C) 2017 Intel Corporation, Inc.
> > + *
> > + * Authors:
> > + * Kang Luwei <luwei.kang@intel.com>
> > + * Zhang Yi <yi.z.zhang@intel.com>
> > + * Wu Hao <hao.wu@intel.com>
> > + * Xiao Guangrong <guangrong.xiao@linux.intel.com>
> > + *
> > + * This work is licensed under the terms of the GNU GPL version 2. See
> > + * the COPYING file in the top-level directory.
> > + */
> > +
> > +#ifndef __INTEL_FPGA_FEATURE_H
> > +#define __INTEL_FPGA_FEATURE_H
> > +
> > +#include <linux/fs.h>
> > +#include <linux/pci.h>
> > +#include <linux/uuid.h>
> > +#include <linux/delay.h>
> > +#include <linux/iopoll.h>
> > +#include <linux/platform_device.h>
> > +
> > +#ifndef readq
> > +static inline u64 readq(void __iomem *addr)
> > +{
> > + return readl(addr) + ((u64)readl(addr + 4) << 32);
> > +}
> > +#endif
> > +
> > +#ifndef writeq
> > +static inline void writeq(u64 val, void __iomem *addr)
> > +{
> > + writel((u32) (val), addr);
> > + writel((u32) (val >> 32), (addr + 4));
> > +}
> > +#endif
>
> Hi Hao,
>
> Was there a reason readq and writeq had to be created for this? Do
> these get used?
>
Hi Alan
Thanks for your review.
Driver uses writeq and readq to access HW registers.
Actually this is a problem reported by kbuild against the patch set v1[1].
Writeq/readq are missed in some arch, so I added writeq/readq definitions to
resolve this problem following the same way done by some existing drivers.
After recheck this today, I found I should use linux/io-64-nonatomic-lo-hi.h
instead of rewriting them. I will fix it in the next version.
[1] http://marc.info/?l=linux-kernel&m=149100396816882&w=2
Thanks
Hao
> Alan
next prev parent reply other threads:[~2017-07-18 2:29 UTC|newest]
Thread overview: 94+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-06-26 1:51 [PATCH v2 00/22] Intel FPGA Device Drivers Wu Hao
[not found] ` <1498441938-14046-1-git-send-email-hao.wu-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>
2017-06-26 1:51 ` [PATCH v2 01/22] docs: fpga: add a document for Intel FPGA driver overview Wu Hao
2017-07-12 14:51 ` Alan Tull
[not found] ` <CANk1AXTDVVRG05H9kwZujFYGGS=AjQ2cdfrBm=bRNz9S7p6R6w-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2017-07-13 4:25 ` Wu Hao
2017-07-14 23:59 ` Luebbers, Enno
2017-07-17 20:14 ` Alan Tull
[not found] ` <CANk1AXTLhbczboA=wCYGUhnJyyYfvmUqUpk490sk34eh-MU5Ew-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2017-07-18 5:22 ` Greg KH
[not found] ` <20170718052228.GA10631-U8xfFu+wG4EAvxtiuMwx3w@public.gmane.org>
2017-07-18 14:32 ` Alan Tull
2017-06-26 1:51 ` [PATCH v2 02/22] fpga: add FPGA device framework Wu Hao
2017-07-27 16:35 ` Alan Tull
[not found] ` <CANk1AXRoxz7nOY--UYfBtg-3kGFy0gqCz0cbF9mOvzU2+EdzpA-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2017-07-27 19:10 ` Rob Herring
[not found] ` <CAL_JsqJfGJwDcXtpBs73TsSKTCwfAPywgyTPwzy1GQotJ7DTzw-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2017-07-31 21:40 ` Alan Tull
[not found] ` <CANk1AXTsBQgX+0hYZA6mMhESApB-MkG9CETWExSPOpf7MXeKFw-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2017-08-01 8:43 ` Wu Hao
2017-08-01 21:04 ` Alan Tull
2017-08-02 14:07 ` Wu Hao
2017-08-02 21:01 ` Alan Tull
2017-08-07 15:13 ` Alan Tull
2017-07-27 16:44 ` Alan Tull
[not found] ` <CANk1AXR-nSB-6TKpVyskbvfj_F2=jbSv48hpp+UXtKxkTseLqw-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2017-07-28 7:55 ` Wu Hao
2017-06-26 1:51 ` [PATCH v2 03/22] fpga: bridge: remove OF dependency for fpga-bridge Wu Hao
2017-08-02 21:21 ` Alan Tull
2017-09-25 16:34 ` Moritz Fischer
[not found] ` <1498441938-14046-4-git-send-email-hao.wu-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>
2017-09-21 19:11 ` Moritz Fischer
2017-09-21 19:50 ` Alan Tull
[not found] ` <CANk1AXRbXybjwq-ha=G6Z7nXwd8fNjPWP5awTz6=23KVXbd=kQ-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2017-09-22 2:15 ` Wu Hao
2017-09-23 1:53 ` Alan Tull
2017-06-26 1:52 ` [PATCH v2 04/22] fpga: mgr: add region_id to fpga_image_info Wu Hao
[not found] ` <1498441938-14046-5-git-send-email-hao.wu-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>
2017-07-26 18:33 ` Alan Tull
2017-07-27 5:14 ` Wu Hao
2017-06-26 1:52 ` [PATCH v2 09/22] fpga: intel: pcie: adds fpga_for_each_port callback for fme device Wu Hao
2017-08-17 21:31 ` Alan Tull
[not found] ` <CANk1AXRQfGViXn+vEErmN6N8LtOsX7Arh-VPPbDjKiEyGGvV-A-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2017-08-18 7:03 ` Wu Hao
2017-06-26 1:52 ` [PATCH v2 10/22] fpga: intel: add feature device infrastructure Wu Hao
2017-06-26 1:52 ` [PATCH v2 12/22] fpga: intel: fme: add header sub feature support Wu Hao
2017-07-17 18:53 ` Alan Tull
2017-07-18 1:17 ` Wu, Hao
[not found] ` <BE8371DA886269458E0220A16DC1F8277E058300-0J0gbvR4kTg/UvCtAeCM4rfspsVTdybXVpNB7YpNyf8@public.gmane.org>
2017-07-18 14:33 ` Alan Tull
2017-06-26 1:52 ` [PATCH v2 14/22] fpga: intel: fme: add partial reconfiguration " Wu Hao
2017-06-26 1:52 ` [PATCH v2 16/22] fpga: intel: add fpga bridge platform driver for FME Wu Hao
[not found] ` <1498441938-14046-17-git-send-email-hao.wu-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>
2017-08-17 19:34 ` Alan Tull
2017-08-17 19:55 ` Moritz Fischer
2017-08-18 3:06 ` Wu Hao
2017-06-26 1:52 ` [PATCH v2 18/22] fpga: intel: add FPGA Accelerated Function Unit driver basic framework Wu Hao
[not found] ` <1498441938-14046-19-git-send-email-hao.wu-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>
2017-08-17 19:00 ` Alan Tull
[not found] ` <CANk1AXSN76qZD+h8iBeYGPEGwquvGms9VC2tXG7rf16NeNUoiw-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2017-08-18 6:40 ` Wu Hao
2017-08-17 19:09 ` Moritz Fischer
[not found] ` <CAAtXAHca6R7rKOmFHD0eic1dv-NxfG3fBS+yRVFNYoX_M0eVbw-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2017-08-18 6:42 ` Wu Hao
2017-06-26 1:52 ` [PATCH v2 19/22] fpga: intel: afu: add header sub feature support Wu Hao
2017-08-14 21:37 ` Alan Tull
[not found] ` <CANk1AXSb==KikMjw4PJ4Yx97vT5JxDkHR5k2Cb0cdrQFUOZqQw-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2017-08-16 5:11 ` Wu, Hao
2017-08-17 21:41 ` Alan Tull
2017-06-26 1:52 ` [PATCH v2 20/22] fpga: intel: afu add FPGA_GET_API_VERSION/CHECK_EXTENSION ioctls support Wu Hao
2017-08-17 19:07 ` Alan Tull
2017-08-17 19:12 ` Moritz Fischer
[not found] ` <CAAtXAHdyCNBRHdk-9L+AOT7g7BEsxBN-EkdhxO2-aSqdDovTHg-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2017-08-18 3:20 ` Wu Hao
2017-06-26 1:52 ` [PATCH v2 21/22] fpga: intel: afu: add user afu sub feature support Wu Hao
2017-06-26 1:52 ` [PATCH v2 22/22] fpga: intel: afu: add FPGA_PORT_DMA_MAP/UNMAP ioctls support Wu Hao
2017-07-31 21:41 ` Alan Tull
[not found] ` <CANk1AXQ0kKnDOWo_BLA_r3P_rsmiZ1LQCVWqXtmXYmkUnzDtog-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2017-08-01 7:21 ` Wu Hao
2017-08-01 18:15 ` Moritz Fischer
[not found] ` <CAAtXAHfB906JNRzwzrx9kB4kMwcTz-201QQSr=486j8hrH7WMA-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2017-08-02 7:30 ` Wu Hao
2017-07-28 13:28 ` [PATCH v2 00/22] Intel FPGA Device Drivers Alan Tull
2017-06-26 1:52 ` [PATCH v2 05/22] fpga: mgr: add status for fpga-mgr Wu Hao
[not found] ` <1498441938-14046-6-git-send-email-hao.wu-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>
2017-07-12 15:22 ` Alan Tull
[not found] ` <CANk1AXQ4-BWzhRjR+BTmnSae+4FeBamZyYbH1MMZWaAqeW_CEA-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2017-07-13 3:11 ` Wu Hao
2017-06-26 1:52 ` [PATCH v2 06/22] fpga: intel: add FPGA PCIe device driver Wu Hao
2017-08-07 20:43 ` Alan Tull
[not found] ` <CANk1AXQ__fFCfv335ySGMxG=8UXReEk8V1=a-3pCw5S-v=sSRQ-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2017-08-14 12:33 ` Wu, Hao
2017-06-26 1:52 ` [PATCH v2 07/22] fpga: intel: pcie: parse feature list and create platform device for features Wu Hao
2017-06-26 18:42 ` Moritz Fischer
2017-06-27 3:17 ` Wu Hao
[not found] ` <20170626184205.GA13190-R0KNJUYl863z/wjs7L+eiWPmTBeX6bocVpNB7YpNyf8@public.gmane.org>
2017-06-27 15:34 ` Alan Tull
[not found] ` <1498441938-14046-8-git-send-email-hao.wu-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>
2017-07-13 17:52 ` Alan Tull
[not found] ` <CANk1AXS-VftzKmmK4P3Anas+DQZ0ZPQ=7yVQt=QrNULPY7PaDA-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2017-07-14 9:22 ` Wu Hao
2017-07-17 19:15 ` Alan Tull
2017-07-18 2:29 ` Wu, Hao [this message]
2017-09-20 21:24 ` Alan Tull
2017-09-21 19:58 ` Alan Tull
[not found] ` <CANk1AXTvHm-y0vUmCTPX47T9G1TJsatfwoC-bx-tPFRoJA9+AA-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2017-09-22 7:33 ` Wu Hao
2017-09-22 7:28 ` Wu Hao
2017-09-27 20:27 ` Alan Tull
[not found] ` <CANk1AXQe2mrpqq-7uc8QvPPBYaMvQjBhbjLaee1XQ6L+kiCKTQ-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2017-09-28 9:32 ` Wu Hao
2017-06-26 1:52 ` [PATCH v2 08/22] fpga: intel: pcie: add chardev support for feature devices Wu Hao
2017-06-26 1:52 ` [PATCH v2 11/22] fpga: intel: add FPGA Management Engine driver basic framework Wu Hao
2017-06-26 1:52 ` [PATCH v2 13/22] fpga: intel: fme: add FPGA_GET_API_VERSION/CHECK_EXTENSION ioctls support Wu Hao
2017-08-17 19:11 ` Alan Tull
2017-06-26 1:52 ` [PATCH v2 15/22] fpga: intel: add fpga manager platform driver for FME Wu Hao
2017-09-25 21:24 ` Moritz Fischer
[not found] ` <20170925212457.GB14795-KFgJe6S/L2nknyRNNOXSQ2IaLvZF3x2V0E9HWUfgJXw@public.gmane.org>
2017-09-27 1:18 ` Wu Hao
2017-09-27 18:54 ` Alan Tull
[not found] ` <CANk1AXTQLiR7ayLzsgU9TOePY2Zc01P-mMOy7n509S7+bcS-5A-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2017-09-28 8:25 ` Wu Hao
2017-06-26 1:52 ` [PATCH v2 17/22] fpga: intel: add fpga region " Wu Hao
[not found] ` <1498441938-14046-18-git-send-email-hao.wu-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>
2017-07-12 16:09 ` Alan Tull
[not found] ` <CANk1AXRioZsobi9k_VVcRypV+LrviPLjRejb_Og9VwKhCRth5g-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2017-07-13 2:31 ` Wu Hao
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