From: Alan Tull <atull@kernel.org>
To: "Wu, Hao" <hao.wu@intel.com>
Cc: Moritz Fischer <mdf@kernel.org>,
"linux-fpga@vger.kernel.org" <linux-fpga@vger.kernel.org>,
linux-kernel <linux-kernel@vger.kernel.org>,
"linux-api@vger.kernel.org" <linux-api@vger.kernel.org>,
"Kang, Luwei" <luwei.kang@intel.com>,
"Zhang, Yi Z" <yi.z.zhang@intel.com>,
"Whisonant, Tim" <tim.whisonant@intel.com>,
"Luebbers, Enno" <enno.luebbers@intel.com>,
"Rao, Shiva" <shiva.rao@intel.com>,
"Rauer, Christopher" <christopher.rauer@intel.com>
Subject: Re: [PATCH v2 19/22] fpga: intel: afu: add header sub feature support
Date: Thu, 17 Aug 2017 16:41:00 -0500 [thread overview]
Message-ID: <CANk1AXQiNLgE6fmty=7kMCU1Zh2xrH85koeieAngyLkf0eeDqA@mail.gmail.com> (raw)
In-Reply-To: <BE8371DA886269458E0220A16DC1F8277E07F3DE@SHSMSX104.ccr.corp.intel.com>
On Wed, Aug 16, 2017 at 12:11 AM, Wu, Hao <hao.wu@intel.com> wrote:
>> On Sun, Jun 25, 2017 at 8:52 PM, Wu Hao <hao.wu@intel.com> wrote:
>>
>> Hi Hao,
>>
>> > The header register set is always present for the Port/AFU, it is mainly
>> > for capability, control and status of the ports that AFU connected to.
>>
>> So just to be clear, the reset function is acting on the Port, not the
>> AFU, right?
>
> Hi Alan
>
> AFU will be reset as well. Once port reset is issued, a compliant HW
> AFU will reset all its state and stop sending requests, and HW will set
> port reset ack bit when all outstanding requests initiated have been
> drained.
>
> Will add some notes here.
>
>>
>> >
>> > This patch implements header sub feature support.
>>
>> Please add a brief reminder here what the 'header' is. It's defined
>> in patch 7 as being part of the feature list, but hardly mentioned
>> when I grep intel-fpga.txt.
>
> Sure, will adds some notes here.
>
> Actually the header sub feature means the registers belong to the
> feature device (e.g port and FME), not any sub features (e.g PR,
> Power management).
>
>>
>> > Below user interfaces
>> > are created by this patch.
>> >
>> > Sysfs interface:
>> > * /sys/class/fpga/<fpga.x>/<intel-fpga-port.x>/id
>> > Read-only. Port ID.
>> >
>> > Ioctl interface:
>> > * FPGA_PORT_RESET
>> > Reset the FPGA AFU Port.
>> >
>> > Signed-off-by: Tim Whisonant <tim.whisonant@intel.com>
>> > Signed-off-by: Enno Luebbers <enno.luebbers@intel.com>
>> > Signed-off-by: Shiva Rao <shiva.rao@intel.com>
>> > Signed-off-by: Christopher Rauer <christopher.rauer@intel.com>
>> > Signed-off-by: Xiao Guangrong <guangrong.xiao@linux.intel.com>
>> > Signed-off-by: Wu Hao <hao.wu@intel.com>
>> > ---
>> > v2: add sysfs documentation.
>> > ---
>> > .../ABI/testing/sysfs-platform-intel-fpga-afu | 7 ++++
>> > drivers/fpga/intel-afu-main.c | 44 +++++++++++++++++++++-
>> > include/uapi/linux/intel-fpga.h | 14 +++++++
>> > 3 files changed, 64 insertions(+), 1 deletion(-)
>> > create mode 100644 Documentation/ABI/testing/sysfs-platform-intel-fpga-
>> afu
>> >
>> > diff --git a/Documentation/ABI/testing/sysfs-platform-intel-fpga-afu
>> b/Documentation/ABI/testing/sysfs-platform-intel-fpga-afu
>> > new file mode 100644
>> > index 0000000..8ad22c9
>> > --- /dev/null
>> > +++ b/Documentation/ABI/testing/sysfs-platform-intel-fpga-afu
>> > @@ -0,0 +1,7 @@
>> > +What: /sys/bus/platform/devices/intel-fpga-port.0/id
>> > +Date: June 2017
>> > +KernelVersion: 4.12
>> > +Contact: Wu Hao <hao.wu@intel.com>
>> > +Description: Read-only. It returns id of this port. One Intel FPGA device
>> > + may have more than one port. Userspace could use this id to
>> > + distinguish different ports under same FPGA device.
>> > diff --git a/drivers/fpga/intel-afu-main.c b/drivers/fpga/intel-afu-main.c
>> > index 96d0367..2a17cde 100644
>> > --- a/drivers/fpga/intel-afu-main.c
>> > +++ b/drivers/fpga/intel-afu-main.c
>> > @@ -18,25 +18,66 @@
>> >
>> > #include <linux/kernel.h>
>> > #include <linux/module.h>
>> > +#include <linux/intel-fpga.h>
>> >
>> > #include "intel-feature-dev.h"
>> >
>> > +static ssize_t
>> > +id_show(struct device *dev, struct device_attribute *attr, char *buf)
>> > +{
>> > + int id = fpga_port_id(to_platform_device(dev));
>> > +
>> > + return scnprintf(buf, PAGE_SIZE, "%d\n", id);
>> > +}
>> > +static DEVICE_ATTR_RO(id);
>> > +
>> > +static const struct attribute *port_hdr_attrs[] = {
>> > + &dev_attr_id.attr,
>> > + NULL,
>> > +};
>> > +
>> > static int port_hdr_init(struct platform_device *pdev, struct feature *feature)
>> > {
>> > dev_dbg(&pdev->dev, "PORT HDR Init.\n");
>> >
>> > - return 0;
>> > + fpga_port_reset(pdev);
>>
>> So the port will be reset here, which happens during fme_probe().
>> IIUC the PR region is empty then, there is just the static region,
>> right?
>
> port_hdr_init is invoked during afu_probe() function. The fpga_port_reset
> only resets the AFU's state and not empty the PR region. User doesn't need
> to program it again after port reset.
>
> The purpose of this reset in port_hdr_init function, is to make sure that we
> could have a clean start whenever the port driver module is loaded. And
> similar as the one added in afu release.
>
>>
>> > +
>> > + return sysfs_create_files(&pdev->dev.kobj, port_hdr_attrs);
>>
>> Greg wrote an article that there could be a race condition caused by
>> creating sysfs files this late [1] and I see sysfs_create_files() used
>> very sparingly in the kernel. I'm thinking that fpga-bridge should
>> provide a place to create sysfs files earlier by adding an
>> attribute_group to fpga_bridge_ops (same for fpga-mgr and fpga-region)
>> and then fpga_bridge_register could do bridge->dev.groups =
>> br_ops->groups. I'll put a patch for that out soon.
>>
>
> Hm... I understand there could be a race condition if creates sysfs files late.
> Actually the reasons I prefer to have each sub feature to create its own sysfs
> files are, 1) if any sub feature is not present, then related init function won't
> be invoked and related sysfs files won't be created at all. Then end user could
> know which sub features are present by checking these sysfs nodes easily.
> 2) Another point of view is about extension of each sub feature, for example,
> Some new registers introduced when sub feature's revision > n, so each sub
> feature's init function could check the sub feature's revision to decide which
> sysfs interfaces are needed. I think this should be a flexible way for extension.
>
>> > }
>> >
>> > static void port_hdr_uinit(struct platform_device *pdev,
>> > struct feature *feature)
>> > {
>> > dev_dbg(&pdev->dev, "PORT HDR UInit.\n");
>> > +
>> > + sysfs_remove_files(&pdev->dev.kobj, port_hdr_attrs);
>> > +}
>> > +
>> > +static long
>> > +port_hdr_ioctl(struct platform_device *pdev, struct feature *feature,
>> > + unsigned int cmd, unsigned long arg)
>> > +{
>> > + long ret;
>> > +
>> > + switch (cmd) {
>> > + case FPGA_PORT_RESET:
>> > + if (!arg)
>> > + ret = fpga_port_reset(pdev);
>>
>> fpga_port_reset() disables and reenables traffic on the port. Is
>> there ever a time when that would be unsafe to do? Like while DMA is
>> happening? When I see a function called 'reset' exposed to userspace,
>> I become concerned that hitting that reset at the wrong time could
>> cause problems. We've discussed this some, but could you please
>> remind me when userspace would need to reset the port? Please add
>> documentation of what the intended use of this ioctl would be, when it
>> is valid to request a reset from userspace and when userspace should
>> never do that.
>
> Sure, I will add some more description in uapi header file on this IOCTL.
>
> Per my understanding, this API could be invoked at any time, even there
> is some DMA operation or PR operation at the same time. It should not
> cause any system level problem, but may cause functional failures ( e.g
> DMA or PR operation failure) and it should be recoverable.
OK that was my biggest concern here with the reset.
>
>>
>> The pcie code, the AFU file interface, and the bridge code all do port
>> reset. This code is spread out over a few patches, but I'll comment
>> here for now. I'm trying to keep track of everything that resets the
>> port. The port gets reset in afu_probe, fme_probe, the AFU file
>> release, and intel-pcie.c after parsing the features. Also the port
>> is esentially reset after doing reprogramming, since that involves a
>> bridge disable/enable. In the v1 review, the issue raised that the
>> port functionality could be an expansion of fpga-bridge. If reset
>> were added to the fpga_bridge_ops and a fpga_bridge_reset API added to
>> fpga-bridge, then anything in the kernel that owns the bridge could
>> reset it. That is of course assuming that this code doesn't need to
>> reset the port before the fpga-bridge is created.
>
> Actually in the pcie code, it needs to enable fpga port (put it out of reset,
> as port is in reset by default), otherwise the AFU MMIO region is not
> accessible. It's only a one time action.
>
> For the AFU interface, it gives application a way to reset the AFU if
> anything goes wrong or application wants to make AFU back to
> default state.
>
> For the bridge code, it just makes sure port is in reset during PR, which
> is requested by the PR flow of Intel FPGA device.
>
> As you know, the fpga-bridge is created under FME module now, and
> port/AFU is another module which could be turned into a VF and assigned
> to a virtual machine, even we added a reset ops to fpga-bridge, we still
> need an interface to do port reset as fpga-bridges (and FME) are always
> in PF in host. :)
OK
Alan
>
> Thanks
> Hao
>
>>
>> Thanks,
>> Alan Tull
>>
>> [1] http://www.kroah.com/log/blog/2013/06/26/how-to-create-a-sysfs-file-
>> correctly/
>>
>> > + else
>> > + ret = -EINVAL;
>> > + break;
>> > + default:
>> > + dev_dbg(&pdev->dev, "%x cmd not handled", cmd);
>> > + ret = -ENODEV;
>> > + }
>> > +
>> > + return ret;
>> > }
>> >
>> > struct feature_ops port_hdr_ops = {
>> > .init = port_hdr_init,
>> > .uinit = port_hdr_uinit,
>> > + .ioctl = port_hdr_ioctl,
>> > };
>> >
>> > static struct feature_driver port_feature_drvs[] = {
>> > @@ -76,6 +117,7 @@ static int afu_release(struct inode *inode, struct file
>> *filp)
>> >
>> > dev_dbg(&pdev->dev, "Device File Release\n");
>> >
>> > + fpga_port_reset(pdev);
>> > feature_dev_use_end(pdata);
>> > return 0;
>> > }
>> > diff --git a/include/uapi/linux/intel-fpga.h b/include/uapi/linux/intel-fpga.h
>> > index be295ae..be5f813 100644
>> > --- a/include/uapi/linux/intel-fpga.h
>> > +++ b/include/uapi/linux/intel-fpga.h
>> > @@ -30,8 +30,11 @@
>> > #define FPGA_MAGIC 0xB6
>> >
>> > #define FPGA_BASE 0
>> > +#define PORT_BASE 0x40
>> > #define FME_BASE 0x80
>> >
>> > +/* Common IOCTLs for both FME and AFU file descriptor */
>> > +
>> > /**
>> > * FPGA_GET_API_VERSION - _IO(FPGA_MAGIC, FPGA_BASE + 0)
>> > *
>> > @@ -50,6 +53,17 @@
>> >
>> > #define FPGA_CHECK_EXTENSION _IO(FPGA_MAGIC, FPGA_BASE + 1)
>> >
>> > +/* IOCTLs for AFU file descriptor */
>> > +
>> > +/**
>> > + * FPGA_PORT_RESET - _IO(FPGA_MAGIC, PORT_BASE + 0)
>> > + *
>> > + * Reset the FPGA AFU Port. No parameters are supported.
>> > + * Return: 0 on success, -errno of failure
>> > + */
>> > +
>> > +#define FPGA_PORT_RESET _IO(FPGA_MAGIC, PORT_BASE + 0)
>> > +
>> > /* IOCTLs for FME file descriptor */
>> >
>> > /**
>> > --
>> > 1.8.3.1
>> >
next prev parent reply other threads:[~2017-08-17 21:41 UTC|newest]
Thread overview: 94+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-06-26 1:51 [PATCH v2 00/22] Intel FPGA Device Drivers Wu Hao
[not found] ` <1498441938-14046-1-git-send-email-hao.wu-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>
2017-06-26 1:51 ` [PATCH v2 01/22] docs: fpga: add a document for Intel FPGA driver overview Wu Hao
2017-07-12 14:51 ` Alan Tull
[not found] ` <CANk1AXTDVVRG05H9kwZujFYGGS=AjQ2cdfrBm=bRNz9S7p6R6w-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2017-07-13 4:25 ` Wu Hao
2017-07-14 23:59 ` Luebbers, Enno
2017-07-17 20:14 ` Alan Tull
[not found] ` <CANk1AXTLhbczboA=wCYGUhnJyyYfvmUqUpk490sk34eh-MU5Ew-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2017-07-18 5:22 ` Greg KH
[not found] ` <20170718052228.GA10631-U8xfFu+wG4EAvxtiuMwx3w@public.gmane.org>
2017-07-18 14:32 ` Alan Tull
2017-06-26 1:51 ` [PATCH v2 02/22] fpga: add FPGA device framework Wu Hao
2017-07-27 16:35 ` Alan Tull
[not found] ` <CANk1AXRoxz7nOY--UYfBtg-3kGFy0gqCz0cbF9mOvzU2+EdzpA-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2017-07-27 19:10 ` Rob Herring
[not found] ` <CAL_JsqJfGJwDcXtpBs73TsSKTCwfAPywgyTPwzy1GQotJ7DTzw-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2017-07-31 21:40 ` Alan Tull
[not found] ` <CANk1AXTsBQgX+0hYZA6mMhESApB-MkG9CETWExSPOpf7MXeKFw-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2017-08-01 8:43 ` Wu Hao
2017-08-01 21:04 ` Alan Tull
2017-08-02 14:07 ` Wu Hao
2017-08-02 21:01 ` Alan Tull
2017-08-07 15:13 ` Alan Tull
2017-07-27 16:44 ` Alan Tull
[not found] ` <CANk1AXR-nSB-6TKpVyskbvfj_F2=jbSv48hpp+UXtKxkTseLqw-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2017-07-28 7:55 ` Wu Hao
2017-06-26 1:51 ` [PATCH v2 03/22] fpga: bridge: remove OF dependency for fpga-bridge Wu Hao
2017-08-02 21:21 ` Alan Tull
2017-09-25 16:34 ` Moritz Fischer
[not found] ` <1498441938-14046-4-git-send-email-hao.wu-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>
2017-09-21 19:11 ` Moritz Fischer
2017-09-21 19:50 ` Alan Tull
[not found] ` <CANk1AXRbXybjwq-ha=G6Z7nXwd8fNjPWP5awTz6=23KVXbd=kQ-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2017-09-22 2:15 ` Wu Hao
2017-09-23 1:53 ` Alan Tull
2017-06-26 1:52 ` [PATCH v2 04/22] fpga: mgr: add region_id to fpga_image_info Wu Hao
[not found] ` <1498441938-14046-5-git-send-email-hao.wu-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>
2017-07-26 18:33 ` Alan Tull
2017-07-27 5:14 ` Wu Hao
2017-06-26 1:52 ` [PATCH v2 09/22] fpga: intel: pcie: adds fpga_for_each_port callback for fme device Wu Hao
2017-08-17 21:31 ` Alan Tull
[not found] ` <CANk1AXRQfGViXn+vEErmN6N8LtOsX7Arh-VPPbDjKiEyGGvV-A-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2017-08-18 7:03 ` Wu Hao
2017-06-26 1:52 ` [PATCH v2 10/22] fpga: intel: add feature device infrastructure Wu Hao
2017-06-26 1:52 ` [PATCH v2 12/22] fpga: intel: fme: add header sub feature support Wu Hao
2017-07-17 18:53 ` Alan Tull
2017-07-18 1:17 ` Wu, Hao
[not found] ` <BE8371DA886269458E0220A16DC1F8277E058300-0J0gbvR4kTg/UvCtAeCM4rfspsVTdybXVpNB7YpNyf8@public.gmane.org>
2017-07-18 14:33 ` Alan Tull
2017-06-26 1:52 ` [PATCH v2 14/22] fpga: intel: fme: add partial reconfiguration " Wu Hao
2017-06-26 1:52 ` [PATCH v2 16/22] fpga: intel: add fpga bridge platform driver for FME Wu Hao
[not found] ` <1498441938-14046-17-git-send-email-hao.wu-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>
2017-08-17 19:34 ` Alan Tull
2017-08-17 19:55 ` Moritz Fischer
2017-08-18 3:06 ` Wu Hao
2017-06-26 1:52 ` [PATCH v2 18/22] fpga: intel: add FPGA Accelerated Function Unit driver basic framework Wu Hao
[not found] ` <1498441938-14046-19-git-send-email-hao.wu-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>
2017-08-17 19:00 ` Alan Tull
[not found] ` <CANk1AXSN76qZD+h8iBeYGPEGwquvGms9VC2tXG7rf16NeNUoiw-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2017-08-18 6:40 ` Wu Hao
2017-08-17 19:09 ` Moritz Fischer
[not found] ` <CAAtXAHca6R7rKOmFHD0eic1dv-NxfG3fBS+yRVFNYoX_M0eVbw-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2017-08-18 6:42 ` Wu Hao
2017-06-26 1:52 ` [PATCH v2 19/22] fpga: intel: afu: add header sub feature support Wu Hao
2017-08-14 21:37 ` Alan Tull
[not found] ` <CANk1AXSb==KikMjw4PJ4Yx97vT5JxDkHR5k2Cb0cdrQFUOZqQw-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2017-08-16 5:11 ` Wu, Hao
2017-08-17 21:41 ` Alan Tull [this message]
2017-06-26 1:52 ` [PATCH v2 20/22] fpga: intel: afu add FPGA_GET_API_VERSION/CHECK_EXTENSION ioctls support Wu Hao
2017-08-17 19:07 ` Alan Tull
2017-08-17 19:12 ` Moritz Fischer
[not found] ` <CAAtXAHdyCNBRHdk-9L+AOT7g7BEsxBN-EkdhxO2-aSqdDovTHg-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2017-08-18 3:20 ` Wu Hao
2017-06-26 1:52 ` [PATCH v2 21/22] fpga: intel: afu: add user afu sub feature support Wu Hao
2017-06-26 1:52 ` [PATCH v2 22/22] fpga: intel: afu: add FPGA_PORT_DMA_MAP/UNMAP ioctls support Wu Hao
2017-07-31 21:41 ` Alan Tull
[not found] ` <CANk1AXQ0kKnDOWo_BLA_r3P_rsmiZ1LQCVWqXtmXYmkUnzDtog-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2017-08-01 7:21 ` Wu Hao
2017-08-01 18:15 ` Moritz Fischer
[not found] ` <CAAtXAHfB906JNRzwzrx9kB4kMwcTz-201QQSr=486j8hrH7WMA-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2017-08-02 7:30 ` Wu Hao
2017-07-28 13:28 ` [PATCH v2 00/22] Intel FPGA Device Drivers Alan Tull
2017-06-26 1:52 ` [PATCH v2 05/22] fpga: mgr: add status for fpga-mgr Wu Hao
[not found] ` <1498441938-14046-6-git-send-email-hao.wu-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>
2017-07-12 15:22 ` Alan Tull
[not found] ` <CANk1AXQ4-BWzhRjR+BTmnSae+4FeBamZyYbH1MMZWaAqeW_CEA-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2017-07-13 3:11 ` Wu Hao
2017-06-26 1:52 ` [PATCH v2 06/22] fpga: intel: add FPGA PCIe device driver Wu Hao
2017-08-07 20:43 ` Alan Tull
[not found] ` <CANk1AXQ__fFCfv335ySGMxG=8UXReEk8V1=a-3pCw5S-v=sSRQ-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2017-08-14 12:33 ` Wu, Hao
2017-06-26 1:52 ` [PATCH v2 07/22] fpga: intel: pcie: parse feature list and create platform device for features Wu Hao
2017-06-26 18:42 ` Moritz Fischer
2017-06-27 3:17 ` Wu Hao
[not found] ` <20170626184205.GA13190-R0KNJUYl863z/wjs7L+eiWPmTBeX6bocVpNB7YpNyf8@public.gmane.org>
2017-06-27 15:34 ` Alan Tull
[not found] ` <1498441938-14046-8-git-send-email-hao.wu-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>
2017-07-13 17:52 ` Alan Tull
[not found] ` <CANk1AXS-VftzKmmK4P3Anas+DQZ0ZPQ=7yVQt=QrNULPY7PaDA-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2017-07-14 9:22 ` Wu Hao
2017-07-17 19:15 ` Alan Tull
2017-07-18 2:29 ` Wu, Hao
2017-09-20 21:24 ` Alan Tull
2017-09-21 19:58 ` Alan Tull
[not found] ` <CANk1AXTvHm-y0vUmCTPX47T9G1TJsatfwoC-bx-tPFRoJA9+AA-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2017-09-22 7:33 ` Wu Hao
2017-09-22 7:28 ` Wu Hao
2017-09-27 20:27 ` Alan Tull
[not found] ` <CANk1AXQe2mrpqq-7uc8QvPPBYaMvQjBhbjLaee1XQ6L+kiCKTQ-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2017-09-28 9:32 ` Wu Hao
2017-06-26 1:52 ` [PATCH v2 08/22] fpga: intel: pcie: add chardev support for feature devices Wu Hao
2017-06-26 1:52 ` [PATCH v2 11/22] fpga: intel: add FPGA Management Engine driver basic framework Wu Hao
2017-06-26 1:52 ` [PATCH v2 13/22] fpga: intel: fme: add FPGA_GET_API_VERSION/CHECK_EXTENSION ioctls support Wu Hao
2017-08-17 19:11 ` Alan Tull
2017-06-26 1:52 ` [PATCH v2 15/22] fpga: intel: add fpga manager platform driver for FME Wu Hao
2017-09-25 21:24 ` Moritz Fischer
[not found] ` <20170925212457.GB14795-KFgJe6S/L2nknyRNNOXSQ2IaLvZF3x2V0E9HWUfgJXw@public.gmane.org>
2017-09-27 1:18 ` Wu Hao
2017-09-27 18:54 ` Alan Tull
[not found] ` <CANk1AXTQLiR7ayLzsgU9TOePY2Zc01P-mMOy7n509S7+bcS-5A-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2017-09-28 8:25 ` Wu Hao
2017-06-26 1:52 ` [PATCH v2 17/22] fpga: intel: add fpga region " Wu Hao
[not found] ` <1498441938-14046-18-git-send-email-hao.wu-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>
2017-07-12 16:09 ` Alan Tull
[not found] ` <CANk1AXRioZsobi9k_VVcRypV+LrviPLjRejb_Og9VwKhCRth5g-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2017-07-13 2:31 ` Wu Hao
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to='CANk1AXQiNLgE6fmty=7kMCU1Zh2xrH85koeieAngyLkf0eeDqA@mail.gmail.com' \
--to=atull@kernel.org \
--cc=christopher.rauer@intel.com \
--cc=enno.luebbers@intel.com \
--cc=hao.wu@intel.com \
--cc=linux-api@vger.kernel.org \
--cc=linux-fpga@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=luwei.kang@intel.com \
--cc=mdf@kernel.org \
--cc=shiva.rao@intel.com \
--cc=tim.whisonant@intel.com \
--cc=yi.z.zhang@intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).