* [PATCH 0/2] clk: sun8i: Add MBUS support
@ 2014-09-12 16:48 Chen-Yu Tsai
2014-09-12 16:48 ` [PATCH 1/2] clk: sunxi: Add sun8i MBUS clock support Chen-Yu Tsai
2014-09-12 16:48 ` [PATCH 2/2] ARM: dts: sun8i: Add PLL6 and MBUS clock nodes Chen-Yu Tsai
0 siblings, 2 replies; 5+ messages in thread
From: Chen-Yu Tsai @ 2014-09-12 16:48 UTC (permalink / raw)
To: linux-arm-kernel
Hi,
This series adds support for the MBUS clock on sun8i. It is slightly
different from the old mod0 clocks in that the divider is 3 bits wider,
while also needing a divider table.
This series depends on Maxime's "clk: sunxi: Improve MMC clocks support"
series, specifically the patches that change the factor clocks and move
out mod0 and mbus. Ideally this series should also be merged after my
"clk: sun6i: Unify AHB1 clock and fix rate calculation" for the PLL6
corrections, but I don't think it would cause any issues if it didn't.
Patch 1 adds the sun8i specific MBUS clock driver.
Patch 2 adds proper PLL6 and MBUS clock nodes to the DT, with a dummy
PLL5 clock node as a parent to MBUS.
Cheers
ChenYu
Chen-Yu Tsai (2):
clk: sunxi: Add sun8i MBUS clock support
ARM: dts: sun8i: Add PLL6 and MBUS clock nodes
Documentation/devicetree/bindings/clock/sunxi.txt | 1 +
arch/arm/boot/dts/sun8i-a23.dtsi | 29 +++++++++++-
drivers/clk/sunxi/clk-mod0.c | 55 +++++++++++++++++++++++
3 files changed, 83 insertions(+), 2 deletions(-)
--
2.1.0
^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH 1/2] clk: sunxi: Add sun8i MBUS clock support
2014-09-12 16:48 [PATCH 0/2] clk: sun8i: Add MBUS support Chen-Yu Tsai
@ 2014-09-12 16:48 ` Chen-Yu Tsai
2014-09-15 8:20 ` Maxime Ripard
2014-09-12 16:48 ` [PATCH 2/2] ARM: dts: sun8i: Add PLL6 and MBUS clock nodes Chen-Yu Tsai
1 sibling, 1 reply; 5+ messages in thread
From: Chen-Yu Tsai @ 2014-09-12 16:48 UTC (permalink / raw)
To: linux-arm-kernel
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
Documentation/devicetree/bindings/clock/sunxi.txt | 1 +
drivers/clk/sunxi/clk-mod0.c | 55 +++++++++++++++++++++++
2 files changed, 56 insertions(+)
diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt
index 425b109..fb3b7aa 100644
--- a/Documentation/devicetree/bindings/clock/sunxi.txt
+++ b/Documentation/devicetree/bindings/clock/sunxi.txt
@@ -50,6 +50,7 @@ Required properties:
"allwinner,sun4i-a10-mmc-output-clk" - for the MMC output clock on A10
"allwinner,sun4i-a10-mmc-sample-clk" - for the MMC sample clock on A10
"allwinner,sun4i-a10-mod0-clk" - for the module 0 family of clocks
+ "allwinner,sun8i-a23-mbus-clk" - for the MBUS clock on A23
"allwinner,sun7i-a20-out-clk" - for the external output clocks
"allwinner,sun7i-a20-gmac-clk" - for the GMAC clock module on A20/A31
"allwinner,sun4i-a10-usb-clk" - for usb gates + resets on A10 / A20
diff --git a/drivers/clk/sunxi/clk-mod0.c b/drivers/clk/sunxi/clk-mod0.c
index 4a56385..9850887 100644
--- a/drivers/clk/sunxi/clk-mod0.c
+++ b/drivers/clk/sunxi/clk-mod0.c
@@ -94,6 +94,61 @@ static void __init sun5i_a13_mbus_setup(struct device_node *node)
}
CLK_OF_DECLARE(sun5i_a13_mbus, "allwinner,sun5i-a13-mbus-clk", sun5i_a13_mbus_setup);
+/**
+ * sun8i_a23_get_mbus_factors() - calculates m factor for MBUS clocks
+ * MBUS rate is calculated as follows
+ * rate = parent_rate / (m + 1);
+ */
+
+static void sun8i_a23_get_mbus_factors(u32 *freq, u32 parent_rate,
+ u8 *n, u8 *k, u8 *m, u8 *p)
+{
+ u8 div;
+
+ /* These clocks can only divide, so we will never be able to achieve
+ * frequencies higher than the parent frequency */
+ if (*freq > parent_rate)
+ *freq = parent_rate;
+
+ div = DIV_ROUND_UP(parent_rate, *freq);
+
+ if (div > 8)
+ div = 8;
+
+ *freq = parent_rate / div;
+
+ /* we were called to round the frequency, we can now return */
+ if (m == NULL)
+ return;
+
+ *m = div - 1;
+}
+
+static struct clk_factors_config sun8i_a23_mbus_config = {
+ .mshift = 0,
+ .mwidth = 3,
+};
+
+static const struct factors_data sun8i_a23_mbus_data __initconst = {
+ .enable = 31,
+ .mux = 24,
+ .table = &sun8i_a23_mbus_config,
+ .getter = sun8i_a23_get_mbus_factors,
+};
+
+static DEFINE_SPINLOCK(sun8i_a23_mbus_lock);
+
+static void __init sun8i_a23_mbus_setup(struct device_node *node)
+{
+ struct clk *mbus = sunxi_factors_register(node, &sun8i_a23_mbus_data,
+ &sun8i_a23_mbus_lock);
+
+ /* The MBUS clocks needs to be always enabled */
+ __clk_get(mbus);
+ clk_prepare_enable(mbus);
+}
+CLK_OF_DECLARE(sun8i_a23_mbus, "allwinner,sun8i-a23-mbus-clk", sun8i_a23_mbus_setup);
+
struct mmc_phase_data {
u8 offset;
};
--
2.1.0
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH 2/2] ARM: dts: sun8i: Add PLL6 and MBUS clock nodes
2014-09-12 16:48 [PATCH 0/2] clk: sun8i: Add MBUS support Chen-Yu Tsai
2014-09-12 16:48 ` [PATCH 1/2] clk: sunxi: Add sun8i MBUS clock support Chen-Yu Tsai
@ 2014-09-12 16:48 ` Chen-Yu Tsai
1 sibling, 0 replies; 5+ messages in thread
From: Chen-Yu Tsai @ 2014-09-12 16:48 UTC (permalink / raw)
To: linux-arm-kernel
Now that the clock driver supports PLL6 and MBUS on sun8i correctly,
add the corresponding clock nodes to the dtsi.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
arch/arm/boot/dts/sun8i-a23.dtsi | 29 +++++++++++++++++++++++++++--
1 file changed, 27 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/sun8i-a23.dtsi b/arch/arm/boot/dts/sun8i-a23.dtsi
index fc0d023..c32091e 100644
--- a/arch/arm/boot/dts/sun8i-a23.dtsi
+++ b/arch/arm/boot/dts/sun8i-a23.dtsi
@@ -74,13 +74,30 @@
};
/* dummy clock until actually implemented */
- pll6: pll6_clk {
+ pll5: pll5_clk {
#clock-cells = <0>;
compatible = "fixed-clock";
- clock-frequency = <600000000>;
+ clock-frequency = <0>;
+ clock-output-names = "pll5";
+ };
+
+ pll6: clk at 01c20028 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun6i-a31-pll6-clk";
+ reg = <0x01c20028 0x4>;
+ clocks = <&osc24M>;
clock-output-names = "pll6";
};
+ pll6x2: pll6x2_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clock-div = <1>;
+ clock-mult = <2>;
+ clocks = <&pll6>;
+ clock-output-names = "pll6x2";
+ };
+
cpu: cpu_clk at 01c20050 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-a10-cpu-clk";
@@ -243,6 +260,14 @@
clocks = <&mmc2_clk>;
clock-output-names = "mmc2_sample";
};
+
+ mbus_clk: clk at 01c2015c {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun8i-a23-mbus-clk";
+ reg = <0x01c2015c 0x4>;
+ clocks = <&osc24M>, <&pll6x2>, <&pll5>;
+ clock-output-names = "mbus";
+ };
};
soc at 01c00000 {
--
2.1.0
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH 1/2] clk: sunxi: Add sun8i MBUS clock support
2014-09-12 16:48 ` [PATCH 1/2] clk: sunxi: Add sun8i MBUS clock support Chen-Yu Tsai
@ 2014-09-15 8:20 ` Maxime Ripard
2014-09-15 8:29 ` Chen-Yu Tsai
0 siblings, 1 reply; 5+ messages in thread
From: Maxime Ripard @ 2014-09-15 8:20 UTC (permalink / raw)
To: linux-arm-kernel
Hi Chen-Yu,
On Sat, Sep 13, 2014 at 12:48:05AM +0800, Chen-Yu Tsai wrote:
> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
A commit log would be nice here. Is it different from A31? do you know
wether later SoCs reuses it?
> ---
> Documentation/devicetree/bindings/clock/sunxi.txt | 1 +
> drivers/clk/sunxi/clk-mod0.c | 55 +++++++++++++++++++++++
> 2 files changed, 56 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt
> index 425b109..fb3b7aa 100644
> --- a/Documentation/devicetree/bindings/clock/sunxi.txt
> +++ b/Documentation/devicetree/bindings/clock/sunxi.txt
> @@ -50,6 +50,7 @@ Required properties:
> "allwinner,sun4i-a10-mmc-output-clk" - for the MMC output clock on A10
> "allwinner,sun4i-a10-mmc-sample-clk" - for the MMC sample clock on A10
> "allwinner,sun4i-a10-mod0-clk" - for the module 0 family of clocks
> + "allwinner,sun8i-a23-mbus-clk" - for the MBUS clock on A23
> "allwinner,sun7i-a20-out-clk" - for the external output clocks
> "allwinner,sun7i-a20-gmac-clk" - for the GMAC clock module on A20/A31
> "allwinner,sun4i-a10-usb-clk" - for usb gates + resets on A10 / A20
> diff --git a/drivers/clk/sunxi/clk-mod0.c b/drivers/clk/sunxi/clk-mod0.c
> index 4a56385..9850887 100644
> --- a/drivers/clk/sunxi/clk-mod0.c
> +++ b/drivers/clk/sunxi/clk-mod0.c
> @@ -94,6 +94,61 @@ static void __init sun5i_a13_mbus_setup(struct device_node *node)
> }
> CLK_OF_DECLARE(sun5i_a13_mbus, "allwinner,sun5i-a13-mbus-clk", sun5i_a13_mbus_setup);
>
> +/**
> + * sun8i_a23_get_mbus_factors() - calculates m factor for MBUS clocks
> + * MBUS rate is calculated as follows
> + * rate = parent_rate / (m + 1);
> + */
> +
> +static void sun8i_a23_get_mbus_factors(u32 *freq, u32 parent_rate,
> + u8 *n, u8 *k, u8 *m, u8 *p)
> +{
> + u8 div;
> +
> + /* These clocks can only divide, so we will never be able to achieve
> + * frequencies higher than the parent frequency */
This doesn't follow the multi-line comment style.
> + if (*freq > parent_rate)
> + *freq = parent_rate;
> +
> + div = DIV_ROUND_UP(parent_rate, *freq);
> +
> + if (div > 8)
> + div = 8;
> +
> + *freq = parent_rate / div;
> +
> + /* we were called to round the frequency, we can now return */
> + if (m == NULL)
> + return;
> +
> + *m = div - 1;
> +}
> +
> +static struct clk_factors_config sun8i_a23_mbus_config = {
> + .mshift = 0,
> + .mwidth = 3,
> +};
> +
> +static const struct factors_data sun8i_a23_mbus_data __initconst = {
> + .enable = 31,
> + .mux = 24,
> + .table = &sun8i_a23_mbus_config,
> + .getter = sun8i_a23_get_mbus_factors,
> +};
> +
> +static DEFINE_SPINLOCK(sun8i_a23_mbus_lock);
> +
> +static void __init sun8i_a23_mbus_setup(struct device_node *node)
> +{
> + struct clk *mbus = sunxi_factors_register(node, &sun8i_a23_mbus_data,
> + &sun8i_a23_mbus_lock);
> +
> + /* The MBUS clocks needs to be always enabled */
> + __clk_get(mbus);
> + clk_prepare_enable(mbus);
> +}
> +CLK_OF_DECLARE(sun8i_a23_mbus, "allwinner,sun8i-a23-mbus-clk", sun8i_a23_mbus_setup);
> +
It looks like it's pretty much stand alone. Would you mind putting it
into a file of its own? something like clk-sun8i-mbus.c?
Thanks,
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH 1/2] clk: sunxi: Add sun8i MBUS clock support
2014-09-15 8:20 ` Maxime Ripard
@ 2014-09-15 8:29 ` Chen-Yu Tsai
0 siblings, 0 replies; 5+ messages in thread
From: Chen-Yu Tsai @ 2014-09-15 8:29 UTC (permalink / raw)
To: linux-arm-kernel
On Mon, Sep 15, 2014 at 4:20 PM, Maxime Ripard
<maxime.ripard@free-electrons.com> wrote:
> Hi Chen-Yu,
>
> On Sat, Sep 13, 2014 at 12:48:05AM +0800, Chen-Yu Tsai wrote:
>> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
>
> A commit log would be nice here. Is it different from A31? do you know
> wether later SoCs reuses it?
I will copy the description from the cover letter.
>> ---
>> Documentation/devicetree/bindings/clock/sunxi.txt | 1 +
>> drivers/clk/sunxi/clk-mod0.c | 55 +++++++++++++++++++++++
>> 2 files changed, 56 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt
>> index 425b109..fb3b7aa 100644
>> --- a/Documentation/devicetree/bindings/clock/sunxi.txt
>> +++ b/Documentation/devicetree/bindings/clock/sunxi.txt
>> @@ -50,6 +50,7 @@ Required properties:
>> "allwinner,sun4i-a10-mmc-output-clk" - for the MMC output clock on A10
>> "allwinner,sun4i-a10-mmc-sample-clk" - for the MMC sample clock on A10
>> "allwinner,sun4i-a10-mod0-clk" - for the module 0 family of clocks
>> + "allwinner,sun8i-a23-mbus-clk" - for the MBUS clock on A23
>> "allwinner,sun7i-a20-out-clk" - for the external output clocks
>> "allwinner,sun7i-a20-gmac-clk" - for the GMAC clock module on A20/A31
>> "allwinner,sun4i-a10-usb-clk" - for usb gates + resets on A10 / A20
>> diff --git a/drivers/clk/sunxi/clk-mod0.c b/drivers/clk/sunxi/clk-mod0.c
>> index 4a56385..9850887 100644
>> --- a/drivers/clk/sunxi/clk-mod0.c
>> +++ b/drivers/clk/sunxi/clk-mod0.c
>> @@ -94,6 +94,61 @@ static void __init sun5i_a13_mbus_setup(struct device_node *node)
>> }
>> CLK_OF_DECLARE(sun5i_a13_mbus, "allwinner,sun5i-a13-mbus-clk", sun5i_a13_mbus_setup);
>>
>> +/**
>> + * sun8i_a23_get_mbus_factors() - calculates m factor for MBUS clocks
>> + * MBUS rate is calculated as follows
>> + * rate = parent_rate / (m + 1);
>> + */
>> +
>> +static void sun8i_a23_get_mbus_factors(u32 *freq, u32 parent_rate,
>> + u8 *n, u8 *k, u8 *m, u8 *p)
>> +{
>> + u8 div;
>> +
>> + /* These clocks can only divide, so we will never be able to achieve
>> + * frequencies higher than the parent frequency */
>
> This doesn't follow the multi-line comment style.
Will fix. This was copied from clk-sunxi.c though, meaning a few of them
might be lying around.
>> + if (*freq > parent_rate)
>> + *freq = parent_rate;
>> +
>> + div = DIV_ROUND_UP(parent_rate, *freq);
>> +
>> + if (div > 8)
>> + div = 8;
>> +
>> + *freq = parent_rate / div;
>> +
>> + /* we were called to round the frequency, we can now return */
>> + if (m == NULL)
>> + return;
>> +
>> + *m = div - 1;
>> +}
>> +
>> +static struct clk_factors_config sun8i_a23_mbus_config = {
>> + .mshift = 0,
>> + .mwidth = 3,
>> +};
>> +
>> +static const struct factors_data sun8i_a23_mbus_data __initconst = {
>> + .enable = 31,
>> + .mux = 24,
>> + .table = &sun8i_a23_mbus_config,
>> + .getter = sun8i_a23_get_mbus_factors,
>> +};
>> +
>> +static DEFINE_SPINLOCK(sun8i_a23_mbus_lock);
>> +
>> +static void __init sun8i_a23_mbus_setup(struct device_node *node)
>> +{
>> + struct clk *mbus = sunxi_factors_register(node, &sun8i_a23_mbus_data,
>> + &sun8i_a23_mbus_lock);
>> +
>> + /* The MBUS clocks needs to be always enabled */
>> + __clk_get(mbus);
>> + clk_prepare_enable(mbus);
>> +}
>> +CLK_OF_DECLARE(sun8i_a23_mbus, "allwinner,sun8i-a23-mbus-clk", sun8i_a23_mbus_setup);
>> +
>
> It looks like it's pretty much stand alone. Would you mind putting it
> into a file of its own? something like clk-sun8i-mbus.c?
No problem. Just thought it would fit nicely with the sun4i version.
Thanks
ChenYu
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2014-09-15 8:29 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
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2014-09-12 16:48 [PATCH 0/2] clk: sun8i: Add MBUS support Chen-Yu Tsai
2014-09-12 16:48 ` [PATCH 1/2] clk: sunxi: Add sun8i MBUS clock support Chen-Yu Tsai
2014-09-15 8:20 ` Maxime Ripard
2014-09-15 8:29 ` Chen-Yu Tsai
2014-09-12 16:48 ` [PATCH 2/2] ARM: dts: sun8i: Add PLL6 and MBUS clock nodes Chen-Yu Tsai
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