[PATCH v2 1/6] cpufreq: dt: disable unsupported OPPs

[PATCH v2 1/6] cpufreq: dt: disable unsupported OPPs

[Lucas Stach]

If the regulator connected to the CPU voltage plane doesn't
support an OPP specified voltage with the acceptable tolerance
it's better to just disable the OPP instead of constantly
failing the voltage scaling later on.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
---
v2:
- rebase on top of pm/linux-next
---
 drivers/cpufreq/cpufreq-dt.c | 66 +++++++++++++++++++++++++++-----------------
 1 file changed, 40 insertions(+), 26 deletions(-)

diff --git a/drivers/cpufreq/cpufreq-dt.c b/drivers/cpufreq/cpufreq-dt.c
index 6bbb8b913446..4485c8eccdc2 100644
--- a/drivers/cpufreq/cpufreq-dt.c
+++ b/drivers/cpufreq/cpufreq-dt.c
@@ -185,6 +185,7 @@ static int cpufreq_init(struct cpufreq_policy *policy)
 	struct device *cpu_dev;
 	struct regulator *cpu_reg;
 	struct clk *cpu_clk;
+	unsigned long min_uV = ~0, max_uV = 0;
 	unsigned int transition_latency;
 	int ret;
 
@@ -204,16 +205,10 @@ static int cpufreq_init(struct cpufreq_policy *policy)
 	/* OPPs might be populated at runtime, don't check for error here */
 	of_init_opp_table(cpu_dev);
 
-	ret = dev_pm_opp_init_cpufreq_table(cpu_dev, &freq_table);
-	if (ret) {
-		dev_err(cpu_dev, "failed to init cpufreq table: %d\n", ret);
-		goto out_put_node;
-	}
-
 	priv = kzalloc(sizeof(*priv), GFP_KERNEL);
 	if (!priv) {
 		ret = -ENOMEM;
-		goto out_free_table;
+		goto out_put_node;
 	}
 
 	of_property_read_u32(np, "voltage-tolerance", &priv->voltage_tolerance);
@@ -222,30 +217,49 @@ static int cpufreq_init(struct cpufreq_policy *policy)
 		transition_latency = CPUFREQ_ETERNAL;
 
 	if (!IS_ERR(cpu_reg)) {
-		struct dev_pm_opp *opp;
-		unsigned long min_uV, max_uV;
-		int i;
-
 		/*
-		 * OPP is maintained in order of increasing frequency, and
-		 * freq_table initialised from OPP is therefore sorted in the
-		 * same order.
+		 * Disable any OPPs where the connected regulator isn't able to
+		 * provide the specified voltage and record minimum and maximum
+		 * voltage levels.
 		 */
-		for (i = 0; freq_table[i].frequency != CPUFREQ_TABLE_END; i++)
-			;
-		rcu_read_lock();
-		opp = dev_pm_opp_find_freq_exact(cpu_dev,
-				freq_table[0].frequency * 1000, true);
-		min_uV = dev_pm_opp_get_voltage(opp);
-		opp = dev_pm_opp_find_freq_exact(cpu_dev,
-				freq_table[i-1].frequency * 1000, true);
-		max_uV = dev_pm_opp_get_voltage(opp);
-		rcu_read_unlock();
+		while (1) {
+			struct dev_pm_opp *opp;
+			unsigned long opp_freq = 0, opp_uV, tol_uV;
+
+			rcu_read_lock();
+			opp = dev_pm_opp_find_freq_ceil(cpu_dev, &opp_freq);
+			if (IS_ERR(opp)) {
+				rcu_read_unlock();
+				break;
+			}
+			opp_uV = dev_pm_opp_get_voltage(opp);
+			rcu_read_unlock();
+
+			tol_uV = opp_uV * priv->voltage_tolerance / 100;
+			if (regulator_is_supported_voltage(cpu_reg, opp_uV,
+							   opp_uV + tol_uV)) {
+				if (opp_uV < min_uV)
+					min_uV = opp_uV;
+				if (opp_uV > max_uV)
+					max_uV = opp_uV;
+			} else {
+				dev_pm_opp_disable(cpu_dev, opp_freq);
+			}
+
+			opp_freq++;
+		}
+
 		ret = regulator_set_voltage_time(cpu_reg, min_uV, max_uV);
 		if (ret > 0)
 			transition_latency += ret * 1000;
 	}
 
+	ret = dev_pm_opp_init_cpufreq_table(cpu_dev, &freq_table);
+	if (ret) {
+		pr_err("failed to init cpufreq table: %d\n", ret);
+		goto out_free_priv;
+	}
+
 	/*
 	 * For now, just loading the cooling device;
 	 * thermal DT code takes care of matching them.
@@ -275,9 +289,9 @@ static int cpufreq_init(struct cpufreq_policy *policy)
 
 out_cooling_unregister:
 	cpufreq_cooling_unregister(priv->cdev);
-	kfree(priv);
-out_free_table:
 	dev_pm_opp_free_cpufreq_table(cpu_dev, &freq_table);
+out_free_priv:
+	kfree(priv);
 out_put_node:
 	of_node_put(np);
 out_put_reg_clk:
-- 
2.1.0

[PATCH v2 2/6] clk: imx5: add step clock, used when reprogramming PLL1

[Lucas Stach]

This is the bypass clock used to feed the ARM partition
while we reprogram PLL1 to another rate.

Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
---
 arch/arm/mach-imx/clk-imx51-imx53.c    | 9 ++++++++-
 include/dt-bindings/clock/imx5-clock.h | 4 +++-
 2 files changed, 11 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-imx/clk-imx51-imx53.c b/arch/arm/mach-imx/clk-imx51-imx53.c
index 72d65214223e..aafccf4b47c2 100644
--- a/arch/arm/mach-imx/clk-imx51-imx53.c
+++ b/arch/arm/mach-imx/clk-imx51-imx53.c
@@ -125,6 +125,8 @@ static const char *mx53_spdif_xtal_sel[] = { "osc", "ckih", "ckih2", "pll4_sw",
 static const char *spdif_sel[] = { "pll1_sw", "pll2_sw", "pll3_sw", "spdif_xtal_sel", };
 static const char *spdif0_com_sel[] = { "spdif0_podf", "ssi1_root_gate", };
 static const char *mx51_spdif1_com_sel[] = { "spdif1_podf", "ssi2_root_gate", };
+static const char *step_sels[] = { "lp_apm", };
+static const char *cpu_podf_sels[] = { "pll1_sw", "step_sel" };
 
 static struct clk *clk[IMX5_CLK_END];
 static struct clk_onecell_data clk_data;
@@ -193,7 +195,9 @@ static void __init mx5_clocks_common_init(void __iomem *ccm_base)
 	clk[IMX5_CLK_USB_PHY_PODF]	= imx_clk_divider("usb_phy_podf", "usb_phy_pred", MXC_CCM_CDCDR, 0, 3);
 	clk[IMX5_CLK_USB_PHY_SEL]	= imx_clk_mux("usb_phy_sel", MXC_CCM_CSCMR1, 26, 1,
 						usb_phy_sel_str, ARRAY_SIZE(usb_phy_sel_str));
-	clk[IMX5_CLK_CPU_PODF]		= imx_clk_divider("cpu_podf", "pll1_sw", MXC_CCM_CACRR, 0, 3);
+	clk[IMX5_CLK_STEP_SEL]		= imx_clk_mux("step_sel", MXC_CCM_CCSR, 7, 2, step_sels, ARRAY_SIZE(step_sels));
+	clk[IMX5_CLK_CPU_PODF_SEL]	= imx_clk_mux("cpu_podf_sel", MXC_CCM_CCSR, 2, 1, cpu_podf_sels, ARRAY_SIZE(cpu_podf_sels));
+	clk[IMX5_CLK_CPU_PODF]		= imx_clk_divider("cpu_podf", "cpu_podf_sel", MXC_CCM_CACRR, 0, 3);
 	clk[IMX5_CLK_DI_PRED]		= imx_clk_divider("di_pred", "pll3_sw", MXC_CCM_CDCDR, 6, 3);
 	clk[IMX5_CLK_IIM_GATE]		= imx_clk_gate2("iim_gate", "ipg", MXC_CCM_CCGR0, 30);
 	clk[IMX5_CLK_UART1_IPG_GATE]	= imx_clk_gate2("uart1_ipg_gate", "ipg", MXC_CCM_CCGR1, 6);
@@ -551,6 +555,9 @@ static void __init mx53_clocks_init(struct device_node *np)
 	/* move can bus clk to 24MHz */
 	clk_set_parent(clk[IMX5_CLK_CAN_SEL], clk[IMX5_CLK_LP_APM]);
 
+	/* make sure step clock is running from 24MHz */
+	clk_set_parent(clk[IMX5_CLK_STEP_SEL], clk[IMX5_CLK_LP_APM]);
+
 	clk_prepare_enable(clk[IMX5_CLK_IIM_GATE]);
 	imx_print_silicon_rev("i.MX53", mx53_revision());
 	clk_disable_unprepare(clk[IMX5_CLK_IIM_GATE]);
diff --git a/include/dt-bindings/clock/imx5-clock.h b/include/dt-bindings/clock/imx5-clock.h
index 5f2667ecd98e..1a36ff4ace1e 100644
--- a/include/dt-bindings/clock/imx5-clock.h
+++ b/include/dt-bindings/clock/imx5-clock.h
@@ -198,6 +198,8 @@
 #define IMX5_CLK_OCRAM			186
 #define IMX5_CLK_SAHARA_IPG_GATE	187
 #define IMX5_CLK_SATA_REF		188
-#define IMX5_CLK_END			189
+#define IMX5_CLK_STEP_SEL		189
+#define IMX5_CLK_CPU_PODF_SEL		190
+#define IMX5_CLK_END			191
 
 #endif /* __DT_BINDINGS_CLOCK_IMX5_H */
-- 
2.1.0

[PATCH v2 3/6] clk: imx: add CPU clock type

[Lucas Stach]

This implements a virtual clock used to abstract away
all the steps needed in order to change the ARM clock,
so we don't have to push all this clock handling into
the cpufreq driver.

While it will be used for i.MX53 at first it is generic
enough to be used on i.MX6 later on.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
---
v2:
- split clk into multiple line
- fix my email address
---
 arch/arm/mach-imx/Makefile  |   2 +-
 arch/arm/mach-imx/clk-cpu.c | 107 ++++++++++++++++++++++++++++++++++++++++++++
 arch/arm/mach-imx/clk.h     |   4 ++
 3 files changed, 112 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/mach-imx/clk-cpu.c

diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index 23c02932bf84..0e708a9d607d 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -12,7 +12,7 @@ obj-$(CONFIG_SOC_IMX31) += mm-imx3.o cpu-imx31.o clk-imx31.o iomux-imx31.o ehci-
 obj-$(CONFIG_SOC_IMX35) += mm-imx3.o cpu-imx35.o clk-imx35.o ehci-imx35.o pm-imx3.o
 
 imx5-pm-$(CONFIG_PM) += pm-imx5.o
-obj-$(CONFIG_SOC_IMX5) += cpu-imx5.o clk-imx51-imx53.o $(imx5-pm-y)
+obj-$(CONFIG_SOC_IMX5) += cpu-imx5.o clk-imx51-imx53.o clk-cpu.o $(imx5-pm-y)
 
 obj-$(CONFIG_COMMON_CLK) += clk-pllv1.o clk-pllv2.o clk-pllv3.o clk-gate2.o \
 			    clk-pfd.o clk-busy.o clk.o \
diff --git a/arch/arm/mach-imx/clk-cpu.c b/arch/arm/mach-imx/clk-cpu.c
new file mode 100644
index 000000000000..aa1c345e2a19
--- /dev/null
+++ b/arch/arm/mach-imx/clk-cpu.c
@@ -0,0 +1,107 @@
+/*
+ * Copyright (c) 2014 Lucas Stach <l.stach@pengutronix.de>, Pengutronix
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/slab.h>
+
+struct clk_cpu {
+	struct clk_hw	hw;
+	struct clk	*div;
+	struct clk	*mux;
+	struct clk	*pll;
+	struct clk	*step;
+};
+
+static inline struct clk_cpu *to_clk_cpu(struct clk_hw *hw)
+{
+	return container_of(hw, struct clk_cpu, hw);
+}
+
+static unsigned long clk_cpu_recalc_rate(struct clk_hw *hw,
+					 unsigned long parent_rate)
+{
+	struct clk_cpu *cpu = to_clk_cpu(hw);
+
+	return clk_get_rate(cpu->div);
+}
+
+static long clk_cpu_round_rate(struct clk_hw *hw, unsigned long rate,
+			       unsigned long *prate)
+{
+	struct clk_cpu *cpu = to_clk_cpu(hw);
+
+	return clk_round_rate(cpu->pll, rate);
+}
+
+static int clk_cpu_set_rate(struct clk_hw *hw, unsigned long rate,
+			    unsigned long parent_rate)
+{
+	struct clk_cpu *cpu = to_clk_cpu(hw);
+	int ret;
+
+	/* switch to PLL bypass clock */
+	ret = clk_set_parent(cpu->mux, cpu->step);
+	if (ret)
+		return ret;
+
+	/* reprogram PLL */
+	ret = clk_set_rate(cpu->pll, rate);
+	if (ret) {
+		clk_set_parent(cpu->mux, cpu->pll);
+		return ret;
+	}
+	/* switch back to PLL clock */
+	clk_set_parent(cpu->mux, cpu->pll);
+
+	/* Ensure the divider is what we expect */
+	clk_set_rate(cpu->div, rate);
+
+	return 0;
+}
+
+static const struct clk_ops clk_cpu_ops = {
+	.recalc_rate	= clk_cpu_recalc_rate,
+	.round_rate	= clk_cpu_round_rate,
+	.set_rate	= clk_cpu_set_rate,
+};
+
+struct clk *imx_clk_cpu(const char *name, const char *parent_name,
+		struct clk *div, struct clk *mux, struct clk *pll,
+		struct clk *step)
+{
+	struct clk_cpu *cpu;
+	struct clk *clk;
+	struct clk_init_data init;
+
+	cpu = kzalloc(sizeof(*cpu), GFP_KERNEL);
+	if (!cpu)
+		return ERR_PTR(-ENOMEM);
+
+	cpu->div = div;
+	cpu->mux = mux;
+	cpu->pll = pll;
+	cpu->step = step;
+
+	init.name = name;
+	init.ops = &clk_cpu_ops;
+	init.flags = 0;
+	init.parent_names = &parent_name;
+	init.num_parents = 1;
+
+	cpu->hw.init = &init;
+
+	clk = clk_register(NULL, &cpu->hw);
+	if (IS_ERR(clk))
+		kfree(cpu);
+
+	return clk;
+}
diff --git a/arch/arm/mach-imx/clk.h b/arch/arm/mach-imx/clk.h
index d5ba76fee115..5de8b53ec208 100644
--- a/arch/arm/mach-imx/clk.h
+++ b/arch/arm/mach-imx/clk.h
@@ -128,4 +128,8 @@ static inline struct clk *imx_clk_fixed_factor(const char *name,
 			CLK_SET_RATE_PARENT, mult, div);
 }
 
+struct clk *imx_clk_cpu(const char *name, const char *parent_name,
+		struct clk *div, struct clk *mux, struct clk *pll,
+		struct clk *step);
+
 #endif
-- 
2.1.0

[PATCH v2 4/6] arm: imx53: clk: add ARM clock

[Lucas Stach]

The ARM clock is a virtual clock feeding the ARM partition of
the SoC. It controls multiple other clocks to ensure the right
sequencing when cpufreq changes the CPU clock rate.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
---
 arch/arm/mach-imx/clk-imx51-imx53.c    | 5 +++++
 include/dt-bindings/clock/imx5-clock.h | 3 ++-
 2 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-imx/clk-imx51-imx53.c b/arch/arm/mach-imx/clk-imx51-imx53.c
index aafccf4b47c2..0f7e536147cb 100644
--- a/arch/arm/mach-imx/clk-imx51-imx53.c
+++ b/arch/arm/mach-imx/clk-imx51-imx53.c
@@ -541,6 +541,11 @@ static void __init mx53_clocks_init(struct device_node *np)
 	clk[IMX5_CLK_CKO2]		= imx_clk_gate2("cko2", "cko2_podf", MXC_CCM_CCOSR, 24);
 	clk[IMX5_CLK_SPDIF_XTAL_SEL]	= imx_clk_mux("spdif_xtal_sel", MXC_CCM_CSCMR1, 2, 2,
 						mx53_spdif_xtal_sel, ARRAY_SIZE(mx53_spdif_xtal_sel));
+	clk[IMX5_CLK_ARM]		= imx_clk_cpu("arm", "cpu_podf",
+						clk[IMX5_CLK_CPU_PODF],
+						clk[IMX5_CLK_CPU_PODF_SEL],
+						clk[IMX5_CLK_PLL1_SW],
+						clk[IMX5_CLK_STEP_SEL]);
 
 	imx_check_clocks(clk, ARRAY_SIZE(clk));
 
diff --git a/include/dt-bindings/clock/imx5-clock.h b/include/dt-bindings/clock/imx5-clock.h
index 1a36ff4ace1e..f4b7478e23c8 100644
--- a/include/dt-bindings/clock/imx5-clock.h
+++ b/include/dt-bindings/clock/imx5-clock.h
@@ -200,6 +200,7 @@
 #define IMX5_CLK_SATA_REF		188
 #define IMX5_CLK_STEP_SEL		189
 #define IMX5_CLK_CPU_PODF_SEL		190
-#define IMX5_CLK_END			191
+#define IMX5_CLK_ARM			191
+#define IMX5_CLK_END			192
 
 #endif /* __DT_BINDINGS_CLOCK_IMX5_H */
-- 
2.1.0

[PATCH v2 5/6] ARM: dts: imx53: add cpufreq-dt support

[Lucas Stach]

Add all required properties for the cpufreq-dt driver.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
---
v2:
- split out device instantiation
---
 arch/arm/boot/dts/imx53.dtsi | 13 ++++++++++++-
 1 file changed, 12 insertions(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi
index c6c58c1c00e3..aa2fb2f3616d 100644
--- a/arch/arm/boot/dts/imx53.dtsi
+++ b/arch/arm/boot/dts/imx53.dtsi
@@ -46,10 +46,21 @@
 	cpus {
 		#address-cells = <1>;
 		#size-cells = <0>;
-		cpu at 0 {
+		cpu0: cpu at 0 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a8";
 			reg = <0x0>;
+			clocks = <&clks IMX5_CLK_ARM>;
+			clock-latency = <61036>;
+			voltage-tolerance = <5>;
+			operating-points = <
+				/* kHz */
+				 166666  850000
+				 400000  900000
+				 800000 1050000
+				1000000 1200000
+				1200000 1300000
+			>;
 		};
 	};
 
-- 
2.1.0

[PATCH v2 6/6] ARM: imx53: add cpufreq support

[Lucas Stach]

Instanciate device for the generic cpufreq-dt driver.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
---
v2:
- new patch, split out from DTS changes and rebased
  with new name for cpufreq driver
---
 arch/arm/mach-imx/mach-imx53.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/mach-imx/mach-imx53.c b/arch/arm/mach-imx/mach-imx53.c
index 03dd6ea13acc..7587cf0cba3e 100644
--- a/arch/arm/mach-imx/mach-imx53.c
+++ b/arch/arm/mach-imx/mach-imx53.c
@@ -41,6 +41,8 @@ static void __init imx53_dt_init(void)
 static void __init imx53_init_late(void)
 {
 	imx53_pm_init();
+
+	platform_device_register_simple("cpufreq-dt", -1, NULL, 0);
 }
 
 static const char * const imx53_dt_board_compat[] __initconst = {
-- 
2.1.0

[PATCH v2 1/6] cpufreq: dt: disable unsupported OPPs

[Rafael J. Wysocki]

On Friday, September 26, 2014 03:40:59 PM Lucas Stach wrote:
> If the regulator connected to the CPU voltage plane doesn't
> support an OPP specified voltage with the acceptable tolerance
> it's better to just disable the OPP instead of constantly
> failing the voltage scaling later on.
> 
> Signed-off-by: Lucas Stach <l.stach@pengutronix.de>

Why do you need this to be part of the whole series?  Is there any
hard dependency on it?

> ---
> v2:
> - rebase on top of pm/linux-next
> ---
>  drivers/cpufreq/cpufreq-dt.c | 66 +++++++++++++++++++++++++++-----------------
>  1 file changed, 40 insertions(+), 26 deletions(-)
> 
> diff --git a/drivers/cpufreq/cpufreq-dt.c b/drivers/cpufreq/cpufreq-dt.c
> index 6bbb8b913446..4485c8eccdc2 100644
> --- a/drivers/cpufreq/cpufreq-dt.c
> +++ b/drivers/cpufreq/cpufreq-dt.c
> @@ -185,6 +185,7 @@ static int cpufreq_init(struct cpufreq_policy *policy)
>  	struct device *cpu_dev;
>  	struct regulator *cpu_reg;
>  	struct clk *cpu_clk;
> +	unsigned long min_uV = ~0, max_uV = 0;
>  	unsigned int transition_latency;
>  	int ret;
>  
> @@ -204,16 +205,10 @@ static int cpufreq_init(struct cpufreq_policy *policy)
>  	/* OPPs might be populated at runtime, don't check for error here */
>  	of_init_opp_table(cpu_dev);
>  
> -	ret = dev_pm_opp_init_cpufreq_table(cpu_dev, &freq_table);
> -	if (ret) {
> -		dev_err(cpu_dev, "failed to init cpufreq table: %d\n", ret);
> -		goto out_put_node;
> -	}
> -
>  	priv = kzalloc(sizeof(*priv), GFP_KERNEL);
>  	if (!priv) {
>  		ret = -ENOMEM;
> -		goto out_free_table;
> +		goto out_put_node;
>  	}
>  
>  	of_property_read_u32(np, "voltage-tolerance", &priv->voltage_tolerance);
> @@ -222,30 +217,49 @@ static int cpufreq_init(struct cpufreq_policy *policy)
>  		transition_latency = CPUFREQ_ETERNAL;
>  
>  	if (!IS_ERR(cpu_reg)) {
> -		struct dev_pm_opp *opp;
> -		unsigned long min_uV, max_uV;
> -		int i;
> -
>  		/*
> -		 * OPP is maintained in order of increasing frequency, and
> -		 * freq_table initialised from OPP is therefore sorted in the
> -		 * same order.
> +		 * Disable any OPPs where the connected regulator isn't able to
> +		 * provide the specified voltage and record minimum and maximum
> +		 * voltage levels.
>  		 */
> -		for (i = 0; freq_table[i].frequency != CPUFREQ_TABLE_END; i++)
> -			;
> -		rcu_read_lock();
> -		opp = dev_pm_opp_find_freq_exact(cpu_dev,
> -				freq_table[0].frequency * 1000, true);
> -		min_uV = dev_pm_opp_get_voltage(opp);
> -		opp = dev_pm_opp_find_freq_exact(cpu_dev,
> -				freq_table[i-1].frequency * 1000, true);
> -		max_uV = dev_pm_opp_get_voltage(opp);
> -		rcu_read_unlock();
> +		while (1) {
> +			struct dev_pm_opp *opp;
> +			unsigned long opp_freq = 0, opp_uV, tol_uV;
> +
> +			rcu_read_lock();
> +			opp = dev_pm_opp_find_freq_ceil(cpu_dev, &opp_freq);
> +			if (IS_ERR(opp)) {
> +				rcu_read_unlock();
> +				break;
> +			}
> +			opp_uV = dev_pm_opp_get_voltage(opp);
> +			rcu_read_unlock();
> +
> +			tol_uV = opp_uV * priv->voltage_tolerance / 100;
> +			if (regulator_is_supported_voltage(cpu_reg, opp_uV,
> +							   opp_uV + tol_uV)) {
> +				if (opp_uV < min_uV)
> +					min_uV = opp_uV;
> +				if (opp_uV > max_uV)
> +					max_uV = opp_uV;
> +			} else {
> +				dev_pm_opp_disable(cpu_dev, opp_freq);
> +			}
> +
> +			opp_freq++;
> +		}
> +
>  		ret = regulator_set_voltage_time(cpu_reg, min_uV, max_uV);
>  		if (ret > 0)
>  			transition_latency += ret * 1000;
>  	}
>  
> +	ret = dev_pm_opp_init_cpufreq_table(cpu_dev, &freq_table);
> +	if (ret) {
> +		pr_err("failed to init cpufreq table: %d\n", ret);
> +		goto out_free_priv;
> +	}
> +
>  	/*
>  	 * For now, just loading the cooling device;
>  	 * thermal DT code takes care of matching them.
> @@ -275,9 +289,9 @@ static int cpufreq_init(struct cpufreq_policy *policy)
>  
>  out_cooling_unregister:
>  	cpufreq_cooling_unregister(priv->cdev);
> -	kfree(priv);
> -out_free_table:
>  	dev_pm_opp_free_cpufreq_table(cpu_dev, &freq_table);
> +out_free_priv:
> +	kfree(priv);
>  out_put_node:
>  	of_node_put(np);
>  out_put_reg_clk:
> 

-- 
I speak only for myself.
Rafael J. Wysocki, Intel Open Source Technology Center.

[PATCH v2 2/6] clk: imx5: add step clock, used when reprogramming PLL1

[Shawn Guo]

On Fri, Sep 26, 2014 at 03:41:00PM +0200, Lucas Stach wrote:
> This is the bypass clock used to feed the ARM partition
> while we reprogram PLL1 to another rate.
> 
> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
> Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
> ---
>  arch/arm/mach-imx/clk-imx51-imx53.c    | 9 ++++++++-

This is a patch touching arch/arm/ file, so should be prefixed with "ARM".
I fixed those prefix up and applied patch 2-5.

Shawn

>  include/dt-bindings/clock/imx5-clock.h | 4 +++-
>  2 files changed, 11 insertions(+), 2 deletions(-)

[PATCH v2 6/6] ARM: imx53: add cpufreq support

[Shawn Guo]

On Fri, Sep 26, 2014 at 03:41:04PM +0200, Lucas Stach wrote:
> Instanciate device for the generic cpufreq-dt driver.
> 
> Signed-off-by: Lucas Stach <l.stach@pengutronix.de>

I assume that I should only apply this patch after the cpufreq-dt change
gets merged and shows up on my base.

Shawn

> ---
> v2:
> - new patch, split out from DTS changes and rebased
>   with new name for cpufreq driver
> ---
>  arch/arm/mach-imx/mach-imx53.c | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/arch/arm/mach-imx/mach-imx53.c b/arch/arm/mach-imx/mach-imx53.c
> index 03dd6ea13acc..7587cf0cba3e 100644
> --- a/arch/arm/mach-imx/mach-imx53.c
> +++ b/arch/arm/mach-imx/mach-imx53.c
> @@ -41,6 +41,8 @@ static void __init imx53_dt_init(void)
>  static void __init imx53_init_late(void)
>  {
>  	imx53_pm_init();
> +
> +	platform_device_register_simple("cpufreq-dt", -1, NULL, 0);
>  }
>  
>  static const char * const imx53_dt_board_compat[] __initconst = {
> -- 
> 2.1.0
> 

[PATCH v2 1/6] cpufreq: dt: disable unsupported OPPs

[Lucas Stach]

Am Freitag, den 26.09.2014, 23:55 +0200 schrieb Rafael J. Wysocki:
> On Friday, September 26, 2014 03:40:59 PM Lucas Stach wrote:
> > If the regulator connected to the CPU voltage plane doesn't
> > support an OPP specified voltage with the acceptable tolerance
> > it's better to just disable the OPP instead of constantly
> > failing the voltage scaling later on.
> > 
> > Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
> 
> Why do you need this to be part of the whole series?  Is there any
> hard dependency on it?
> 
No there isn't any hard dependency. It's just that one of the boards I
was testing this series with needs this to properly disable one invalid
OPP.

So it's no problem to rip this one out of the series. Sorry for the
confusion.

> > ---
> > v2:
> > - rebase on top of pm/linux-next
> > ---
> >  drivers/cpufreq/cpufreq-dt.c | 66 +++++++++++++++++++++++++++-----------------
> >  1 file changed, 40 insertions(+), 26 deletions(-)
> > 
> > diff --git a/drivers/cpufreq/cpufreq-dt.c b/drivers/cpufreq/cpufreq-dt.c
> > index 6bbb8b913446..4485c8eccdc2 100644
> > --- a/drivers/cpufreq/cpufreq-dt.c
> > +++ b/drivers/cpufreq/cpufreq-dt.c
> > @@ -185,6 +185,7 @@ static int cpufreq_init(struct cpufreq_policy *policy)
> >  	struct device *cpu_dev;
> >  	struct regulator *cpu_reg;
> >  	struct clk *cpu_clk;
> > +	unsigned long min_uV = ~0, max_uV = 0;
> >  	unsigned int transition_latency;
> >  	int ret;
> >  
> > @@ -204,16 +205,10 @@ static int cpufreq_init(struct cpufreq_policy *policy)
> >  	/* OPPs might be populated at runtime, don't check for error here */
> >  	of_init_opp_table(cpu_dev);
> >  
> > -	ret = dev_pm_opp_init_cpufreq_table(cpu_dev, &freq_table);
> > -	if (ret) {
> > -		dev_err(cpu_dev, "failed to init cpufreq table: %d\n", ret);
> > -		goto out_put_node;
> > -	}
> > -
> >  	priv = kzalloc(sizeof(*priv), GFP_KERNEL);
> >  	if (!priv) {
> >  		ret = -ENOMEM;
> > -		goto out_free_table;
> > +		goto out_put_node;
> >  	}
> >  
> >  	of_property_read_u32(np, "voltage-tolerance", &priv->voltage_tolerance);
> > @@ -222,30 +217,49 @@ static int cpufreq_init(struct cpufreq_policy *policy)
> >  		transition_latency = CPUFREQ_ETERNAL;
> >  
> >  	if (!IS_ERR(cpu_reg)) {
> > -		struct dev_pm_opp *opp;
> > -		unsigned long min_uV, max_uV;
> > -		int i;
> > -
> >  		/*
> > -		 * OPP is maintained in order of increasing frequency, and
> > -		 * freq_table initialised from OPP is therefore sorted in the
> > -		 * same order.
> > +		 * Disable any OPPs where the connected regulator isn't able to
> > +		 * provide the specified voltage and record minimum and maximum
> > +		 * voltage levels.
> >  		 */
> > -		for (i = 0; freq_table[i].frequency != CPUFREQ_TABLE_END; i++)
> > -			;
> > -		rcu_read_lock();
> > -		opp = dev_pm_opp_find_freq_exact(cpu_dev,
> > -				freq_table[0].frequency * 1000, true);
> > -		min_uV = dev_pm_opp_get_voltage(opp);
> > -		opp = dev_pm_opp_find_freq_exact(cpu_dev,
> > -				freq_table[i-1].frequency * 1000, true);
> > -		max_uV = dev_pm_opp_get_voltage(opp);
> > -		rcu_read_unlock();
> > +		while (1) {
> > +			struct dev_pm_opp *opp;
> > +			unsigned long opp_freq = 0, opp_uV, tol_uV;
> > +
> > +			rcu_read_lock();
> > +			opp = dev_pm_opp_find_freq_ceil(cpu_dev, &opp_freq);
> > +			if (IS_ERR(opp)) {
> > +				rcu_read_unlock();
> > +				break;
> > +			}
> > +			opp_uV = dev_pm_opp_get_voltage(opp);
> > +			rcu_read_unlock();
> > +
> > +			tol_uV = opp_uV * priv->voltage_tolerance / 100;
> > +			if (regulator_is_supported_voltage(cpu_reg, opp_uV,
> > +							   opp_uV + tol_uV)) {
> > +				if (opp_uV < min_uV)
> > +					min_uV = opp_uV;
> > +				if (opp_uV > max_uV)
> > +					max_uV = opp_uV;
> > +			} else {
> > +				dev_pm_opp_disable(cpu_dev, opp_freq);
> > +			}
> > +
> > +			opp_freq++;
> > +		}
> > +
> >  		ret = regulator_set_voltage_time(cpu_reg, min_uV, max_uV);
> >  		if (ret > 0)
> >  			transition_latency += ret * 1000;
> >  	}
> >  
> > +	ret = dev_pm_opp_init_cpufreq_table(cpu_dev, &freq_table);
> > +	if (ret) {
> > +		pr_err("failed to init cpufreq table: %d\n", ret);
> > +		goto out_free_priv;
> > +	}
> > +
> >  	/*
> >  	 * For now, just loading the cooling device;
> >  	 * thermal DT code takes care of matching them.
> > @@ -275,9 +289,9 @@ static int cpufreq_init(struct cpufreq_policy *policy)
> >  
> >  out_cooling_unregister:
> >  	cpufreq_cooling_unregister(priv->cdev);
> > -	kfree(priv);
> > -out_free_table:
> >  	dev_pm_opp_free_cpufreq_table(cpu_dev, &freq_table);
> > +out_free_priv:
> > +	kfree(priv);
> >  out_put_node:
> >  	of_node_put(np);
> >  out_put_reg_clk:
> > 
> 

-- 
Pengutronix e.K.             | Lucas Stach                 |
Industrial Linux Solutions   | http://www.pengutronix.de/  |

[PATCH v2 6/6] ARM: imx53: add cpufreq support

[Lucas Stach]

Am Sonntag, den 28.09.2014, 12:15 +0800 schrieb Shawn Guo:
> On Fri, Sep 26, 2014 at 03:41:04PM +0200, Lucas Stach wrote:
> > Instanciate device for the generic cpufreq-dt driver.
> > 
> > Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
> 
> I assume that I should only apply this patch after the cpufreq-dt change
> gets merged and shows up on my base.
> 
> Shawn
> 
I would think its safe to merge this patch. The cpufreq-dt change will
be merged with 3.18. Until then the worst that could happen is that the
cpufreq driver doesn't bind to the mx5 cpu device.

> > ---
> > v2:
> > - new patch, split out from DTS changes and rebased
> >   with new name for cpufreq driver
> > ---
> >  arch/arm/mach-imx/mach-imx53.c | 2 ++
> >  1 file changed, 2 insertions(+)
> > 
> > diff --git a/arch/arm/mach-imx/mach-imx53.c b/arch/arm/mach-imx/mach-imx53.c
> > index 03dd6ea13acc..7587cf0cba3e 100644
> > --- a/arch/arm/mach-imx/mach-imx53.c
> > +++ b/arch/arm/mach-imx/mach-imx53.c
> > @@ -41,6 +41,8 @@ static void __init imx53_dt_init(void)
> >  static void __init imx53_init_late(void)
> >  {
> >  	imx53_pm_init();
> > +
> > +	platform_device_register_simple("cpufreq-dt", -1, NULL, 0);
> >  }
> >  
> >  static const char * const imx53_dt_board_compat[] __initconst = {
> > -- 
> > 2.1.0
> > 
> --
> To unsubscribe from this list: send the line "unsubscribe linux-pm" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html

-- 
Pengutronix e.K.             | Lucas Stach                 |
Industrial Linux Solutions   | http://www.pengutronix.de/  |

[PATCH v2 6/6] ARM: imx53: add cpufreq support

[Shawn Guo]

On Mon, Sep 29, 2014 at 10:33:48AM +0200, Lucas Stach wrote:
> Am Sonntag, den 28.09.2014, 12:15 +0800 schrieb Shawn Guo:
> > On Fri, Sep 26, 2014 at 03:41:04PM +0200, Lucas Stach wrote:
> > > Instanciate device for the generic cpufreq-dt driver.
> > > 
> > > Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
> > 
> > I assume that I should only apply this patch after the cpufreq-dt change
> > gets merged and shows up on my base.
> > 
> > Shawn
> > 
> I would think its safe to merge this patch. The cpufreq-dt change will
> be merged with 3.18. Until then the worst that could happen is that the
> cpufreq driver doesn't bind to the mx5 cpu device.

Ah, right.  The device will not bind on my tree, so it's safe to apply
it right away.

Applied, thanks.

[PATCH v2 1/6] cpufreq: dt: disable unsupported OPPs

[Rafael J. Wysocki]

On Monday, September 29, 2014 10:24:48 AM Lucas Stach wrote:
> Am Freitag, den 26.09.2014, 23:55 +0200 schrieb Rafael J. Wysocki:
> > On Friday, September 26, 2014 03:40:59 PM Lucas Stach wrote:
> > > If the regulator connected to the CPU voltage plane doesn't
> > > support an OPP specified voltage with the acceptable tolerance
> > > it's better to just disable the OPP instead of constantly
> > > failing the voltage scaling later on.
> > > 
> > > Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
> > 
> > Why do you need this to be part of the whole series?  Is there any
> > hard dependency on it?
> > 
> No there isn't any hard dependency. It's just that one of the boards I
> was testing this series with needs this to properly disable one invalid
> OPP.
> 
> So it's no problem to rip this one out of the series. Sorry for the
> confusion.

OK

Please resend it as a separate fix, then.

-- 
I speak only for myself.
Rafael J. Wysocki, Intel Open Source Technology Center.

[PATCH v2 5/6] ARM: dts: imx53: add cpufreq-dt support

[Stefan Wahren]

Hi Lucas,
 
i know the patch is already applied, but ...

> Lucas Stach <l.stach@pengutronix.de> hat am 26. September 2014 um 15:41
> geschrieben:
>
>
> Add all required properties for the cpufreq-dt driver.
>
> Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
> ---
> v2:
> - split out device instantiation
> ---
> arch/arm/boot/dts/imx53.dtsi | 13 ++++++++++++-
> 1 file changed, 12 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi
> index c6c58c1c00e3..aa2fb2f3616d 100644
> --- a/arch/arm/boot/dts/imx53.dtsi
> +++ b/arch/arm/boot/dts/imx53.dtsi
> @@ -46,10 +46,21 @@
> cpus {
> #address-cells = <1>;
> #size-cells = <0>;
> - cpu at 0 {
> + cpu0: cpu at 0 {
> device_type = "cpu";
> compatible = "arm,cortex-a8";
> reg = <0x0>;
> + clocks = <&clks IMX5_CLK_ARM>;
> + clock-latency = <61036>;
> + voltage-tolerance = <5>;
> + operating-points = <
> + /* kHz */
> + 166666 850000
 
shouldn't it be "166667 850000"?
 
I ran into the same issue on i.MX28. If i round down the frequencies the voltage
of the next higher OPP will be set.
 
Best regards
 
Stefan
 
> + 400000 900000
> + 800000 1050000
> + 1000000 1200000
> + 1200000 1300000
> + >;
> };
> };
>
> --
> 2.1.0
>
>
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