[PATCH 0/9] ARM: DRA7: add display support

[PATCH 0/9] ARM: DRA7: add display support

[Tomi Valkeinen]

Hi,

This series adds the arch/arm/ side of the display support for DRA7 (DRA72x,
DRA74x, AM54xx) SoCs. Also support for HDMI output on x15 and DRA72 EVM boards
is added.

The series is based on OMAPDSS driver patches in fbdev changes for 3.20, which
have been merged to Linus' tree.

The changes are very similar to OMAP5 DSS. All the other patches look fine to
me except the "RFC: ARM: DRA7: enable DSS_DESHDCP_CLKEN". That's been discussed
earlier with Paul and Tero, but I don't think we have any good solution for it
yet.

 Tomi

Tomi Valkeinen (9):
  arm/dts: dra7xx: add 'ti,set-rate-parent' for dss_dss_clk
  ARM: DRA7: hwmod: add DMM hwmod description
  ARM: DRA7: hwmod: set DSS submodule parent hwmods
  ARM: OMAP: display: change compat names to array
  ARM: OMAP2+: display: detect DRA7 DSS
  arm/dts: dra7.dtsi: add DSS support
  arm/dts: dra72-evm.dts: add HDMI
  arm/dts: am57xx-beagle-x15.dts: add HDMI
  RFC: ARM: DRA7: enable DSS_DESHDCP_CLKEN

 arch/arm/boot/dts/am57xx-beagle-x15.dts   |  80 +++++++++++++++++++++
 arch/arm/boot/dts/dra7.dtsi               |  38 ++++++++++
 arch/arm/boot/dts/dra72-evm.dts           | 111 ++++++++++++++++++++++++++++++
 arch/arm/boot/dts/dra72x.dtsi             |  11 +++
 arch/arm/boot/dts/dra74x.dtsi             |  15 ++++
 arch/arm/boot/dts/dra7xx-clocks.dtsi      |   1 +
 arch/arm/mach-omap2/display.c             |  32 +++++----
 arch/arm/mach-omap2/io.c                  |  11 +++
 arch/arm/mach-omap2/omap_hwmod_7xx_data.c |  32 +++++++++
 9 files changed, 316 insertions(+), 15 deletions(-)

-- 
2.3.0

[PATCH 1/9] arm/dts: dra7xx: add 'ti, set-rate-parent' for dss_dss_clk

[Tomi Valkeinen]

We need set-rate-parent flags for the display's clock path so that the
DSS driver can change the clock rate of the PLL.

This patchs adds the ti,set-rate-parent flag to 'dss_dss_clk' clock
node, which is only a gate clock, allowing the setting of the clock rate
to propagate to the PLL.

Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Cc: devicetree at vger.kernel.org
---
 arch/arm/boot/dts/dra7xx-clocks.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi
index 4bdcbd61ce47..0d76233840e6 100644
--- a/arch/arm/boot/dts/dra7xx-clocks.dtsi
+++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi
@@ -1451,6 +1451,7 @@
 		clocks = <&dpll_per_h12x2_ck>;
 		ti,bit-shift = <8>;
 		reg = <0x1120>;
+		ti,set-rate-parent;
 	};
 
 	dss_hdmi_clk: dss_hdmi_clk {
-- 
2.3.0

[PATCH 2/9] ARM: DRA7: hwmod: add DMM hwmod description

[Tomi Valkeinen]

Add DMM hwmod entries for DRA7. This is identical to DMM on OMAP5.

Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
---
 arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 30 ++++++++++++++++++++++++++++++
 1 file changed, 30 insertions(+)

diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
index ffd6604cd546..47664bab5b57 100644
--- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
@@ -49,6 +49,27 @@
  */
 
 /*
+ * 'dmm' class
+ * instance(s): dmm
+ */
+static struct omap_hwmod_class dra7xx_dmm_hwmod_class = {
+	.name	= "dmm",
+};
+
+/* dmm */
+static struct omap_hwmod dra7xx_dmm_hwmod = {
+	.name		= "dmm",
+	.class		= &dra7xx_dmm_hwmod_class,
+	.clkdm_name	= "emif_clkdm",
+	.prcm = {
+		.omap4 = {
+			.clkctrl_offs = DRA7XX_CM_EMIF_DMM_CLKCTRL_OFFSET,
+			.context_offs = DRA7XX_RM_EMIF_DMM_CONTEXT_OFFSET,
+		},
+	},
+};
+
+/*
  * 'l3' class
  * instance(s): l3_instr, l3_main_1, l3_main_2
  */
@@ -2312,6 +2333,14 @@ static struct omap_hwmod dra7xx_wd_timer2_hwmod = {
  * Interfaces
  */
 
+/* l3_main_1 -> dmm */
+static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dmm = {
+	.master		= &dra7xx_l3_main_1_hwmod,
+	.slave		= &dra7xx_dmm_hwmod,
+	.clk		= "l3_iclk_div",
+	.user		= OCP_USER_SDMA,
+};
+
 /* l3_main_2 -> l3_instr */
 static struct omap_hwmod_ocp_if dra7xx_l3_main_2__l3_instr = {
 	.master		= &dra7xx_l3_main_2_hwmod,
@@ -3264,6 +3293,7 @@ static struct omap_hwmod_ocp_if dra7xx_l4_wkup__wd_timer2 = {
 };
 
 static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
+	&dra7xx_l3_main_1__dmm,
 	&dra7xx_l3_main_2__l3_instr,
 	&dra7xx_l4_cfg__l3_main_1,
 	&dra7xx_mpu__l3_main_1,
-- 
2.3.0

[PATCH 3/9] ARM: DRA7: hwmod: set DSS submodule parent hwmods

[Tomi Valkeinen]

Set DSS core hwmod as the parent for all the DSS submodules.

Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
---
 arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
index 47664bab5b57..d7d2404f5f28 100644
--- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
@@ -521,6 +521,7 @@ static struct omap_hwmod dra7xx_dss_dispc_hwmod = {
 		},
 	},
 	.dev_attr	= &dss_dispc_dev_attr,
+	.parent_hwmod	= &dra7xx_dss_hwmod,
 };
 
 /*
@@ -562,6 +563,7 @@ static struct omap_hwmod dra7xx_dss_hdmi_hwmod = {
 	},
 	.opt_clks	= dss_hdmi_opt_clks,
 	.opt_clks_cnt	= ARRAY_SIZE(dss_hdmi_opt_clks),
+	.parent_hwmod	= &dra7xx_dss_hwmod,
 };
 
 /*
-- 
2.3.0

[PATCH 4/9] ARM: OMAP: display: change compat names to array

[Tomi Valkeinen]

Simplify the DSS detection logic by creating a list of the omapdss
compat strings, instead of checking each separately with an 'if'.

Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
---
 arch/arm/mach-omap2/display.c | 29 ++++++++++++++---------------
 1 file changed, 14 insertions(+), 15 deletions(-)

diff --git a/arch/arm/mach-omap2/display.c b/arch/arm/mach-omap2/display.c
index 7a050f9c37ff..156d022b1e09 100644
--- a/arch/arm/mach-omap2/display.c
+++ b/arch/arm/mach-omap2/display.c
@@ -562,25 +562,24 @@ void __init omapdss_early_init_of(void)
 
 }
 
+static const char * const omapdss_compat_names[] __initconst = {
+	"ti,omap2-dss",
+	"ti,omap3-dss",
+	"ti,omap4-dss",
+	"ti,omap5-dss",
+};
+
 struct device_node * __init omapdss_find_dss_of_node(void)
 {
 	struct device_node *node;
+	int i;
 
-	node = of_find_compatible_node(NULL, NULL, "ti,omap2-dss");
-	if (node)
-		return node;
-
-	node = of_find_compatible_node(NULL, NULL, "ti,omap3-dss");
-	if (node)
-		return node;
-
-	node = of_find_compatible_node(NULL, NULL, "ti,omap4-dss");
-	if (node)
-		return node;
-
-	node = of_find_compatible_node(NULL, NULL, "ti,omap5-dss");
-	if (node)
-		return node;
+	for (i = 0; i < ARRAY_SIZE(omapdss_compat_names); ++i) {
+		node = of_find_compatible_node(NULL, NULL,
+			omapdss_compat_names[i]);
+		if (node)
+			return node;
+	}
 
 	return NULL;
 }
-- 
2.3.0

[PATCH 5/9] ARM: OMAP2+: display: detect DRA7 DSS

[Tomi Valkeinen]

Add platform code to detect DRA7 DSS.

Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
---
 arch/arm/mach-omap2/display.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/arm/mach-omap2/display.c b/arch/arm/mach-omap2/display.c
index 156d022b1e09..7f596fe2bfeb 100644
--- a/arch/arm/mach-omap2/display.c
+++ b/arch/arm/mach-omap2/display.c
@@ -281,6 +281,8 @@ static enum omapdss_version __init omap_display_get_version(void)
 		return OMAPDSS_VER_OMAP5;
 	else if (soc_is_am43xx())
 		return OMAPDSS_VER_AM43xx;
+	else if (soc_is_dra7xx())
+		return OMAPDSS_VER_DRA7xx;
 	else
 		return OMAPDSS_VER_UNKNOWN;
 }
@@ -567,6 +569,7 @@ static const char * const omapdss_compat_names[] __initconst = {
 	"ti,omap3-dss",
 	"ti,omap4-dss",
 	"ti,omap5-dss",
+	"ti,dra7-dss",
 };
 
 struct device_node * __init omapdss_find_dss_of_node(void)
-- 
2.3.0

[PATCH 6/9] arm/dts: dra7.dtsi: add DSS support

[Tomi Valkeinen]

DRA7xxx contains a very similar DSS to OMAP5. The main differences are:

* no DSI or RFBI support.
* 1 or 2 dedicated video PLLs.
* need to do additional configuration to the DRA7 CONTROL module.

DRA72xx has only one video PLL, and DRA74xx has two.

Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Cc: devicetree at vger.kernel.org
---
 arch/arm/boot/dts/dra7.dtsi   | 38 ++++++++++++++++++++++++++++++++++++++
 arch/arm/boot/dts/dra72x.dtsi | 11 +++++++++++
 arch/arm/boot/dts/dra74x.dtsi | 15 +++++++++++++++
 3 files changed, 64 insertions(+)

diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index 22771bc1643a..fc35a8a06d95 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -1421,6 +1421,44 @@
 			clocks = <&sys_clkin1>;
 			status = "disabled";
 		};
+
+		dss: dss at 58000000 {
+			compatible = "ti,dra7-dss";
+			/* 'reg' defined in dra72x.dtsi and dra74x.dtsi */
+			/* 'clocks' defined in dra72x.dtsi and dra74x.dtsi */
+			status = "disabled";
+			ti,hwmods = "dss_core";
+			/* CTRL_CORE_DSS_PLL_CONTROL */
+			syscon-pll-ctrl = <&dra7_ctrl_core 0x538>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;
+
+			dispc at 58001000 {
+				compatible = "ti,dra7-dispc";
+				reg = <0x58001000 0x1000>;
+				interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+				ti,hwmods = "dss_dispc";
+				clocks = <&dss_dss_clk>;
+				clock-names = "fck";
+				/* CTRL_CORE_SMA_SW_1 */
+				syscon-pol = <&dra7_ctrl_core 0x534>;
+			};
+
+			hdmi: encoder at 58060000 {
+				compatible = "ti,dra7-hdmi";
+				reg = <0x58040000 0x200>,
+				      <0x58040200 0x80>,
+				      <0x58040300 0x80>,
+				      <0x58060000 0x19000>;
+				reg-names = "wp", "pll", "phy", "core";
+				interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+				ti,hwmods = "dss_hdmi";
+				clocks = <&dss_48mhz_clk>, <&dss_hdmi_clk>;
+				clock-names = "fck", "sys_clk";
+			};
+		};
 	};
 };
 
diff --git a/arch/arm/boot/dts/dra72x.dtsi b/arch/arm/boot/dts/dra72x.dtsi
index e5a3d23a3df1..0866866c8e94 100644
--- a/arch/arm/boot/dts/dra72x.dtsi
+++ b/arch/arm/boot/dts/dra72x.dtsi
@@ -28,3 +28,14 @@
 		interrupts = <GIC_SPI DIRECT_IRQ(131) IRQ_TYPE_LEVEL_HIGH>;
 	};
 };
+
+&dss {
+	reg = <0x58000000 0x80>,
+	      <0x58004054 0x4>,
+	      <0x58004300 0x20>;
+	reg-names = "dss", "pll1_clkctrl", "pll1";
+
+	clocks = <&dss_dss_clk>,
+		 <&dss_video1_clk>;
+	clock-names = "fck", "video1_clk";
+};
diff --git a/arch/arm/boot/dts/dra74x.dtsi b/arch/arm/boot/dts/dra74x.dtsi
index 10173fab1a15..1a4f4970aaad 100644
--- a/arch/arm/boot/dts/dra74x.dtsi
+++ b/arch/arm/boot/dts/dra74x.dtsi
@@ -67,3 +67,18 @@
 		};
 	};
 };
+
+&dss {
+	reg = <0x58000000 0x80>,
+	      <0x58004054 0x4>,
+	      <0x58004300 0x20>,
+	      <0x58005054 0x4>,
+	      <0x58005300 0x20>;
+	reg-names = "dss", "pll1_clkctrl", "pll1",
+		    "pll2_clkctrl", "pll2";
+
+	clocks = <&dss_dss_clk>,
+		 <&dss_video1_clk>,
+		 <&dss_video2_clk>;
+	clock-names = "fck", "video1_clk", "video2_clk";
+};
-- 
2.3.0

[PATCH 7/9] arm/dts: dra72-evm.dts: add HDMI

[Tomi Valkeinen]

DRA72 EVM has a HDMI output. This patch adds the device tree nodes
required for HDMI.

Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Cc: devicetree at vger.kernel.org
---
 arch/arm/boot/dts/dra72-evm.dts | 111 ++++++++++++++++++++++++++++++++++++++++
 1 file changed, 111 insertions(+)

diff --git a/arch/arm/boot/dts/dra72-evm.dts b/arch/arm/boot/dts/dra72-evm.dts
index 89085d066c65..85f9aa4fc94f 100644
--- a/arch/arm/boot/dts/dra72-evm.dts
+++ b/arch/arm/boot/dts/dra72-evm.dts
@@ -8,6 +8,7 @@
 /dts-v1/;
 
 #include "dra72x.dtsi"
+#include <dt-bindings/gpio/gpio.h>
 
 / {
 	model = "TI DRA722";
@@ -18,12 +19,61 @@
 		reg = <0x80000000 0x40000000>; /* 1024 MB */
 	};
 
+	aliases {
+		display0 = &hdmi0;
+	};
+
 	evm_3v3: fixedregulator-evm_3v3 {
 		compatible = "regulator-fixed";
 		regulator-name = "evm_3v3";
 		regulator-min-microvolt = <3300000>;
 		regulator-max-microvolt = <3300000>;
 	};
+
+	hdmi0: connector {
+		compatible = "hdmi-connector";
+		label = "hdmi";
+
+		type = "a";
+
+		port {
+			hdmi_connector_in: endpoint {
+				remote-endpoint = <&tpd12s015_out>;
+			};
+		};
+	};
+
+	tpd12s015: encoder {
+		compatible = "ti,tpd12s015";
+
+		pinctrl-names = "default";
+		pinctrl-0 = <&tpd12s015_pins>;
+
+		gpios = <&pcf_hdmi 4 GPIO_ACTIVE_HIGH>,	/* P4, CT CP HPD */
+			<&pcf_hdmi 5 GPIO_ACTIVE_HIGH>,	/* P5, LS OE */
+			<&gpio7 12 GPIO_ACTIVE_HIGH>;	/* gpio7_12/sp1_cs2, HPD */
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port at 0 {
+				reg = <0>;
+
+				tpd12s015_in: endpoint {
+					remote-endpoint = <&hdmi_out>;
+				};
+			};
+
+			port at 1 {
+				reg = <1>;
+
+				tpd12s015_out: endpoint {
+					remote-endpoint = <&hdmi_connector_in>;
+				};
+			};
+		};
+	};
 };
 
 &dra7_pmx_core {
@@ -34,6 +84,13 @@
 		>;
 	};
 
+	i2c5_pins: pinmux_i2c5_pins {
+		pinctrl-single,pins = <
+			0x2b4 (PIN_INPUT | MUX_MODE10) /* mcasp1_axr0.i2c5_sda */
+			0x2b8 (PIN_INPUT | MUX_MODE10) /* mcasp1_axr1.i2c5_scl */
+		>;
+	};
+
 	nand_default: nand_default {
 		pinctrl-single,pins = <
 			0x0	(PIN_INPUT  | MUX_MODE0) /* gpmc_ad0 */
@@ -121,6 +178,19 @@
 			0x418   (MUX_MODE15)	/* wakeup0.off */
 		>;
 	};
+
+	hdmi_pins: pinmux_hdmi_pins {
+		pinctrl-single,pins = <
+			0x408 (PIN_INPUT | MUX_MODE1) /* i2c2_sda.hdmi1_ddc_scl */
+			0x40c (PIN_INPUT | MUX_MODE1) /* i2c2_scl.hdmi1_ddc_sda */
+		>;
+	};
+
+	tpd12s015_pins: pinmux_tpd12s015_pins {
+		pinctrl-single,pins = <
+			0x3b8 (PIN_INPUT_PULLDOWN | MUX_MODE14) /* gpio7_12 HPD */
+		>;
+	};
 };
 
 &i2c1 {
@@ -245,6 +315,27 @@
 	};
 };
 
+&i2c5 {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c5_pins>;
+	clock-frequency = <400000>;
+
+	pcf_hdmi: pcf8575 at 26 {
+		compatible = "nxp,pcf8575";
+		reg = <0x26>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		/*
+		 * initial state is used here to keep the mdio interface
+		 * selected on RU89 through SEL_VIN4_MUX_S0, VIN2_S1 and
+		 * VIN2_S0 driven high otherwise Ethernet stops working
+		 * VIN6_SEL_S0 is low, thus selecting McASP3 over VIN6
+		 */
+		lines-initial-states = <0x0f2b>;
+	};
+};
+
 &uart1 {
 	status = "okay";
 };
@@ -461,3 +552,23 @@
 	pinctrl-0 = <&dcan1_pins_default>;
 	pinctrl-1 = <&dcan1_pins_sleep>;
 };
+
+&dss {
+	status = "ok";
+
+	vdda_video-supply = <&ldo5_reg>;
+};
+
+&hdmi {
+	status = "ok";
+	vdda-supply = <&ldo3_reg>;
+
+	pinctrl-names = "default";
+	pinctrl-0 = <&hdmi_pins>;
+
+	port {
+		hdmi_out: endpoint {
+			remote-endpoint = <&tpd12s015_in>;
+		};
+	};
+};
-- 
2.3.0

[PATCH 8/9] arm/dts: am57xx-beagle-x15.dts: add HDMI

[Tomi Valkeinen]

AM57xx Beagle X15 has a HDMI output. This patch adds the device tree
nodes required for HDMI.

Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Cc: devicetree at vger.kernel.org
---
 arch/arm/boot/dts/am57xx-beagle-x15.dts | 80 +++++++++++++++++++++++++++++++++
 1 file changed, 80 insertions(+)

diff --git a/arch/arm/boot/dts/am57xx-beagle-x15.dts b/arch/arm/boot/dts/am57xx-beagle-x15.dts
index 49edbda68cd5..0b838d34b8a1 100644
--- a/arch/arm/boot/dts/am57xx-beagle-x15.dts
+++ b/arch/arm/boot/dts/am57xx-beagle-x15.dts
@@ -19,6 +19,7 @@
 	aliases {
 		rtc0 = &mcp_rtc;
 		rtc1 = &tps659038_rtc;
+		display0 = &hdmi0;
 	};
 
 	memory {
@@ -80,6 +81,51 @@
 			default-state = "off";
 		};
 	};
+
+	hdmi0: connector {
+		compatible = "hdmi-connector";
+		label = "hdmi";
+
+		type = "a";
+
+		port {
+			hdmi_connector_in: endpoint {
+				remote-endpoint = <&tpd12s015_out>;
+			};
+		};
+	};
+
+	tpd12s015: encoder {
+		compatible = "ti,tpd12s015";
+
+		pinctrl-names = "default";
+		pinctrl-0 = <&tpd12s015_pins>;
+
+		gpios = <&gpio7 10 GPIO_ACTIVE_HIGH>,	/* gpio7_10, CT CP HPD */
+			<&gpio6 28 GPIO_ACTIVE_HIGH>,	/* gpio6_28, LS OE */
+			<&gpio7 12 GPIO_ACTIVE_HIGH>;	/* gpio7_12/sp1_cs2, HPD */
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port at 0 {
+				reg = <0>;
+
+				tpd12s015_in: endpoint {
+					remote-endpoint = <&hdmi_out>;
+				};
+			};
+
+			port at 1 {
+				reg = <1>;
+
+				tpd12s015_out: endpoint {
+					remote-endpoint = <&hdmi_connector_in>;
+				};
+			};
+		};
+	};
 };
 
 &dra7_pmx_core {
@@ -99,6 +145,13 @@
 		>;
 	};
 
+	hdmi_pins: pinmux_hdmi_pins {
+		pinctrl-single,pins = <
+			0x408 (PIN_INPUT | MUX_MODE1)	/* i2c2_sda.hdmi1_ddc_scl */
+			0x40c (PIN_INPUT | MUX_MODE1)	/* i2c2_scl.hdmi1_ddc_sda */
+		>;
+	};
+
 	i2c3_pins_default: i2c3_pins_default {
 		pinctrl-single,pins = <
 			0x2a4 (PIN_INPUT| MUX_MODE10)	/* mcasp1_aclkx.i2c3_sda */
@@ -164,6 +217,13 @@
 		>;
 	};
 
+	tpd12s015_pins: pinmux_tpd12s015_pins {
+		pinctrl-single,pins = <
+			0x3b0 (PIN_OUTPUT | MUX_MODE14)		/* gpio7_10 CT_CP_HPD */
+			0x3b8 (PIN_INPUT_PULLDOWN | MUX_MODE14)	/* gpio7_12 HPD */
+			0x370 (PIN_OUTPUT | MUX_MODE14)		/* gpio6_28 LS_OE */
+		>;
+	};
 };
 
 &i2c1 {
@@ -403,3 +463,23 @@
 	pinctrl-names = "default";
 	pinctrl-0 = <&usb1_pins>;
 };
+
+&dss {
+	status = "ok";
+
+	vdda_video-supply = <&ldoln_reg>;
+};
+
+&hdmi {
+	status = "ok";
+	vdda-supply = <&ldo3_reg>;
+
+	pinctrl-names = "default";
+	pinctrl-0 = <&hdmi_pins>;
+
+	port {
+		hdmi_out: endpoint {
+			remote-endpoint = <&tpd12s015_in>;
+		};
+	};
+};
-- 
2.3.0

[PATCH 9/9] RFC: ARM: DRA7: enable DSS_DESHDCP_CLKEN

[Tomi Valkeinen]

DRA7xx's CTRL_CORE_CONTROL_IO_2 register contains bits for various
subsystems, including PCIe, DCAN, QSPI and DSS. At the moment only DCAN
bits are used by the SW via syscon.

For DSS there is DSS_DESHDCP_CLKEN bit. This (presumably) enables a
clock related to DSS's HDCP. If that clock is off, DSS module does not
start at all, causing OCP errors. This means that the HWMOD code is not
able to reset and initialize DSS.

Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
---
 arch/arm/mach-omap2/io.c | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index a1bd6affb508..2206fb13f195 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -700,6 +700,17 @@ void __init dra7xx_init_early(void)
 	dra7xx_hwmod_init();
 	omap_hwmod_init_postsetup();
 	omap_clk_soc_init = dra7xx_dt_clk_init;
+
+	if (soc_is_dra7xx()) {
+		u32 v;
+		const u16 ctrl_core_control_io_2 = 0x558;
+
+		/* set CTRL_CORE_CONTROL_IO_2:DSS_DESHDCP_CLKEN */
+
+		v = omap_ctrl_readl(ctrl_core_control_io_2);
+		v |= 1;
+		omap_ctrl_writel(v, ctrl_core_control_io_2);
+	}
 }
 
 void __init dra7xx_init_late(void)
-- 
2.3.0

[PATCH 9/9] RFC: ARM: DRA7: enable DSS_DESHDCP_CLKEN

[Nishanth Menon]

On Fri, Feb 13, 2015 at 9:11 AM, Tomi Valkeinen <tomi.valkeinen@ti.com> wrote:
> DRA7xx's CTRL_CORE_CONTROL_IO_2 register contains bits for various
> subsystems, including PCIe, DCAN, QSPI and DSS. At the moment only DCAN
> bits are used by the SW via syscon.
>
> For DSS there is DSS_DESHDCP_CLKEN bit. This (presumably) enables a
> clock related to DSS's HDCP. If that clock is off, DSS module does not
> start at all, causing OCP errors. This means that the HWMOD code is not
> able to reset and initialize DSS.
>
> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
> ---
>  arch/arm/mach-omap2/io.c | 11 +++++++++++
>  1 file changed, 11 insertions(+)
>
> diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
> index a1bd6affb508..2206fb13f195 100644
> --- a/arch/arm/mach-omap2/io.c
> +++ b/arch/arm/mach-omap2/io.c
> @@ -700,6 +700,17 @@ void __init dra7xx_init_early(void)
>         dra7xx_hwmod_init();
>         omap_hwmod_init_postsetup();
>         omap_clk_soc_init = dra7xx_dt_clk_init;
> +
> +       if (soc_is_dra7xx()) {

Umm.. this code will only be executed for dra7xx :)

> +               u32 v;
> +               const u16 ctrl_core_control_io_2 = 0x558;
> +
> +               /* set CTRL_CORE_CONTROL_IO_2:DSS_DESHDCP_CLKEN */
> +
> +               v = omap_ctrl_readl(ctrl_core_control_io_2);
> +               v |= 1;
> +               omap_ctrl_writel(v, ctrl_core_control_io_2);
> +       }
>  }
>
>  void __init dra7xx_init_late(void)
just my 2 cents.
I would probably wait for control module to become syscon and probably
model this as syscon clk - I thin we should be seeing a series
sometime soon.

-- 
---
Regards,
Nishanth Menon

[PATCH 9/9] RFC: ARM: DRA7: enable DSS_DESHDCP_CLKEN

[Tero Kristo]

On 02/13/2015 05:25 PM, Nishanth Menon wrote:
> On Fri, Feb 13, 2015 at 9:11 AM, Tomi Valkeinen <tomi.valkeinen@ti.com> wrote:
>> DRA7xx's CTRL_CORE_CONTROL_IO_2 register contains bits for various
>> subsystems, including PCIe, DCAN, QSPI and DSS. At the moment only DCAN
>> bits are used by the SW via syscon.
>>
>> For DSS there is DSS_DESHDCP_CLKEN bit. This (presumably) enables a
>> clock related to DSS's HDCP. If that clock is off, DSS module does not
>> start at all, causing OCP errors. This means that the HWMOD code is not
>> able to reset and initialize DSS.
>>
>> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
>> ---
>>   arch/arm/mach-omap2/io.c | 11 +++++++++++
>>   1 file changed, 11 insertions(+)
>>
>> diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
>> index a1bd6affb508..2206fb13f195 100644
>> --- a/arch/arm/mach-omap2/io.c
>> +++ b/arch/arm/mach-omap2/io.c
>> @@ -700,6 +700,17 @@ void __init dra7xx_init_early(void)
>>          dra7xx_hwmod_init();
>>          omap_hwmod_init_postsetup();
>>          omap_clk_soc_init = dra7xx_dt_clk_init;
>> +
>> +       if (soc_is_dra7xx()) {
>
> Umm.. this code will only be executed for dra7xx :)
>
>> +               u32 v;
>> +               const u16 ctrl_core_control_io_2 = 0x558;
>> +
>> +               /* set CTRL_CORE_CONTROL_IO_2:DSS_DESHDCP_CLKEN */
>> +
>> +               v = omap_ctrl_readl(ctrl_core_control_io_2);
>> +               v |= 1;
>> +               omap_ctrl_writel(v, ctrl_core_control_io_2);
>> +       }
>>   }
>>
>>   void __init dra7xx_init_late(void)
> just my 2 cents.
> I would probably wait for control module to become syscon and probably
> model this as syscon clk - I thin we should be seeing a series
> sometime soon.

Yeah, I will be posting a series in a bit, just running some final tests 
on it.

-Tero

[PATCH 0/9] ARM: DRA7: add display support

[Nishanth Menon]

On 02/13/2015 09:11 AM, Tomi Valkeinen wrote:
> Hi,
> 
> This series adds the arch/arm/ side of the display support for DRA7 (DRA72x,
> DRA74x, AM54xx) SoCs. Also support for HDMI output on x15 and DRA72 EVM boards
> is added.
> 
> The series is based on OMAPDSS driver patches in fbdev changes for 3.20, which
> have been merged to Linus' tree.
> 
> The changes are very similar to OMAP5 DSS. All the other patches look fine to
> me except the "RFC: ARM: DRA7: enable DSS_DESHDCP_CLKEN". That's been discussed
> earlier with Paul and Tero, but I don't think we have any good solution for it
> yet.

Is there some specific tag I can test this on (some next perhaps?), I
get the following error:
build fail, Error:
arch/arm/mach-omap2/display.c: In function ?omap_display_get_version?:
arch/arm/mach-omap2/display.c:285:10: error: ?OMAPDSS_VER_DRA7xx?
undeclared (first use in this function)
arch/arm/mach-omap2/display.c:285:10: note: each undeclared identifier
is reported only once for each function it appears in
arch/arm/mach-omap2/display.c:288:1: warning: control reaches end of
non-void function [-Wreturn-type]
make[1]: *** [arch/arm/mach-omap2/display.o] Error 1
make: *** [arch/arm/mach-omap2] Error 2
make: *** Waiting for unfinished jobs....


Further are you proposing this for 3.20 or 3.21 window? 3.20, we seem
to have already missed.


> 
>  Tomi
> 
> Tomi Valkeinen (9):
>   arm/dts: dra7xx: add 'ti,set-rate-parent' for dss_dss_clk
^^
>   ARM: DRA7: hwmod: add DMM hwmod description
>   ARM: DRA7: hwmod: set DSS submodule parent hwmods
>   ARM: OMAP: display: change compat names to array
>   ARM: OMAP2+: display: detect DRA7 DSS
>   arm/dts: dra7.dtsi: add DSS support
^^
>   arm/dts: dra72-evm.dts: add HDMI
^^
>   arm/dts: am57xx-beagle-x15.dts: add HDMI

ARM: dts: am57xx-beagle-x15: Add HDMI

Would be good to follow above convention for all dts patches $subject.


>   RFC: ARM: DRA7: enable DSS_DESHDCP_CLKEN
> 
>  arch/arm/boot/dts/am57xx-beagle-x15.dts   |  80 +++++++++++++++++++++
>  arch/arm/boot/dts/dra7.dtsi               |  38 ++++++++++
>  arch/arm/boot/dts/dra72-evm.dts           | 111 ++++++++++++++++++++++++++++++
>  arch/arm/boot/dts/dra72x.dtsi             |  11 +++
>  arch/arm/boot/dts/dra74x.dtsi             |  15 ++++
>  arch/arm/boot/dts/dra7xx-clocks.dtsi      |   1 +
>  arch/arm/mach-omap2/display.c             |  32 +++++----
>  arch/arm/mach-omap2/io.c                  |  11 +++
>  arch/arm/mach-omap2/omap_hwmod_7xx_data.c |  32 +++++++++
>  9 files changed, 316 insertions(+), 15 deletions(-)
> 


-- 
Regards,
Nishanth Menon

[PATCH 9/9] RFC: ARM: DRA7: enable DSS_DESHDCP_CLKEN

[Tomi Valkeinen]

On 13/02/15 17:25, Nishanth Menon wrote:
> On Fri, Feb 13, 2015 at 9:11 AM, Tomi Valkeinen <tomi.valkeinen@ti.com> wrote:
>> DRA7xx's CTRL_CORE_CONTROL_IO_2 register contains bits for various
>> subsystems, including PCIe, DCAN, QSPI and DSS. At the moment only DCAN
>> bits are used by the SW via syscon.
>>
>> For DSS there is DSS_DESHDCP_CLKEN bit. This (presumably) enables a
>> clock related to DSS's HDCP. If that clock is off, DSS module does not
>> start at all, causing OCP errors. This means that the HWMOD code is not
>> able to reset and initialize DSS.
>>
>> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
>> ---
>>  arch/arm/mach-omap2/io.c | 11 +++++++++++
>>  1 file changed, 11 insertions(+)
>>
>> diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
>> index a1bd6affb508..2206fb13f195 100644
>> --- a/arch/arm/mach-omap2/io.c
>> +++ b/arch/arm/mach-omap2/io.c
>> @@ -700,6 +700,17 @@ void __init dra7xx_init_early(void)
>>         dra7xx_hwmod_init();
>>         omap_hwmod_init_postsetup();
>>         omap_clk_soc_init = dra7xx_dt_clk_init;
>> +
>> +       if (soc_is_dra7xx()) {
> 
> Umm.. this code will only be executed for dra7xx :)

Better safe than sorry! But you're right, I'll remove the if =).

>> +               u32 v;
>> +               const u16 ctrl_core_control_io_2 = 0x558;
>> +
>> +               /* set CTRL_CORE_CONTROL_IO_2:DSS_DESHDCP_CLKEN */
>> +
>> +               v = omap_ctrl_readl(ctrl_core_control_io_2);
>> +               v |= 1;
>> +               omap_ctrl_writel(v, ctrl_core_control_io_2);
>> +       }
>>  }
>>
>>  void __init dra7xx_init_late(void)
> just my 2 cents.
> I would probably wait for control module to become syscon and probably
> model this as syscon clk - I thin we should be seeing a series
> sometime soon.

Yep, I hope Tero's work will make this patch not needed. I wanted to
include something in this series that makes the DSS usable.

 Tomi


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[PATCH 0/9] ARM: DRA7: add display support

[Tomi Valkeinen]

On 13/02/15 18:01, Nishanth Menon wrote:
> On 02/13/2015 09:11 AM, Tomi Valkeinen wrote:
>> Hi,
>>
>> This series adds the arch/arm/ side of the display support for DRA7 (DRA72x,
>> DRA74x, AM54xx) SoCs. Also support for HDMI output on x15 and DRA72 EVM boards
>> is added.
>>
>> The series is based on OMAPDSS driver patches in fbdev changes for 3.20, which
>> have been merged to Linus' tree.
>>
>> The changes are very similar to OMAP5 DSS. All the other patches look fine to
>> me except the "RFC: ARM: DRA7: enable DSS_DESHDCP_CLKEN". That's been discussed
>> earlier with Paul and Tero, but I don't think we have any good solution for it
>> yet.
> 
> Is there some specific tag I can test this on (some next perhaps?), I

Linus's master or linux-next should work. This series is based on the
fbdev changes for 3.20. So if Linus' master or linux-next doesn't work,
v3.19 + fbdev-3.20 + this series should work.

> Further are you proposing this for 3.20 or 3.21 window? 3.20, we seem
> to have already missed.

3.21.

 Tomi


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[PATCH 9/9] RFC: ARM: DRA7: enable DSS_DESHDCP_CLKEN

[Tomi Valkeinen]

On 13/02/15 17:42, Tero Kristo wrote:
> On 02/13/2015 05:25 PM, Nishanth Menon wrote:

>> I would probably wait for control module to become syscon and probably
>> model this as syscon clk - I thin we should be seeing a series
>> sometime soon.
> 
> Yeah, I will be posting a series in a bit, just running some final tests
> on it.

I did the above with Tero's series. Adding the DES HDCP clock works ok.

However, I'm not able to do this in HWMOD framework. To enable the DSS
IP block I need to enable both the DSS func clock and the DES HDCP
clock, but the HWMOD framework only allows one mainclock.

I added the HDCP clock as an opt clock, but those are not enabled
intially by the HWMOD framework, and the call in omap_hwmod.c:_enable()
to soc_ops.wait_target_ready(oh) calls fails.

So... Any ideas how to proceed?

 Tomi


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[PATCH 9/9] RFC: ARM: DRA7: enable DSS_DESHDCP_CLKEN

[Tero Kristo]

On 02/20/2015 01:46 PM, Tomi Valkeinen wrote:
> On 13/02/15 17:42, Tero Kristo wrote:
>> On 02/13/2015 05:25 PM, Nishanth Menon wrote:
>
>>> I would probably wait for control module to become syscon and probably
>>> model this as syscon clk - I thin we should be seeing a series
>>> sometime soon.
>>
>> Yeah, I will be posting a series in a bit, just running some final tests
>> on it.
>
> I did the above with Tero's series. Adding the DES HDCP clock works ok.
>
> However, I'm not able to do this in HWMOD framework. To enable the DSS
> IP block I need to enable both the DSS func clock and the DES HDCP
> clock, but the HWMOD framework only allows one mainclock.
>
> I added the HDCP clock as an opt clock, but those are not enabled
> intially by the HWMOD framework, and the call in omap_hwmod.c:_enable()
> to soc_ops.wait_target_ready(oh) calls fails.
>
> So... Any ideas how to proceed?

Add the clock enable at the end of dra7xx_dt_clk_init()?

You need to disable the clock at some point though.

-Tero

[PATCH 9/9] RFC: ARM: DRA7: enable DSS_DESHDCP_CLKEN

[Tomi Valkeinen]

On 20/02/15 14:59, Tero Kristo wrote:
> On 02/20/2015 01:46 PM, Tomi Valkeinen wrote:
>> On 13/02/15 17:42, Tero Kristo wrote:
>>> On 02/13/2015 05:25 PM, Nishanth Menon wrote:
>>
>>>> I would probably wait for control module to become syscon and probably
>>>> model this as syscon clk - I thin we should be seeing a series
>>>> sometime soon.
>>>
>>> Yeah, I will be posting a series in a bit, just running some final tests
>>> on it.
>>
>> I did the above with Tero's series. Adding the DES HDCP clock works ok.
>>
>> However, I'm not able to do this in HWMOD framework. To enable the DSS
>> IP block I need to enable both the DSS func clock and the DES HDCP
>> clock, but the HWMOD framework only allows one mainclock.
>>
>> I added the HDCP clock as an opt clock, but those are not enabled
>> intially by the HWMOD framework, and the call in omap_hwmod.c:_enable()
>> to soc_ops.wait_target_ready(oh) calls fails.
>>
>> So... Any ideas how to proceed?
> 
> Add the clock enable at the end of dra7xx_dt_clk_init()?
> 
> You need to disable the clock at some point though.

Where would I disable it? And if the clock is disabled, doesn't this
again fail when the dss driver tries to enable the IP block? The driver
can enable the HDCP opt clock only later, when the IP block should be up
already.

 Tomi


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[PATCH 9/9] RFC: ARM: DRA7: enable DSS_DESHDCP_CLKEN

[Tero Kristo]

On 02/20/2015 03:48 PM, Tomi Valkeinen wrote:
> On 20/02/15 14:59, Tero Kristo wrote:
>> On 02/20/2015 01:46 PM, Tomi Valkeinen wrote:
>>> On 13/02/15 17:42, Tero Kristo wrote:
>>>> On 02/13/2015 05:25 PM, Nishanth Menon wrote:
>>>
>>>>> I would probably wait for control module to become syscon and probably
>>>>> model this as syscon clk - I thin we should be seeing a series
>>>>> sometime soon.
>>>>
>>>> Yeah, I will be posting a series in a bit, just running some final tests
>>>> on it.
>>>
>>> I did the above with Tero's series. Adding the DES HDCP clock works ok.
>>>
>>> However, I'm not able to do this in HWMOD framework. To enable the DSS
>>> IP block I need to enable both the DSS func clock and the DES HDCP
>>> clock, but the HWMOD framework only allows one mainclock.
>>>
>>> I added the HDCP clock as an opt clock, but those are not enabled
>>> intially by the HWMOD framework, and the call in omap_hwmod.c:_enable()
>>> to soc_ops.wait_target_ready(oh) calls fails.
>>>
>>> So... Any ideas how to proceed?
>>
>> Add the clock enable at the end of dra7xx_dt_clk_init()?
>>
>> You need to disable the clock at some point though.
>
> Where would I disable it? And if the clock is disabled, doesn't this
> again fail when the dss driver tries to enable the IP block? The driver
> can enable the HDCP opt clock only later, when the IP block should be up
> already.

I guess in the display driver itself.

-Tero