* [PATCH 1/4] arm64: dts: juno/fast models: using GIC macros instead of hardcoded values
@ 2019-01-25 17:56 Sudeep Holla
2019-01-25 17:56 ` [PATCH 2/4] arm64: dts: models: use list instead of tuple for mmci interrupts Sudeep Holla
` (3 more replies)
0 siblings, 4 replies; 7+ messages in thread
From: Sudeep Holla @ 2019-01-25 17:56 UTC (permalink / raw)
To: linux-arm-kernel; +Cc: devicetree, Liviu Dudau, Sudeep Holla
There are macros that exist to indicate the GIC specific flags and
custom cell values as per the GIC DT bindings. It's used in most of the
places in these DTS files but not all. To maintain consistency, lets
use the macros at all the places.
Since DTC doesn't even warn is any cells are missing, it's very hard to
debug if that's the case. Changing to use macros avoids missing cells/
columns.
Cc: Liviu Dudau <liviu.dudau@arm.com>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
---
.../boot/dts/arm/foundation-v8-gicv2.dtsi | 2 +-
.../boot/dts/arm/foundation-v8-gicv3.dtsi | 2 +-
arch/arm64/boot/dts/arm/foundation-v8.dtsi | 106 +++++++++---------
arch/arm64/boot/dts/arm/juno-base.dtsi | 38 +++----
arch/arm64/boot/dts/arm/rtsm_ve-aemv8a.dts | 106 +++++++++---------
5 files changed, 129 insertions(+), 125 deletions(-)
Hi,
Found this annoying when someone making use of motherboard.dtsi to
support new platform missed the parent address cells for gic. None of
the motherboard interrupts were working. So to avoid the same issue
happening in future, moved them to use macros that is quite easy to
follow.
Regards,
Sudeep
diff --git a/arch/arm64/boot/dts/arm/foundation-v8-gicv2.dtsi b/arch/arm64/boot/dts/arm/foundation-v8-gicv2.dtsi
index 851abf34fc80..15fe81738e94 100644
--- a/arch/arm64/boot/dts/arm/foundation-v8-gicv2.dtsi
+++ b/arch/arm64/boot/dts/arm/foundation-v8-gicv2.dtsi
@@ -14,6 +14,6 @@
<0x0 0x2c002000 0 0x2000>,
<0x0 0x2c004000 0 0x2000>,
<0x0 0x2c006000 0 0x2000>;
- interrupts = <1 9 0xf04>;
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
};
};
diff --git a/arch/arm64/boot/dts/arm/foundation-v8-gicv3.dtsi b/arch/arm64/boot/dts/arm/foundation-v8-gicv3.dtsi
index 91fc5c60d88b..f2c75c756039 100644
--- a/arch/arm64/boot/dts/arm/foundation-v8-gicv3.dtsi
+++ b/arch/arm64/boot/dts/arm/foundation-v8-gicv3.dtsi
@@ -17,7 +17,7 @@
<0x0 0x2c000000 0x0 0x2000>,
<0x0 0x2c010000 0x0 0x2000>,
<0x0 0x2c02f000 0x0 0x2000>;
- interrupts = <1 9 4>;
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
its: its@2f020000 {
compatible = "arm,gic-v3-its";
diff --git a/arch/arm64/boot/dts/arm/foundation-v8.dtsi b/arch/arm64/boot/dts/arm/foundation-v8.dtsi
index e080277d27ae..3f78373f708a 100644
--- a/arch/arm64/boot/dts/arm/foundation-v8.dtsi
+++ b/arch/arm64/boot/dts/arm/foundation-v8.dtsi
@@ -7,6 +7,8 @@
/dts-v1/;
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
/memreserve/ 0x80000000 0x00010000;
/ {
@@ -67,26 +69,26 @@
timer {
compatible = "arm,armv8-timer";
- interrupts = <1 13 0xf08>,
- <1 14 0xf08>,
- <1 11 0xf08>,
- <1 10 0xf08>;
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
clock-frequency = <100000000>;
};
pmu {
compatible = "arm,armv8-pmuv3";
- interrupts = <0 60 4>,
- <0 61 4>,
- <0 62 4>,
- <0 63 4>;
+ interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
};
watchdog@2a440000 {
compatible = "arm,sbsa-gwdt";
reg = <0x0 0x2a440000 0 0x1000>,
<0x0 0x2a450000 0 0x1000>;
- interrupts = <0 27 4>;
+ interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
timeout-sec = <30>;
};
@@ -105,49 +107,49 @@
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 63>;
- interrupt-map = <0 0 0 &gic 0 0 0 0 4>,
- <0 0 1 &gic 0 0 0 1 4>,
- <0 0 2 &gic 0 0 0 2 4>,
- <0 0 3 &gic 0 0 0 3 4>,
- <0 0 4 &gic 0 0 0 4 4>,
- <0 0 5 &gic 0 0 0 5 4>,
- <0 0 6 &gic 0 0 0 6 4>,
- <0 0 7 &gic 0 0 0 7 4>,
- <0 0 8 &gic 0 0 0 8 4>,
- <0 0 9 &gic 0 0 0 9 4>,
- <0 0 10 &gic 0 0 0 10 4>,
- <0 0 11 &gic 0 0 0 11 4>,
- <0 0 12 &gic 0 0 0 12 4>,
- <0 0 13 &gic 0 0 0 13 4>,
- <0 0 14 &gic 0 0 0 14 4>,
- <0 0 15 &gic 0 0 0 15 4>,
- <0 0 16 &gic 0 0 0 16 4>,
- <0 0 17 &gic 0 0 0 17 4>,
- <0 0 18 &gic 0 0 0 18 4>,
- <0 0 19 &gic 0 0 0 19 4>,
- <0 0 20 &gic 0 0 0 20 4>,
- <0 0 21 &gic 0 0 0 21 4>,
- <0 0 22 &gic 0 0 0 22 4>,
- <0 0 23 &gic 0 0 0 23 4>,
- <0 0 24 &gic 0 0 0 24 4>,
- <0 0 25 &gic 0 0 0 25 4>,
- <0 0 26 &gic 0 0 0 26 4>,
- <0 0 27 &gic 0 0 0 27 4>,
- <0 0 28 &gic 0 0 0 28 4>,
- <0 0 29 &gic 0 0 0 29 4>,
- <0 0 30 &gic 0 0 0 30 4>,
- <0 0 31 &gic 0 0 0 31 4>,
- <0 0 32 &gic 0 0 0 32 4>,
- <0 0 33 &gic 0 0 0 33 4>,
- <0 0 34 &gic 0 0 0 34 4>,
- <0 0 35 &gic 0 0 0 35 4>,
- <0 0 36 &gic 0 0 0 36 4>,
- <0 0 37 &gic 0 0 0 37 4>,
- <0 0 38 &gic 0 0 0 38 4>,
- <0 0 39 &gic 0 0 0 39 4>,
- <0 0 40 &gic 0 0 0 40 4>,
- <0 0 41 &gic 0 0 0 41 4>,
- <0 0 42 &gic 0 0 0 42 4>;
+ interrupt-map = <0 0 0 &gic 0 0 GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 1 &gic 0 0 GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 2 &gic 0 0 GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 3 &gic 0 0 GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 4 &gic 0 0 GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 5 &gic 0 0 GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 6 &gic 0 0 GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 7 &gic 0 0 GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 8 &gic 0 0 GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 9 &gic 0 0 GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 10 &gic 0 0 GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 11 &gic 0 0 GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 12 &gic 0 0 GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 13 &gic 0 0 GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 14 &gic 0 0 GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 15 &gic 0 0 GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 16 &gic 0 0 GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 17 &gic 0 0 GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 18 &gic 0 0 GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 19 &gic 0 0 GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 20 &gic 0 0 GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 21 &gic 0 0 GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 22 &gic 0 0 GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 23 &gic 0 0 GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 24 &gic 0 0 GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 25 &gic 0 0 GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 26 &gic 0 0 GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 27 &gic 0 0 GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 28 &gic 0 0 GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 29 &gic 0 0 GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 30 &gic 0 0 GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 31 &gic 0 0 GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 32 &gic 0 0 GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 33 &gic 0 0 GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 34 &gic 0 0 GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 35 &gic 0 0 GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 36 &gic 0 0 GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 37 &gic 0 0 GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 38 &gic 0 0 GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 39 &gic 0 0 GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 40 &gic 0 0 GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 41 &gic 0 0 GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 42 &gic 0 0 GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
ethernet@2,02000000 {
compatible = "smsc,lan91c111";
diff --git a/arch/arm64/boot/dts/arm/juno-base.dtsi b/arch/arm64/boot/dts/arm/juno-base.dtsi
index ed774ee8f659..3a72c04247cb 100644
--- a/arch/arm64/boot/dts/arm/juno-base.dtsi
+++ b/arch/arm64/boot/dts/arm/juno-base.dtsi
@@ -18,7 +18,7 @@
status = "disabled";
frame@2a830000 {
frame-number = <1>;
- interrupts = <0 60 4>;
+ interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x0 0x2a830000 0x0 0x10000>;
};
};
@@ -520,10 +520,10 @@
<0x42000000 0x40 0x00000000 0x40 0x00000000 0x1 0x00000000>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
- interrupt-map = <0 0 0 1 &gic 0 0 0 136 4>,
- <0 0 0 2 &gic 0 0 0 137 4>,
- <0 0 0 3 &gic 0 0 0 138 4>,
- <0 0 0 4 &gic 0 0 0 139 4>;
+ interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 2 &gic 0 0 GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 3 &gic 0 0 GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 4 &gic 0 0 GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
msi-parent = <&v2m_0>;
status = "disabled";
iommu-map-mask = <0x0>; /* RC has no means to output PCI RID */
@@ -787,19 +787,19 @@
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 15>;
- interrupt-map = <0 0 0 &gic 0 0 0 68 IRQ_TYPE_LEVEL_HIGH>,
- <0 0 1 &gic 0 0 0 69 IRQ_TYPE_LEVEL_HIGH>,
- <0 0 2 &gic 0 0 0 70 IRQ_TYPE_LEVEL_HIGH>,
- <0 0 3 &gic 0 0 0 160 IRQ_TYPE_LEVEL_HIGH>,
- <0 0 4 &gic 0 0 0 161 IRQ_TYPE_LEVEL_HIGH>,
- <0 0 5 &gic 0 0 0 162 IRQ_TYPE_LEVEL_HIGH>,
- <0 0 6 &gic 0 0 0 163 IRQ_TYPE_LEVEL_HIGH>,
- <0 0 7 &gic 0 0 0 164 IRQ_TYPE_LEVEL_HIGH>,
- <0 0 8 &gic 0 0 0 165 IRQ_TYPE_LEVEL_HIGH>,
- <0 0 9 &gic 0 0 0 166 IRQ_TYPE_LEVEL_HIGH>,
- <0 0 10 &gic 0 0 0 167 IRQ_TYPE_LEVEL_HIGH>,
- <0 0 11 &gic 0 0 0 168 IRQ_TYPE_LEVEL_HIGH>,
- <0 0 12 &gic 0 0 0 169 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-map = <0 0 0 &gic 0 0 GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 1 &gic 0 0 GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 2 &gic 0 0 GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 3 &gic 0 0 GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 4 &gic 0 0 GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 5 &gic 0 0 GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 6 &gic 0 0 GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 7 &gic 0 0 GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 8 &gic 0 0 GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 9 &gic 0 0 GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 10 &gic 0 0 GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 11 &gic 0 0 GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 12 &gic 0 0 GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
};
site2: tlx@60000000 {
@@ -809,6 +809,6 @@
ranges = <0 0 0x60000000 0x10000000>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0>;
- interrupt-map = <0 0 &gic 0 0 0 168 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-map = <0 0 &gic 0 0 GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
};
};
diff --git a/arch/arm64/boot/dts/arm/rtsm_ve-aemv8a.dts b/arch/arm64/boot/dts/arm/rtsm_ve-aemv8a.dts
index fe4fda473c0a..6e685d883303 100644
--- a/arch/arm64/boot/dts/arm/rtsm_ve-aemv8a.dts
+++ b/arch/arm64/boot/dts/arm/rtsm_ve-aemv8a.dts
@@ -10,6 +10,8 @@
/dts-v1/;
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
/memreserve/ 0x80000000 0x00010000;
#include "rtsm_ve-motherboard.dtsi"
@@ -101,24 +103,24 @@
<0x0 0x2c002000 0 0x2000>,
<0x0 0x2c004000 0 0x2000>,
<0x0 0x2c006000 0 0x2000>;
- interrupts = <1 9 0xf04>;
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
};
timer {
compatible = "arm,armv8-timer";
- interrupts = <1 13 0xf08>,
- <1 14 0xf08>,
- <1 11 0xf08>,
- <1 10 0xf08>;
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
clock-frequency = <100000000>;
};
pmu {
compatible = "arm,armv8-pmuv3";
- interrupts = <0 60 4>,
- <0 61 4>,
- <0 62 4>,
- <0 63 4>;
+ interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
};
panel {
@@ -144,48 +146,48 @@
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 63>;
- interrupt-map = <0 0 0 &gic 0 0 4>,
- <0 0 1 &gic 0 1 4>,
- <0 0 2 &gic 0 2 4>,
- <0 0 3 &gic 0 3 4>,
- <0 0 4 &gic 0 4 4>,
- <0 0 5 &gic 0 5 4>,
- <0 0 6 &gic 0 6 4>,
- <0 0 7 &gic 0 7 4>,
- <0 0 8 &gic 0 8 4>,
- <0 0 9 &gic 0 9 4>,
- <0 0 10 &gic 0 10 4>,
- <0 0 11 &gic 0 11 4>,
- <0 0 12 &gic 0 12 4>,
- <0 0 13 &gic 0 13 4>,
- <0 0 14 &gic 0 14 4>,
- <0 0 15 &gic 0 15 4>,
- <0 0 16 &gic 0 16 4>,
- <0 0 17 &gic 0 17 4>,
- <0 0 18 &gic 0 18 4>,
- <0 0 19 &gic 0 19 4>,
- <0 0 20 &gic 0 20 4>,
- <0 0 21 &gic 0 21 4>,
- <0 0 22 &gic 0 22 4>,
- <0 0 23 &gic 0 23 4>,
- <0 0 24 &gic 0 24 4>,
- <0 0 25 &gic 0 25 4>,
- <0 0 26 &gic 0 26 4>,
- <0 0 27 &gic 0 27 4>,
- <0 0 28 &gic 0 28 4>,
- <0 0 29 &gic 0 29 4>,
- <0 0 30 &gic 0 30 4>,
- <0 0 31 &gic 0 31 4>,
- <0 0 32 &gic 0 32 4>,
- <0 0 33 &gic 0 33 4>,
- <0 0 34 &gic 0 34 4>,
- <0 0 35 &gic 0 35 4>,
- <0 0 36 &gic 0 36 4>,
- <0 0 37 &gic 0 37 4>,
- <0 0 38 &gic 0 38 4>,
- <0 0 39 &gic 0 39 4>,
- <0 0 40 &gic 0 40 4>,
- <0 0 41 &gic 0 41 4>,
- <0 0 42 &gic 0 42 4>;
+ interrupt-map = <0 0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 1 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 2 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 3 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 4 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 5 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 6 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 7 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 8 &gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 9 &gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 10 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 11 &gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 12 &gic GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 13 &gic GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 14 &gic GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 15 &gic GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 16 &gic GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 17 &gic GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 18 &gic GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 19 &gic GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 20 &gic GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 21 &gic GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 22 &gic GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 23 &gic GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 24 &gic GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 25 &gic GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 26 &gic GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 27 &gic GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 28 &gic GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 29 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 30 &gic GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 31 &gic GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 32 &gic GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 33 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 34 &gic GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 35 &gic GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 36 &gic GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 37 &gic GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 38 &gic GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 39 &gic GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 40 &gic GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 41 &gic GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 42 &gic GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
};
};
--
2.17.1
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^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH 2/4] arm64: dts: models: use list instead of tuple for mmci interrupts
2019-01-25 17:56 [PATCH 1/4] arm64: dts: juno/fast models: using GIC macros instead of hardcoded values Sudeep Holla
@ 2019-01-25 17:56 ` Sudeep Holla
2019-01-28 10:37 ` Vladimir Murzin
2019-01-29 14:35 ` Liviu Dudau
2019-01-25 17:56 ` [PATCH 3/4] arm64: dts: juno/fast models: sort couple of device nodes Sudeep Holla
` (2 subsequent siblings)
3 siblings, 2 replies; 7+ messages in thread
From: Sudeep Holla @ 2019-01-25 17:56 UTC (permalink / raw)
To: linux-arm-kernel; +Cc: devicetree, Liviu Dudau, Sudeep Holla
RTSM/FVP vexpress motherboard model MMCI requires dedicated interrupts
for CMD and PIO, which obviously should be expressed as a list. Current
form uses tuple and it works fine since interrupt-cells equal to 1.
Cc: Liviu Dudau <liviu.dudau@arm.com>
Reported-by: Vladimir Murzin <vladimir.murzin@arm.com>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
---
arch/arm64/boot/dts/arm/rtsm_ve-motherboard.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/arm/rtsm_ve-motherboard.dtsi b/arch/arm64/boot/dts/arm/rtsm_ve-motherboard.dtsi
index b25f3cbd3da8..102e93744edc 100644
--- a/arch/arm64/boot/dts/arm/rtsm_ve-motherboard.dtsi
+++ b/arch/arm64/boot/dts/arm/rtsm_ve-motherboard.dtsi
@@ -86,7 +86,7 @@
mmci@50000 {
compatible = "arm,pl180", "arm,primecell";
reg = <0x050000 0x1000>;
- interrupts = <9 10>;
+ interrupts = <9>, <10>;
cd-gpios = <&v2m_sysreg 0 0>;
wp-gpios = <&v2m_sysreg 1 0>;
max-frequency = <12000000>;
--
2.17.1
_______________________________________________
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^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH 3/4] arm64: dts: juno/fast models: sort couple of device nodes
2019-01-25 17:56 [PATCH 1/4] arm64: dts: juno/fast models: using GIC macros instead of hardcoded values Sudeep Holla
2019-01-25 17:56 ` [PATCH 2/4] arm64: dts: models: use list instead of tuple for mmci interrupts Sudeep Holla
@ 2019-01-25 17:56 ` Sudeep Holla
2019-01-25 17:56 ` [PATCH 4/4] arm64: dts: fast models: Add DTS fo Base RevC FVP Sudeep Holla
2019-01-29 14:00 ` [PATCH 1/4] arm64: dts: juno/fast models: using GIC macros instead of hardcoded values Liviu Dudau
3 siblings, 0 replies; 7+ messages in thread
From: Sudeep Holla @ 2019-01-25 17:56 UTC (permalink / raw)
To: linux-arm-kernel; +Cc: devicetree, Liviu Dudau, Sudeep Holla
Sort the couple device nodes with unit addresses which are out of order.
Cc: Liviu Dudau <liviu.dudau@arm.com>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
---
arch/arm64/boot/dts/arm/juno-base.dtsi | 70 +++++++++----------
.../boot/dts/arm/rtsm_ve-motherboard.dtsi | 12 ++--
2 files changed, 41 insertions(+), 41 deletions(-)
diff --git a/arch/arm64/boot/dts/arm/juno-base.dtsi b/arch/arm64/boot/dts/arm/juno-base.dtsi
index 3a72c04247cb..7446e0dc154d 100644
--- a/arch/arm64/boot/dts/arm/juno-base.dtsi
+++ b/arch/arm64/boot/dts/arm/juno-base.dtsi
@@ -220,6 +220,41 @@
};
};
+ replicator@20120000 {
+ compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
+ reg = <0 0x20120000 0 0x1000>;
+
+ clocks = <&soc_smc50mhz>;
+ clock-names = "apb_pclk";
+ power-domains = <&scpi_devpd 0>;
+
+ out-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* replicator output ports */
+ port@0 {
+ reg = <0>;
+ replicator_out_port0: endpoint {
+ remote-endpoint = <&tpiu_in_port>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ replicator_out_port1: endpoint {
+ remote-endpoint = <&etr_in_port>;
+ };
+ };
+ };
+ in-ports {
+ port {
+ replicator_in_port0: endpoint {
+ };
+ };
+ };
+ };
+
cpu_debug0: cpu-debug@22010000 {
compatible = "arm,coresight-cpu-debug", "arm,primecell";
reg = <0x0 0x22010000 0x0 0x1000>;
@@ -452,41 +487,6 @@
};
};
- replicator@20120000 {
- compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
- reg = <0 0x20120000 0 0x1000>;
-
- clocks = <&soc_smc50mhz>;
- clock-names = "apb_pclk";
- power-domains = <&scpi_devpd 0>;
-
- out-ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- /* replicator output ports */
- port@0 {
- reg = <0>;
- replicator_out_port0: endpoint {
- remote-endpoint = <&tpiu_in_port>;
- };
- };
-
- port@1 {
- reg = <1>;
- replicator_out_port1: endpoint {
- remote-endpoint = <&etr_in_port>;
- };
- };
- };
- in-ports {
- port {
- replicator_in_port0: endpoint {
- };
- };
- };
- };
-
sram: sram@2e000000 {
compatible = "arm,juno-sram-ns", "mmio-sram";
reg = <0x0 0x2e000000 0x0 0x8000>;
diff --git a/arch/arm64/boot/dts/arm/rtsm_ve-motherboard.dtsi b/arch/arm64/boot/dts/arm/rtsm_ve-motherboard.dtsi
index 102e93744edc..454cf6c44c49 100644
--- a/arch/arm64/boot/dts/arm/rtsm_ve-motherboard.dtsi
+++ b/arch/arm64/boot/dts/arm/rtsm_ve-motherboard.dtsi
@@ -167,6 +167,12 @@
clock-names = "timclken1", "timclken2", "apb_pclk";
};
+ virtio-block@130000 {
+ compatible = "virtio,mmio";
+ reg = <0x130000 0x200>;
+ interrupts = <42>;
+ };
+
rtc@170000 {
compatible = "arm,pl031", "arm,primecell";
reg = <0x170000 0x1000>;
@@ -193,12 +199,6 @@
};
};
};
-
- virtio-block@130000 {
- compatible = "virtio,mmio";
- reg = <0x130000 0x200>;
- interrupts = <42>;
- };
};
v2m_fixed_3v3: v2m-3v3 {
--
2.17.1
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^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH 4/4] arm64: dts: fast models: Add DTS fo Base RevC FVP
2019-01-25 17:56 [PATCH 1/4] arm64: dts: juno/fast models: using GIC macros instead of hardcoded values Sudeep Holla
2019-01-25 17:56 ` [PATCH 2/4] arm64: dts: models: use list instead of tuple for mmci interrupts Sudeep Holla
2019-01-25 17:56 ` [PATCH 3/4] arm64: dts: juno/fast models: sort couple of device nodes Sudeep Holla
@ 2019-01-25 17:56 ` Sudeep Holla
2019-01-29 14:00 ` [PATCH 1/4] arm64: dts: juno/fast models: using GIC macros instead of hardcoded values Liviu Dudau
3 siblings, 0 replies; 7+ messages in thread
From: Sudeep Holla @ 2019-01-25 17:56 UTC (permalink / raw)
To: linux-arm-kernel
Cc: Jean-Philippe Brucker, devicetree, Vincent Stehlé,
Liviu Dudau, Sudeep Holla
From: Jean-Philippe Brucker <jean-philippe.brucker@arm.com>
Fixed Virtual Platforms(FVP) Base RevC model is an emulated Arm platform
with GICv3, PCIe, SMMUv3 and various other features. These are available
free of charge on the Arm Community website at Arm Development
Platforms[1].
It resembles the Foundation Platform, which is a simple FVP that
includes an Armv8‑A AEM processor model but this has two cluster of four
cores, a CCI-550 interconnect, an SMMU and two PCI devices.
In order to enable development of software, let's add a description of
the Revison C version of Base platform.
The documentation for this FVP model is available @[2] for reference.
[1] https://community.arm.com/dev-platforms/
[2] https://static.docs.arm.com/100966/1104/fast_models_fvp_rg_100966_1104_00_en.pdf
Cc: Vincent Stehlé <vincent.stehle@arm.com>
Cc: Liviu Dudau <liviu.dudau@arm.com>
Signed-off-by: Jean-Philippe Brucker <jean-philippe.brucker@arm.com>
[sudeep.holla: aligned interrupt-map with other DTS, added SPE, changed
PMU to use GIC PPI, commit log rewording]
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
---
arch/arm64/boot/dts/arm/Makefile | 1 +
arch/arm64/boot/dts/arm/fvp-base-revc.dts | 280 ++++++++++++++++++
.../boot/dts/arm/rtsm_ve-motherboard-rs2.dtsi | 27 ++
3 files changed, 308 insertions(+)
create mode 100644 arch/arm64/boot/dts/arm/fvp-base-revc.dts
create mode 100644 arch/arm64/boot/dts/arm/rtsm_ve-motherboard-rs2.dtsi
diff --git a/arch/arm64/boot/dts/arm/Makefile b/arch/arm64/boot/dts/arm/Makefile
index 5b45144b371a..800da2e84f3f 100644
--- a/arch/arm64/boot/dts/arm/Makefile
+++ b/arch/arm64/boot/dts/arm/Makefile
@@ -5,3 +5,4 @@ dtb-$(CONFIG_ARCH_VEXPRESS) += \
dtb-$(CONFIG_ARCH_VEXPRESS) += juno.dtb juno-r1.dtb juno-r2.dtb
dtb-$(CONFIG_ARCH_VEXPRESS) += rtsm_ve-aemv8a.dtb
dtb-$(CONFIG_ARCH_VEXPRESS) += vexpress-v2f-1xv7-ca53x2.dtb
+dtb-$(CONFIG_ARCH_VEXPRESS) += fvp-base-revc.dtb
diff --git a/arch/arm64/boot/dts/arm/fvp-base-revc.dts b/arch/arm64/boot/dts/arm/fvp-base-revc.dts
new file mode 100644
index 000000000000..1aa37f0bfc62
--- /dev/null
+++ b/arch/arm64/boot/dts/arm/fvp-base-revc.dts
@@ -0,0 +1,280 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * ARM Ltd. Fast Models
+ *
+ * Architecture Envelope Model (AEM) ARMv8-A
+ * ARMAEMv8AMPCT
+ *
+ * FVP Base RevC
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/memreserve/ 0x80000000 0x00010000;
+
+#include "rtsm_ve-motherboard.dtsi"
+#include "rtsm_ve-motherboard-rs2.dtsi"
+
+/ {
+ model = "FVP Base RevC";
+ compatible = "arm,fvp-base-revc", "arm,vexpress";
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ chosen { };
+
+ aliases {
+ serial0 = &v2m_serial0;
+ serial1 = &v2m_serial1;
+ serial2 = &v2m_serial2;
+ serial3 = &v2m_serial3;
+ };
+
+ psci {
+ compatible = "arm,psci";
+ method = "smc";
+ cpu_suspend = <0x84000000>;
+ cpu_off = <0x84000001>;
+ cpu_on = <0x84000002>;
+ };
+
+ cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x0 0x000>;
+ enable-method = "psci";
+ };
+ cpu1: cpu@100 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x0 0x100>;
+ enable-method = "psci";
+ };
+ cpu2: cpu@200 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x0 0x200>;
+ enable-method = "psci";
+ };
+ cpu3: cpu@300 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x0 0x300>;
+ enable-method = "psci";
+ };
+ cpu4: cpu@10000 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x0 0x10000>;
+ enable-method = "psci";
+ };
+ cpu5: cpu@10100 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x0 0x10100>;
+ enable-method = "psci";
+ };
+ cpu6: cpu@10200 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x0 0x10200>;
+ enable-method = "psci";
+ };
+ cpu7: cpu@10300 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x0 0x10300>;
+ enable-method = "psci";
+ };
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x00000000 0x80000000 0 0x80000000>,
+ <0x00000008 0x80000000 0 0x80000000>;
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ /* Chipselect 2,00000000 is physically at 0x18000000 */
+ vram: vram@18000000 {
+ /* 8 MB of designated video RAM */
+ compatible = "shared-dma-pool";
+ reg = <0x00000000 0x18000000 0 0x00800000>;
+ no-map;
+ };
+ };
+
+ gic: interrupt-controller@2f000000 {
+ compatible = "arm,gic-v3";
+ #interrupt-cells = <3>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ interrupt-controller;
+ reg = <0x0 0x2f000000 0 0x10000>, // GICD
+ <0x0 0x2f100000 0 0x200000>, // GICR
+ <0x0 0x2c000000 0 0x2000>, // GICC
+ <0x0 0x2c010000 0 0x2000>, // GICH
+ <0x0 0x2c02f000 0 0x2000>; // GICV
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+
+ its: its@2f020000 {
+ #msi-cells = <1>;
+ compatible = "arm,gic-v3-its";
+ reg = <0x0 0x2f020000 0x0 0x20000>; // GITS
+ msi-controller;
+ };
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
+ };
+
+ pmu {
+ compatible = "arm,armv8-pmuv3";
+ interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ spe-pmu {
+ compatible = "arm,statistical-profiling-extension-v1";
+ interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ pci: pci@40000000 {
+ #address-cells = <0x3>;
+ #size-cells = <0x2>;
+ #interrupt-cells = <0x1>;
+ compatible = "pci-host-ecam-generic";
+ device_type = "pci";
+ bus-range = <0x0 0x1>;
+ reg = <0x0 0x40000000 0x0 0x10000000>;
+ ranges = <0x2000000 0x0 0x50000000 0x0 0x50000000 0x0 0x10000000>;
+ interrupt-map = <0 0 0 1 &gic GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 2 &gic GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 3 &gic GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 4 &gic GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-map-mask = <0x0 0x0 0x0 0x7>;
+ msi-map = <0x0 &its 0x0 0x10000>;
+ iommu-map = <0x0 &smmu 0x0 0x10000>;
+
+ dma-coherent;
+ };
+
+ smmu: smmu@2b400000 {
+ compatible = "arm,smmu-v3";
+ reg = <0x0 0x2b400000 0x0 0x100000>;
+ interrupts = <GIC_SPI 74 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 77 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "eventq", "priq", "cmdq-sync", "gerror";
+ dma-coherent;
+ #iommu-cells = <1>;
+ msi-parent = <&its 0x10000>;
+ };
+
+ panel {
+ compatible = "arm,rtsm-display", "panel-dpi";
+ port {
+ panel_in: endpoint {
+ remote-endpoint = <&clcd_pads>;
+ };
+ };
+
+ panel-timing {
+ clock-frequency = <63500127>;
+ hactive = <1024>;
+ hback-porch = <152>;
+ hfront-porch = <48>;
+ hsync-len = <104>;
+ vactive = <768>;
+ vback-porch = <23>;
+ vfront-porch = <3>;
+ vsync-len = <4>;
+ };
+ };
+
+ smb@8000000 {
+ compatible = "simple-bus";
+
+ #address-cells = <2>;
+ #size-cells = <1>;
+ ranges = <0 0 0 0x08000000 0x04000000>,
+ <1 0 0 0x14000000 0x04000000>,
+ <2 0 0 0x18000000 0x04000000>,
+ <3 0 0 0x1c000000 0x04000000>,
+ <4 0 0 0x0c000000 0x04000000>,
+ <5 0 0 0x10000000 0x04000000>;
+
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 63>;
+ interrupt-map = <0 0 0 &gic 0 0 GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 1 &gic 0 0 GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 2 &gic 0 0 GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 3 &gic 0 0 GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 4 &gic 0 0 GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 5 &gic 0 0 GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 6 &gic 0 0 GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 7 &gic 0 0 GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 8 &gic 0 0 GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 9 &gic 0 0 GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 10 &gic 0 0 GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 11 &gic 0 0 GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 12 &gic 0 0 GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 13 &gic 0 0 GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 14 &gic 0 0 GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 15 &gic 0 0 GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 16 &gic 0 0 GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 17 &gic 0 0 GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 18 &gic 0 0 GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 19 &gic 0 0 GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 20 &gic 0 0 GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 21 &gic 0 0 GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 22 &gic 0 0 GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 23 &gic 0 0 GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 24 &gic 0 0 GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 25 &gic 0 0 GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 26 &gic 0 0 GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 27 &gic 0 0 GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 28 &gic 0 0 GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 29 &gic 0 0 GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 30 &gic 0 0 GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 31 &gic 0 0 GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 32 &gic 0 0 GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 33 &gic 0 0 GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 34 &gic 0 0 GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 35 &gic 0 0 GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 36 &gic 0 0 GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 37 &gic 0 0 GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 38 &gic 0 0 GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 39 &gic 0 0 GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 40 &gic 0 0 GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 41 &gic 0 0 GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 42 &gic 0 0 GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 43 &gic 0 0 GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 44 &gic 0 0 GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
+
+ motherboard {
+ iofpga@3,00000000 {
+ clcd@1f0000 {
+ max-memory-bandwidth = <130000000>; /* 16bpp @ 63.5MHz */
+ };
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/arm/rtsm_ve-motherboard-rs2.dtsi b/arch/arm64/boot/dts/arm/rtsm_ve-motherboard-rs2.dtsi
new file mode 100644
index 000000000000..57b0b9d7f3fa
--- /dev/null
+++ b/arch/arm64/boot/dts/arm/rtsm_ve-motherboard-rs2.dtsi
@@ -0,0 +1,27 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * ARM Ltd. Fast Models
+ *
+ * "rs2" extension for the v2m motherboard
+ */
+/ {
+ smb@8000000 {
+ motherboard {
+ arm,v2m-memory-map = "rs2";
+
+ iofpga@3,00000000 {
+ virtio-p9@140000 {
+ compatible = "virtio,mmio";
+ reg = <0x140000 0x200>;
+ interrupts = <43>;
+ };
+
+ virtio-net@150000 {
+ compatible = "virtio,mmio";
+ reg = <0x150000 0x200>;
+ interrupts = <44>;
+ };
+ };
+ };
+ };
+};
--
2.17.1
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^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH 2/4] arm64: dts: models: use list instead of tuple for mmci interrupts
2019-01-25 17:56 ` [PATCH 2/4] arm64: dts: models: use list instead of tuple for mmci interrupts Sudeep Holla
@ 2019-01-28 10:37 ` Vladimir Murzin
2019-01-29 14:35 ` Liviu Dudau
1 sibling, 0 replies; 7+ messages in thread
From: Vladimir Murzin @ 2019-01-28 10:37 UTC (permalink / raw)
To: Sudeep Holla, linux-arm-kernel; +Cc: devicetree, Liviu Dudau
On 1/25/19 5:56 PM, Sudeep Holla wrote:
> RTSM/FVP vexpress motherboard model MMCI requires dedicated interrupts
> for CMD and PIO, which obviously should be expressed as a list. Current
> form uses tuple and it works fine since interrupt-cells equal to 1.
>
> Cc: Liviu Dudau <liviu.dudau@arm.com>
> Reported-by: Vladimir Murzin <vladimir.murzin@arm.com>
> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
> ---
> arch/arm64/boot/dts/arm/rtsm_ve-motherboard.dtsi | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm64/boot/dts/arm/rtsm_ve-motherboard.dtsi b/arch/arm64/boot/dts/arm/rtsm_ve-motherboard.dtsi
> index b25f3cbd3da8..102e93744edc 100644
> --- a/arch/arm64/boot/dts/arm/rtsm_ve-motherboard.dtsi
> +++ b/arch/arm64/boot/dts/arm/rtsm_ve-motherboard.dtsi
> @@ -86,7 +86,7 @@
> mmci@50000 {
> compatible = "arm,pl180", "arm,primecell";
> reg = <0x050000 0x1000>;
> - interrupts = <9 10>;
> + interrupts = <9>, <10>;
> cd-gpios = <&v2m_sysreg 0 0>;
> wp-gpios = <&v2m_sysreg 1 0>;
> max-frequency = <12000000>;
>
FWIW
Reviewed-by: Vladimir Murzin <vladimir.murzin@arm.com>
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^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 1/4] arm64: dts: juno/fast models: using GIC macros instead of hardcoded values
2019-01-25 17:56 [PATCH 1/4] arm64: dts: juno/fast models: using GIC macros instead of hardcoded values Sudeep Holla
` (2 preceding siblings ...)
2019-01-25 17:56 ` [PATCH 4/4] arm64: dts: fast models: Add DTS fo Base RevC FVP Sudeep Holla
@ 2019-01-29 14:00 ` Liviu Dudau
3 siblings, 0 replies; 7+ messages in thread
From: Liviu Dudau @ 2019-01-29 14:00 UTC (permalink / raw)
To: Sudeep Holla; +Cc: devicetree, linux-arm-kernel
On Fri, Jan 25, 2019 at 05:56:03PM +0000, Sudeep Holla wrote:
> There are macros that exist to indicate the GIC specific flags and
> custom cell values as per the GIC DT bindings. It's used in most of the
> places in these DTS files but not all. To maintain consistency, lets
> use the macros at all the places.
>
> Since DTC doesn't even warn is any cells are missing, it's very hard to
> debug if that's the case. Changing to use macros avoids missing cells/
> columns.
>
> Cc: Liviu Dudau <liviu.dudau@arm.com>
Acked-by: Liviu Dudau <liviu.dudau@arm.com>
Thanks!
Liviu
> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
> ---
> .../boot/dts/arm/foundation-v8-gicv2.dtsi | 2 +-
> .../boot/dts/arm/foundation-v8-gicv3.dtsi | 2 +-
> arch/arm64/boot/dts/arm/foundation-v8.dtsi | 106 +++++++++---------
> arch/arm64/boot/dts/arm/juno-base.dtsi | 38 +++----
> arch/arm64/boot/dts/arm/rtsm_ve-aemv8a.dts | 106 +++++++++---------
> 5 files changed, 129 insertions(+), 125 deletions(-)
>
> Hi,
>
> Found this annoying when someone making use of motherboard.dtsi to
> support new platform missed the parent address cells for gic. None of
> the motherboard interrupts were working. So to avoid the same issue
> happening in future, moved them to use macros that is quite easy to
> follow.
>
> Regards,
> Sudeep
>
> diff --git a/arch/arm64/boot/dts/arm/foundation-v8-gicv2.dtsi b/arch/arm64/boot/dts/arm/foundation-v8-gicv2.dtsi
> index 851abf34fc80..15fe81738e94 100644
> --- a/arch/arm64/boot/dts/arm/foundation-v8-gicv2.dtsi
> +++ b/arch/arm64/boot/dts/arm/foundation-v8-gicv2.dtsi
> @@ -14,6 +14,6 @@
> <0x0 0x2c002000 0 0x2000>,
> <0x0 0x2c004000 0 0x2000>,
> <0x0 0x2c006000 0 0x2000>;
> - interrupts = <1 9 0xf04>;
> + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
> };
> };
> diff --git a/arch/arm64/boot/dts/arm/foundation-v8-gicv3.dtsi b/arch/arm64/boot/dts/arm/foundation-v8-gicv3.dtsi
> index 91fc5c60d88b..f2c75c756039 100644
> --- a/arch/arm64/boot/dts/arm/foundation-v8-gicv3.dtsi
> +++ b/arch/arm64/boot/dts/arm/foundation-v8-gicv3.dtsi
> @@ -17,7 +17,7 @@
> <0x0 0x2c000000 0x0 0x2000>,
> <0x0 0x2c010000 0x0 0x2000>,
> <0x0 0x2c02f000 0x0 0x2000>;
> - interrupts = <1 9 4>;
> + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
>
> its: its@2f020000 {
> compatible = "arm,gic-v3-its";
> diff --git a/arch/arm64/boot/dts/arm/foundation-v8.dtsi b/arch/arm64/boot/dts/arm/foundation-v8.dtsi
> index e080277d27ae..3f78373f708a 100644
> --- a/arch/arm64/boot/dts/arm/foundation-v8.dtsi
> +++ b/arch/arm64/boot/dts/arm/foundation-v8.dtsi
> @@ -7,6 +7,8 @@
>
> /dts-v1/;
>
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> /memreserve/ 0x80000000 0x00010000;
>
> / {
> @@ -67,26 +69,26 @@
>
> timer {
> compatible = "arm,armv8-timer";
> - interrupts = <1 13 0xf08>,
> - <1 14 0xf08>,
> - <1 11 0xf08>,
> - <1 10 0xf08>;
> + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
> clock-frequency = <100000000>;
> };
>
> pmu {
> compatible = "arm,armv8-pmuv3";
> - interrupts = <0 60 4>,
> - <0 61 4>,
> - <0 62 4>,
> - <0 63 4>;
> + interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
> };
>
> watchdog@2a440000 {
> compatible = "arm,sbsa-gwdt";
> reg = <0x0 0x2a440000 0 0x1000>,
> <0x0 0x2a450000 0 0x1000>;
> - interrupts = <0 27 4>;
> + interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
> timeout-sec = <30>;
> };
>
> @@ -105,49 +107,49 @@
>
> #interrupt-cells = <1>;
> interrupt-map-mask = <0 0 63>;
> - interrupt-map = <0 0 0 &gic 0 0 0 0 4>,
> - <0 0 1 &gic 0 0 0 1 4>,
> - <0 0 2 &gic 0 0 0 2 4>,
> - <0 0 3 &gic 0 0 0 3 4>,
> - <0 0 4 &gic 0 0 0 4 4>,
> - <0 0 5 &gic 0 0 0 5 4>,
> - <0 0 6 &gic 0 0 0 6 4>,
> - <0 0 7 &gic 0 0 0 7 4>,
> - <0 0 8 &gic 0 0 0 8 4>,
> - <0 0 9 &gic 0 0 0 9 4>,
> - <0 0 10 &gic 0 0 0 10 4>,
> - <0 0 11 &gic 0 0 0 11 4>,
> - <0 0 12 &gic 0 0 0 12 4>,
> - <0 0 13 &gic 0 0 0 13 4>,
> - <0 0 14 &gic 0 0 0 14 4>,
> - <0 0 15 &gic 0 0 0 15 4>,
> - <0 0 16 &gic 0 0 0 16 4>,
> - <0 0 17 &gic 0 0 0 17 4>,
> - <0 0 18 &gic 0 0 0 18 4>,
> - <0 0 19 &gic 0 0 0 19 4>,
> - <0 0 20 &gic 0 0 0 20 4>,
> - <0 0 21 &gic 0 0 0 21 4>,
> - <0 0 22 &gic 0 0 0 22 4>,
> - <0 0 23 &gic 0 0 0 23 4>,
> - <0 0 24 &gic 0 0 0 24 4>,
> - <0 0 25 &gic 0 0 0 25 4>,
> - <0 0 26 &gic 0 0 0 26 4>,
> - <0 0 27 &gic 0 0 0 27 4>,
> - <0 0 28 &gic 0 0 0 28 4>,
> - <0 0 29 &gic 0 0 0 29 4>,
> - <0 0 30 &gic 0 0 0 30 4>,
> - <0 0 31 &gic 0 0 0 31 4>,
> - <0 0 32 &gic 0 0 0 32 4>,
> - <0 0 33 &gic 0 0 0 33 4>,
> - <0 0 34 &gic 0 0 0 34 4>,
> - <0 0 35 &gic 0 0 0 35 4>,
> - <0 0 36 &gic 0 0 0 36 4>,
> - <0 0 37 &gic 0 0 0 37 4>,
> - <0 0 38 &gic 0 0 0 38 4>,
> - <0 0 39 &gic 0 0 0 39 4>,
> - <0 0 40 &gic 0 0 0 40 4>,
> - <0 0 41 &gic 0 0 0 41 4>,
> - <0 0 42 &gic 0 0 0 42 4>;
> + interrupt-map = <0 0 0 &gic 0 0 GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 1 &gic 0 0 GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 2 &gic 0 0 GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 3 &gic 0 0 GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 4 &gic 0 0 GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 5 &gic 0 0 GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 6 &gic 0 0 GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 7 &gic 0 0 GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 8 &gic 0 0 GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 9 &gic 0 0 GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 10 &gic 0 0 GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 11 &gic 0 0 GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 12 &gic 0 0 GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 13 &gic 0 0 GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 14 &gic 0 0 GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 15 &gic 0 0 GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 16 &gic 0 0 GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 17 &gic 0 0 GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 18 &gic 0 0 GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 19 &gic 0 0 GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 20 &gic 0 0 GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 21 &gic 0 0 GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 22 &gic 0 0 GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 23 &gic 0 0 GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 24 &gic 0 0 GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 25 &gic 0 0 GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 26 &gic 0 0 GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 27 &gic 0 0 GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 28 &gic 0 0 GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 29 &gic 0 0 GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 30 &gic 0 0 GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 31 &gic 0 0 GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 32 &gic 0 0 GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 33 &gic 0 0 GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 34 &gic 0 0 GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 35 &gic 0 0 GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 36 &gic 0 0 GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 37 &gic 0 0 GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 38 &gic 0 0 GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 39 &gic 0 0 GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 40 &gic 0 0 GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 41 &gic 0 0 GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 42 &gic 0 0 GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
>
> ethernet@2,02000000 {
> compatible = "smsc,lan91c111";
> diff --git a/arch/arm64/boot/dts/arm/juno-base.dtsi b/arch/arm64/boot/dts/arm/juno-base.dtsi
> index ed774ee8f659..3a72c04247cb 100644
> --- a/arch/arm64/boot/dts/arm/juno-base.dtsi
> +++ b/arch/arm64/boot/dts/arm/juno-base.dtsi
> @@ -18,7 +18,7 @@
> status = "disabled";
> frame@2a830000 {
> frame-number = <1>;
> - interrupts = <0 60 4>;
> + interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
> reg = <0x0 0x2a830000 0x0 0x10000>;
> };
> };
> @@ -520,10 +520,10 @@
> <0x42000000 0x40 0x00000000 0x40 0x00000000 0x1 0x00000000>;
> #interrupt-cells = <1>;
> interrupt-map-mask = <0 0 0 7>;
> - interrupt-map = <0 0 0 1 &gic 0 0 0 136 4>,
> - <0 0 0 2 &gic 0 0 0 137 4>,
> - <0 0 0 3 &gic 0 0 0 138 4>,
> - <0 0 0 4 &gic 0 0 0 139 4>;
> + interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 0 2 &gic 0 0 GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 0 3 &gic 0 0 GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 0 4 &gic 0 0 GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
> msi-parent = <&v2m_0>;
> status = "disabled";
> iommu-map-mask = <0x0>; /* RC has no means to output PCI RID */
> @@ -787,19 +787,19 @@
>
> #interrupt-cells = <1>;
> interrupt-map-mask = <0 0 15>;
> - interrupt-map = <0 0 0 &gic 0 0 0 68 IRQ_TYPE_LEVEL_HIGH>,
> - <0 0 1 &gic 0 0 0 69 IRQ_TYPE_LEVEL_HIGH>,
> - <0 0 2 &gic 0 0 0 70 IRQ_TYPE_LEVEL_HIGH>,
> - <0 0 3 &gic 0 0 0 160 IRQ_TYPE_LEVEL_HIGH>,
> - <0 0 4 &gic 0 0 0 161 IRQ_TYPE_LEVEL_HIGH>,
> - <0 0 5 &gic 0 0 0 162 IRQ_TYPE_LEVEL_HIGH>,
> - <0 0 6 &gic 0 0 0 163 IRQ_TYPE_LEVEL_HIGH>,
> - <0 0 7 &gic 0 0 0 164 IRQ_TYPE_LEVEL_HIGH>,
> - <0 0 8 &gic 0 0 0 165 IRQ_TYPE_LEVEL_HIGH>,
> - <0 0 9 &gic 0 0 0 166 IRQ_TYPE_LEVEL_HIGH>,
> - <0 0 10 &gic 0 0 0 167 IRQ_TYPE_LEVEL_HIGH>,
> - <0 0 11 &gic 0 0 0 168 IRQ_TYPE_LEVEL_HIGH>,
> - <0 0 12 &gic 0 0 0 169 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-map = <0 0 0 &gic 0 0 GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 1 &gic 0 0 GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 2 &gic 0 0 GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 3 &gic 0 0 GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 4 &gic 0 0 GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 5 &gic 0 0 GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 6 &gic 0 0 GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 7 &gic 0 0 GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 8 &gic 0 0 GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 9 &gic 0 0 GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 10 &gic 0 0 GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 11 &gic 0 0 GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 12 &gic 0 0 GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
> };
>
> site2: tlx@60000000 {
> @@ -809,6 +809,6 @@
> ranges = <0 0 0x60000000 0x10000000>;
> #interrupt-cells = <1>;
> interrupt-map-mask = <0 0>;
> - interrupt-map = <0 0 &gic 0 0 0 168 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-map = <0 0 &gic 0 0 GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
> };
> };
> diff --git a/arch/arm64/boot/dts/arm/rtsm_ve-aemv8a.dts b/arch/arm64/boot/dts/arm/rtsm_ve-aemv8a.dts
> index fe4fda473c0a..6e685d883303 100644
> --- a/arch/arm64/boot/dts/arm/rtsm_ve-aemv8a.dts
> +++ b/arch/arm64/boot/dts/arm/rtsm_ve-aemv8a.dts
> @@ -10,6 +10,8 @@
>
> /dts-v1/;
>
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> /memreserve/ 0x80000000 0x00010000;
>
> #include "rtsm_ve-motherboard.dtsi"
> @@ -101,24 +103,24 @@
> <0x0 0x2c002000 0 0x2000>,
> <0x0 0x2c004000 0 0x2000>,
> <0x0 0x2c006000 0 0x2000>;
> - interrupts = <1 9 0xf04>;
> + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
> };
>
> timer {
> compatible = "arm,armv8-timer";
> - interrupts = <1 13 0xf08>,
> - <1 14 0xf08>,
> - <1 11 0xf08>,
> - <1 10 0xf08>;
> + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
> clock-frequency = <100000000>;
> };
>
> pmu {
> compatible = "arm,armv8-pmuv3";
> - interrupts = <0 60 4>,
> - <0 61 4>,
> - <0 62 4>,
> - <0 63 4>;
> + interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
> };
>
> panel {
> @@ -144,48 +146,48 @@
>
> #interrupt-cells = <1>;
> interrupt-map-mask = <0 0 63>;
> - interrupt-map = <0 0 0 &gic 0 0 4>,
> - <0 0 1 &gic 0 1 4>,
> - <0 0 2 &gic 0 2 4>,
> - <0 0 3 &gic 0 3 4>,
> - <0 0 4 &gic 0 4 4>,
> - <0 0 5 &gic 0 5 4>,
> - <0 0 6 &gic 0 6 4>,
> - <0 0 7 &gic 0 7 4>,
> - <0 0 8 &gic 0 8 4>,
> - <0 0 9 &gic 0 9 4>,
> - <0 0 10 &gic 0 10 4>,
> - <0 0 11 &gic 0 11 4>,
> - <0 0 12 &gic 0 12 4>,
> - <0 0 13 &gic 0 13 4>,
> - <0 0 14 &gic 0 14 4>,
> - <0 0 15 &gic 0 15 4>,
> - <0 0 16 &gic 0 16 4>,
> - <0 0 17 &gic 0 17 4>,
> - <0 0 18 &gic 0 18 4>,
> - <0 0 19 &gic 0 19 4>,
> - <0 0 20 &gic 0 20 4>,
> - <0 0 21 &gic 0 21 4>,
> - <0 0 22 &gic 0 22 4>,
> - <0 0 23 &gic 0 23 4>,
> - <0 0 24 &gic 0 24 4>,
> - <0 0 25 &gic 0 25 4>,
> - <0 0 26 &gic 0 26 4>,
> - <0 0 27 &gic 0 27 4>,
> - <0 0 28 &gic 0 28 4>,
> - <0 0 29 &gic 0 29 4>,
> - <0 0 30 &gic 0 30 4>,
> - <0 0 31 &gic 0 31 4>,
> - <0 0 32 &gic 0 32 4>,
> - <0 0 33 &gic 0 33 4>,
> - <0 0 34 &gic 0 34 4>,
> - <0 0 35 &gic 0 35 4>,
> - <0 0 36 &gic 0 36 4>,
> - <0 0 37 &gic 0 37 4>,
> - <0 0 38 &gic 0 38 4>,
> - <0 0 39 &gic 0 39 4>,
> - <0 0 40 &gic 0 40 4>,
> - <0 0 41 &gic 0 41 4>,
> - <0 0 42 &gic 0 42 4>;
> + interrupt-map = <0 0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 1 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 2 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 3 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 4 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 5 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 6 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 7 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 8 &gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 9 &gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 10 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 11 &gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 12 &gic GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 13 &gic GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 14 &gic GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 15 &gic GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 16 &gic GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 17 &gic GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 18 &gic GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 19 &gic GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 20 &gic GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 21 &gic GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 22 &gic GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 23 &gic GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 24 &gic GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 25 &gic GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 26 &gic GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 27 &gic GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 28 &gic GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 29 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 30 &gic GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 31 &gic GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 32 &gic GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 33 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 34 &gic GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 35 &gic GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 36 &gic GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 37 &gic GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 38 &gic GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 39 &gic GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 40 &gic GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 41 &gic GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 42 &gic GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
> };
> };
> --
> 2.17.1
>
--
====================
| I would like to |
| fix the world, |
| but they're not |
| giving me the |
\ source code! /
---------------
¯\_(ツ)_/¯
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^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 2/4] arm64: dts: models: use list instead of tuple for mmci interrupts
2019-01-25 17:56 ` [PATCH 2/4] arm64: dts: models: use list instead of tuple for mmci interrupts Sudeep Holla
2019-01-28 10:37 ` Vladimir Murzin
@ 2019-01-29 14:35 ` Liviu Dudau
1 sibling, 0 replies; 7+ messages in thread
From: Liviu Dudau @ 2019-01-29 14:35 UTC (permalink / raw)
To: Sudeep Holla; +Cc: devicetree, linux-arm-kernel
On Fri, Jan 25, 2019 at 05:56:04PM +0000, Sudeep Holla wrote:
> RTSM/FVP vexpress motherboard model MMCI requires dedicated interrupts
> for CMD and PIO, which obviously should be expressed as a list. Current
> form uses tuple and it works fine since interrupt-cells equal to 1.
>
> Cc: Liviu Dudau <liviu.dudau@arm.com>
For the rest of the series:
Acked-by: Liviu Dudau <liviu.dudau@arm.com>
Best regards,
Liviu
> Reported-by: Vladimir Murzin <vladimir.murzin@arm.com>
> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
> ---
> arch/arm64/boot/dts/arm/rtsm_ve-motherboard.dtsi | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm64/boot/dts/arm/rtsm_ve-motherboard.dtsi b/arch/arm64/boot/dts/arm/rtsm_ve-motherboard.dtsi
> index b25f3cbd3da8..102e93744edc 100644
> --- a/arch/arm64/boot/dts/arm/rtsm_ve-motherboard.dtsi
> +++ b/arch/arm64/boot/dts/arm/rtsm_ve-motherboard.dtsi
> @@ -86,7 +86,7 @@
> mmci@50000 {
> compatible = "arm,pl180", "arm,primecell";
> reg = <0x050000 0x1000>;
> - interrupts = <9 10>;
> + interrupts = <9>, <10>;
> cd-gpios = <&v2m_sysreg 0 0>;
> wp-gpios = <&v2m_sysreg 1 0>;
> max-frequency = <12000000>;
> --
> 2.17.1
>
--
====================
| I would like to |
| fix the world, |
| but they're not |
| giving me the |
\ source code! /
---------------
¯\_(ツ)_/¯
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^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2019-01-29 14:35 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-01-25 17:56 [PATCH 1/4] arm64: dts: juno/fast models: using GIC macros instead of hardcoded values Sudeep Holla
2019-01-25 17:56 ` [PATCH 2/4] arm64: dts: models: use list instead of tuple for mmci interrupts Sudeep Holla
2019-01-28 10:37 ` Vladimir Murzin
2019-01-29 14:35 ` Liviu Dudau
2019-01-25 17:56 ` [PATCH 3/4] arm64: dts: juno/fast models: sort couple of device nodes Sudeep Holla
2019-01-25 17:56 ` [PATCH 4/4] arm64: dts: fast models: Add DTS fo Base RevC FVP Sudeep Holla
2019-01-29 14:00 ` [PATCH 1/4] arm64: dts: juno/fast models: using GIC macros instead of hardcoded values Liviu Dudau
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