[PATCH v1 0/3] arm64: Boot requirements clarifications

[PATCH v1 0/3] arm64: Boot requirements clarifications

[Mark Brown]

This series makes explicit our booting requirements in a number of
areas, mainly the initialisation of optional floating point features.
While no issues have been encountered it seems better to be explict,
particularly given that new extensions frequently require setup from
higher exception levels to be functional so our list of explicit
requirement is tending to become more and more exhaustive creating some
expecation that requirements will be stated clearly.

Due to a collision with my recent FGT series this series is based on top
of arm64/for-next/fgt-boot-init.

Mark Brown (3):
  arm64: Relax booting requirements for configuration of traps
  arm64: Explicitly require that FPSIMD instructions do not trap
  arm64: Explicitly document boot requirements for SVE

 Documentation/arm64/booting.rst | 33 ++++++++++++++++++++++++++++++++-
 1 file changed, 32 insertions(+), 1 deletion(-)


base-commit: 230800cd315cd5e2093e603cf7ee150b7591ce1a
-- 
2.20.1


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[PATCH v1 1/3] arm64: Relax booting requirements for configuration of traps

[Mark Brown]

Currently we require that a number of system registers be configured to
disable traps when starting the kernel. Add an explicit note that the
requirement is that the system behave as if the traps are disabled so
transparent handling of the traps is fine, this should be implicit for
people familiar with working with standards documents but it doesn't hurt
to be explicit.

Signed-off-by: Mark Brown <broonie@kernel.org>
---
 Documentation/arm64/booting.rst | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/Documentation/arm64/booting.rst b/Documentation/arm64/booting.rst
index 4fcc00add117..b21049ab6c69 100644
--- a/Documentation/arm64/booting.rst
+++ b/Documentation/arm64/booting.rst
@@ -279,7 +279,10 @@ Before jumping into the kernel, the following conditions must be met:
 
 The requirements described above for CPU mode, caches, MMUs, architected
 timers, coherency and system registers apply to all CPUs.  All CPUs must
-enter the kernel in the same exception level.
+enter the kernel in the same exception level.  Where the values documented
+disable traps it is permissible for these traps to be enabled so long as
+those traps are handled transparently by higher exception levels as though
+the values documented were set.
 
 The boot loader is expected to enter the kernel on each CPU in the
 following manner:
-- 
2.20.1


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[PATCH v1 2/3] arm64: Explicitly require that FPSIMD instructions do not trap

[Mark Brown]

We do not explicitly require that systems with FPSIMD support and EL3 have
disabled EL3 traps when the kernel is started, while it is unlikely that
systems will get this wrong for the sake of completeness let's spell it
out.

Signed-off-by: Mark Brown <broonie@kernel.org>
---
 Documentation/arm64/booting.rst | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/Documentation/arm64/booting.rst b/Documentation/arm64/booting.rst
index b21049ab6c69..4d0e323c0a35 100644
--- a/Documentation/arm64/booting.rst
+++ b/Documentation/arm64/booting.rst
@@ -277,6 +277,16 @@ Before jumping into the kernel, the following conditions must be met:
 
     - SCR_EL3.FGTEn (bit 27) must be initialised to 0b1.
 
+  For CPUs with Advanced SIMD and floating point support:
+
+  - If EL3 is present:
+
+    - CPTR_EL3.TFP (bit 10) must be initialised to 0b0.
+
+  - If EL2 is present and the kernel is entered at EL1:
+
+    - CPTR_EL2.TFP (bit 10) must be initialised to 0b0.
+
 The requirements described above for CPU mode, caches, MMUs, architected
 timers, coherency and system registers apply to all CPUs.  All CPUs must
 enter the kernel in the same exception level.  Where the values documented
-- 
2.20.1


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[PATCH v1 3/3] arm64: Explicitly document boot requirements for SVE

[Mark Brown]

We do not currently document the requirements for configuration of the
SVE system registers when booting the kernel, let's do so for completeness.

We don't have a hard requirement that the vector lengths configured on
different CPUs on initial boot be consistent since we have logic to
constrain to the minimum supported value but we will reject any late CPUs
which can't support the current maximum and introducing the concept of
late CPUs seemed more complex than was useful so we require that all CPUs
use the same value.

Signed-off-by: Mark Brown <broonie@kernel.org>
---
 Documentation/arm64/booting.rst | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/Documentation/arm64/booting.rst b/Documentation/arm64/booting.rst
index 4d0e323c0a35..18b8cc1bf32c 100644
--- a/Documentation/arm64/booting.rst
+++ b/Documentation/arm64/booting.rst
@@ -287,6 +287,24 @@ Before jumping into the kernel, the following conditions must be met:
 
     - CPTR_EL2.TFP (bit 10) must be initialised to 0b0.
 
+  For CPUs with the Scalable Vector Extension (FEAT_SVE) present:
+
+  - if EL3 is present:
+
+    - CPTR_EL3.EZ (bit 8) must be initialised to 0b1.
+
+    - ZCR_EL3.LEN must be initialised to the same value for all CPUs the
+      kernel is executed on.
+
+  - If the kernel is entered at EL1 and EL2 is present:
+
+    - CPTR_EL2.TZ (bit 8) must be initialised to 0b0.
+
+    - CPTR_EL2.ZEN (bits 17:16) must be initialised to 0b11.
+
+    - ZCR_EL2.LEN must be initialised to the same value for all CPUs the
+      kernel will execute on.
+
 The requirements described above for CPU mode, caches, MMUs, architected
 timers, coherency and system registers apply to all CPUs.  All CPUs must
 enter the kernel in the same exception level.  Where the values documented
-- 
2.20.1


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Re: [PATCH v1 0/3] arm64: Boot requirements clarifications

[Catalin Marinas]

On Mon, 12 Apr 2021 16:19:52 +0100, Mark Brown wrote:
> This series makes explicit our booting requirements in a number of
> areas, mainly the initialisation of optional floating point features.
> While no issues have been encountered it seems better to be explict,
> particularly given that new extensions frequently require setup from
> higher exception levels to be functional so our list of explicit
> requirement is tending to become more and more exhaustive creating some
> expecation that requirements will be stated clearly.
> 
> [...]

Applied to arm64 (for-next/core), thanks!

[1/3] arm64: Relax booting requirements for configuration of traps
      https://git.kernel.org/arm64/c/ee61f36d3e46
[2/3] arm64: Explicitly require that FPSIMD instructions do not trap
      https://git.kernel.org/arm64/c/b30dbf4d9362
[3/3] arm64: Explicitly document boot requirements for SVE
      https://git.kernel.org/arm64/c/ff1c42cdfbcf

-- 
Catalin


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