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[Jingchang Lu]

This series contain the support for Freescale LS1021A CPU and LS1021A-QDS
and LS1021A-TWR board.

The LS1021A SoC combines two ARM Cortex-A7 cores that have been optimized
for high reliability and pack the highest level of integration available
for sub-3W embedded communications processors and with a comprehensive
enablement model focused on ease of programmability.

The LS1021A SoC shares IPs with i.MX family, Vybrid family and Freescale
PowerPC platform. 

For the detail information about LS1021A SoC, please refer to the RM doc.

---
changes in v4:
add "syscon" compatible to device tree scfg and dcfg node, and 
remove uncompleted dcsr related node.
remove mxc_restart reference in DT_MACHINE_START.
remove dma_zone_size defination in DT_MACHINE_START.

changes in v3:
rewrite scfg and dcfg binding doc description.
remove sai related node leaving to the driver support.

changes in v2:
remove unused nodes.
wakeup the secondary core by IPI call to u-boot standby procedure. 
add dt-bindings for LS1021A SoC and platform gerenal configuration nodes.

----------------------------------------------------------------
Jingchang Lu (6):
	ARM: dts: Add SoC level device tree support for LS1021A
	ARM: dts: Add initial LS1021A QDS board dts support
	ARM: dts: Add initial LS1021A TWR board dts support
	dt-bindings: arm: add Freescale LS1021A SoC device tree binding
	ARM: imx: Add initial support for Freescale LS1021A
	ARM: imx: Add Freescale LS1021A SMP support

 Documentation/devicetree/bindings/arm/fsl.txt |  38 ++++
 arch/arm/boot/dts/Makefile                    |   2 +
 arch/arm/boot/dts/ls1021a-qds.dts             | 285 ++++++++++++++++++++++++++
 arch/arm/boot/dts/ls1021a-twr.dts             | 117 +++++++++++
 arch/arm/boot/dts/ls1021a.dtsi                | 539 ++++++++++++++++++++++++++++++++++++++++++++++++++
 arch/arm/mach-imx/Kconfig                     |  14 ++
 arch/arm/mach-imx/Makefile                    |   4 +-
 arch/arm/mach-imx/common.h                    |   1 +
 arch/arm/mach-imx/mach-ls1021a.c              |  22 +++
 arch/arm/mach-imx/platsmp.c                   |  32 +++
 10 files changed, 1053 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/boot/dts/ls1021a-qds.dts
 create mode 100755 arch/arm/boot/dts/ls1021a-twr.dts
 create mode 100644 arch/arm/boot/dts/ls1021a.dtsi
 create mode 100644 arch/arm/mach-imx/mach-ls1021a.c

[PATCHv4 1/6] ARM: dts: Add SoC level device tree support for LS1021A

[Jingchang Lu]

From: Jingchang Lu <b35083@freescale.com>

Add Freescale LS1021A SoC device tree support

Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com>
Signed-off-by: Chenhui Zhao <chenhui.zhao@freescale.com>
Signed-off-by: Suresh Gupta <suresh.gupta@freescale.com>
Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com>
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
Signed-off-by: Chao Fu <b44548@freescale.com>
Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com>
Signed-off-by: Jingchang Lu <jingchang.lu@freescale.com>
---
 arch/arm/boot/dts/ls1021a.dtsi | 539 +++++++++++++++++++++++++++++++++++++++++
 1 file changed, 539 insertions(+)
 create mode 100644 arch/arm/boot/dts/ls1021a.dtsi

diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi
new file mode 100644
index 0000000..b498838
--- /dev/null
+++ b/arch/arm/boot/dts/ls1021a.dtsi
@@ -0,0 +1,539 @@
+/*
+ * Copyright 2013-2014 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include "skeleton64.dtsi"
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+	compatible = "fsl,ls1021a";
+	interrupt-parent = <&gic>;
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	aliases {
+		serial0 = &lpuart0;
+		serial1 = &lpuart1;
+		serial2 = &lpuart2;
+		serial3 = &lpuart3;
+		serial4 = &lpuart4;
+		serial5 = &lpuart5;
+		ethernet0 = &enet0;
+		ethernet1 = &enet1;
+		ethernet2 = &enet2;
+		sysclk = &sysclk;
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu at f00 {
+			compatible = "arm,cortex-a7";
+			device_type = "cpu";
+			reg = <0xf00>;
+		};
+
+		cpu at f01 {
+			compatible = "arm,cortex-a7";
+			device_type = "cpu";
+			reg = <0xf01>;
+		};
+	};
+
+	timer {
+		compatible = "arm,armv7-timer";
+		interrupts = 	<GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+				<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+				<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+				<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
+	};
+
+	pmu {
+		compatible = "arm,cortex-a7-pmu";
+		interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	soc {
+		compatible = "simple-bus";
+		#address-cells = <2>;
+		#size-cells = <2>;
+		interrupt-parent = <&gic>;
+		ranges;
+
+		gic: interrupt-controller at 1400000 {
+			compatible = "arm,cortex-a7-gic";
+			#interrupt-cells = <3>;
+			interrupt-controller;
+			reg = <0x0 0x1401000 0x0 0x1000>,
+				<0x0 0x1402000 0x0 0x1000>,
+				<0x0 0x1404000 0x0 0x2000>,
+				<0x0 0x1406000 0x0 0x2000>;
+			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
+
+		};
+
+		ifc: ifc at 1530000 {
+			compatible = "fsl,ifc", "simple-bus";
+			reg = <0x0 0x1530000 0x0 0x10000>;
+			interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
+		dcfg: dcfg at 1ee0000 {
+			compatible = "fsl,ls1021a-dcfg", "syscon";
+			reg = <0x0 0x1ee0000 0x0 0x10000>;
+			big-endian;
+		};
+
+		esdhc: esdhc at 1560000 {
+			compatible = "fsl,esdhc";
+			reg = <0x0 0x1560000 0x0 0x10000>;
+			interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
+			clock-frequency = <0>;
+			voltage-ranges = <1800 1800 3300 3300>;
+			sdhci,auto-cmd12;
+			big-endian;
+			bus-width = <4>;
+			status = "disabled";
+		};
+
+		scfg: scfg at 1570000 {
+			compatible = "fsl,ls1021a-scfg", "syscon";
+			reg = <0x0 0x1570000 0x0 0x10000>;
+		};
+
+		crypto: crypto at 1700000 {
+			compatible = "fsl,sec-v5.3", "fsl,sec-v5.0", "fsl,sec-v4.0";
+			fsl,sec-era = <4>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			reg		 = <0x0 0x1700000 0x0 0x100000>;
+			ranges		 = <0x0 0x0 0x1700000 0x100000>;
+			interrupts	 = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+
+			sec_jr0: jr at 10000 {
+				compatible = "fsl,sec-v5.3-job-ring",
+				     "fsl,sec-v5.0-job-ring",
+				     "fsl,sec-v4.0-job-ring";
+				reg = <0x10000 0x10000>;
+				interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
+			};
+
+			sec_jr1: jr at 20000 {
+				compatible = "fsl,sec-v5.3-job-ring",
+				     "fsl,sec-v5.0-job-ring",
+				     "fsl,sec-v4.0-job-ring";
+				reg = <0x20000 0x10000>;
+				interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
+			};
+
+			sec_jr2: jr at 30000 {
+				compatible = "fsl,sec-v5.3-job-ring",
+				     "fsl,sec-v5.0-job-ring",
+				     "fsl,sec-v4.0-job-ring";
+				reg = <0x30000 0x10000>;
+				interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
+			};
+
+			sec_jr3: jr at 40000 {
+				compatible = "fsl,sec-v5.3-job-ring",
+				     "fsl,sec-v5.0-job-ring",
+				     "fsl,sec-v4.0-job-ring";
+				reg = <0x40000 0x10000>;
+				interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
+			};
+
+		};
+
+		clockgen: clocking at 1ee1000 {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0x0 0x0 0x1ee1000 0x10000>;
+
+			sysclk: sysclk {
+				compatible = "fixed-clock";
+				#clock-cells = <0>;
+				clock-output-names = "sysclk";
+			};
+
+			cga_pll1: pll1 at 800 {
+				compatible = "fsl,qoriq-core-pll-2.0";
+				#clock-cells = <1>;
+				reg = <0x800 0x10>;
+				clocks = <&sysclk>;
+				clock-output-names = "cga-pll1", "cga-pll1-div2",
+						"cga-pll1-div3", "cga-pll1-div4";
+			};
+
+			platform_clk: pll at c00 {
+				compatible = "fsl,qoriq-core-pll-2.0";
+				#clock-cells = <1>;
+				reg = <0xc00 0x10>;
+				clocks = <&sysclk>;
+				clock-output-names = "platform-clk", "platform-clk-div2";
+			};
+
+			cluster1_clk: clk0c0 at 0 {
+				compatible = "fsl,qoriq-core-mux-2.0";
+				#clock-cells = <0>;
+				reg = <0x0 0x10>;
+				clock-names = "pll1cga", "pll1cga-div2";
+				clocks = <&cga_pll1 0>, <&cga_pll1 2>;
+				clock-output-names = "cluster1-clk";
+			};
+		};
+
+		dspi0: dspi at 2100000 {
+			compatible = "fsl,vf610-dspi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x0 0x2100000 0x0 0x10000>;
+			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "dspi";
+			clocks = <&platform_clk 1>;
+			spi-num-chipselects = <5>;
+			big-endian;
+			status = "disabled";
+		};
+
+		dspi1: dspi at 2110000 {
+			compatible = "fsl,vf610-dspi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x0 0x2110000 0x0 0x10000>;
+			interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "dspi";
+			clocks = <&platform_clk 1>;
+			spi-num-chipselects = <5>;
+			big-endian;
+			status = "disabled";
+		};
+
+		i2c0: i2c at 2180000 {
+			compatible = "fsl,vf610-i2c";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x0 0x2180000 0x0 0x10000>;
+			interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "i2c";
+			clocks = <&platform_clk 1>;
+			status = "disabled";
+		};
+
+		i2c1: i2c at 2190000 {
+			compatible = "fsl,vf610-i2c";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x0 0x2190000 0x0 0x10000>;
+			interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "i2c";
+			clocks = <&platform_clk 1>;
+			status = "disabled";
+		};
+
+		i2c2: i2c at 21a0000 {
+			compatible = "fsl,vf610-i2c";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x0 0x21a0000 0x0 0x10000>;
+			interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "i2c";
+			clocks = <&platform_clk 1>;
+			status = "disabled";
+		};
+
+		uart0: serial at 21c0500 {
+			compatible = "fsl,16550-FIFO64", "ns16550a";
+			reg = <0x0 0x21c0500 0x0 0x100>;
+			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+			clock-frequency = <0>;
+			fifo-size = <15>;
+			status = "disabled";
+		};
+
+		uart1: serial at 21c0600 {
+			compatible = "fsl,16550-FIFO64", "ns16550a";
+			reg = <0x0 0x21c0600 0x0 0x100>;
+			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+			clock-frequency = <0>;
+			fifo-size = <15>;
+			status = "disabled";
+		};
+
+		uart2: serial at 21d0500 {
+			compatible = "fsl,16550-FIFO64", "ns16550a";
+			reg = <0x0 0x21d0500 0x0 0x100>;
+			interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
+			clock-frequency = <0>;
+			fifo-size = <15>;
+			status = "disabled";
+		};
+
+		uart3: serial at 21d0600 {
+			compatible = "fsl,16550-FIFO64", "ns16550a";
+			reg = <0x0 0x21d0600 0x0 0x100>;
+			interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
+			clock-frequency = <0>;
+			fifo-size = <15>;
+			status = "disabled";
+		};
+
+		lpuart0: serial at 2950000 {
+			compatible = "fsl,ls1021a-lpuart";
+			reg = <0x0 0x2950000 0x0 0x1000>;
+			interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&sysclk>;
+			clock-names = "ipg";
+			status = "disabled";
+		};
+
+		lpuart1: serial at 2960000 {
+			compatible = "fsl,ls1021a-lpuart";
+			reg = <0x0 0x2960000 0x0 0x1000>;
+			interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&platform_clk 1>;
+			clock-names = "ipg";
+			status = "disabled";
+		};
+
+		lpuart2: serial at 2970000 {
+			compatible = "fsl,ls1021a-lpuart";
+			reg = <0x0 0x2970000 0x0 0x1000>;
+			interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&platform_clk 1>;
+			clock-names = "ipg";
+			status = "disabled";
+		};
+
+		lpuart3: serial at 2980000 {
+			compatible = "fsl,ls1021a-lpuart";
+			reg = <0x0 0x2980000 0x0 0x1000>;
+			interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&platform_clk 1>;
+			clock-names = "ipg";
+			status = "disabled";
+		};
+
+		lpuart4: serial at 2990000 {
+			compatible = "fsl,ls1021a-lpuart";
+			reg = <0x0 0x2990000 0x0 0x1000>;
+			interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&platform_clk 1>;
+			clock-names = "ipg";
+			status = "disabled";
+		};
+
+		lpuart5: serial at 29a0000 {
+			compatible = "fsl,ls1021a-lpuart";
+			reg = <0x0 0x29a0000 0x0 0x1000>;
+			interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&platform_clk 1>;
+			clock-names = "ipg";
+			status = "disabled";
+		};
+
+		ftm0_1: ftm0_1 at 29d0000 {
+			compatible = "fsl,ftm-timer";
+			reg = <0x0 0x29d0000 0x0 0x10000>,
+				<0x0 0x29e0000 0x0 0x10000>;
+			interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "ftm-evt", "ftm-src",
+			        "ftm-evt-counter-en", "ftm-src-counter-en";
+			clocks = <&platform_clk 1>, <&platform_clk 1>,
+			       <&platform_clk 1>, <&platform_clk 1>;
+			big-endian;
+			status = "disabled";
+		};
+
+		pwm3: ftm at 2a00000 {
+			compatible = "fsl,vf610-ftm-pwm";
+			#pwm-cells = <3>;
+			reg = <0x0 0x2a00000 0x0 0x10000>;
+			interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "ftm_sys", "ftm_ext",
+				"ftm_fix", "ftm_cnt_clk_en";
+			clocks = <&platform_clk 1>, <&platform_clk 1>,
+				<&platform_clk 1>, <&platform_clk 1>;
+			big-endian;
+			status = "disabled";
+		};
+
+		pwm6: ftm at 2a30000 {
+			compatible = "fsl,vf610-ftm-pwm";
+			#pwm-cells = <3>;
+			reg = <0x0 0x2a30000 0x0 0x10000>;
+			interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "ftm_sys", "ftm_ext",
+				"ftm_fix", "ftm_cnt_clk_en";
+			clocks = <&platform_clk 1>, <&platform_clk 1>,
+				<&platform_clk 1>, <&platform_clk 1>;
+			big-endian;
+			status = "disabled";
+		};
+
+		pwm7: ftm at 2a40000 {
+			compatible = "fsl,vf610-ftm-pwm";
+			#pwm-cells = <3>;
+			reg = <0x0 0x2a40000 0x0 0x10000>;
+			interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "ftm_sys", "ftm_ext",
+				"ftm_fix", "ftm_cnt_clk_en";
+			clocks = <&platform_clk 1>, <&platform_clk 1>,
+				<&platform_clk 1>, <&platform_clk 1>;
+			big-endian;
+			status = "disabled";
+		};
+
+		wdog0: wdog at 2ad0000 {
+			compatible = "fsl,imx21-wdt";
+			reg = <0x0 0x2ad0000 0x0 0x10000>;
+			interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&platform_clk 1>;
+			clock-names = "wdog";
+			big-endian;
+		};
+
+		sai1: sai at 2b50000 {
+			compatible = "fsl,vf610-sai";
+			reg = <0x0 0x2b50000 0x0 0x10000>;
+			interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&platform_clk 1>;
+			clock-names = "sai";
+			dma-names = "tx", "rx";
+			dmas = <&edma0 1 47>,
+				<&edma0 1 46>;
+			big-endian-regs;
+			status = "disabled";
+		};
+
+		sai2: sai at 2b60000 {
+			compatible = "fsl,vf610-sai";
+			reg = <0x0 0x2b60000 0x0 0x10000>;
+			interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&platform_clk 1>;
+			clock-names = "sai";
+			dma-names = "tx", "rx";
+			dmas = <&edma0 1 45>,
+				<&edma0 1 44>;
+			big-endian-regs;
+			status = "disabled";
+		};
+
+		edma0: edma at 2c00000 {
+			#dma-cells = <2>;
+			compatible = "fsl,vf610-edma";
+			reg = <0x0 0x2c00000 0x0 0x10000>,
+				<0x0 0x2c10000 0x0 0x10000>,
+				<0x0 0x2c20000 0x0 0x10000>;
+			interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "edma-tx", "edma-err";
+			dma-channels = <32>;
+			big-endian;
+			clock-names = "dmamux0", "dmamux1";
+			clocks = <&platform_clk 1>,
+				<&platform_clk 1>;
+		};
+
+		mdio0: mdio at 2d24000 {
+			compatible = "gianfar";
+			device_type = "mdio";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x0 0x2d24000 0x0 0x4000>;
+		};
+
+		enet0: ethernet at 2d10000 {
+			compatible = "fsl,etsec2";
+			device_type = "network";
+			#address-cells = <2>;
+			#size-cells = <2>;
+			interrupt-parent = <&gic>;
+			model = "eTSEC";
+			fsl,dma-endian-le;
+			fsl,num_rx_queues = <0x1>;
+			fsl,num_tx_queues = <0x1>;
+			ranges;
+
+			queue-group at 0 {
+				#address-cells = <1>;
+				#size-cells = <1>;
+				reg = <0x0 0x2d10000 0x0 0x8000>;
+				fsl,rx-bit-map = <0xff>;
+				fsl,tx-bit-map = <0xff>;
+				interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
+			};
+		};
+
+		enet1: ethernet at 2d50000 {
+			compatible = "fsl,etsec2";
+			device_type = "network";
+			#address-cells = <2>;
+			#size-cells = <2>;
+			interrupt-parent = <&gic>;
+			model = "eTSEC";
+			fsl,dma-endian-le;
+			fsl,num_rx_queues = <0x1>;
+			fsl,num_tx_queues = <0x1>;
+			ranges;
+
+			queue-group at 0 {
+				#address-cells = <1>;
+				#size-cells = <1>;
+				reg = <0x0 0x2d50000 0x0 0x8000>;
+				fsl,rx-bit-map = <0xff>;
+				fsl,tx-bit-map = <0xff>;
+				interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
+			};
+		};
+
+		enet2: ethernet at 2d90000 {
+			compatible = "fsl,etsec2";
+			device_type = "network";
+			#address-cells = <2>;
+			#size-cells = <2>;
+			interrupt-parent = <&gic>;
+			model = "eTSEC";
+			fsl,dma-endian-le;
+			fsl,num_rx_queues = <0x1>;
+			fsl,num_tx_queues = <0x1>;
+			ranges;
+
+			queue-group at 0 {
+				#address-cells = <1>;
+				#size-cells = <1>;
+				reg = <0x0 0x2d90000 0x0 0x8000>;
+				fsl,rx-bit-map = <0xff>;
+				fsl,tx-bit-map = <0xff>;
+				interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
+			};
+		};
+
+		usb at 8600000 {
+			compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr";
+			reg = <0x0 0x8600000 0x0 0x1000>;
+			interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
+			dr_mode = "host";
+			phy_type = "ulpi";
+		};
+
+		usb3 at 3100000 {
+			compatible = "snps,dwc3";
+			reg = <0x0 0x3100000 0x0 0x10000>;
+			interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
+			dr_mode = "host";
+		};
+	};
+};
-- 
1.8.0

[PATCHv4 2/6] ARM: dts: Add initial LS1021A QDS board dts support

[Jingchang Lu]

From: Jingchang Lu <b35083@freescale.com>

Signed-off-by: Alison Wang <alison.wang@freescale.com>
Signed-off-by: Chao Fu <B44548@freescale.com>
Signed-off-by: Jason Jin <Jason.Jin@freescale.com>
Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com>
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
Signed-off-by: Jaiprakash Singh <b44839@freescale.com>
Signed-off-by: Jingchang Lu <jingchang.lu@freescale.com>
---
 arch/arm/boot/dts/Makefile        |   1 +
 arch/arm/boot/dts/ls1021a-qds.dts | 285 ++++++++++++++++++++++++++++++++++++++
 2 files changed, 286 insertions(+)
 create mode 100644 arch/arm/boot/dts/ls1021a-qds.dts

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index e12fe46..384aa74 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -245,6 +245,7 @@ dtb-$(CONFIG_ARCH_MXC) += \
 	imx6q-tx6q-1110.dtb \
 	imx6sl-evk.dtb \
 	imx6sx-sdb.dtb \
+	ls1021a-qds.dtb \
 	vf610-colibri-eval-v3.dtb \
 	vf610-cosmic.dtb \
 	vf610-twr.dtb
diff --git a/arch/arm/boot/dts/ls1021a-qds.dts b/arch/arm/boot/dts/ls1021a-qds.dts
new file mode 100644
index 0000000..a0a95f51
--- /dev/null
+++ b/arch/arm/boot/dts/ls1021a-qds.dts
@@ -0,0 +1,285 @@
+/*
+ * Copyright 2013-2014 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+/dts-v1/;
+#include "ls1021a.dtsi"
+
+/ {
+	model = "LS1021A QDS Board";
+
+	aliases {
+		enet0_rgmii_phy = &rgmii_phy1;
+		enet1_rgmii_phy = &rgmii_phy2;
+		enet2_rgmii_phy = &rgmii_phy3;
+		enet0_sgmii_phy = &sgmii_phy1c;
+		enet1_sgmii_phy = &sgmii_phy1d;
+	};
+
+	soc {
+		leds {
+			compatible = "pwm-leds";
+			led0 {
+				label = "led0";
+				pwms = <&pwm3 0 150000 0>;
+				max-brightness = <100>;
+			};
+			led1 {
+				label = "led1";
+				pwms = <&pwm3 1 150000 0>;
+				max-brightness = <100>;
+			};
+			led2 {
+				label = "led2";
+				pwms = <&pwm3 2 150000 0>;
+				max-brightness = <100>;
+			};
+			led3 {
+				label = "led3";
+				pwms = <&pwm3 3 150000 0>;
+				max-brightness = <100>;
+			};
+			led4 {
+				label = "led4";
+				pwms = <&pwm3 4 150000 0>;
+				max-brightness = <100>;
+			};
+			led5 {
+				label = "led5";
+				pwms = <&pwm3 5 150000 0>;
+				max-brightness = <100>;
+			};
+			led6 {
+				label = "led6";
+				pwms = <&pwm3 6 150000 0>;
+				max-brightness = <100>;
+			};
+			led7 {
+				label = "led7";
+				pwms = <&pwm3 7 150000 0>;
+				max-brightness = <100>;
+			};
+		};
+	};
+};
+
+&dspi0 {
+	bus-num = <0>;
+	status = "okay";
+
+	dspiflash: at45db021d at 0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "atmel,at45db021d", "atmel,at45", "atmel,dataflash";
+		spi-max-frequency = <16000000>;
+		spi-cpol;
+		spi-cpha;
+		reg = <0>;
+	};
+};
+
+&enet0 {
+	tbi-handle = <&tbi0>;
+	phy-handle = <&sgmii_phy1c>;
+	phy-connection-type = "sgmii";
+	status = "okay";
+};
+
+&enet1 {
+	tbi-handle = <&tbi0>;
+	phy-handle = <&sgmii_phy1d>;
+	phy-connection-type = "sgmii";
+	status = "okay";
+};
+
+&enet2 {
+	phy-handle = <&rgmii_phy3>;
+	phy-connection-type = "rgmii-id";
+	status = "okay";
+};
+
+&i2c0 {
+	status = "okay";
+	pca9547 at 77 {
+		compatible = "philips,pca9547";
+		reg = <0x77>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		i2c at 0 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x0>;
+
+			rtc at 68 {
+				compatible = "dallas,ds3232";
+				reg = <0x68>;
+				interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
+			};
+		};
+
+		i2c at 2 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x2>;
+
+			ina220 at 40 {
+				compatible = "ti,ina220";
+				reg = <0x40>;
+				shunt-resistor = <1000>;
+			};
+
+			ina220 at 41 {
+				compatible = "ti,ina220";
+				reg = <0x41>;
+				shunt-resistor = <1000>;
+			};
+		};
+
+		i2c at 3 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x3>;
+
+			eeprom at 56 {
+				compatible = "at24,24c512";
+				reg = <0x56>;
+			};
+
+			eeprom at 57 {
+				compatible = "at24,24c512";
+				reg = <0x57>;
+			};
+
+			adt7461a at 4c {
+				compatible = "adt7461a";
+				reg = <0x4c>;
+			};
+		};
+
+		i2c at 4 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x4>;
+		};
+	};
+};
+
+&ifc {
+	status = "okay";
+	#address-cells = <2>;
+	#size-cells = <1>;
+	/* NOR, NAND Flashes and FPGA on board */
+	ranges = <0x0 0x0 0x0 0x60000000 0x08000000
+		0x2 0x0 0x0 0x7e800000 0x00010000
+		0x3 0x0 0x0 0x7fb00000 0x00000100>;
+
+		nor at 0,0 {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			compatible = "cfi-flash";
+			reg = <0x0 0x0 0x8000000>;
+			bank-width = <2>;
+			device-width = <1>;
+		};
+
+		nand at 2,0 {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			compatible = "fsl,ifc-nand";
+			reg = <0x2 0x0 0x10000>;
+		};
+
+		fpga: board-control at 3,0 {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			compatible = "simple-bus";
+			reg = <0x3 0x0 0x0000100>;
+			bank-width = <1>;
+			device-width = <1>;
+			ranges = <0 3 0 0x100>;
+
+			mdio-mux-emi1 {
+				compatible = "mdio-mux-mmioreg";
+				mdio-parent-bus = <&mdio0>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				reg = <0x54 1>; /* BRDCFG4 */
+				mux-mask = <0xe0>; /* EMI1[2:0] */
+
+				/* Onboard PHYs */
+				ls1021amdio0: mdio at 0 {
+					reg = <0>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+					rgmii_phy1: ethernet-phy at 1 {
+						reg = <0x1>;
+					};
+				};
+				ls1021amdio1: mdio at 20 {
+					reg = <0x20>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+					rgmii_phy2: ethernet-phy at 2 {
+						reg = <0x2>;
+					};
+				};
+				ls1021amdio2: mdio at 40 {
+					reg = <0x40>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+					rgmii_phy3: ethernet-phy at 3 {
+						reg = <0x3>;
+					};
+				};
+				ls1021amdio3: mdio at 60 {
+					reg = <0x60>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+					sgmii_phy1c: ethernet-phy at 1c {
+						reg = <0x1c>;
+					};
+				};
+				ls1021amdio4: mdio at 80 {
+					reg = <0x80>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+					sgmii_phy1d: ethernet-phy at 1d {
+						reg = <0x1d>;
+					};
+				};
+			};
+		};
+};
+
+&lpuart0 {
+	status = "okay";
+};
+
+&mdio0 {
+	tbi0: tbi-phy at 8 {
+		reg = <0x8>;
+		device_type = "tbi-phy";
+	};
+};
+
+&pwm3 {
+	status = "okay";
+};
+
+&pwm7 {
+	status = "okay";
+};
+
+&uart0 {
+	status = "okay";
+};
+
+&uart1 {
+	status = "okay";
+};
-- 
1.8.0

[PATCHv4 3/6] ARM: dts: Add initial LS1021A TWR board dts support

[Jingchang Lu]

Signed-off-by: Chen Lu <B46807@freescale.com>
Signed-off-by: Chao Fu <B44548@freescale.com>
Signed-off-by: Jingchang Lu <jingchang.lu@freescale.com>
---
 arch/arm/boot/dts/Makefile        |   1 +
 arch/arm/boot/dts/ls1021a-twr.dts | 117 ++++++++++++++++++++++++++++++++++++++
 2 files changed, 118 insertions(+)
 create mode 100755 arch/arm/boot/dts/ls1021a-twr.dts

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 384aa74..f716461 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -246,6 +246,7 @@ dtb-$(CONFIG_ARCH_MXC) += \
 	imx6sl-evk.dtb \
 	imx6sx-sdb.dtb \
 	ls1021a-qds.dtb \
+	ls1021a-twr.dtb \
 	vf610-colibri-eval-v3.dtb \
 	vf610-cosmic.dtb \
 	vf610-twr.dtb
diff --git a/arch/arm/boot/dts/ls1021a-twr.dts b/arch/arm/boot/dts/ls1021a-twr.dts
new file mode 100755
index 0000000..1a7e9fb
--- /dev/null
+++ b/arch/arm/boot/dts/ls1021a-twr.dts
@@ -0,0 +1,117 @@
+/*
+ * Copyright 2013-2014 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+/dts-v1/;
+#include "ls1021a.dtsi"
+
+/ {
+	model = "LS1021A TWR Board";
+
+	aliases {
+		enet2_rgmii_phy = &rgmii_phy1;
+		enet0_sgmii_phy = &sgmii_phy2;
+		enet1_sgmii_phy = &sgmii_phy0;
+	};
+};
+
+&dspi1 {
+	bus-num = <0>;
+	status = "okay";
+
+	dspiflash: s25fl064k at 0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "spansion,s25fl064k";
+		spi-max-frequency = <16000000>;
+		spi-cpol;
+		spi-cpha;
+		reg = <0>;
+	};
+};
+
+&enet0 {
+	tbi-handle = <&tbi1>;
+	phy-handle = <&sgmii_phy2>;
+	phy-connection-type = "sgmii";
+	status = "okay";
+};
+
+&enet1 {
+	tbi-handle = <&tbi1>;
+	phy-handle = <&sgmii_phy0>;
+	phy-connection-type = "sgmii";
+	status = "okay";
+};
+
+&enet2 {
+	phy-handle = <&rgmii_phy1>;
+	phy-connection-type = "rgmii-id";
+	status = "okay";
+};
+
+&i2c0 {
+	status = "okay";
+};
+
+&i2c1 {
+	status = "okay";
+};
+
+&ifc {
+	status = "okay";
+	#address-cells = <2>;
+	#size-cells = <1>;
+	/* NOR, and CPLD on board */
+	ranges = <0x0 0x0 0x0 0x60000000 0x08000000>;
+
+		nor at 0,0 {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			compatible = "cfi-flash";
+			reg = <0x0 0x0 0x8000000>;
+			bank-width = <2>;
+			device-width = <1>;
+		};
+};
+
+&lpuart0 {
+	status = "okay";
+};
+
+&mdio0 {
+	sgmii_phy0: ethernet-phy at 0 {
+		reg = <0x0>;
+	};
+	rgmii_phy1: ethernet-phy at 1 {
+		reg = <0x1>;
+	};
+	sgmii_phy2: ethernet-phy at 2 {
+		reg = <0x2>;
+	};
+	tbi1: tbi-phy at 1f {
+		reg = <0x1f>;
+		device_type = "tbi-phy";
+	};
+};
+
+&pwm6 {
+	status = "okay";
+};
+
+&pwm7 {
+	status = "okay";
+};
+
+&uart0 {
+	status = "okay";
+};
+
+&uart1 {
+	status = "okay";
+};
-- 
1.8.0

[PATCHv4 4/6] dt-bindings: arm: add Freescale LS1021A SoC device tree binding

[Jingchang Lu]

Signed-off-by: Jingchang Lu <jingchang.lu@freescale.com>
---
 Documentation/devicetree/bindings/arm/fsl.txt | 38 +++++++++++++++++++++++++++
 1 file changed, 38 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/fsl.txt b/Documentation/devicetree/bindings/arm/fsl.txt
index e935d7d..2e0ba09 100644
--- a/Documentation/devicetree/bindings/arm/fsl.txt
+++ b/Documentation/devicetree/bindings/arm/fsl.txt
@@ -74,3 +74,41 @@ Required root node properties:
 i.MX6q generic board
 Required root node properties:
     - compatible = "fsl,imx6q";
+
+
+Freescale LS1021A Platform Device Tree Bindings
+------------------------------------------------
+
+Required root node compatible properties:
+  - compatible = "fsl,ls1021a";
+
+Freescale LS1021A SoC-specific Device Tree Bindings
+-------------------------------------------
+
+Freescale SCFG
+  scfg is the supplemental configuration unit, that provides SoC specific
+configuration and status registers for the chip. Such as getting PEX port
+status.
+  Required properties:
+  - compatible: should be "fsl,ls1021a-scfg"
+  - reg: should contain base address and length of SCFG memory-mapped registers
+
+Example:
+	scfg: scfg at 1570000 {
+		compatible = "fsl,ls1021a-scfg";
+		reg = <0x0 0x1570000 0x0 0x10000>;
+	};
+
+Freescale DCFG
+  dcfg is the device configuration unit, that provides general purpose
+configuration and status for the device. Such as setting the secondary
+core start address and release the secondary core from holdoff and startup.
+  Required properties:
+  - compatible: should be "fsl,ls1021a-dcfg"
+  - reg : should contain base address and length of DCFG memory-mapped registers
+
+Example:
+	dcfg: dcfg at 1ee0000 {
+		compatible = "fsl,ls1021a-dcfg";
+		reg = <0x0 0x1ee0000 0x0 0x10000>;
+	};
-- 
1.8.0

[PATCHv4 5/6] ARM: imx: Add initial support for Freescale LS1021A

[Jingchang Lu]

From: Jingchang Lu <b35083@freescale.com>

The LS1021A SoC is a dual-core Cortex-A7 based processor,
this add the initial support for it.

Signed-off-by: Jingchang Lu <b35083@freescale.com>
---
 arch/arm/mach-imx/Kconfig        | 14 ++++++++++++++
 arch/arm/mach-imx/Makefile       |  2 ++
 arch/arm/mach-imx/mach-ls1021a.c | 21 +++++++++++++++++++++
 3 files changed, 37 insertions(+)
 create mode 100644 arch/arm/mach-imx/mach-ls1021a.c

diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 11b2957..2cc64a3 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -639,6 +639,20 @@ config SOC_VF610
 	help
 	  This enable support for Freescale Vybrid VF610 processor.
 
+config SOC_LS1021A
+	bool "Freescale LS1021A support"
+	select CPU_V7
+	select ARM_GIC
+	select CLKSRC_OF
+	select HAVE_ARM_ARCH_TIMER
+	select HAVE_SMP
+	select MIGHT_HAVE_PCI
+	select PCI_DOMAINS if PCI
+	select ZONE_DMA if ARM_LPAE
+
+	help
+	  This enable support for Freescale LS1021A processor.
+
 endif
 
 source "arch/arm/mach-imx/devices/Kconfig"
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index 6e4fcd8..ce137bc 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -110,4 +110,6 @@ obj-$(CONFIG_SOC_IMX53) += mach-imx53.o
 
 obj-$(CONFIG_SOC_VF610) += clk-vf610.o mach-vf610.o
 
+obj-$(CONFIG_SOC_LS1021A) += mach-ls1021a.o
+
 obj-y += devices/
diff --git a/arch/arm/mach-imx/mach-ls1021a.c b/arch/arm/mach-imx/mach-ls1021a.c
new file mode 100644
index 0000000..9d2034b
--- /dev/null
+++ b/arch/arm/mach-imx/mach-ls1021a.c
@@ -0,0 +1,21 @@
+/*
+ * Copyright 2013-2014 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <asm/mach/arch.h>
+
+#include "common.h"
+
+static const char * const ls1021a_dt_compat[] __initconst = {
+	"fsl,ls1021a",
+	NULL,
+};
+
+DT_MACHINE_START(LS1021A, "Freescale LS1021A")
+	.dt_compat	= ls1021a_dt_compat,
+MACHINE_END
-- 
1.8.0

[PATCHv4 6/6] ARM: imx: Add Freescale LS1021A SMP support

[Jingchang Lu]

From: Jingchang Lu <b35083@freescale.com>

Freescale LS1021A SoCs deploy two cortex-A7 processors,
this adds bring-up support for the secondary core.

Signed-off-by: Jingchang Lu <b35083@freescale.com>
---
 arch/arm/mach-imx/Makefile       |  2 +-
 arch/arm/mach-imx/common.h       |  1 +
 arch/arm/mach-imx/mach-ls1021a.c |  1 +
 arch/arm/mach-imx/platsmp.c      | 32 ++++++++++++++++++++++++++++++++
 4 files changed, 35 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index ce137bc..38d75e2 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -89,7 +89,7 @@ obj-$(CONFIG_HAVE_IMX_ANATOP) += anatop.o
 obj-$(CONFIG_HAVE_IMX_GPC) += gpc.o
 obj-$(CONFIG_HAVE_IMX_MMDC) += mmdc.o
 obj-$(CONFIG_HAVE_IMX_SRC) += src.o
-ifdef CONFIG_SOC_IMX6
+ifneq ($(CONFIG_SOC_IMX6)$(CONFIG_SOC_LS1021A),)
 AFLAGS_headsmp.o :=-Wa,-march=armv7-a
 obj-$(CONFIG_SMP) += headsmp.o platsmp.o
 obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h
index 1dabf43..c473ca5 100644
--- a/arch/arm/mach-imx/common.h
+++ b/arch/arm/mach-imx/common.h
@@ -157,5 +157,6 @@ static inline void imx_init_l2cache(void) {}
 #endif
 
 extern struct smp_operations imx_smp_ops;
+extern struct smp_operations ls1021a_smp_ops;
 
 #endif
diff --git a/arch/arm/mach-imx/mach-ls1021a.c b/arch/arm/mach-imx/mach-ls1021a.c
index 9d2034b..b89c858 100644
--- a/arch/arm/mach-imx/mach-ls1021a.c
+++ b/arch/arm/mach-imx/mach-ls1021a.c
@@ -17,5 +17,6 @@ static const char * const ls1021a_dt_compat[] __initconst = {
 };
 
 DT_MACHINE_START(LS1021A, "Freescale LS1021A")
+	.smp		= smp_ops(ls1021a_smp_ops),
 	.dt_compat	= ls1021a_dt_compat,
 MACHINE_END
diff --git a/arch/arm/mach-imx/platsmp.c b/arch/arm/mach-imx/platsmp.c
index 771bd25..62376f0 100644
--- a/arch/arm/mach-imx/platsmp.c
+++ b/arch/arm/mach-imx/platsmp.c
@@ -16,6 +16,8 @@
 #include <asm/page.h>
 #include <asm/smp_scu.h>
 #include <asm/mach/map.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
 
 #include "common.h"
 #include "hardware.h"
@@ -94,3 +96,33 @@ struct smp_operations  imx_smp_ops __initdata = {
 	.cpu_kill		= imx_cpu_kill,
 #endif
 };
+
+#define DCFG_CCSR_SCRATCHRW1	0x200
+
+static int ls1021a_boot_secondary(unsigned int cpu, struct task_struct *idle)
+{
+	arch_send_wakeup_ipi_mask(cpumask_of(cpu));
+
+	return 0;
+}
+
+static void __init ls1021a_smp_prepare_cpus(unsigned int max_cpus)
+{
+	struct device_node *np;
+	void __iomem *dcfg_base;
+	unsigned long paddr;
+
+	np = of_find_compatible_node(NULL, NULL, "fsl,ls1021a-dcfg");
+	dcfg_base = of_iomap(np, 0);
+	BUG_ON(!dcfg_base);
+
+	paddr = virt_to_phys(secondary_startup);
+	writel_relaxed(cpu_to_be32(paddr), dcfg_base + DCFG_CCSR_SCRATCHRW1);
+
+	iounmap(dcfg_base);
+}
+
+struct smp_operations  ls1021a_smp_ops __initdata = {
+	.smp_prepare_cpus	= ls1021a_smp_prepare_cpus,
+	.smp_boot_secondary	= ls1021a_boot_secondary,
+};
-- 
1.8.0

[PATCHv4 3/6] ARM: dts: Add initial LS1021A TWR board dts support

[Arnd Bergmann]

On Monday 22 September 2014 15:45:49 Jingchang Lu wrote:
> @@ -0,0 +1,117 @@
> +/*
> + * Copyright 2013-2014 Freescale Semiconductor, Inc.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + */

Can you change the license so this file is available under both GPL and
BSD or X11 license?

> +/dts-v1/;
> +#include "ls1021a.dtsi"
> +
> +/ {
> +       model = "LS1021A TWR Board";
> +
> +       aliases {
> +               enet2_rgmii_phy = &rgmii_phy1;
> +               enet0_sgmii_phy = &sgmii_phy2;
> +               enet1_sgmii_phy = &sgmii_phy0;
> +       };
> +};
> 

I've never seen alias nodes for mdio devices. What are these used for?
Shouldn't you use 'phy-handle' properties in the ethernet nodes instead?

	Arnd

[PATCHv4 3/6] ARM: dts: Add initial LS1021A TWR board dts support

[Jingchang Lu]

>-----Original Message-----
>From: Arnd Bergmann [mailto:arnd at arndb.de]
>Sent: Tuesday, September 23, 2014 10:54 PM
>To: Lu Jingchang-B35083
>Cc: Guo Shawn-R65073; mark.rutland at arm.com; linux-arm-
>kernel at lists.infradead.org; devicetree at vger.kernel.org; Lu Chen-B46807; Fu
>Chao-B44548
>Subject: Re: [PATCHv4 3/6] ARM: dts: Add initial LS1021A TWR board dts
>support
>
>On Monday 22 September 2014 15:45:49 Jingchang Lu wrote:
>> @@ -0,0 +1,117 @@
>> +/*
>> + * Copyright 2013-2014 Freescale Semiconductor, Inc.
>> + *
>> + * This program is free software; you can redistribute it and/or
>> +modify
>> + * it under the terms of the GNU General Public License as published
>> +by
>> + * the Free Software Foundation; either version 2 of the License, or
>> + * (at your option) any later version.
>> + */
>
>Can you change the license so this file is available under both GPL and
>BSD or X11 license?
>
I'd like to add this. Is there any template for my reference? Thanks.

>> +/dts-v1/;
>> +#include "ls1021a.dtsi"
>> +
>> +/ {
>> +       model = "LS1021A TWR Board";
>> +
>> +       aliases {
>> +               enet2_rgmii_phy = &rgmii_phy1;
>> +               enet0_sgmii_phy = &sgmii_phy2;
>> +               enet1_sgmii_phy = &sgmii_phy0;
>> +       };
>> +};
>>
>
>I've never seen alias nodes for mdio devices. What are these used for?
>Shouldn't you use 'phy-handle' properties in the ethernet nodes instead?
>
>	Arnd

The ethernet device nodes already have the phy-handle properties to their mdio nodes.

The alias for PHY nodes here is:
  The ethernet has two kind of PHY interface, one is SGMII, and the other is RGMII,
The selection is done by the reset configuration word(RCW), so Phy-handle properties
should be change properly to reflecting the PHY interface selection. This is done
by fixing up dtb in u-boot before booting the kernel. Thus the alias for PHY nodes
is added here for fdt finding the PHY nodes easily.

Best Regards,
Jingchang

[PATCHv4 3/6] ARM: dts: Add initial LS1021A TWR board dts support

[Arnd Bergmann]

On Wednesday 24 September 2014 05:47:53 Jingchang Lu wrote:
> 
> The ethernet device nodes already have the phy-handle properties to their mdio nodes.
> 
> The alias for PHY nodes here is:
>   The ethernet has two kind of PHY interface, one is SGMII, and the other is RGMII,
> The selection is done by the reset configuration word(RCW), so Phy-handle properties
> should be change properly to reflecting the PHY interface selection. This is done
> by fixing up dtb in u-boot before booting the kernel. Thus the alias for PHY nodes
> is added here for fdt finding the PHY nodes easily.

Ok, I see. I thought that this was what the labels in the dtb were supposed
to be used for. Can't you do the same thing in u-boot by using a label
as opposed to the alias?

IIRC you should be able to add an additional label like

+&mdio0 {
+       enet1_sgmii_phy: sgmii_phy0: ethernet-phy at 0 {
+               reg = <0x0>;
+       };

and then use libfdt to find the node through that, rather than through
the alias. I don't know how things are handled on other platforms, but
I think that was how it was initially thought up when we introduced
the fdt format on PowerPC.

	Arnd

[PATCHv4 3/6] ARM: dts: Add initial LS1021A TWR board dts support

[Jingchang Lu]

>-----Original Message-----
>From: Arnd Bergmann [mailto:arnd at arndb.de]
>Sent: Wednesday, September 24, 2014 5:36 PM
>To: Lu Jingchang-B35083
>Cc: Guo Shawn-R65073; mark.rutland at arm.com; linux-arm-
>kernel at lists.infradead.org; devicetree at vger.kernel.org; Lu Chen-B46807; Fu
>Chao-B44548
>Subject: Re: [PATCHv4 3/6] ARM: dts: Add initial LS1021A TWR board dts
>support
>
>On Wednesday 24 September 2014 05:47:53 Jingchang Lu wrote:
>>
>> The ethernet device nodes already have the phy-handle properties to
>their mdio nodes.
>>
>> The alias for PHY nodes here is:
>>   The ethernet has two kind of PHY interface, one is SGMII, and the
>> other is RGMII, The selection is done by the reset configuration
>> word(RCW), so Phy-handle properties should be change properly to
>> reflecting the PHY interface selection. This is done by fixing up dtb
>> in u-boot before booting the kernel. Thus the alias for PHY nodes is
>added here for fdt finding the PHY nodes easily.
>
>Ok, I see. I thought that this was what the labels in the dtb were
>supposed to be used for. Can't you do the same thing in u-boot by using a
>label as opposed to the alias?
>
>IIRC you should be able to add an additional label like
>
>+&mdio0 {
>+       enet1_sgmii_phy: sgmii_phy0: ethernet-phy at 0 {
>+               reg = <0x0>;
>+       };
>
>and then use libfdt to find the node through that, rather than through the
>alias. I don't know how things are handled on other platforms, but I think
>that was how it was initially thought up when we introduced the fdt format
>on PowerPC.
>
>	Arnd

We also do the phy-handle fixup on our PowerPC platform based on the aliases,
and so I adopt the same way to make these fixup consistent between SoCs.
And the u-boot fdt fixup code base on the aliases has been upstreamed, so may
we keep this aliases unchanged?

BTW, find a node by alias is easily, could you give me some clue on finding a node
by a label directly, Thanks.


Best Regards,
Jingchang

[PATCHv4 3/6] ARM: dts: Add initial LS1021A TWR board dts support

[Arnd Bergmann]

On Wednesday 24 September 2014 11:00:34 Jingchang Lu wrote:
> 
> We also do the phy-handle fixup on our PowerPC platform based on the aliases,
> and so I adopt the same way to make these fixup consistent between SoCs.
> And the u-boot fdt fixup code base on the aliases has been upstreamed, so may
> we keep this aliases unchanged?

I don't see a strong reason to change it, it just seemed strange to me.

> BTW, find a node by alias is easily, could you give me some clue on finding a node
> by a label directly, Thanks.

I haven't used libfdt in this way myself, so I don't know how it would
be done. However, the idea is that the labels in dts files end up as
ELF symbols in the dtb, so you can look them up by following the ELF
headers.

	Arnd

[PATCHv4 3/6] ARM: dts: Add initial LS1021A TWR board dts support

[Jingchang Lu]

>-----Original Message-----
>From: Arnd Bergmann [mailto:arnd at arndb.de]
>Sent: Wednesday, September 24, 2014 11:55 PM
>To: Lu Jingchang-B35083
>Cc: Guo Shawn-R65073; mark.rutland at arm.com; linux-arm-
>kernel at lists.infradead.org; devicetree at vger.kernel.org; Lu Chen-B46807; Fu
>Chao-B44548
>Subject: Re: [PATCHv4 3/6] ARM: dts: Add initial LS1021A TWR board dts
>support
>
>On Wednesday 24 September 2014 11:00:34 Jingchang Lu wrote:
>>
>> We also do the phy-handle fixup on our PowerPC platform based on the
>> aliases, and so I adopt the same way to make these fixup consistent
>between SoCs.
>> And the u-boot fdt fixup code base on the aliases has been upstreamed,
>> so may we keep this aliases unchanged?
>
>I don't see a strong reason to change it, it just seemed strange to me.
>
>> BTW, find a node by alias is easily, could you give me some clue on
>> finding a node by a label directly, Thanks.
>
>I haven't used libfdt in this way myself, so I don't know how it would be
>done. However, the idea is that the labels in dts files end up as ELF
>symbols in the dtb, so you can look them up by following the ELF headers.
>
>	Arnd

Libfdt doesn't provide way to find a node by label. Label is just a shortcut to
a full absolute path, it's useful in device tree source reference, but is hard
to find a label after build to dtb. Aliases just provide the way to save a
full absolute path in properties like label, but they can be find in dtb after
build so that fixup on dtb can find a node efficiently. So I think the aliases
for the phy nodes is also reasonable. Many others boards also use labels for
various dts nodes.
Thanks.

Best Regards,
Jingchang
 

[PATCHv4 3/6] ARM: dts: Add initial LS1021A TWR board dts support

[Arnd Bergmann]

On Thursday 25 September 2014 08:06:27 Jingchang Lu wrote:
> 
> Libfdt doesn't provide way to find a node by label. Label is just a shortcut to
> a full absolute path, it's useful in device tree source reference, but is hard
> to find a label after build to dtb. Aliases just provide the way to save a
> full absolute path in properties like label, but they can be find in dtb after
> build so that fixup on dtb can find a node efficiently. So I think the aliases
> for the phy nodes is also reasonable. Many others boards also use labels for
> various dts nodes.

Ok, fair enough.

I still think it would be a good idea in general to let all boot loaders
find nodes and properties by label, which in theory should be simpler
than finding them by aliases, but if they don't do that today it should
not stop your file from getting merged.

	Arnd

[PATCHv4 1/6] ARM: dts: Add SoC level device tree support for LS1021A

[Shawn Guo]

On Mon, Sep 22, 2014 at 03:45:47PM +0800, Jingchang Lu wrote:
> From: Jingchang Lu <b35083@freescale.com>
> 
> Add Freescale LS1021A SoC device tree support
> 
> Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com>
> Signed-off-by: Chenhui Zhao <chenhui.zhao@freescale.com>
> Signed-off-by: Suresh Gupta <suresh.gupta@freescale.com>
> Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
> Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com>
> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
> Signed-off-by: Chao Fu <b44548@freescale.com>
> Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com>
> Signed-off-by: Jingchang Lu <jingchang.lu@freescale.com>
> ---
>  arch/arm/boot/dts/ls1021a.dtsi | 539 +++++++++++++++++++++++++++++++++++++++++
>  1 file changed, 539 insertions(+)
>  create mode 100644 arch/arm/boot/dts/ls1021a.dtsi
> 
> diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi
> new file mode 100644
> index 0000000..b498838
> --- /dev/null
> +++ b/arch/arm/boot/dts/ls1021a.dtsi
> @@ -0,0 +1,539 @@
> +/*
> + * Copyright 2013-2014 Freescale Semiconductor, Inc.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + */
> +
> +#include "skeleton64.dtsi"
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> +/ {
> +	compatible = "fsl,ls1021a";
> +	interrupt-parent = <&gic>;
> +	#address-cells = <2>;
> +	#size-cells = <2>;

These two are already in skeleton64.dtsi.

> +
> +	aliases {
> +		serial0 = &lpuart0;
> +		serial1 = &lpuart1;
> +		serial2 = &lpuart2;
> +		serial3 = &lpuart3;
> +		serial4 = &lpuart4;
> +		serial5 = &lpuart5;
> +		ethernet0 = &enet0;
> +		ethernet1 = &enet1;
> +		ethernet2 = &enet2;
> +		sysclk = &sysclk;

Sort these aliases alphabetically.

> +	};
> +
> +	cpus {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		cpu at f00 {
> +			compatible = "arm,cortex-a7";
> +			device_type = "cpu";
> +			reg = <0xf00>;
> +		};
> +
> +		cpu at f01 {
> +			compatible = "arm,cortex-a7";
> +			device_type = "cpu";
> +			reg = <0xf01>;
> +		};
> +	};
> +
> +	timer {
> +		compatible = "arm,armv7-timer";
> +		interrupts = 	<GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,

For consistency, please use space than tab after "=".

> +				<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
> +				<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
> +				<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
> +	};
> +
> +	pmu {
> +		compatible = "arm,cortex-a7-pmu";
> +		interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
> +				<GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
> +	};
> +
> +	soc {
> +		compatible = "simple-bus";
> +		#address-cells = <2>;
> +		#size-cells = <2>;
> +		interrupt-parent = <&gic>;
> +		ranges;
> +
> +		gic: interrupt-controller at 1400000 {
> +			compatible = "arm,cortex-a7-gic";
> +			#interrupt-cells = <3>;
> +			interrupt-controller;
> +			reg = <0x0 0x1401000 0x0 0x1000>,
> +				<0x0 0x1402000 0x0 0x1000>,
> +				<0x0 0x1404000 0x0 0x2000>,
> +				<0x0 0x1406000 0x0 0x2000>;
> +			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
> +
> +		};
> +
> +		ifc: ifc at 1530000 {
> +			compatible = "fsl,ifc", "simple-bus";
> +			reg = <0x0 0x1530000 0x0 0x10000>;
> +			interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
> +		};
> +
> +		dcfg: dcfg at 1ee0000 {
> +			compatible = "fsl,ls1021a-dcfg", "syscon";
> +			reg = <0x0 0x1ee0000 0x0 0x10000>;
> +			big-endian;
> +		};
> +
> +		esdhc: esdhc at 1560000 {
> +			compatible = "fsl,esdhc";
> +			reg = <0x0 0x1560000 0x0 0x10000>;
> +			interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
> +			clock-frequency = <0>;
> +			voltage-ranges = <1800 1800 3300 3300>;
> +			sdhci,auto-cmd12;
> +			big-endian;
> +			bus-width = <4>;
> +			status = "disabled";
> +		};
> +
> +		scfg: scfg at 1570000 {
> +			compatible = "fsl,ls1021a-scfg", "syscon";
> +			reg = <0x0 0x1570000 0x0 0x10000>;
> +		};
> +
> +		crypto: crypto at 1700000 {
> +			compatible = "fsl,sec-v5.3", "fsl,sec-v5.0", "fsl,sec-v4.0";

Is it really necessary to have the compatible string so long with so
many version history.  In the end, device driver only needs one to bind
the device.

> +			fsl,sec-era = <4>;
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			reg		 = <0x0 0x1700000 0x0 0x100000>;
> +			ranges		 = <0x0 0x0 0x1700000 0x100000>;
> +			interrupts	 = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
> +
> +			sec_jr0: jr at 10000 {
> +				compatible = "fsl,sec-v5.3-job-ring",
> +				     "fsl,sec-v5.0-job-ring",
> +				     "fsl,sec-v4.0-job-ring";

Ditto

> +				reg = <0x10000 0x10000>;
> +				interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
> +			};
> +
> +			sec_jr1: jr at 20000 {

Is "jr" the name of the device name given by hardware manual?

> +				compatible = "fsl,sec-v5.3-job-ring",
> +				     "fsl,sec-v5.0-job-ring",
> +				     "fsl,sec-v4.0-job-ring";
> +				reg = <0x20000 0x10000>;
> +				interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
> +			};
> +
> +			sec_jr2: jr at 30000 {
> +				compatible = "fsl,sec-v5.3-job-ring",
> +				     "fsl,sec-v5.0-job-ring",
> +				     "fsl,sec-v4.0-job-ring";
> +				reg = <0x30000 0x10000>;
> +				interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
> +			};
> +
> +			sec_jr3: jr at 40000 {
> +				compatible = "fsl,sec-v5.3-job-ring",
> +				     "fsl,sec-v5.0-job-ring",
> +				     "fsl,sec-v4.0-job-ring";
> +				reg = <0x40000 0x10000>;
> +				interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
> +			};
> +
> +		};
> +
> +		clockgen: clocking at 1ee1000 {
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			ranges = <0x0 0x0 0x1ee1000 0x10000>;
> +
> +			sysclk: sysclk {
> +				compatible = "fixed-clock";
> +				#clock-cells = <0>;
> +				clock-output-names = "sysclk";
> +			};
> +
> +			cga_pll1: pll1 at 800 {

The node name should just be "pll".

> +				compatible = "fsl,qoriq-core-pll-2.0";
> +				#clock-cells = <1>;
> +				reg = <0x800 0x10>;
> +				clocks = <&sysclk>;
> +				clock-output-names = "cga-pll1", "cga-pll1-div2",
> +						"cga-pll1-div3", "cga-pll1-div4";
> +			};
> +
> +			platform_clk: pll at c00 {
> +				compatible = "fsl,qoriq-core-pll-2.0";
> +				#clock-cells = <1>;
> +				reg = <0xc00 0x10>;
> +				clocks = <&sysclk>;
> +				clock-output-names = "platform-clk", "platform-clk-div2";
> +			};
> +
> +			cluster1_clk: clk0c0 at 0 {
> +				compatible = "fsl,qoriq-core-mux-2.0";
> +				#clock-cells = <0>;
> +				reg = <0x0 0x10>;
> +				clock-names = "pll1cga", "pll1cga-div2";
> +				clocks = <&cga_pll1 0>, <&cga_pll1 2>;
> +				clock-output-names = "cluster1-clk";
> +			};
> +		};
> +
> +		dspi0: dspi at 2100000 {
> +			compatible = "fsl,vf610-dspi";
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			reg = <0x0 0x2100000 0x0 0x10000>;
> +			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
> +			clock-names = "dspi";
> +			clocks = <&platform_clk 1>;
> +			spi-num-chipselects = <5>;
> +			big-endian;
> +			status = "disabled";
> +		};
> +
> +		dspi1: dspi at 2110000 {
> +			compatible = "fsl,vf610-dspi";
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			reg = <0x0 0x2110000 0x0 0x10000>;
> +			interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
> +			clock-names = "dspi";
> +			clocks = <&platform_clk 1>;
> +			spi-num-chipselects = <5>;
> +			big-endian;
> +			status = "disabled";
> +		};
> +
> +		i2c0: i2c at 2180000 {
> +			compatible = "fsl,vf610-i2c";
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			reg = <0x0 0x2180000 0x0 0x10000>;
> +			interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
> +			clock-names = "i2c";
> +			clocks = <&platform_clk 1>;
> +			status = "disabled";
> +		};
> +
> +		i2c1: i2c at 2190000 {
> +			compatible = "fsl,vf610-i2c";
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			reg = <0x0 0x2190000 0x0 0x10000>;
> +			interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
> +			clock-names = "i2c";
> +			clocks = <&platform_clk 1>;
> +			status = "disabled";
> +		};
> +
> +		i2c2: i2c at 21a0000 {
> +			compatible = "fsl,vf610-i2c";
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			reg = <0x0 0x21a0000 0x0 0x10000>;
> +			interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
> +			clock-names = "i2c";
> +			clocks = <&platform_clk 1>;
> +			status = "disabled";
> +		};
> +
> +		uart0: serial at 21c0500 {
> +			compatible = "fsl,16550-FIFO64", "ns16550a";

We generally use lowercase only for compatible string.

> +			reg = <0x0 0x21c0500 0x0 0x100>;
> +			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
> +			clock-frequency = <0>;
> +			fifo-size = <15>;
> +			status = "disabled";
> +		};
> +
> +		uart1: serial at 21c0600 {
> +			compatible = "fsl,16550-FIFO64", "ns16550a";
> +			reg = <0x0 0x21c0600 0x0 0x100>;
> +			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
> +			clock-frequency = <0>;
> +			fifo-size = <15>;
> +			status = "disabled";
> +		};
> +
> +		uart2: serial at 21d0500 {
> +			compatible = "fsl,16550-FIFO64", "ns16550a";
> +			reg = <0x0 0x21d0500 0x0 0x100>;
> +			interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
> +			clock-frequency = <0>;
> +			fifo-size = <15>;
> +			status = "disabled";
> +		};
> +
> +		uart3: serial at 21d0600 {
> +			compatible = "fsl,16550-FIFO64", "ns16550a";
> +			reg = <0x0 0x21d0600 0x0 0x100>;
> +			interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
> +			clock-frequency = <0>;
> +			fifo-size = <15>;
> +			status = "disabled";
> +		};
> +
> +		lpuart0: serial at 2950000 {
> +			compatible = "fsl,ls1021a-lpuart";
> +			reg = <0x0 0x2950000 0x0 0x1000>;
> +			interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&sysclk>;
> +			clock-names = "ipg";
> +			status = "disabled";
> +		};
> +
> +		lpuart1: serial at 2960000 {
> +			compatible = "fsl,ls1021a-lpuart";
> +			reg = <0x0 0x2960000 0x0 0x1000>;
> +			interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&platform_clk 1>;
> +			clock-names = "ipg";
> +			status = "disabled";
> +		};
> +
> +		lpuart2: serial at 2970000 {
> +			compatible = "fsl,ls1021a-lpuart";
> +			reg = <0x0 0x2970000 0x0 0x1000>;
> +			interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&platform_clk 1>;
> +			clock-names = "ipg";
> +			status = "disabled";
> +		};
> +
> +		lpuart3: serial at 2980000 {
> +			compatible = "fsl,ls1021a-lpuart";
> +			reg = <0x0 0x2980000 0x0 0x1000>;
> +			interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&platform_clk 1>;
> +			clock-names = "ipg";
> +			status = "disabled";
> +		};
> +
> +		lpuart4: serial at 2990000 {
> +			compatible = "fsl,ls1021a-lpuart";
> +			reg = <0x0 0x2990000 0x0 0x1000>;
> +			interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&platform_clk 1>;
> +			clock-names = "ipg";
> +			status = "disabled";
> +		};
> +
> +		lpuart5: serial at 29a0000 {
> +			compatible = "fsl,ls1021a-lpuart";
> +			reg = <0x0 0x29a0000 0x0 0x1000>;
> +			interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&platform_clk 1>;
> +			clock-names = "ipg";
> +			status = "disabled";
> +		};
> +
> +		ftm0_1: ftm0_1 at 29d0000 {

ftm0_1?  It doesn't sounds like a good name for a timer device node.

> +			compatible = "fsl,ftm-timer";
> +			reg = <0x0 0x29d0000 0x0 0x10000>,
> +				<0x0 0x29e0000 0x0 0x10000>;
> +			interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
> +			clock-names = "ftm-evt", "ftm-src",
> +			        "ftm-evt-counter-en", "ftm-src-counter-en";
> +			clocks = <&platform_clk 1>, <&platform_clk 1>,
> +			       <&platform_clk 1>, <&platform_clk 1>;
> +			big-endian;
> +			status = "disabled";
> +		};
> +
> +		pwm3: ftm at 2a00000 {

"ftm" doesn't sounds like a good name for a pwm device node.

> +			compatible = "fsl,vf610-ftm-pwm";
> +			#pwm-cells = <3>;
> +			reg = <0x0 0x2a00000 0x0 0x10000>;
> +			interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
> +			clock-names = "ftm_sys", "ftm_ext",
> +				"ftm_fix", "ftm_cnt_clk_en";
> +			clocks = <&platform_clk 1>, <&platform_clk 1>,
> +				<&platform_clk 1>, <&platform_clk 1>;
> +			big-endian;
> +			status = "disabled";
> +		};
> +
> +		pwm6: ftm at 2a30000 {
> +			compatible = "fsl,vf610-ftm-pwm";
> +			#pwm-cells = <3>;
> +			reg = <0x0 0x2a30000 0x0 0x10000>;
> +			interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
> +			clock-names = "ftm_sys", "ftm_ext",
> +				"ftm_fix", "ftm_cnt_clk_en";
> +			clocks = <&platform_clk 1>, <&platform_clk 1>,
> +				<&platform_clk 1>, <&platform_clk 1>;
> +			big-endian;
> +			status = "disabled";
> +		};
> +
> +		pwm7: ftm at 2a40000 {
> +			compatible = "fsl,vf610-ftm-pwm";
> +			#pwm-cells = <3>;
> +			reg = <0x0 0x2a40000 0x0 0x10000>;
> +			interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
> +			clock-names = "ftm_sys", "ftm_ext",
> +				"ftm_fix", "ftm_cnt_clk_en";
> +			clocks = <&platform_clk 1>, <&platform_clk 1>,
> +				<&platform_clk 1>, <&platform_clk 1>;
> +			big-endian;
> +			status = "disabled";
> +		};
> +
> +		wdog0: wdog at 2ad0000 {

Use "watchdog" to name the node.

> +			compatible = "fsl,imx21-wdt";
> +			reg = <0x0 0x2ad0000 0x0 0x10000>;
> +			interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&platform_clk 1>;
> +			clock-names = "wdog";

The property is to describe the clock from wdog inside point of view,
not from outside, so "wdog" isn't a good description.

> +			big-endian;
> +		};
> +
> +		sai1: sai at 2b50000 {
> +			compatible = "fsl,vf610-sai";
> +			reg = <0x0 0x2b50000 0x0 0x10000>;
> +			interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&platform_clk 1>;
> +			clock-names = "sai";
> +			dma-names = "tx", "rx";
> +			dmas = <&edma0 1 47>,
> +				<&edma0 1 46>;
> +			big-endian-regs;

Is it a valid property for SAI device?  At least I cannot find in
Documentation/devicetree/bindings.

> +			status = "disabled";
> +		};
> +
> +		sai2: sai at 2b60000 {
> +			compatible = "fsl,vf610-sai";
> +			reg = <0x0 0x2b60000 0x0 0x10000>;
> +			interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&platform_clk 1>;
> +			clock-names = "sai";
> +			dma-names = "tx", "rx";
> +			dmas = <&edma0 1 45>,
> +				<&edma0 1 44>;
> +			big-endian-regs;
> +			status = "disabled";
> +		};
> +
> +		edma0: edma at 2c00000 {
> +			#dma-cells = <2>;
> +			compatible = "fsl,vf610-edma";
> +			reg = <0x0 0x2c00000 0x0 0x10000>,
> +				<0x0 0x2c10000 0x0 0x10000>,
> +				<0x0 0x2c20000 0x0 0x10000>;
> +			interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
> +					<GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupt-names = "edma-tx", "edma-err";
> +			dma-channels = <32>;
> +			big-endian;
> +			clock-names = "dmamux0", "dmamux1";
> +			clocks = <&platform_clk 1>,
> +				<&platform_clk 1>;
> +		};
> +
> +		mdio0: mdio at 2d24000 {
> +			compatible = "gianfar";
> +			device_type = "mdio";
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			reg = <0x0 0x2d24000 0x0 0x4000>;
> +		};
> +
> +		enet0: ethernet at 2d10000 {
> +			compatible = "fsl,etsec2";
> +			device_type = "network";
> +			#address-cells = <2>;
> +			#size-cells = <2>;
> +			interrupt-parent = <&gic>;
> +			model = "eTSEC";
> +			fsl,dma-endian-le;
> +			fsl,num_rx_queues = <0x1>;
> +			fsl,num_tx_queues = <0x1>;
> +			ranges;
> +
> +			queue-group at 0 {
> +				#address-cells = <1>;
> +				#size-cells = <1>;
> +				reg = <0x0 0x2d10000 0x0 0x8000>;
> +				fsl,rx-bit-map = <0xff>;
> +				fsl,tx-bit-map = <0xff>;
> +				interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
> +					<GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
> +					<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
> +			};
> +		};

Are the device tree bindings for this ethernet device accepted?  I
cannot find anything about it on even linux-next.

Shawn

> +
> +		enet1: ethernet at 2d50000 {
> +			compatible = "fsl,etsec2";
> +			device_type = "network";
> +			#address-cells = <2>;
> +			#size-cells = <2>;
> +			interrupt-parent = <&gic>;
> +			model = "eTSEC";
> +			fsl,dma-endian-le;
> +			fsl,num_rx_queues = <0x1>;
> +			fsl,num_tx_queues = <0x1>;
> +			ranges;
> +
> +			queue-group at 0 {
> +				#address-cells = <1>;
> +				#size-cells = <1>;
> +				reg = <0x0 0x2d50000 0x0 0x8000>;
> +				fsl,rx-bit-map = <0xff>;
> +				fsl,tx-bit-map = <0xff>;
> +				interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
> +					<GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
> +					<GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
> +			};
> +		};
> +
> +		enet2: ethernet at 2d90000 {
> +			compatible = "fsl,etsec2";
> +			device_type = "network";
> +			#address-cells = <2>;
> +			#size-cells = <2>;
> +			interrupt-parent = <&gic>;
> +			model = "eTSEC";
> +			fsl,dma-endian-le;
> +			fsl,num_rx_queues = <0x1>;
> +			fsl,num_tx_queues = <0x1>;
> +			ranges;
> +
> +			queue-group at 0 {
> +				#address-cells = <1>;
> +				#size-cells = <1>;
> +				reg = <0x0 0x2d90000 0x0 0x8000>;
> +				fsl,rx-bit-map = <0xff>;
> +				fsl,tx-bit-map = <0xff>;
> +				interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
> +					<GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
> +					<GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
> +			};
> +		};
> +
> +		usb at 8600000 {
> +			compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr";
> +			reg = <0x0 0x8600000 0x0 0x1000>;
> +			interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
> +			dr_mode = "host";
> +			phy_type = "ulpi";
> +		};
> +
> +		usb3 at 3100000 {
> +			compatible = "snps,dwc3";
> +			reg = <0x0 0x3100000 0x0 0x10000>;
> +			interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
> +			dr_mode = "host";
> +		};
> +	};
> +};
> -- 
> 1.8.0
> 

[PATCHv4 2/6] ARM: dts: Add initial LS1021A QDS board dts support

[Shawn Guo]

On Mon, Sep 22, 2014 at 03:45:48PM +0800, Jingchang Lu wrote:
> From: Jingchang Lu <b35083@freescale.com>
> 
> Signed-off-by: Alison Wang <alison.wang@freescale.com>
> Signed-off-by: Chao Fu <B44548@freescale.com>
> Signed-off-by: Jason Jin <Jason.Jin@freescale.com>
> Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com>
> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
> Signed-off-by: Jaiprakash Singh <b44839@freescale.com>
> Signed-off-by: Jingchang Lu <jingchang.lu@freescale.com>
> ---
>  arch/arm/boot/dts/Makefile        |   1 +
>  arch/arm/boot/dts/ls1021a-qds.dts | 285 ++++++++++++++++++++++++++++++++++++++
>  2 files changed, 286 insertions(+)
>  create mode 100644 arch/arm/boot/dts/ls1021a-qds.dts
> 
> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> index e12fe46..384aa74 100644
> --- a/arch/arm/boot/dts/Makefile
> +++ b/arch/arm/boot/dts/Makefile
> @@ -245,6 +245,7 @@ dtb-$(CONFIG_ARCH_MXC) += \
>  	imx6q-tx6q-1110.dtb \
>  	imx6sl-evk.dtb \
>  	imx6sx-sdb.dtb \
> +	ls1021a-qds.dtb \
>  	vf610-colibri-eval-v3.dtb \
>  	vf610-cosmic.dtb \
>  	vf610-twr.dtb
> diff --git a/arch/arm/boot/dts/ls1021a-qds.dts b/arch/arm/boot/dts/ls1021a-qds.dts
> new file mode 100644
> index 0000000..a0a95f51
> --- /dev/null
> +++ b/arch/arm/boot/dts/ls1021a-qds.dts
> @@ -0,0 +1,285 @@
> +/*
> + * Copyright 2013-2014 Freescale Semiconductor, Inc.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + */
> +
> +/dts-v1/;
> +#include "ls1021a.dtsi"
> +
> +/ {
> +	model = "LS1021A QDS Board";
> +
> +	aliases {
> +		enet0_rgmii_phy = &rgmii_phy1;
> +		enet1_rgmii_phy = &rgmii_phy2;
> +		enet2_rgmii_phy = &rgmii_phy3;
> +		enet0_sgmii_phy = &sgmii_phy1c;
> +		enet1_sgmii_phy = &sgmii_phy1d;
> +	};
> +
> +	soc {
> +		leds {

I think leds are board level devices and do not have to be under node
"soc"?

> +			compatible = "pwm-leds";

Please have a new line between property list and device node ...

> +			led0 {

Usually, the instance number shouldn't be directly encoded in node name,
but be part of node name in form of unit-address, i.e. led at 0.  That also
means we will need a 'reg' property for the node and the following for
the parent node.

	#address-cells = <1>;
	#size-cells = <0>;


> +				label = "led0";
> +				pwms = <&pwm3 0 150000 0>;
> +				max-brightness = <100>;
> +			};

Please also put a new line between device nodes.

> +			led1 {
> +				label = "led1";
> +				pwms = <&pwm3 1 150000 0>;
> +				max-brightness = <100>;
> +			};
> +			led2 {
> +				label = "led2";
> +				pwms = <&pwm3 2 150000 0>;
> +				max-brightness = <100>;
> +			};
> +			led3 {
> +				label = "led3";
> +				pwms = <&pwm3 3 150000 0>;
> +				max-brightness = <100>;
> +			};
> +			led4 {
> +				label = "led4";
> +				pwms = <&pwm3 4 150000 0>;
> +				max-brightness = <100>;
> +			};
> +			led5 {
> +				label = "led5";
> +				pwms = <&pwm3 5 150000 0>;
> +				max-brightness = <100>;
> +			};
> +			led6 {
> +				label = "led6";
> +				pwms = <&pwm3 6 150000 0>;
> +				max-brightness = <100>;
> +			};
> +			led7 {
> +				label = "led7";
> +				pwms = <&pwm3 7 150000 0>;
> +				max-brightness = <100>;
> +			};
> +		};
> +	};
> +};
> +
> +&dspi0 {
> +	bus-num = <0>;
> +	status = "okay";
> +
> +	dspiflash: at45db021d at 0 {
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		compatible = "atmel,at45db021d", "atmel,at45", "atmel,dataflash";
> +		spi-max-frequency = <16000000>;
> +		spi-cpol;
> +		spi-cpha;
> +		reg = <0>;
> +	};
> +};
> +
> +&enet0 {
> +	tbi-handle = <&tbi0>;

I cannot find this property in any binding doc.

> +	phy-handle = <&sgmii_phy1c>;
> +	phy-connection-type = "sgmii";
> +	status = "okay";
> +};
> +
> +&enet1 {
> +	tbi-handle = <&tbi0>;
> +	phy-handle = <&sgmii_phy1d>;
> +	phy-connection-type = "sgmii";
> +	status = "okay";
> +};
> +
> +&enet2 {
> +	phy-handle = <&rgmii_phy3>;
> +	phy-connection-type = "rgmii-id";
> +	status = "okay";
> +};
> +
> +&i2c0 {
> +	status = "okay";

Add a new line.

> +	pca9547 at 77 {
> +		compatible = "philips,pca9547";

Undocumented compatible.

> +		reg = <0x77>;
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		i2c at 0 {
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			reg = <0x0>;
> +
> +			rtc at 68 {
> +				compatible = "dallas,ds3232";
> +				reg = <0x68>;
> +				interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
> +			};
> +		};
> +
> +		i2c at 2 {
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			reg = <0x2>;
> +
> +			ina220 at 40 {
> +				compatible = "ti,ina220";
> +				reg = <0x40>;
> +				shunt-resistor = <1000>;
> +			};
> +
> +			ina220 at 41 {
> +				compatible = "ti,ina220";
> +				reg = <0x41>;
> +				shunt-resistor = <1000>;
> +			};
> +		};
> +
> +		i2c at 3 {
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			reg = <0x3>;
> +
> +			eeprom at 56 {
> +				compatible = "at24,24c512";

Undocumented property.

> +				reg = <0x56>;
> +			};
> +
> +			eeprom at 57 {
> +				compatible = "at24,24c512";
> +				reg = <0x57>;
> +			};
> +
> +			adt7461a at 4c {
> +				compatible = "adt7461a";

Shouldn't it be "adi,adt7461a"?  And if that's case, per
Documentation/devicetree/bindings/hwmon/lm90.txt, vcc-supply is a
required property.

> +				reg = <0x4c>;
> +			};
> +		};
> +
> +		i2c at 4 {
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			reg = <0x4>;
> +		};

What's this device?  Drop it and add it only when you actually need it.

> +	};
> +};
> +
> +&ifc {
> +	status = "okay";

I generally prefer to put 'status' at the bottom of the property list.

> +	#address-cells = <2>;
> +	#size-cells = <1>;
> +	/* NOR, NAND Flashes and FPGA on board */
> +	ranges = <0x0 0x0 0x0 0x60000000 0x08000000
> +		0x2 0x0 0x0 0x7e800000 0x00010000
> +		0x3 0x0 0x0 0x7fb00000 0x00000100>;
> +
> +		nor at 0,0 {

Drop one level of indentation.

> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			compatible = "cfi-flash";
> +			reg = <0x0 0x0 0x8000000>;
> +			bank-width = <2>;
> +			device-width = <1>;
> +		};
> +
> +		nand at 2,0 {
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			compatible = "fsl,ifc-nand";

"fsl,ifc" is a documented property, but "fsl,ifc-nand" is not.

> +			reg = <0x2 0x0 0x10000>;
> +		};
> +
> +		fpga: board-control at 3,0 {
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			compatible = "simple-bus";
> +			reg = <0x3 0x0 0x0000100>;
> +			bank-width = <1>;
> +			device-width = <1>;
> +			ranges = <0 3 0 0x100>;
> +
> +			mdio-mux-emi1 {
> +				compatible = "mdio-mux-mmioreg";
> +				mdio-parent-bus = <&mdio0>;
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +				reg = <0x54 1>; /* BRDCFG4 */
> +				mux-mask = <0xe0>; /* EMI1[2:0] */
> +
> +				/* Onboard PHYs */
> +				ls1021amdio0: mdio at 0 {
> +					reg = <0>;
> +					#address-cells = <1>;
> +					#size-cells = <0>;
> +					rgmii_phy1: ethernet-phy at 1 {
> +						reg = <0x1>;
> +					};
> +				};

Have a new line.

Shawn

> +				ls1021amdio1: mdio at 20 {
> +					reg = <0x20>;
> +					#address-cells = <1>;
> +					#size-cells = <0>;
> +					rgmii_phy2: ethernet-phy at 2 {
> +						reg = <0x2>;
> +					};
> +				};
> +				ls1021amdio2: mdio at 40 {
> +					reg = <0x40>;
> +					#address-cells = <1>;
> +					#size-cells = <0>;
> +					rgmii_phy3: ethernet-phy at 3 {
> +						reg = <0x3>;
> +					};
> +				};
> +				ls1021amdio3: mdio at 60 {
> +					reg = <0x60>;
> +					#address-cells = <1>;
> +					#size-cells = <0>;
> +					sgmii_phy1c: ethernet-phy at 1c {
> +						reg = <0x1c>;
> +					};
> +				};
> +				ls1021amdio4: mdio at 80 {
> +					reg = <0x80>;
> +					#address-cells = <1>;
> +					#size-cells = <0>;
> +					sgmii_phy1d: ethernet-phy at 1d {
> +						reg = <0x1d>;
> +					};
> +				};
> +			};
> +		};
> +};
> +
> +&lpuart0 {
> +	status = "okay";
> +};
> +
> +&mdio0 {
> +	tbi0: tbi-phy at 8 {
> +		reg = <0x8>;
> +		device_type = "tbi-phy";
> +	};
> +};
> +
> +&pwm3 {
> +	status = "okay";
> +};
> +
> +&pwm7 {
> +	status = "okay";
> +};
> +
> +&uart0 {
> +	status = "okay";
> +};
> +
> +&uart1 {
> +	status = "okay";
> +};
> -- 
> 1.8.0
> 

[PATCHv4 4/6] dt-bindings: arm: add Freescale LS1021A SoC device tree binding

[Shawn Guo]

On Mon, Sep 22, 2014 at 03:45:50PM +0800, Jingchang Lu wrote:
> Signed-off-by: Jingchang Lu <jingchang.lu@freescale.com>
> ---
>  Documentation/devicetree/bindings/arm/fsl.txt | 38 +++++++++++++++++++++++++++
>  1 file changed, 38 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/arm/fsl.txt b/Documentation/devicetree/bindings/arm/fsl.txt
> index e935d7d..2e0ba09 100644
> --- a/Documentation/devicetree/bindings/arm/fsl.txt
> +++ b/Documentation/devicetree/bindings/arm/fsl.txt
> @@ -74,3 +74,41 @@ Required root node properties:
>  i.MX6q generic board
>  Required root node properties:
>      - compatible = "fsl,imx6q";
> +
> +
> +Freescale LS1021A Platform Device Tree Bindings
> +------------------------------------------------
> +
> +Required root node compatible properties:
> +  - compatible = "fsl,ls1021a";
> +
> +Freescale LS1021A SoC-specific Device Tree Bindings
> +-------------------------------------------
> +
> +Freescale SCFG
> +  scfg is the supplemental configuration unit, that provides SoC specific

s/scfg/SCFG

> +configuration and status registers for the chip. Such as getting PEX port
> +status.
> +  Required properties:
> +  - compatible: should be "fsl,ls1021a-scfg"
> +  - reg: should contain base address and length of SCFG memory-mapped registers
> +
> +Example:
> +	scfg: scfg at 1570000 {
> +		compatible = "fsl,ls1021a-scfg";
> +		reg = <0x0 0x1570000 0x0 0x10000>;
> +	};
> +
> +Freescale DCFG
> +  dcfg is the device configuration unit, that provides general purpose

s/dcfg/DCFG

Shawn

> +configuration and status for the device. Such as setting the secondary
> +core start address and release the secondary core from holdoff and startup.
> +  Required properties:
> +  - compatible: should be "fsl,ls1021a-dcfg"
> +  - reg : should contain base address and length of DCFG memory-mapped registers
> +
> +Example:
> +	dcfg: dcfg at 1ee0000 {
> +		compatible = "fsl,ls1021a-dcfg";
> +		reg = <0x0 0x1ee0000 0x0 0x10000>;
> +	};
> -- 
> 1.8.0
> 

[PATCHv4 5/6] ARM: imx: Add initial support for Freescale LS1021A

[Shawn Guo]

On Mon, Sep 22, 2014 at 03:45:51PM +0800, Jingchang Lu wrote:
> From: Jingchang Lu <b35083@freescale.com>
> 
> The LS1021A SoC is a dual-core Cortex-A7 based processor,
> this add the initial support for it.
> 
> Signed-off-by: Jingchang Lu <b35083@freescale.com>
> ---
>  arch/arm/mach-imx/Kconfig        | 14 ++++++++++++++
>  arch/arm/mach-imx/Makefile       |  2 ++
>  arch/arm/mach-imx/mach-ls1021a.c | 21 +++++++++++++++++++++
>  3 files changed, 37 insertions(+)
>  create mode 100644 arch/arm/mach-imx/mach-ls1021a.c
> 
> diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
> index 11b2957..2cc64a3 100644
> --- a/arch/arm/mach-imx/Kconfig
> +++ b/arch/arm/mach-imx/Kconfig
> @@ -639,6 +639,20 @@ config SOC_VF610
>  	help
>  	  This enable support for Freescale Vybrid VF610 processor.
>  
> +config SOC_LS1021A
> +	bool "Freescale LS1021A support"
> +	select CPU_V7

Has been selected by ARCH_MULTI_V7.

> +	select ARM_GIC
> +	select CLKSRC_OF

Has been selected by ARCH_MULTIPLATFORM.

> +	select HAVE_ARM_ARCH_TIMER
> +	select HAVE_SMP

Has been selected by ARCH_MULTI_V7.

> +	select MIGHT_HAVE_PCI

Has been selected by ARCH_MULTIPLATFORM.

Shawn

> +	select PCI_DOMAINS if PCI
> +	select ZONE_DMA if ARM_LPAE
> +
> +	help
> +	  This enable support for Freescale LS1021A processor.
> +
>  endif
>  
>  source "arch/arm/mach-imx/devices/Kconfig"
> diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
> index 6e4fcd8..ce137bc 100644
> --- a/arch/arm/mach-imx/Makefile
> +++ b/arch/arm/mach-imx/Makefile
> @@ -110,4 +110,6 @@ obj-$(CONFIG_SOC_IMX53) += mach-imx53.o
>  
>  obj-$(CONFIG_SOC_VF610) += clk-vf610.o mach-vf610.o
>  
> +obj-$(CONFIG_SOC_LS1021A) += mach-ls1021a.o
> +
>  obj-y += devices/
> diff --git a/arch/arm/mach-imx/mach-ls1021a.c b/arch/arm/mach-imx/mach-ls1021a.c
> new file mode 100644
> index 0000000..9d2034b
> --- /dev/null
> +++ b/arch/arm/mach-imx/mach-ls1021a.c
> @@ -0,0 +1,21 @@
> +/*
> + * Copyright 2013-2014 Freescale Semiconductor, Inc.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + */
> +
> +#include <asm/mach/arch.h>
> +
> +#include "common.h"
> +
> +static const char * const ls1021a_dt_compat[] __initconst = {
> +	"fsl,ls1021a",
> +	NULL,
> +};
> +
> +DT_MACHINE_START(LS1021A, "Freescale LS1021A")
> +	.dt_compat	= ls1021a_dt_compat,
> +MACHINE_END
> -- 
> 1.8.0
> 

[PATCHv4 6/6] ARM: imx: Add Freescale LS1021A SMP support

[Shawn Guo]

On Mon, Sep 22, 2014 at 03:45:52PM +0800, Jingchang Lu wrote:
> From: Jingchang Lu <b35083@freescale.com>
> 
> Freescale LS1021A SoCs deploy two cortex-A7 processors,
> this adds bring-up support for the secondary core.
> 
> Signed-off-by: Jingchang Lu <b35083@freescale.com>
> ---
>  arch/arm/mach-imx/Makefile       |  2 +-
>  arch/arm/mach-imx/common.h       |  1 +
>  arch/arm/mach-imx/mach-ls1021a.c |  1 +
>  arch/arm/mach-imx/platsmp.c      | 32 ++++++++++++++++++++++++++++++++
>  4 files changed, 35 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
> index ce137bc..38d75e2 100644
> --- a/arch/arm/mach-imx/Makefile
> +++ b/arch/arm/mach-imx/Makefile
> @@ -89,7 +89,7 @@ obj-$(CONFIG_HAVE_IMX_ANATOP) += anatop.o
>  obj-$(CONFIG_HAVE_IMX_GPC) += gpc.o
>  obj-$(CONFIG_HAVE_IMX_MMDC) += mmdc.o
>  obj-$(CONFIG_HAVE_IMX_SRC) += src.o
> -ifdef CONFIG_SOC_IMX6
> +ifneq ($(CONFIG_SOC_IMX6)$(CONFIG_SOC_LS1021A),)
>  AFLAGS_headsmp.o :=-Wa,-march=armv7-a
>  obj-$(CONFIG_SMP) += headsmp.o platsmp.o
>  obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
> diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h
> index 1dabf43..c473ca5 100644
> --- a/arch/arm/mach-imx/common.h
> +++ b/arch/arm/mach-imx/common.h
> @@ -157,5 +157,6 @@ static inline void imx_init_l2cache(void) {}
>  #endif
>  
>  extern struct smp_operations imx_smp_ops;
> +extern struct smp_operations ls1021a_smp_ops;
>  
>  #endif
> diff --git a/arch/arm/mach-imx/mach-ls1021a.c b/arch/arm/mach-imx/mach-ls1021a.c
> index 9d2034b..b89c858 100644
> --- a/arch/arm/mach-imx/mach-ls1021a.c
> +++ b/arch/arm/mach-imx/mach-ls1021a.c
> @@ -17,5 +17,6 @@ static const char * const ls1021a_dt_compat[] __initconst = {
>  };
>  
>  DT_MACHINE_START(LS1021A, "Freescale LS1021A")
> +	.smp		= smp_ops(ls1021a_smp_ops),
>  	.dt_compat	= ls1021a_dt_compat,
>  MACHINE_END
> diff --git a/arch/arm/mach-imx/platsmp.c b/arch/arm/mach-imx/platsmp.c
> index 771bd25..62376f0 100644
> --- a/arch/arm/mach-imx/platsmp.c
> +++ b/arch/arm/mach-imx/platsmp.c
> @@ -16,6 +16,8 @@
>  #include <asm/page.h>
>  #include <asm/smp_scu.h>
>  #include <asm/mach/map.h>
> +#include <linux/of.h>
> +#include <linux/of_address.h>

Move them above to the <linux/*> group of headers.

Shawn

>  
>  #include "common.h"
>  #include "hardware.h"
> @@ -94,3 +96,33 @@ struct smp_operations  imx_smp_ops __initdata = {
>  	.cpu_kill		= imx_cpu_kill,
>  #endif
>  };
> +
> +#define DCFG_CCSR_SCRATCHRW1	0x200
> +
> +static int ls1021a_boot_secondary(unsigned int cpu, struct task_struct *idle)
> +{
> +	arch_send_wakeup_ipi_mask(cpumask_of(cpu));
> +
> +	return 0;
> +}
> +
> +static void __init ls1021a_smp_prepare_cpus(unsigned int max_cpus)
> +{
> +	struct device_node *np;
> +	void __iomem *dcfg_base;
> +	unsigned long paddr;
> +
> +	np = of_find_compatible_node(NULL, NULL, "fsl,ls1021a-dcfg");
> +	dcfg_base = of_iomap(np, 0);
> +	BUG_ON(!dcfg_base);
> +
> +	paddr = virt_to_phys(secondary_startup);
> +	writel_relaxed(cpu_to_be32(paddr), dcfg_base + DCFG_CCSR_SCRATCHRW1);
> +
> +	iounmap(dcfg_base);
> +}
> +
> +struct smp_operations  ls1021a_smp_ops __initdata = {
> +	.smp_prepare_cpus	= ls1021a_smp_prepare_cpus,
> +	.smp_boot_secondary	= ls1021a_boot_secondary,
> +};
> -- 
> 1.8.0
> 

[PATCHv4 2/6] ARM: dts: Add initial LS1021A QDS board dts support

[Li.Xiubo at freescale.com]

Hi,

[...]
> > +
> > +	soc {
> > +		leds {
> 
> I think leds are board level devices and do not have to be under node
> "soc"?
> 
@Shawn,
Yes, it is.

@Jingchang,
For now we could just remove the led nodes here. There hasn't any real leds
On QDS(and for now we have to test their output pulse).

So this could be added later when need.

> > +			compatible = "pwm-leds";
> 
> Please have a new line between property list and device node ...
> 
This and the following issues about led will be fixed when adding this node separately
In the future.

[...]

Thanks,

BRs
Xiubo

[PATCHv4 2/6] ARM: dts: Add initial LS1021A QDS board dts support

[Jingchang Lu]

>-----Original Message-----
>From: Shawn Guo [mailto:shawn.guo at freescale.com]
>Sent: Friday, September 26, 2014 2:14 PM
>To: Lu Jingchang-B35083
>Cc: arnd at arndb.de; mark.rutland at arm.com; linux-arm-
>kernel at lists.infradead.org; devicetree at vger.kernel.org; Lu Jingchang-
>B35083; Wang Huan-B18965; Fu Chao-B44548; Jin Zhengxiong-R64188; Xiubo Li-
>B47053; Sharma Bhupesh-B45370; Singh Jaiprakash-B44839
>Subject: Re: [PATCHv4 2/6] ARM: dts: Add initial LS1021A QDS board dts
>support
>
>On Mon, Sep 22, 2014 at 03:45:48PM +0800, Jingchang Lu wrote:
>> From: Jingchang Lu <b35083@freescale.com>
>>
>> Signed-off-by: Alison Wang <alison.wang@freescale.com>
>> Signed-off-by: Chao Fu <B44548@freescale.com>
>> Signed-off-by: Jason Jin <Jason.Jin@freescale.com>
>> Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com>
>> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
>> Signed-off-by: Jaiprakash Singh <b44839@freescale.com>
>> Signed-off-by: Jingchang Lu <jingchang.lu@freescale.com>
>> ---
>>  arch/arm/boot/dts/Makefile        |   1 +
>>  arch/arm/boot/dts/ls1021a-qds.dts | 285
>> ++++++++++++++++++++++++++++++++++++++
>>  2 files changed, 286 insertions(+)
>>  create mode 100644 arch/arm/boot/dts/ls1021a-qds.dts
>>
[ ... ]
>> +
>> +&enet0 {
>> +	tbi-handle = <&tbi0>;
>
>I cannot find this property in any binding doc.
This property has been used on PowerPC platform for a long time, I will investigate its binding. Thanks.

>
>> +	phy-handle = <&sgmii_phy1c>;
>> +	phy-connection-type = "sgmii";
>> +	status = "okay";
>> +};
>> +
>> +&enet1 {
>> +	tbi-handle = <&tbi0>;
>> +	phy-handle = <&sgmii_phy1d>;
>> +	phy-connection-type = "sgmii";
>> +	status = "okay";
>> +};
>> +
>> +&enet2 {
>> +	phy-handle = <&rgmii_phy3>;
>> +	phy-connection-type = "rgmii-id";
>> +	status = "okay";
>> +};
>> +
>> +&i2c0 {
>> +	status = "okay";
>
>Add a new line.
>
>> +	pca9547 at 77 {
>> +		compatible = "philips,pca9547";
>
>Undocumented compatible.
I will check this, if it is not documented, I will remove this since the i2c attached device doesn't rely on the compatible. Thanks. 
>
>> +		reg = <0x77>;
>> +		#address-cells = <1>;
>> +		#size-cells = <0>;
>> +
>> +		i2c at 0 {
>> +			#address-cells = <1>;
>> +			#size-cells = <0>;
>> +			reg = <0x0>;
>> +
>> +			rtc at 68 {
>> +				compatible = "dallas,ds3232";
>> +				reg = <0x68>;
>> +				interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
>> +			};
>> +		};
>> +
>> +		i2c at 2 {
>> +			#address-cells = <1>;
>> +			#size-cells = <0>;
>> +			reg = <0x2>;
>> +
>> +			ina220 at 40 {
>> +				compatible = "ti,ina220";
>> +				reg = <0x40>;
>> +				shunt-resistor = <1000>;
>> +			};
>> +
>> +			ina220 at 41 {
>> +				compatible = "ti,ina220";
>> +				reg = <0x41>;
>> +				shunt-resistor = <1000>;
>> +			};
>> +		};
>> +
>> +		i2c at 3 {
>> +			#address-cells = <1>;
>> +			#size-cells = <0>;
>> +			reg = <0x3>;
>> +
>> +			eeprom at 56 {
>> +				compatible = "at24,24c512";
>
>Undocumented property.
It documented in Documentation/devicetree/bindings/eeprom.txt as the form of "<manufacturer>,<type>". Thanks.
>
>> +				reg = <0x56>;
>> +			};
>> +
>> +			eeprom at 57 {
>> +				compatible = "at24,24c512";
>> +				reg = <0x57>;
>> +			};
>> +
>> +			adt7461a at 4c {
>> +				compatible = "adt7461a";
>
>Shouldn't it be "adi,adt7461a"?  And if that's case, per
>Documentation/devicetree/bindings/hwmon/lm90.txt, vcc-supply is a required
>property.
Yes, I will update this. Thanks.
>
>> +				reg = <0x4c>;
>> +			};
>> +		};
>> +
>> +		i2c at 4 {
>> +			#address-cells = <1>;
>> +			#size-cells = <0>;
>> +			reg = <0x4>;
>> +		};
>
>What's this device?  Drop it and add it only when you actually need it.
I will remove this, thanks.

Best Regards,
Jingchang

[PATCHv4 2/6] ARM: dts: Add initial LS1021A QDS board dts support

[Arnd Bergmann]

On Sunday 28 September 2014 08:48:17 Jingchang Lu wrote:
> >> +            i2c at 3 {
> >> +                    #address-cells = <1>;
> >> +                    #size-cells = <0>;
> >> +                    reg = <0x3>;
> >> +
> >> +                    eeprom at 56 {
> >> +                            compatible = "at24,24c512";
> >
> >Undocumented property.
> It documented in Documentation/devicetree/bindings/eeprom.txt as the form of "<manufacturer>,<type>". Thanks.
> >
> 

The documented vendor name for Atmel is "atmel", not "at24".

	Arnd