From: "liwei (GF)" <liwei391@huawei.com>
To: Leo Yan <leo.yan@linaro.org>
Cc: Mark Rutland <mark.rutland@arm.com>,
Will Deacon <will@kernel.org>,
Suzuki K Poulose <suzuki.poulose@arm.com>,
Alexander Shishkin <alexander.shishkin@linux.intel.com>,
Catalin Marinas <catalin.marinas@arm.com>,
Adrian Hunter <adrian.hunter@intel.com>,
Arnaldo Carvalho de Melo <acme@kernel.org>,
linux-kernel@vger.kernel.org, zhangshaokun@hisilicon.com,
Peter Zijlstra <peterz@infradead.org>,
Ingo Molnar <mingo@redhat.com>, James Clark <james.clark@arm.com>,
guohanjun@huawei.com, Namhyung Kim <namhyung@kernel.org>,
Jiri Olsa <jolsa@redhat.com>,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH 2/4] perf: arm-spe: Add support for ARMv8.3-SPE
Date: Wed, 29 Jul 2020 15:21:20 +0800 [thread overview]
Message-ID: <a8f9df67-adf1-09e7-b117-ff4163cc2a03@huawei.com> (raw)
In-Reply-To: <20200729062951.GE4343@leoy-ThinkPad-X240s>
Hi Leo,
On 2020/7/29 14:29, Leo Yan wrote:
> On Fri, Jul 24, 2020 at 05:16:05PM +0800, Wei Li wrote:
>> Armv8.3 extends the SPE by adding:
>> - Alignment field in the Events packet, and filtering on this event
>> using PMSEVFR_EL1.
>> - Support for the Scalable Vector Extension (SVE).
>>
>> The main additions for SVE are:
>> - Recording the vector length for SVE operations in the Operation Type
>> packet. It is not possible to filter on vector length.
>> - Incomplete predicate and empty predicate fields in the Events packet,
>> and filtering on these events using PMSEVFR_EL1.
>
> This comment description is not relevant with the changes in this
> patch, so could remove them.
>
>> Add the corresponding decode process of Events packet and Operation Type
>> packet in perf tool.
>
> This patch is to add the raw dumping for Events packet and Operation Type
> packet.
>
>> Signed-off-by: Wei Li <liwei391@huawei.com>
>> ---
>> .../arm-spe-decoder/arm-spe-pkt-decoder.c | 69 ++++++++++++++++++-
>> 1 file changed, 67 insertions(+), 2 deletions(-)
>>
>> diff --git a/tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.c b/tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.c
>> index b94001b756c7..10a3692839de 100644
>> --- a/tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.c
>> +++ b/tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.c
>> @@ -347,6 +347,24 @@ int arm_spe_pkt_desc(const struct arm_spe_pkt *packet, char *buf,
>> blen -= ret;
>> }
>> }
>> + if (idx > 2) {
>> + if (payload & 0x800) {
>> + ret = snprintf(buf, buf_len, " ALIGNMENT");
>> + buf += ret;
>> + blen -= ret;
>> + }
>> + if (payload & 0x20000) {
>> + ret = snprintf(buf, buf_len, " SVE-PRED-PARTIAL");
>> + buf += ret;
>> + blen -= ret;
>> + }
>> + if (payload & 0x40000) {
>> + ret = snprintf(buf, buf_len, " SVE-PRED-EMPTY");
>> + buf += ret;
>> + blen -= ret;
>> + }
>> + }
>> +
>
> Correct.
>
>> if (ret < 0)
>> return ret;
>> blen -= ret;
>> @@ -354,8 +372,38 @@ int arm_spe_pkt_desc(const struct arm_spe_pkt *packet, char *buf,
>> }
>> case ARM_SPE_OP_TYPE:
>> switch (idx) {
>> - case 0: return snprintf(buf, buf_len, "%s", payload & 0x1 ?
>> - "COND-SELECT" : "INSN-OTHER");
>> + case 0: {
>> + if (payload & 0x8) {
>
> Some nitpicks for packet format checking ...
>
> For SVE operation, the payload partten is: 0b0xxx1xx0.
>
> So it's good to check the partten like:
>
> /* SVE operation subclass is: 0b0xxx1xx0 */
> if ((payload & 0x8081) == 0x80) {
> ....
> }
>
> If later the packet format is extended, this will not introduce any
> confliction.
Get it, but i think what you are really meaning is:
if ((payload & 0x89) == 0x80) {
...
}
>
>> + size_t blen = buf_len;
>> +
>> + ret = snprintf(buf, buf_len, "SVE-OTHER");
>> + buf += ret;
>> + blen -= ret;
>> + if (payload & 0x2) {
>
> Here should express as binary results: " FP" or " INT".
I think this is a style choice, i add these just like the current code where
processing "AT", "EXCL", "AR", "COND" and so on. So should we modify all the corresponding code together?
>
>> + ret = snprintf(buf, buf_len, " FP");
>> + buf += ret;
>> + blen -= ret;
>> + }
>> + if (payload & 0x4) {
>> + ret = snprintf(buf, buf_len, " PRED");
>
> Here should express as binary results: " PRED" or " NOT-PRED".
Ditto.
>
>> + buf += ret;
>> + blen -= ret;
>> + }
>> + if (payload & 0x70) {
>
> This is incorrect. If bits[6:4] is zero, it presents vector length is 32 bits.
>
I am a little confused here.
Refer to the ARM DDI 0487F.b (ID040120), page D10-2830, if bits[6:4] is zero,
it presents vector length is 32 bits indeed.
>> + ret = snprintf(buf, buf_len, " EVL %d",
>> + 32 << ((payload & 0x70) >> 4));
>> + buf += ret;
>> + blen -= ret;
>> + }
>> + if (ret < 0)
>> + return ret;
>> + blen -= ret;
>> + return buf_len - blen;
>> + } else {
>
> Here we can check with more accurate format as defined in ARMv8 ARM:
>
> /* Other operation subclass is: 0b0000000x */
> if ((payload & 0xfe) == 0x0) {
> ....
> }
>
>> + return snprintf(buf, buf_len, "%s", payload & 0x1 ?
>> + "COND-SELECT" : "INSN-OTHER");
>> + }
>> + }
>> case 1: {
>> size_t blen = buf_len;
>>
>> @@ -385,6 +433,23 @@ int arm_spe_pkt_desc(const struct arm_spe_pkt *packet, char *buf,
>> ret = snprintf(buf, buf_len, " SIMD-FP");
>> buf += ret;
>> blen -= ret;
>> + } else if (payload & 0x8) {
>> + if (payload & 0x4) {
>> + ret = snprintf(buf, buf_len, " PRED");
>
> Here should express as binary results: " PRED" or " NOT-PRED".
Ditto.
>> + buf += ret;
>> + blen -= ret;
>> + }
>> + if (payload & 0x70) {
>
> This is incorrect. If bits[6:4] is zero, it presents vector length is 32 bits.
Refer to the ARM DDI 0487F.b (ID040120), page D10-2832, if bits[6:4] is zero,
it presents vector length is 32 bits indeed.
>> + ret = snprintf(buf, buf_len, " EVL %d",
>> + 32 << ((payload & 0x70) >> 4));
>> + buf += ret;
>> + blen -= ret;
>> + }
>> + if (payload & 0x80) {
>> + ret = snprintf(buf, buf_len, " SG");
>
> Here should express as binary results: " SG" or " NOT-SG".
Thanks,
Wei
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next prev parent reply other threads:[~2020-07-29 7:23 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-07-24 9:16 [PATCH 0/4] Add support for ARMv8.3-SPE Wei Li
2020-07-24 9:16 ` [PATCH 1/4] drivers/perf: " Wei Li
2020-07-28 12:27 ` Leo Yan
2020-07-28 13:24 ` liwei (GF)
2020-07-29 7:08 ` Leo Yan
2020-07-29 9:12 ` Suzuki K Poulose
2020-07-30 8:14 ` Leo Yan
2020-07-31 12:18 ` liwei (GF)
2020-07-31 14:01 ` Suzuki K Poulose
2020-09-07 12:51 ` Will Deacon
2020-09-29 8:17 ` liwei (GF)
2020-07-24 9:16 ` [PATCH 2/4] perf: arm-spe: " Wei Li
2020-07-29 6:29 ` Leo Yan
2020-07-29 7:21 ` liwei (GF) [this message]
2020-07-29 7:28 ` Leo Yan
2020-07-29 7:42 ` liwei (GF)
2020-08-17 15:04 ` Leo Yan
2020-07-24 9:16 ` [PATCH 3/4] perf auxtrace: Add new itrace options " Wei Li
2020-07-29 6:51 ` Leo Yan
2020-07-24 9:16 ` [PATCH 4/4] perf: arm-spe: Synthesize new events " Wei Li
2020-07-28 12:06 ` [PATCH 0/4] Add support " Arnaldo Carvalho de Melo
2020-07-28 12:41 ` Leo Yan
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