[PATCH 0/5] NanoPC-T4 (and a bit of NanoPi M4) support

[PATCH 0/5] NanoPC-T4 (and a bit of NanoPi M4) support

[Robin Murphy]

Hi all,

Since I finally got to spend some quality time with my NanoPC-T4 over
the holidays, I set to testing Tomeu's v4 patch, and ended up poring
over the schematics of all 3 boards and doing a fair bit more hacking.
I've taken the liberty of addressing the remaining review comments and
posting it as v5 here so as to also start adding stuff on top. My
current step is trying to get Wifi and Bluetooth working reliably...

Robin.


Robin Murphy (4):
  arm64: dts: rockchip: Add DT for NanoPi M4
  arm64: dts: rockchip: Refine nanopi4 differences
  arm64: dts: rockchip: Add NanoPC-T4 IR receiver
  arm64: dts: rockchip: Fix nanopi4 uSD card detect

Tomeu Vizoso (1):
  arm64: dts: rockchip: Add DT for NanoPC-T4

 .../devicetree/bindings/arm/rockchip.yaml     |  10 +
 arch/arm64/boot/dts/rockchip/Makefile         |   2 +
 .../boot/dts/rockchip/rk3399-nanopc-t4.dts    |  91 +++
 .../boot/dts/rockchip/rk3399-nanopi-m4.dts    |  66 ++
 .../boot/dts/rockchip/rk3399-nanopi4.dtsi     | 677 ++++++++++++++++++
 5 files changed, 846 insertions(+)
 create mode 100644 arch/arm64/boot/dts/rockchip/rk3399-nanopc-t4.dts
 create mode 100644 arch/arm64/boot/dts/rockchip/rk3399-nanopi-m4.dts
 create mode 100644 arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi

-- 
2.17.1


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[PATCH v5 1/5] arm64: dts: rockchip: Add DT for NanoPC-T4

[Robin Murphy]

From: Tomeu Vizoso <tomeu.vizoso@collabora.com>

This adds a device tree for the NanoPC-T4 SBC, which is based on the
Rockchip RK3399 SoC and marketed by FriendlyELEC.

Known working:

- Serial
- Ethernet
- HDMI
- USB 2.0

All of the interesting stuff is in a .dtsi because there are at least
two other boards that share most of it: NanoPi M4 and NanoPi NEO4.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Rob Herring <robh@kernel.org>
[rm: various further cleanup]
Signed-off-by: Robin Murphy <robin.murphy@arm.com>
---

v5:
- Fix remaining unit address/node name errors (RobH)
- Rebase binding to DT-schema
- Prune redundant properties
- Rename a few things to correlate better with schematics
- Sort properties/nodes and tweak formatting
- Replace bogus volume up/down adc-keys with actual recovery key

 .../devicetree/bindings/arm/rockchip.yaml     |   5 +
 arch/arm64/boot/dts/rockchip/Makefile         |   1 +
 .../boot/dts/rockchip/rk3399-nanopc-t4.dts    |  17 +
 .../boot/dts/rockchip/rk3399-nanopi4.dtsi     | 725 ++++++++++++++++++
 4 files changed, 748 insertions(+)
 create mode 100644 arch/arm64/boot/dts/rockchip/rk3399-nanopc-t4.dts
 create mode 100644 arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi

diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml
index b12958bda09c..bcc60c492a12 100644
--- a/Documentation/devicetree/bindings/arm/rockchip.yaml
+++ b/Documentation/devicetree/bindings/arm/rockchip.yaml
@@ -87,6 +87,11 @@ properties:
           - const: firefly,roc-rk3399-pc
           - const: rockchip,rk3399
 
+      - description: FriendlyElec NanoPC-T4
+        items:
+          - const: friendlyarm,nanopc-t4
+          - const: rockchip,rk3399
+
       - description: GeekBuying GeekBox
         items:
           - const: geekbuying,geekbox
diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile
index de0c406c20cc..1c7406111dfd 100644
--- a/arch/arm64/boot/dts/rockchip/Makefile
+++ b/arch/arm64/boot/dts/rockchip/Makefile
@@ -16,6 +16,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-gru-bob.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-gru-kevin.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-gru-scarlet-inx.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-gru-scarlet-kd.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-nanopc-t4.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-puma-haikou.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-roc-pc.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rock960.dtb
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-nanopc-t4.dts b/arch/arm64/boot/dts/rockchip/rk3399-nanopc-t4.dts
new file mode 100644
index 000000000000..af0bb2544709
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopc-t4.dts
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * FriendlyElec NanoPC-T4 board device tree source
+ *
+ * Copyright (c) 2018 FriendlyElec Computer Tech. Co., Ltd.
+ * (http://www.friendlyarm.com)
+ *
+ * Copyright (c) 2018 Collabora Ltd.
+ */
+
+/dts-v1/;
+#include "rk3399-nanopi4.dtsi"
+
+/ {
+	model = "FriendlyElec NanoPC-T4";
+	compatible = "friendlyarm,nanopc-t4", "rockchip,rk3399";
+};
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi
new file mode 100644
index 000000000000..3e8f1c10ba4f
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi
@@ -0,0 +1,725 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * RK3399-based FriendlyElec boards device tree source
+ *
+ * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
+ *
+ * Copyright (c) 2018 FriendlyElec Computer Tech. Co., Ltd.
+ * (http://www.friendlyarm.com)
+ *
+ * Copyright (c) 2018 Collabora Ltd.
+ * Copyright (c) 2019 Arm Ltd.
+ */
+
+/dts-v1/;
+#include <dt-bindings/input/linux-event-codes.h>
+#include "rk3399.dtsi"
+#include "rk3399-opp.dtsi"
+
+/ {
+	chosen {
+		stdout-path = "serial2:1500000n8";
+	};
+
+	clkin_gmac: external-gmac-clock {
+		compatible = "fixed-clock";
+		clock-frequency = <125000000>;
+		clock-output-names = "clkin_gmac";
+		#clock-cells = <0>;
+	};
+
+	vdd_5v: vdd-5v {
+		compatible = "regulator-fixed";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-name = "vdd_5v";
+	};
+
+	vcc5v0_core: vcc5v0-core {
+		compatible = "regulator-fixed";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-name = "vcc5v0_core";
+		vin-supply = <&vdd_5v>;
+	};
+
+	vcc3v3_sys: vcc3v3-sys {
+		compatible = "regulator-fixed";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-name = "vcc3v3_sys";
+		vin-supply = <&vcc5v0_core>;
+	};
+
+	vcc5v0_sys: vcc5v0-sys {
+		compatible = "regulator-fixed";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		regulator-name = "vcc5v0_sys";
+		vin-supply = <&vdd_5v>;
+	};
+
+	vcc5v0_usb1: vcc5v0-usb1 {
+		compatible = "regulator-fixed";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-name = "vcc5v0_usb1";
+		vin-supply = <&vcc5v0_sys>;
+	};
+
+	vcc5v0_usb2: vcc5v0-usb2 {
+		compatible = "regulator-fixed";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-name = "vcc5v0_usb2";
+		vin-supply = <&vcc5v0_sys>;
+	};
+
+	/* switched by pmic_sleep */
+	vcc1v8_s3: vcca1v8_s3: vcc1v8-s3 {
+		compatible = "regulator-fixed";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		regulator-name = "vcc1v8_s3";
+		vin-supply = <&vcc_1v8>;
+	};
+
+	vcc3v0_sd: vcc3v0-sd {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio0 RK_PA1 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&sdmmc0_pwr_h>;
+		regulator-always-on;
+		regulator-min-microvolt = <3000000>;
+		regulator-max-microvolt = <3000000>;
+		regulator-name = "vcc3v0_sd";
+		vin-supply = <&vcc3v3_sys>;
+	};
+
+	vbus_typec: vbus-typec {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpios = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>;
+		regulator-always-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		regulator-name = "vbus_typec";
+		vin-supply = <&vdd_5v>;
+	};
+
+	adc-keys {
+		compatible = "adc-keys";
+		io-channels = <&saradc 1>;
+		io-channel-names = "buttons";
+		keyup-threshold-microvolt = <1800000>;
+		poll-interval = <100>;
+
+		recovery {
+			label = "Recovery";
+			linux,code = <KEY_VENDOR>;
+			press-threshold-microvolt = <18000>;
+		};
+	};
+
+	gpio-keys {
+		compatible = "gpio-keys";
+		autorepeat;
+		pinctrl-names = "default";
+		pinctrl-0 = <&power_key>;
+
+		power {
+			debounce-interval = <100>;
+			gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
+			label = "GPIO Key Power";
+			linux,code = <KEY_POWER>;
+			wakeup-source;
+		};
+	};
+
+	leds: gpio-leds {
+		compatible = "gpio-leds";
+		pinctrl-names = "default";
+		pinctrl-0 = <&leds_gpio>;
+
+		status {
+			gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>;
+			label = "status_led";
+			linux,default-trigger = "heartbeat";
+		};
+	};
+
+	sdio_pwrseq: sdio-pwrseq {
+		compatible = "mmc-pwrseq-simple";
+		clocks = <&rk808 1>;
+		clock-names = "ext_clock";
+		pinctrl-names = "default";
+		pinctrl-0 = <&wifi_reg_on_h>;
+		reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>;
+	};
+};
+
+&cpu_b0 {
+	cpu-supply = <&vdd_cpu_b>;
+};
+
+&cpu_b1 {
+	cpu-supply = <&vdd_cpu_b>;
+};
+
+&cpu_l0 {
+	cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_l1 {
+	cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_l2 {
+	cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_l3 {
+	cpu-supply = <&vdd_cpu_l>;
+};
+
+&emmc_phy {
+	status = "okay";
+};
+
+&gmac {
+	assigned-clock-parents = <&clkin_gmac>;
+	assigned-clocks = <&cru SCLK_RMII_SRC>;
+	clock_in_out = "input";
+	pinctrl-names = "default";
+	pinctrl-0 = <&rgmii_pins>;
+	phy-mode = "rgmii";
+	phy-supply = <&vcc3v3_s3>;
+	snps,reset-active-low;
+	snps,reset-delays-us = <0 10000 50000>;
+	snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
+	tx_delay = <0x28>;
+	rx_delay = <0x11>;
+	status = "okay";
+};
+
+&gpu {
+	mali-supply = <&vdd_gpu>;
+	status = "okay";
+};
+
+&hdmi {
+	ddc-i2c-bus = <&i2c7>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&hdmi_cec>;
+	status = "okay";
+};
+
+&i2c0 {
+	clock-frequency = <400000>;
+	i2c-scl-rising-time-ns = <160>;
+	i2c-scl-falling-time-ns = <30>;
+	status = "okay";
+
+	vdd_cpu_b: regulator@40 {
+		compatible = "silergy,syr827";
+		reg = <0x40>;
+		fcs,suspend-voltage-selector = <1>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&cpu_b_sleep>;
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <712500>;
+		regulator-max-microvolt = <1500000>;
+		regulator-name = "vdd_cpu_b";
+		regulator-ramp-delay = <1000>;
+		vin-supply = <&vcc3v3_sys>;
+
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+
+	vdd_gpu: regulator@41 {
+		compatible = "silergy,syr828";
+		reg = <0x41>;
+		fcs,suspend-voltage-selector = <1>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&gpu_sleep>;
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <712500>;
+		regulator-max-microvolt = <1500000>;
+		regulator-name = "vdd_gpu";
+		regulator-ramp-delay = <1000>;
+		vin-supply = <&vcc3v3_sys>;
+
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+
+	rk808: pmic@1b {
+		compatible = "rockchip,rk808";
+		reg = <0x1b>;
+		clock-output-names = "xin32k", "rk808-clkout2";
+		#clock-cells = <1>;
+		interrupt-parent = <&gpio1>;
+		interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pmic_int_l>;
+		rockchip,system-power-controller;
+		wakeup-source;
+
+		vcc1-supply = <&vcc3v3_sys>;
+		vcc2-supply = <&vcc3v3_sys>;
+		vcc3-supply = <&vcc3v3_sys>;
+		vcc4-supply = <&vcc3v3_sys>;
+		vcc6-supply = <&vcc3v3_sys>;
+		vcc7-supply = <&vcc3v3_sys>;
+		vcc8-supply = <&vcc3v3_sys>;
+		vcc9-supply = <&vcc3v3_sys>;
+		vcc10-supply = <&vcc3v3_sys>;
+		vcc11-supply = <&vcc3v3_sys>;
+		vcc12-supply = <&vcc3v3_sys>;
+		vddio-supply = <&vcc_3v0>;
+
+		regulators {
+			vdd_center: DCDC_REG1 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <750000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-name = "vdd_center";
+				regulator-ramp-delay = <6001>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdd_cpu_l: DCDC_REG2 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <750000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-name = "vdd_cpu_l";
+				regulator-ramp-delay = <6001>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_ddr: DCDC_REG3 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-name = "vcc_ddr";
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+				};
+			};
+
+			vcc_1v8: DCDC_REG4 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-name = "vcc_1v8";
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vcc1v8_cam: LDO_REG1 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-name = "vcc1v8_cam";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc3v0_touch: LDO_REG2 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3000000>;
+				regulator-max-microvolt = <3000000>;
+				regulator-name = "vcc3v0_touch";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc1v8_pmupll: LDO_REG3 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-name = "vcc1v8_pmupll";
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vcc_sdio: LDO_REG4 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-init-microvolt = <3000000>;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-name = "vcc_sdio";
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <3000000>;
+				};
+			};
+
+			vcca3v0_codec: LDO_REG5 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3000000>;
+				regulator-max-microvolt = <3000000>;
+				regulator-name = "vcca3v0_codec";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_1v5: LDO_REG6 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1500000>;
+				regulator-max-microvolt = <1500000>;
+				regulator-name = "vcc_1v5";
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1500000>;
+				};
+			};
+
+			vcca1v8_codec: LDO_REG7 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-name = "vcca1v8_codec";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_3v0: LDO_REG8 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3000000>;
+				regulator-max-microvolt = <3000000>;
+				regulator-name = "vcc_3v0";
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <3000000>;
+				};
+			};
+
+			vcc3v3_s3: SWITCH_REG1 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-name = "vcc3v3_s3";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc3v3_s0: SWITCH_REG2 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-name = "vcc3v3_s0";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+		};
+	};
+};
+
+&i2c1 {
+	clock-frequency = <200000>;
+	i2c-scl-rising-time-ns = <150>;
+	i2c-scl-falling-time-ns = <30>;
+	status = "okay";
+};
+
+&i2c2 {
+	status = "okay";
+};
+
+&i2c4 {
+	clock-frequency = <400000>;
+	i2c-scl-rising-time-ns = <160>;
+	i2c-scl-falling-time-ns = <30>;
+	status = "okay";
+
+	fusb0: typec-portc@22 {
+		compatible = "fcs,fusb302";
+		reg = <0x22>;
+		interrupt-parent = <&gpio1>;
+		interrupts = <RK_PA2 IRQ_TYPE_LEVEL_LOW>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&fusb0_int>;
+		vbus-supply = <&vbus_typec>;
+	};
+};
+
+&i2c7 {
+	status = "okay";
+};
+
+&io_domains {
+	bt656-supply = <&vcc_1v8>;
+	audio-supply = <&vcca1v8_codec>;
+	sdmmc-supply = <&vcc_sdio>;
+	gpio1830-supply = <&vcc_3v0>;
+	status = "okay";
+};
+
+&pcie_phy {
+	assigned-clock-parents = <&cru SCLK_PCIEPHY_REF100M>;
+	assigned-clock-rates = <100000000>;
+	assigned-clocks = <&cru SCLK_PCIEPHY_REF>;
+	status = "okay";
+};
+
+&pcie0 {
+	ep-gpios = <&gpio2 RK_PA4 GPIO_ACTIVE_HIGH>;
+	max-link-speed = <2>;
+	num-lanes = <4>;
+	status = "okay";
+};
+
+&pinctrl {
+	fusb30x {
+		fusb0_int: fusb0-int {
+			rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+
+	gpio-leds {
+		leds_gpio: leds-gpio {
+			rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	pmic {
+		cpu_b_sleep: cpu-b-sleep {
+			rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>;
+		};
+
+		gpu_sleep: gpu-sleep {
+			rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>;
+		};
+
+		pmic_int_l: pmic-int-l {
+			rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+
+	rockchip-key {
+		power_key: power-key {
+			rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+
+	sd {
+		sdmmc0_pwr_h: sdmmc0-pwr-h {
+			rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	sdio-pwrseq {
+		wifi_reg_on_h: wifi-reg_on-h {
+			rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+};
+
+&pmu_io_domains {
+	pmu1830-supply = <&vcc_3v0>;
+	status = "okay";
+};
+
+&pwm0 {
+	status = "okay";
+};
+
+&pwm1 {
+	status = "okay";
+};
+
+&pwm2 {
+	pinctrl-names = "active";
+	pinctrl-0 = <&pwm2_pin_pull_down>;
+	status = "okay";
+};
+
+&saradc {
+	vref-supply = <&vcca1v8_s3>;
+	status = "okay";
+};
+
+&sdhci {
+	bus-width = <8>;
+	mmc-hs400-1_8v;
+	mmc-hs400-enhanced-strobe;
+	non-removable;
+	status = "okay";
+};
+
+&sdio0 {
+	bus-width = <4>;
+	cap-sd-highspeed;
+	cap-sdio-irq;
+	disable-wp;
+	keep-power-in-suspend;
+	mmc-pwrseq = <&sdio_pwrseq>;
+	non-removable;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
+	sd-uhs-sdr104;
+	status = "okay";
+};
+
+&sdmmc {
+	bus-width = <4>;
+	cap-sd-highspeed;
+	cap-mmc-highspeed;
+	disable-wp;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdmmc_bus4 &sdmmc_cd &sdmmc_clk &sdmmc_cmd>;
+	sd-uhs-sdr104;
+	vmmc-supply = <&vcc3v0_sd>;
+	vqmmc-supply = <&vcc_sdio>;
+	status = "okay";
+};
+
+&tcphy0 {
+	status = "okay";
+};
+
+&tcphy1 {
+	status = "okay";
+};
+
+&tsadc {
+	/* tshut mode 0:CRU 1:GPIO */
+	rockchip,hw-tshut-mode = <1>;
+	/* tshut polarity 0:LOW 1:HIGH */
+	rockchip,hw-tshut-polarity = <1>;
+	status = "okay";
+};
+
+&u2phy0 {
+	status = "okay";
+};
+
+&u2phy0_host {
+	phy-supply = <&vcc5v0_usb1>;
+	status = "okay";
+};
+
+&u2phy0_otg {
+	status = "okay";
+};
+
+&u2phy1 {
+	status = "okay";
+};
+
+&u2phy1_host {
+	phy-supply = <&vcc5v0_usb2>;
+	status = "okay";
+};
+
+&u2phy1_otg {
+	status = "okay";
+};
+
+&uart0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart0_xfer &uart0_rts &uart0_cts>;
+	status = "okay";
+};
+
+&uart2 {
+	status = "okay";
+};
+
+&usbdrd3_0 {
+	status = "okay";
+};
+
+&usbdrd3_1 {
+	status = "okay";
+};
+
+&usbdrd_dwc3_0 {
+	status = "okay";
+};
+
+&usbdrd_dwc3_1 {
+	dr_mode = "host";
+	status = "okay";
+};
+
+&usb_host0_ehci {
+	status = "okay";
+};
+
+&usb_host0_ohci {
+	status = "okay";
+};
+
+&usb_host1_ehci {
+	status = "okay";
+};
+
+&usb_host1_ohci {
+	status = "okay";
+};
+
+&vopb {
+	status = "okay";
+};
+
+&vopb_mmu {
+	status = "okay";
+};
+
+&vopl {
+	status = "okay";
+};
+
+&vopl_mmu {
+	status = "okay";
+};
-- 
2.17.1


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[PATCH 2/5] arm64: dts: rockchip: Add DT for NanoPi M4

[Robin Murphy]

There are a number of subtle differences between the nanopi4 variants,
and where they disagree, the common DTSI currently follows the details
of NanoPi M4. In order to improve matters even more, let's add a
separate DTS for the M4 to which we can start splitting things out
appropriately. The third variant, NanoPi NEO4, is a lot closer to the M4
than either is to the larger T4, so arguably could get away with just
sharing the M4 DT for now (plus I have neither of the smaller boards to
actually test with).

Signed-off-by: Robin Murphy <robin.murphy@arm.com>
---
 .../devicetree/bindings/arm/rockchip.yaml      |  5 +++++
 arch/arm64/boot/dts/rockchip/Makefile          |  1 +
 .../boot/dts/rockchip/rk3399-nanopi-m4.dts     | 18 ++++++++++++++++++
 3 files changed, 24 insertions(+)
 create mode 100644 arch/arm64/boot/dts/rockchip/rk3399-nanopi-m4.dts

diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml
index bcc60c492a12..b4756e0cb7d0 100644
--- a/Documentation/devicetree/bindings/arm/rockchip.yaml
+++ b/Documentation/devicetree/bindings/arm/rockchip.yaml
@@ -92,6 +92,11 @@ properties:
           - const: friendlyarm,nanopc-t4
           - const: rockchip,rk3399
 
+      - description: FriendlyElec NanoPi M4
+        items:
+          - const: friendlyarm,nanopi-m4
+          - const: rockchip,rk3399
+
       - description: GeekBuying GeekBox
         items:
           - const: geekbuying,geekbox
diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile
index 1c7406111dfd..91a669378605 100644
--- a/arch/arm64/boot/dts/rockchip/Makefile
+++ b/arch/arm64/boot/dts/rockchip/Makefile
@@ -17,6 +17,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-gru-kevin.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-gru-scarlet-inx.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-gru-scarlet-kd.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-nanopc-t4.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-nanopi-m4.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-puma-haikou.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-roc-pc.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rock960.dtb
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-nanopi-m4.dts b/arch/arm64/boot/dts/rockchip/rk3399-nanopi-m4.dts
new file mode 100644
index 000000000000..8d3f0ba29c72
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi-m4.dts
@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * FriendlyElec NanoPi M4 board device tree source
+ *
+ * Copyright (c) 2018 FriendlyElec Computer Tech. Co., Ltd.
+ * (http://www.friendlyarm.com)
+ *
+ * Copyright (c) 2018 Collabora Ltd.
+ * Copyright (c) 2019 Arm Ltd.
+ */
+
+/dts-v1/;
+#include "rk3399-nanopi4.dtsi"
+
+/ {
+	model = "FriendlyElec NanoPi M4";
+	compatible = "friendlyarm,nanopi-m4", "rockchip,rk3399";
+};
-- 
2.17.1


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[PATCH 3/5] arm64: dts: rockchip: Refine nanopi4 differences

[Robin Murphy]

The nanopi4 boards differ primarily in their power trees, with the main
5V and 3.3V rails having very different topologies on the smaller USB-C
powered boards vs. the 12V-powered T4, as well as minor variation in
other regulators related to various external connectors.

Additionally, the recovery key is only present on the T4 - ADC_IN1 is
simply pulled high and not exposed on the other boards - and the lowest
common denominator for MMC speed is actually HS200 according to the
vendor DTs.

Signed-off-by: Robin Murphy <robin.murphy@arm.com>
---
 .../boot/dts/rockchip/rk3399-nanopc-t4.dts    | 58 +++++++++++++++++++
 .../boot/dts/rockchip/rk3399-nanopi-m4.dts    | 48 +++++++++++++++
 .../boot/dts/rockchip/rk3399-nanopi4.dtsi     | 55 +-----------------
 3 files changed, 107 insertions(+), 54 deletions(-)

diff --git a/arch/arm64/boot/dts/rockchip/rk3399-nanopc-t4.dts b/arch/arm64/boot/dts/rockchip/rk3399-nanopc-t4.dts
index af0bb2544709..623a03f2548a 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399-nanopc-t4.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopc-t4.dts
@@ -14,4 +14,62 @@
 / {
 	model = "FriendlyElec NanoPC-T4";
 	compatible = "friendlyarm,nanopc-t4", "rockchip,rk3399";
+
+	vcc12v0_sys: vcc12v0-sys {
+		compatible = "regulator-fixed";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-max-microvolt = <12000000>;
+		regulator-min-microvolt = <12000000>;
+		regulator-name = "vcc12v0_sys";
+	};
+
+	vcc5v0_host0: vcc5v0-host0 {
+		compatible = "regulator-fixed";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-name = "vcc5v0_host0";
+		vin-supply = <&vcc5v0_sys>;
+	};
+
+	adc-keys {
+		compatible = "adc-keys";
+		io-channels = <&saradc 1>;
+		io-channel-names = "buttons";
+		keyup-threshold-microvolt = <1800000>;
+		poll-interval = <100>;
+
+		recovery {
+			label = "Recovery";
+			linux,code = <KEY_VENDOR>;
+			press-threshold-microvolt = <18000>;
+		};
+	};
+};
+
+&sdhci {
+	mmc-hs400-1_8v;
+	mmc-hs400-enhanced-strobe;
+};
+
+&u2phy0_host {
+	phy-supply = <&vcc5v0_host0>;
+};
+
+&u2phy1_host {
+	phy-supply = <&vcc5v0_host0>;
+};
+
+&vcc5v0_sys {
+	vin-supply = <&vcc12v0_sys>;
+};
+
+&vcc3v3_sys {
+	vin-supply = <&vcc12v0_sys>;
+};
+
+&vbus_typec {
+	enable-active-high;
+	gpios = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>;
+	vin-supply = <&vcc5v0_sys>;
 };
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-nanopi-m4.dts b/arch/arm64/boot/dts/rockchip/rk3399-nanopi-m4.dts
index 8d3f0ba29c72..60358ab8c7df 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399-nanopi-m4.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi-m4.dts
@@ -15,4 +15,52 @@
 / {
 	model = "FriendlyElec NanoPi M4";
 	compatible = "friendlyarm,nanopi-m4", "rockchip,rk3399";
+
+	vdd_5v: vdd-5v {
+		compatible = "regulator-fixed";
+		regulator-name = "vdd_5v";
+		regulator-always-on;
+		regulator-boot-on;
+	};
+
+	vcc5v0_core: vcc5v0-core {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_core";
+		regulator-always-on;
+		regulator-boot-on;
+		vin-supply = <&vdd_5v>;
+	};
+
+	vcc5v0_usb1: vcc5v0-usb1 {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_usb1";
+		regulator-always-on;
+		regulator-boot-on;
+		vin-supply = <&vcc5v0_sys>;
+	};
+
+	vcc5v0_usb2: vcc5v0-usb2 {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_usb2";
+		regulator-always-on;
+		regulator-boot-on;
+		vin-supply = <&vcc5v0_sys>;
+	};
+};
+
+&vcc3v3_sys {
+	vin-supply = <&vcc5v0_core>;
+};
+
+&u2phy0_host {
+	phy-supply = <&vcc5v0_usb1>;
+};
+
+&u2phy1_host {
+	phy-supply = <&vcc5v0_usb2>;
+};
+
+&vbus_typec {
+	regulator-always-on;
+	vin-supply = <&vdd_5v>;
 };
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi
index 3e8f1c10ba4f..9c723038d8f8 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi
@@ -28,21 +28,6 @@
 		#clock-cells = <0>;
 	};
 
-	vdd_5v: vdd-5v {
-		compatible = "regulator-fixed";
-		regulator-always-on;
-		regulator-boot-on;
-		regulator-name = "vdd_5v";
-	};
-
-	vcc5v0_core: vcc5v0-core {
-		compatible = "regulator-fixed";
-		regulator-always-on;
-		regulator-boot-on;
-		regulator-name = "vcc5v0_core";
-		vin-supply = <&vdd_5v>;
-	};
-
 	vcc3v3_sys: vcc3v3-sys {
 		compatible = "regulator-fixed";
 		regulator-always-on;
@@ -50,7 +35,6 @@
 		regulator-min-microvolt = <3300000>;
 		regulator-max-microvolt = <3300000>;
 		regulator-name = "vcc3v3_sys";
-		vin-supply = <&vcc5v0_core>;
 	};
 
 	vcc5v0_sys: vcc5v0-sys {
@@ -63,22 +47,6 @@
 		vin-supply = <&vdd_5v>;
 	};
 
-	vcc5v0_usb1: vcc5v0-usb1 {
-		compatible = "regulator-fixed";
-		regulator-always-on;
-		regulator-boot-on;
-		regulator-name = "vcc5v0_usb1";
-		vin-supply = <&vcc5v0_sys>;
-	};
-
-	vcc5v0_usb2: vcc5v0-usb2 {
-		compatible = "regulator-fixed";
-		regulator-always-on;
-		regulator-boot-on;
-		regulator-name = "vcc5v0_usb2";
-		vin-supply = <&vcc5v0_sys>;
-	};
-
 	/* switched by pmic_sleep */
 	vcc1v8_s3: vcca1v8_s3: vcc1v8-s3 {
 		compatible = "regulator-fixed";
@@ -105,27 +73,9 @@
 
 	vbus_typec: vbus-typec {
 		compatible = "regulator-fixed";
-		enable-active-high;
-		gpios = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>;
-		regulator-always-on;
 		regulator-min-microvolt = <5000000>;
 		regulator-max-microvolt = <5000000>;
 		regulator-name = "vbus_typec";
-		vin-supply = <&vdd_5v>;
-	};
-
-	adc-keys {
-		compatible = "adc-keys";
-		io-channels = <&saradc 1>;
-		io-channel-names = "buttons";
-		keyup-threshold-microvolt = <1800000>;
-		poll-interval = <100>;
-
-		recovery {
-			label = "Recovery";
-			linux,code = <KEY_VENDOR>;
-			press-threshold-microvolt = <18000>;
-		};
 	};
 
 	gpio-keys {
@@ -590,8 +540,7 @@
 
 &sdhci {
 	bus-width = <8>;
-	mmc-hs400-1_8v;
-	mmc-hs400-enhanced-strobe;
+	mmc-hs200-1_8v;
 	non-removable;
 	status = "okay";
 };
@@ -644,7 +593,6 @@
 };
 
 &u2phy0_host {
-	phy-supply = <&vcc5v0_usb1>;
 	status = "okay";
 };
 
@@ -657,7 +605,6 @@
 };
 
 &u2phy1_host {
-	phy-supply = <&vcc5v0_usb2>;
 	status = "okay";
 };
 
-- 
2.17.1


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[PATCH 4/5] arm64: dts: rockchip: Add NanoPC-T4 IR receiver

[Robin Murphy]

In common with most Rockchip reference designs, NanoPC-T4 has a passive
IR receiver connected to PWM3. In lieu of a specialised driver for
PWM-based IR pulse measurement, running the pin as a GPIO with the basic
driver works perfectly well.

Signed-off-by: Robin Murphy <robin.murphy@arm.com>
---
 .../arm64/boot/dts/rockchip/rk3399-nanopc-t4.dts | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk3399-nanopc-t4.dts b/arch/arm64/boot/dts/rockchip/rk3399-nanopc-t4.dts
index 623a03f2548a..84433cf02be9 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399-nanopc-t4.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopc-t4.dts
@@ -45,6 +45,22 @@
 			press-threshold-microvolt = <18000>;
 		};
 	};
+
+	ir-receiver {
+		compatible = "gpio-ir-receiver";
+		gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_LOW>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&ir_rx>;
+	};
+};
+
+&pinctrl {
+	ir {
+		ir_rx: ir-rx {
+			/* external pullup to VCC3V3_SYS, despite being 1.8V :/ */
+			rockchip,pins = <0 RK_PA6 RK_FUNC_1 &pcfg_pull_none>;
+		};
+	};
 };
 
 &sdhci {
-- 
2.17.1


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[PATCH 5/5] arm64: dts: rockchip: Fix nanopi4 uSD card detect

[Robin Murphy]

For whatever reason, the sdmmc_dectn function isn't working properly
as-is, and microSD insertion and removal goes unnoticed. Flipping the
pin into GPIO mode, however, does do the job, so let's just handle it
that way for now until someone feels inclined to figure out what GRF
voodoo or otherwise is needed for correct 'native' operation.

Signed-off-by: Robin Murphy <robin.murphy@arm.com>
---
 arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi
index 9c723038d8f8..2a183a6af150 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi
@@ -505,6 +505,10 @@
 		sdmmc0_pwr_h: sdmmc0-pwr-h {
 			rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>;
 		};
+
+		sdmmc0_det_l: sdmmc0-det-l {
+			rockchip,pins = <0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
 	};
 
 	sdio-pwrseq {
@@ -563,9 +567,10 @@
 	bus-width = <4>;
 	cap-sd-highspeed;
 	cap-mmc-highspeed;
+	cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>;
 	disable-wp;
 	pinctrl-names = "default";
-	pinctrl-0 = <&sdmmc_bus4 &sdmmc_cd &sdmmc_clk &sdmmc_cmd>;
+	pinctrl-0 = <&sdmmc_bus4 &sdmmc0_det_l &sdmmc_clk &sdmmc_cmd>;
 	sd-uhs-sdr104;
 	vmmc-supply = <&vcc3v0_sd>;
 	vqmmc-supply = <&vcc_sdio>;
-- 
2.17.1


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Re: [PATCH 2/5] arm64: dts: rockchip: Add DT for NanoPi M4

[Heiko Stuebner]

Hi Robin,

Am Dienstag, 8. Januar 2019, 22:57:24 CET schrieb Robin Murphy:
> There are a number of subtle differences between the nanopi4 variants,
> and where they disagree, the common DTSI currently follows the details
> of NanoPi M4. In order to improve matters even more, let's add a
> separate DTS for the M4 to which we can start splitting things out
> appropriately. The third variant, NanoPi NEO4, is a lot closer to the M4
> than either is to the larger T4, so arguably could get away with just
> sharing the M4 DT for now (plus I have neither of the smaller boards to
> actually test with).
> 
> Signed-off-by: Robin Murphy <robin.murphy@arm.com>

I'm not sure if Rob actually checks the devicetree list or relies on
patches Cc'ed directly to him for binding review, so you might want
to add the 2 dt maintainers explicitly.

> ---
>  .../devicetree/bindings/arm/rockchip.yaml      |  5 +++++
>  arch/arm64/boot/dts/rockchip/Makefile          |  1 +
>  .../boot/dts/rockchip/rk3399-nanopi-m4.dts     | 18 ++++++++++++++++++
>  3 files changed, 24 insertions(+)
>  create mode 100644 arch/arm64/boot/dts/rockchip/rk3399-nanopi-m4.dts
> 
> diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml
> index bcc60c492a12..b4756e0cb7d0 100644
> --- a/Documentation/devicetree/bindings/arm/rockchip.yaml
> +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml
> @@ -92,6 +92,11 @@ properties:
>            - const: friendlyarm,nanopc-t4
>            - const: rockchip,rk3399
>  
> +      - description: FriendlyElec NanoPi M4
> +        items:
> +          - const: friendlyarm,nanopi-m4
> +          - const: rockchip,rk3399
> +

When we hashed out the Rockchip yaml thingy, there also
came up the possibility of grouping the similar boards together
into an enum, see the rk3399-firefly or the rk3288-evb-* for example.

So the binding for both could possibly become:

      - description: FriendlyElec NanoPi
        items:
	  - enum:
          	- friendlyarm,nanopi-m4
          	- friendlyarm,nanopi-t4
          - const: rockchip,rk3399

We didn't come up with a hard rule for all cases, but the
Nano PI feels like it qualifies ;-)


Heiko



>        - description: GeekBuying GeekBox
>          items:
>            - const: geekbuying,geekbox
> diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile
> index 1c7406111dfd..91a669378605 100644
> --- a/arch/arm64/boot/dts/rockchip/Makefile
> +++ b/arch/arm64/boot/dts/rockchip/Makefile
> @@ -17,6 +17,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-gru-kevin.dtb
>  dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-gru-scarlet-inx.dtb
>  dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-gru-scarlet-kd.dtb
>  dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-nanopc-t4.dtb
> +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-nanopi-m4.dtb
>  dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-puma-haikou.dtb
>  dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-roc-pc.dtb
>  dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rock960.dtb
> diff --git a/arch/arm64/boot/dts/rockchip/rk3399-nanopi-m4.dts b/arch/arm64/boot/dts/rockchip/rk3399-nanopi-m4.dts
> new file mode 100644
> index 000000000000..8d3f0ba29c72
> --- /dev/null
> +++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi-m4.dts
> @@ -0,0 +1,18 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * FriendlyElec NanoPi M4 board device tree source
> + *
> + * Copyright (c) 2018 FriendlyElec Computer Tech. Co., Ltd.
> + * (http://www.friendlyarm.com)
> + *
> + * Copyright (c) 2018 Collabora Ltd.
> + * Copyright (c) 2019 Arm Ltd.
> + */
> +
> +/dts-v1/;
> +#include "rk3399-nanopi4.dtsi"
> +
> +/ {
> +	model = "FriendlyElec NanoPi M4";
> +	compatible = "friendlyarm,nanopi-m4", "rockchip,rk3399";
> +};
> 





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Re: [PATCH 2/5] arm64: dts: rockchip: Add DT for NanoPi M4

[Robin Murphy]

Hi Heiko,

On 2019-01-08 10:15 pm, Heiko Stuebner wrote:
> Hi Robin,
> 
> Am Dienstag, 8. Januar 2019, 22:57:24 CET schrieb Robin Murphy:
>> There are a number of subtle differences between the nanopi4 variants,
>> and where they disagree, the common DTSI currently follows the details
>> of NanoPi M4. In order to improve matters even more, let's add a
>> separate DTS for the M4 to which we can start splitting things out
>> appropriately. The third variant, NanoPi NEO4, is a lot closer to the M4
>> than either is to the larger T4, so arguably could get away with just
>> sharing the M4 DT for now (plus I have neither of the smaller boards to
>> actually test with).
>>
>> Signed-off-by: Robin Murphy <robin.murphy@arm.com>
> 
> I'm not sure if Rob actually checks the devicetree list or relies on
> patches Cc'ed directly to him for binding review, so you might want
> to add the 2 dt maintainers explicitly.

Er, that's embarassing... I somehow failed to register that my mindless 
copy-paste job ends up adding a new binding that *isn't* the one Rob 
already reviewed :(

>> ---
>>   .../devicetree/bindings/arm/rockchip.yaml      |  5 +++++
>>   arch/arm64/boot/dts/rockchip/Makefile          |  1 +
>>   .../boot/dts/rockchip/rk3399-nanopi-m4.dts     | 18 ++++++++++++++++++
>>   3 files changed, 24 insertions(+)
>>   create mode 100644 arch/arm64/boot/dts/rockchip/rk3399-nanopi-m4.dts
>>
>> diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml
>> index bcc60c492a12..b4756e0cb7d0 100644
>> --- a/Documentation/devicetree/bindings/arm/rockchip.yaml
>> +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml
>> @@ -92,6 +92,11 @@ properties:
>>             - const: friendlyarm,nanopc-t4
>>             - const: rockchip,rk3399
>>   
>> +      - description: FriendlyElec NanoPi M4
>> +        items:
>> +          - const: friendlyarm,nanopi-m4
>> +          - const: rockchip,rk3399
>> +
> 
> When we hashed out the Rockchip yaml thingy, there also
> came up the possibility of grouping the similar boards together
> into an enum, see the rk3399-firefly or the rk3288-evb-* for example.
> 
> So the binding for both could possibly become:
> 
>        - description: FriendlyElec NanoPi
>          items:
> 	  - enum:
>            	- friendlyarm,nanopi-m4
>            	- friendlyarm,nanopi-t4
>            - const: rockchip,rk3399
> 
> We didn't come up with a hard rule for all cases, but the
> Nano PI feels like it qualifies ;-)

...but I completely agree with that idea anyway - as the commit log 
alludes to, this was really just somewhere to move the existing nodes to 
without much thought involved. I'll give it a day or two for any more 
comments, then respin at least this patch and make sure the binding 
update goes to the maintainers properly.

Cheers,
Robin.

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Re: [PATCH 5/5] arm64: dts: rockchip: Fix nanopi4 uSD card detect

[Heiko Stuebner]

Am Dienstag, 8. Januar 2019, 22:57:27 CET schrieb Robin Murphy:
> For whatever reason, the sdmmc_dectn function isn't working properly
> as-is, and microSD insertion and removal goes unnoticed. Flipping the
> pin into GPIO mode, however, does do the job, so let's just handle it
> that way for now until someone feels inclined to figure out what GRF
> voodoo or otherwise is needed for correct 'native' operation.
> 
> Signed-off-by: Robin Murphy <robin.murphy@arm.com>
> ---
>  arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi | 7 ++++++-
>  1 file changed, 6 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi
> index 9c723038d8f8..2a183a6af150 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi
> +++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi
> @@ -505,6 +505,10 @@
>  		sdmmc0_pwr_h: sdmmc0-pwr-h {
>  			rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>;
>  		};
> +
> +		sdmmc0_det_l: sdmmc0-det-l {

alphabetically by node-name please,
aka sdmmc0-det-* should be above sdmmc0-pwr-*

If you're respinning the whole series this should be fixed,
otherwise I can also do that when applying.


Heiko

> +			rockchip,pins = <0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>;
> +		};
>  	};
>  
>  	sdio-pwrseq {
> @@ -563,9 +567,10 @@
>  	bus-width = <4>;
>  	cap-sd-highspeed;
>  	cap-mmc-highspeed;
> +	cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>;
>  	disable-wp;
>  	pinctrl-names = "default";
> -	pinctrl-0 = <&sdmmc_bus4 &sdmmc_cd &sdmmc_clk &sdmmc_cmd>;
> +	pinctrl-0 = <&sdmmc_bus4 &sdmmc0_det_l &sdmmc_clk &sdmmc_cmd>;
>  	sd-uhs-sdr104;
>  	vmmc-supply = <&vcc3v0_sd>;
>  	vqmmc-supply = <&vcc_sdio>;
> 





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Re: [PATCH 5/5] arm64: dts: rockchip: Fix nanopi4 uSD card detect

[Robin Murphy]

On 2019-01-08 10:42 pm, Heiko Stuebner wrote:
> Am Dienstag, 8. Januar 2019, 22:57:27 CET schrieb Robin Murphy:
>> For whatever reason, the sdmmc_dectn function isn't working properly
>> as-is, and microSD insertion and removal goes unnoticed. Flipping the
>> pin into GPIO mode, however, does do the job, so let's just handle it
>> that way for now until someone feels inclined to figure out what GRF
>> voodoo or otherwise is needed for correct 'native' operation.
>>
>> Signed-off-by: Robin Murphy <robin.murphy@arm.com>
>> ---
>>   arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi | 7 ++++++-
>>   1 file changed, 6 insertions(+), 1 deletion(-)
>>
>> diff --git a/arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi
>> index 9c723038d8f8..2a183a6af150 100644
>> --- a/arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi
>> +++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi
>> @@ -505,6 +505,10 @@
>>   		sdmmc0_pwr_h: sdmmc0-pwr-h {
>>   			rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>;
>>   		};
>> +
>> +		sdmmc0_det_l: sdmmc0-det-l {
> 
> alphabetically by node-name please,
> aka sdmmc0-det-* should be above sdmmc0-pwr-*

Right you are, not sure how that one slipped through.

> If you're respinning the whole series this should be fixed,
> otherwise I can also do that when applying.

I've fixed it up locally, although it might be worth holding off on this 
particular patch for the moment now that I've taken another look through 
the TRM and noticed those smoking-gun-looking bits in 
GRF_SIG_DETECT_CON{0,1} - I'll investigate...

[ side note - do you reckon there'd be any value in bolting a debugfs 
interface onto the GRF driver, or is the realistic answer to just use 
/dev/mem like everyone else and stop having silly ideas? ]

Thanks,
Robin.

> 
> 
> Heiko
> 
>> +			rockchip,pins = <0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>;
>> +		};
>>   	};
>>   
>>   	sdio-pwrseq {
>> @@ -563,9 +567,10 @@
>>   	bus-width = <4>;
>>   	cap-sd-highspeed;
>>   	cap-mmc-highspeed;
>> +	cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>;
>>   	disable-wp;
>>   	pinctrl-names = "default";
>> -	pinctrl-0 = <&sdmmc_bus4 &sdmmc_cd &sdmmc_clk &sdmmc_cmd>;
>> +	pinctrl-0 = <&sdmmc_bus4 &sdmmc0_det_l &sdmmc_clk &sdmmc_cmd>;
>>   	sd-uhs-sdr104;
>>   	vmmc-supply = <&vcc3v0_sd>;
>>   	vqmmc-supply = <&vcc_sdio>;
>>
> 
> 
> 
> 

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Re: [PATCH 5/5] arm64: dts: rockchip: Fix nanopi4 uSD card detect

[Heiko Stuebner]

Am Mittwoch, 9. Januar 2019, 00:22:01 CET schrieb Robin Murphy:
> On 2019-01-08 10:42 pm, Heiko Stuebner wrote:
> > Am Dienstag, 8. Januar 2019, 22:57:27 CET schrieb Robin Murphy:
> >> For whatever reason, the sdmmc_dectn function isn't working properly
> >> as-is, and microSD insertion and removal goes unnoticed. Flipping the
> >> pin into GPIO mode, however, does do the job, so let's just handle it
> >> that way for now until someone feels inclined to figure out what GRF
> >> voodoo or otherwise is needed for correct 'native' operation.
> >>
> >> Signed-off-by: Robin Murphy <robin.murphy@arm.com>
> >> ---
> >>   arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi | 7 ++++++-
> >>   1 file changed, 6 insertions(+), 1 deletion(-)
> >>
> >> diff --git a/arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi
> >> index 9c723038d8f8..2a183a6af150 100644
> >> --- a/arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi
> >> +++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi
> >> @@ -505,6 +505,10 @@
> >>   		sdmmc0_pwr_h: sdmmc0-pwr-h {
> >>   			rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>;
> >>   		};
> >> +
> >> +		sdmmc0_det_l: sdmmc0-det-l {
> > 
> > alphabetically by node-name please,
> > aka sdmmc0-det-* should be above sdmmc0-pwr-*
> 
> Right you are, not sure how that one slipped through.
> 
> > If you're respinning the whole series this should be fixed,
> > otherwise I can also do that when applying.
> 
> I've fixed it up locally, although it might be worth holding off on this 
> particular patch for the moment now that I've taken another look through 
> the TRM and noticed those smoking-gun-looking bits in 
> GRF_SIG_DETECT_CON{0,1} - I'll investigate...

Personally I'm very much fine with using a cd-gpio instead of trying
to bring order to the GRF "chaos" ;-) as I'm also not really sure
if we gain anything with the IP-internal detect mechanism.

But then do as you like :-D

> [ side note - do you reckon there'd be any value in bolting a debugfs 
> interface onto the GRF driver, or is the realistic answer to just use 
> /dev/mem like everyone else and stop having silly ideas? ]

I don't think it would help much ... especially when it really only outputs
the register contents in the same way as mem or so does.

Having to fiddle with GRF bits really should only happen in rare cases,
so I guess mem should do the trick for that.

And the GRF driver also was a bit controversial anyway, with the title
of "dumping ground" looming over it ... so I'd like to keep it small
and simple ;-) .

Heiko



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Re: [PATCH v5 1/5] arm64: dts: rockchip: Add DT for NanoPC-T4

[Heiko Stuebner]

Am Dienstag, 8. Januar 2019, 22:57:23 CET schrieb Robin Murphy:
> From: Tomeu Vizoso <tomeu.vizoso@collabora.com>
> 
> This adds a device tree for the NanoPC-T4 SBC, which is based on the
> Rockchip RK3399 SoC and marketed by FriendlyELEC.
> 
> Known working:
> 
> - Serial
> - Ethernet
> - HDMI
> - USB 2.0
> 
> All of the interesting stuff is in a .dtsi because there are at least
> two other boards that share most of it: NanoPi M4 and NanoPi NEO4.
> 
> Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
> Reviewed-by: Rob Herring <robh@kernel.org>
> [rm: various further cleanup]
> Signed-off-by: Robin Murphy <robin.murphy@arm.com>

nobody complained, the binding was reviewed and all looks good
so I've gone forward and applied this one for 5.1 already.

Thanks
Heiko



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Re: [PATCH v5 1/5] arm64: dts: rockchip: Add DT for NanoPC-T4

[Robin Murphy]

On 10/01/2019 13:37, Heiko Stuebner wrote:
> Am Dienstag, 8. Januar 2019, 22:57:23 CET schrieb Robin Murphy:
>> From: Tomeu Vizoso <tomeu.vizoso@collabora.com>
>>
>> This adds a device tree for the NanoPC-T4 SBC, which is based on the
>> Rockchip RK3399 SoC and marketed by FriendlyELEC.
>>
>> Known working:
>>
>> - Serial
>> - Ethernet
>> - HDMI
>> - USB 2.0
>>
>> All of the interesting stuff is in a .dtsi because there are at least
>> two other boards that share most of it: NanoPi M4 and NanoPi NEO4.
>>
>> Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
>> Reviewed-by: Rob Herring <robh@kernel.org>
>> [rm: various further cleanup]
>> Signed-off-by: Robin Murphy <robin.murphy@arm.com>
> 
> nobody complained, the binding was reviewed and all looks good
> so I've gone forward and applied this one for 5.1 already.

Awesome, thanks!

I'll probably follow up with a v2 of the rest of the patches next week, 
after I've had the chance to play some more over the weekend.

Cheers,
Robin.

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Re: [PATCH 3/5] arm64: dts: rockchip: Refine nanopi4 differences

[Heiko Stuebner]

Am Dienstag, 8. Januar 2019, 22:57:25 CET schrieb Robin Murphy:
> The nanopi4 boards differ primarily in their power trees, with the main
> 5V and 3.3V rails having very different topologies on the smaller USB-C
> powered boards vs. the 12V-powered T4, as well as minor variation in
> other regulators related to various external connectors.
> 
> Additionally, the recovery key is only present on the T4 - ADC_IN1 is
> simply pulled high and not exposed on the other boards - and the lowest
> common denominator for MMC speed is actually HS200 according to the
> vendor DTs.
> 
> Signed-off-by: Robin Murphy <robin.murphy@arm.com>

this looks good to me, so only need patch2 to adapt and get reviewed.

Heiko



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Re: [PATCH 4/5] arm64: dts: rockchip: Add NanoPC-T4 IR receiver

[Heiko Stuebner]

Am Dienstag, 8. Januar 2019, 22:57:26 CET schrieb Robin Murphy:
> In common with most Rockchip reference designs, NanoPC-T4 has a passive
> IR receiver connected to PWM3. In lieu of a specialised driver for
> PWM-based IR pulse measurement, running the pin as a GPIO with the basic
> driver works perfectly well.
> 
> Signed-off-by: Robin Murphy <robin.murphy@arm.com>

easy change and of course looks good.
As it doesn't apply due to coming after other changes, I'll have
to wait for v2 though.


Heiko



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Re: [PATCH 5/5] arm64: dts: rockchip: Fix nanopi4 uSD card detect

[Robin Murphy]

On 10/01/2019 13:26, Heiko Stuebner wrote:
> Am Mittwoch, 9. Januar 2019, 00:22:01 CET schrieb Robin Murphy:
>> On 2019-01-08 10:42 pm, Heiko Stuebner wrote:
>>> Am Dienstag, 8. Januar 2019, 22:57:27 CET schrieb Robin Murphy:
>>>> For whatever reason, the sdmmc_dectn function isn't working properly
>>>> as-is, and microSD insertion and removal goes unnoticed. Flipping the
>>>> pin into GPIO mode, however, does do the job, so let's just handle it
>>>> that way for now until someone feels inclined to figure out what GRF
>>>> voodoo or otherwise is needed for correct 'native' operation.
>>>>
>>>> Signed-off-by: Robin Murphy <robin.murphy@arm.com>
>>>> ---
>>>>    arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi | 7 ++++++-
>>>>    1 file changed, 6 insertions(+), 1 deletion(-)
>>>>
>>>> diff --git a/arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi
>>>> index 9c723038d8f8..2a183a6af150 100644
>>>> --- a/arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi
>>>> +++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi
>>>> @@ -505,6 +505,10 @@
>>>>    		sdmmc0_pwr_h: sdmmc0-pwr-h {
>>>>    			rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>;
>>>>    		};
>>>> +
>>>> +		sdmmc0_det_l: sdmmc0-det-l {
>>>
>>> alphabetically by node-name please,
>>> aka sdmmc0-det-* should be above sdmmc0-pwr-*
>>
>> Right you are, not sure how that one slipped through.
>>
>>> If you're respinning the whole series this should be fixed,
>>> otherwise I can also do that when applying.
>>
>> I've fixed it up locally, although it might be worth holding off on this
>> particular patch for the moment now that I've taken another look through
>> the TRM and noticed those smoking-gun-looking bits in
>> GRF_SIG_DETECT_CON{0,1} - I'll investigate...
> 
> Personally I'm very much fine with using a cd-gpio instead of trying
> to bring order to the GRF "chaos" ;-) as I'm also not really sure
> if we gain anything with the IP-internal detect mechanism.
> 
> But then do as you like :-D

I'm assuming from the wiring (and from how I recall my 3288/3328 boxes 
behaving) that the dedicated function implements its own debouncing - 
seems the switch in this particular socket is noisy enough that the GPIO 
interrupt is firing well over 100 times per physical event. Not a big 
deal really, I just need to scratch the itch of making things work 
'properly' ;)

>> [ side note - do you reckon there'd be any value in bolting a debugfs
>> interface onto the GRF driver, or is the realistic answer to just use
>> /dev/mem like everyone else and stop having silly ideas? ]
> 
> I don't think it would help much ... especially when it really only outputs
> the register contents in the same way as mem or so does.
> 
> Having to fiddle with GRF bits really should only happen in rare cases,
> so I guess mem should do the trick for that.
> 
> And the GRF driver also was a bit controversial anyway, with the title
> of "dumping ground" looming over it ... so I'd like to keep it small
> and simple ;-) .

Yeah, it would end up being one of those things that's really handy for 
about 5 minutes every couple of years, and a massive pain to maintain 
the rest of the time. Plus I realise that I'd want to compare the 
behaviour of stock kernels anyway, and having to patch and rebuild those 
rather defeats the point.

Thanks,
Robin.

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Re: [PATCH v5 1/5] arm64: dts: rockchip: Add DT for NanoPC-T4

[Tomeu Vizoso]

On 1/10/19 2:42 PM, Robin Murphy wrote:
> On 10/01/2019 13:37, Heiko Stuebner wrote:
>> Am Dienstag, 8. Januar 2019, 22:57:23 CET schrieb Robin Murphy:
>>> From: Tomeu Vizoso <tomeu.vizoso@collabora.com>
>>>
>>> This adds a device tree for the NanoPC-T4 SBC, which is based on the
>>> Rockchip RK3399 SoC and marketed by FriendlyELEC.
>>>
>>> Known working:
>>>
>>> - Serial
>>> - Ethernet
>>> - HDMI
>>> - USB 2.0
>>>
>>> All of the interesting stuff is in a .dtsi because there are at least
>>> two other boards that share most of it: NanoPi M4 and NanoPi NEO4.
>>>
>>> Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
>>> Reviewed-by: Rob Herring <robh@kernel.org>
>>> [rm: various further cleanup]
>>> Signed-off-by: Robin Murphy <robin.murphy@arm.com>
>>
>> nobody complained, the binding was reviewed and all looks good
>> so I've gone forward and applied this one for 5.1 already.
> 
> Awesome, thanks!
> 
> I'll probably follow up with a v2 of the rest of the patches next week, 
> after I've had the chance to play some more over the weekend.

Thanks a lot for picking this up!

Have given the whole series a try and haven't found any issues. I have 
booted with nfsroot and have only run a few OpenGL apps with panfrost, 
using ARM's GPU driver.

In case there's time for it:

Tested-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>

Cheers,

Tomeu

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