[PATCH 0/3] Add support for PCIe PHY in SDX55

From: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
To: vkoul@kernel.org, kishon@ti.com, robh+dt@kernel.org
Cc: bjorn.andersson@linaro.org, linux-arm-msm@vger.kernel.org,
	linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
	Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Subject: [PATCH 0/3] Add support for PCIe PHY in SDX55
Date: Tue, 27 Apr 2021 12:23:57 +0530	[thread overview]
Message-ID: <20210427065400.18958-1-manivannan.sadhasivam@linaro.org> (raw)

Hi,

This series adds support for PCIe PHY found in Qualcomm SDX55 platform.
The PHY version is v4.20 which has different register offsets compared with
previous v4.0x versions. So separate defines are introducted to handle the
differences.

This series has been tested on Telit FN980 EVB with an out of tree PCIe Endpoint
driver.

Thanks,
Mani

Manivannan Sadhasivam (3):
  dt-bindings: phy: qcom,qmp: Add binding for SDX55 PCIe PHY
  phy: qcom-qmp: Use phy_status field for the status bit offset
  phy: qcom-qmp: Add support for SDX55 QMP PCIe PHY

 .../devicetree/bindings/phy/qcom,qmp-phy.yaml |   2 +
 drivers/phy/qualcomm/phy-qcom-qmp.c           | 160 +++++++++++++++++-
 drivers/phy/qualcomm/phy-qcom-qmp.h           |  64 ++++++-
 3 files changed, 224 insertions(+), 2 deletions(-)

-- 
2.25.1