From: Bjorn Andersson <bjorn.andersson@linaro.org>
To: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: vkoul@kernel.org, kishon@ti.com, robh+dt@kernel.org,
linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org,
devicetree@vger.kernel.org
Subject: Re: [PATCH 2/3] phy: qcom-qmp: Use phy_status field for the status bit offset
Date: Sat, 29 May 2021 12:02:09 -0500 [thread overview]
Message-ID: <YLJzkUZ7t5rL0uJ8@builder.lan> (raw)
In-Reply-To: <20210427065400.18958-3-manivannan.sadhasivam@linaro.org>
On Tue 27 Apr 01:53 CDT 2021, Manivannan Sadhasivam wrote:
> In preparation of the support for v4.20 PCIe PHY in SDX55, use a
> separate "phy_status" field for the status bit offset. This is needed
> because, the v4.20 PHY uses a different offset for the PHY Status.
Nit. I think "...uses a different bit for..." would be better.
>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Regards,
Bjorn
> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> ---
> drivers/phy/qualcomm/phy-qcom-qmp.c | 29 ++++++++++++++++++++++++++++-
> 1 file changed, 28 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c b/drivers/phy/qualcomm/phy-qcom-qmp.c
> index 9cdebe7f26cb..c9934b2407c4 100644
> --- a/drivers/phy/qualcomm/phy-qcom-qmp.c
> +++ b/drivers/phy/qualcomm/phy-qcom-qmp.c
> @@ -2323,6 +2323,8 @@ struct qmp_phy_cfg {
> unsigned int start_ctrl;
> unsigned int pwrdn_ctrl;
> unsigned int mask_com_pcs_ready;
> + /* bit offset of PHYSTATUS in QPHY_PCS_STATUS register */
> + unsigned int phy_status;
>
> /* true, if PHY has a separate PHY_COM control block */
> bool has_phy_com_ctrl;
> @@ -2526,6 +2528,7 @@ static const struct qmp_phy_cfg ipq8074_usb3phy_cfg = {
>
> .start_ctrl = SERDES_START | PCS_START,
> .pwrdn_ctrl = SW_PWRDN,
> + .phy_status = PHYSTATUS,
> };
>
> static const struct qmp_phy_cfg msm8996_pciephy_cfg = {
> @@ -2551,6 +2554,7 @@ static const struct qmp_phy_cfg msm8996_pciephy_cfg = {
> .start_ctrl = PCS_START | PLL_READY_GATE_EN,
> .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
> .mask_com_pcs_ready = PCS_READY,
> + .phy_status = PHYSTATUS,
>
> .has_phy_com_ctrl = true,
> .has_lane_rst = true,
> @@ -2580,6 +2584,7 @@ static const struct qmp_phy_cfg msm8996_ufs_cfg = {
>
> .start_ctrl = SERDES_START,
> .pwrdn_ctrl = SW_PWRDN,
> + .phy_status = PHYSTATUS,
>
> .no_pcs_sw_reset = true,
> };
> @@ -2606,6 +2611,7 @@ static const struct qmp_phy_cfg msm8996_usb3phy_cfg = {
>
> .start_ctrl = SERDES_START | PCS_START,
> .pwrdn_ctrl = SW_PWRDN,
> + .phy_status = PHYSTATUS,
> };
>
> static const char * const ipq8074_pciephy_clk_l[] = {
> @@ -2638,6 +2644,7 @@ static const struct qmp_phy_cfg ipq8074_pciephy_cfg = {
>
> .start_ctrl = SERDES_START | PCS_START,
> .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
> + .phy_status = PHYSTATUS,
>
> .has_phy_com_ctrl = false,
> .has_lane_rst = false,
> @@ -2670,6 +2677,7 @@ static const struct qmp_phy_cfg sdm845_qmp_pciephy_cfg = {
>
> .start_ctrl = PCS_START | SERDES_START,
> .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
> + .phy_status = PHYSTATUS,
>
> .has_pwrdn_delay = true,
> .pwrdn_delay_min = 995, /* us */
> @@ -2698,6 +2706,7 @@ static const struct qmp_phy_cfg sdm845_qhp_pciephy_cfg = {
>
> .start_ctrl = PCS_START | SERDES_START,
> .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
> + .phy_status = PHYSTATUS,
>
> .has_pwrdn_delay = true,
> .pwrdn_delay_min = 995, /* us */
> @@ -2736,6 +2745,7 @@ static const struct qmp_phy_cfg sm8250_qmp_gen3x1_pciephy_cfg = {
>
> .start_ctrl = PCS_START | SERDES_START,
> .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
> + .phy_status = PHYSTATUS,
>
> .has_pwrdn_delay = true,
> .pwrdn_delay_min = 995, /* us */
> @@ -2774,6 +2784,7 @@ static const struct qmp_phy_cfg sm8250_qmp_gen3x2_pciephy_cfg = {
>
> .start_ctrl = PCS_START | SERDES_START,
> .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
> + .phy_status = PHYSTATUS,
>
> .is_dual_lane_phy = true,
> .has_pwrdn_delay = true,
> @@ -2803,6 +2814,7 @@ static const struct qmp_phy_cfg qmp_v3_usb3phy_cfg = {
>
> .start_ctrl = SERDES_START | PCS_START,
> .pwrdn_ctrl = SW_PWRDN,
> + .phy_status = PHYSTATUS,
>
> .has_pwrdn_delay = true,
> .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
> @@ -2834,6 +2846,7 @@ static const struct qmp_phy_cfg sc7180_usb3phy_cfg = {
>
> .start_ctrl = SERDES_START | PCS_START,
> .pwrdn_ctrl = SW_PWRDN,
> + .phy_status = PHYSTATUS,
>
> .has_pwrdn_delay = true,
> .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
> @@ -2900,6 +2913,7 @@ static const struct qmp_phy_cfg qmp_v3_usb3_uniphy_cfg = {
>
> .start_ctrl = SERDES_START | PCS_START,
> .pwrdn_ctrl = SW_PWRDN,
> + .phy_status = PHYSTATUS,
>
> .has_pwrdn_delay = true,
> .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
> @@ -2926,6 +2940,7 @@ static const struct qmp_phy_cfg sdm845_ufsphy_cfg = {
>
> .start_ctrl = SERDES_START,
> .pwrdn_ctrl = SW_PWRDN,
> + .phy_status = PHYSTATUS,
>
> .is_dual_lane_phy = true,
> .no_pcs_sw_reset = true,
> @@ -2953,6 +2968,7 @@ static const struct qmp_phy_cfg msm8998_pciephy_cfg = {
>
> .start_ctrl = SERDES_START | PCS_START,
> .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
> + .phy_status = PHYSTATUS,
> };
>
> static const struct qmp_phy_cfg msm8998_usb3phy_cfg = {
> @@ -2977,6 +2993,7 @@ static const struct qmp_phy_cfg msm8998_usb3phy_cfg = {
>
> .start_ctrl = SERDES_START | PCS_START,
> .pwrdn_ctrl = SW_PWRDN,
> + .phy_status = PHYSTATUS,
>
> .is_dual_lane_phy = true,
> };
> @@ -3001,6 +3018,7 @@ static const struct qmp_phy_cfg sm8150_ufsphy_cfg = {
>
> .start_ctrl = SERDES_START,
> .pwrdn_ctrl = SW_PWRDN,
> + .phy_status = PHYSTATUS,
>
> .is_dual_lane_phy = true,
> };
> @@ -3027,6 +3045,8 @@ static const struct qmp_phy_cfg sm8150_usb3phy_cfg = {
>
> .start_ctrl = SERDES_START | PCS_START,
> .pwrdn_ctrl = SW_PWRDN,
> + .phy_status = PHYSTATUS,
> +
>
> .has_pwrdn_delay = true,
> .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
> @@ -3058,6 +3078,7 @@ static const struct qmp_phy_cfg sm8150_usb3_uniphy_cfg = {
>
> .start_ctrl = SERDES_START | PCS_START,
> .pwrdn_ctrl = SW_PWRDN,
> + .phy_status = PHYSTATUS,
>
> .has_pwrdn_delay = true,
> .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
> @@ -3086,6 +3107,7 @@ static const struct qmp_phy_cfg sm8250_usb3phy_cfg = {
>
> .start_ctrl = SERDES_START | PCS_START,
> .pwrdn_ctrl = SW_PWRDN,
> + .phy_status = PHYSTATUS,
>
> .has_pwrdn_delay = true,
> .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
> @@ -3117,6 +3139,7 @@ static const struct qmp_phy_cfg sm8250_usb3_uniphy_cfg = {
>
> .start_ctrl = SERDES_START | PCS_START,
> .pwrdn_ctrl = SW_PWRDN,
> + .phy_status = PHYSTATUS,
>
> .has_pwrdn_delay = true,
> .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
> @@ -3145,6 +3168,7 @@ static const struct qmp_phy_cfg sdx55_usb3_uniphy_cfg = {
>
> .start_ctrl = SERDES_START | PCS_START,
> .pwrdn_ctrl = SW_PWRDN,
> + .phy_status = PHYSTATUS,
>
> .has_pwrdn_delay = true,
> .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
> @@ -3171,6 +3195,7 @@ static const struct qmp_phy_cfg sm8350_ufsphy_cfg = {
>
> .start_ctrl = SERDES_START,
> .pwrdn_ctrl = SW_PWRDN,
> + .phy_status = PHYSTATUS,
>
> .is_dual_lane_phy = true,
> };
> @@ -3197,6 +3222,7 @@ static const struct qmp_phy_cfg sm8350_usb3phy_cfg = {
>
> .start_ctrl = SERDES_START | PCS_START,
> .pwrdn_ctrl = SW_PWRDN,
> + .phy_status = PHYSTATUS,
>
> .has_pwrdn_delay = true,
> .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
> @@ -3228,6 +3254,7 @@ static const struct qmp_phy_cfg sm8350_usb3_uniphy_cfg = {
>
> .start_ctrl = SERDES_START | PCS_START,
> .pwrdn_ctrl = SW_PWRDN,
> + .phy_status = PHYSTATUS,
>
> .has_pwrdn_delay = true,
> .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
> @@ -3843,7 +3870,7 @@ static int qcom_qmp_phy_power_on(struct phy *phy)
> ready = PCS_READY;
> } else {
> status = pcs + cfg->regs[QPHY_PCS_STATUS];
> - mask = PHYSTATUS;
> + mask = cfg->phy_status;
> ready = 0;
> }
>
> --
> 2.25.1
>
next prev parent reply other threads:[~2021-05-29 17:02 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-04-27 6:53 [PATCH 0/3] Add support for PCIe PHY in SDX55 Manivannan Sadhasivam
2021-04-27 6:53 ` [PATCH 1/3] dt-bindings: phy: qcom,qmp: Add binding for SDX55 PCIe PHY Manivannan Sadhasivam
2021-05-03 19:13 ` Rob Herring
2021-05-29 16:25 ` Bjorn Andersson
2021-04-27 6:53 ` [PATCH 2/3] phy: qcom-qmp: Use phy_status field for the status bit offset Manivannan Sadhasivam
2021-05-29 17:02 ` Bjorn Andersson [this message]
2021-04-27 6:54 ` [PATCH 3/3] phy: qcom-qmp: Add support for SDX55 QMP PCIe PHY Manivannan Sadhasivam
2021-05-29 17:05 ` Bjorn Andersson
2021-05-31 6:08 ` [PATCH 0/3] Add support for PCIe PHY in SDX55 Vinod Koul
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