From: Stephen Boyd <sboyd@kernel.org>
To: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>,
linux-clk@vger.kernel.org
Cc: linux-kernel@vger.kernel.org, linux-snps-arc@lists.infradead.org,
Michael Turquette <mturquette@baylibre.com>,
Alexey Brodkin <Alexey.Brodkin@synopsys.com>,
Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Subject: Re: [PATCH 3/3] CLK: HSDK: CGU: add support for 148.5MHz clock
Date: Thu, 28 May 2020 21:07:29 -0700 [thread overview]
Message-ID: <159072524956.69627.10946881962902731416@swboyd.mtv.corp.google.com> (raw)
In-Reply-To: <20200311134115.13257-4-Eugeniy.Paltsev@synopsys.com>
Quoting Eugeniy Paltsev (2020-03-11 06:41:15)
> Add support for 148.5MHz clock for HDMI PLL
>
> Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
> ---
Applied to clk-next
prev parent reply other threads:[~2020-05-29 4:07 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-03-11 13:41 [PATCH 0/3] CLK: HSDK: CGU: updates for HSDK clock management Eugeniy Paltsev
2020-03-11 13:41 ` [PATCH 1/3] CLK: HSDK: CGU: check if PLL is bypassed first Eugeniy Paltsev
2020-05-29 4:07 ` Stephen Boyd
2020-03-11 13:41 ` [PATCH 2/3] CLK: HSDK: CGU: support PLL bypassing Eugeniy Paltsev
2020-05-29 4:07 ` Stephen Boyd
2020-03-11 13:41 ` [PATCH 3/3] CLK: HSDK: CGU: add support for 148.5MHz clock Eugeniy Paltsev
2020-05-29 4:07 ` Stephen Boyd [this message]
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