From: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
To: linux-clk@vger.kernel.org
Cc: linux-kernel@vger.kernel.org, linux-snps-arc@lists.infradead.org,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>,
Alexey Brodkin <Alexey.Brodkin@synopsys.com>,
Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Subject: [PATCH 3/3] CLK: HSDK: CGU: add support for 148.5MHz clock
Date: Wed, 11 Mar 2020 16:41:15 +0300 [thread overview]
Message-ID: <20200311134115.13257-4-Eugeniy.Paltsev@synopsys.com> (raw)
In-Reply-To: <20200311134115.13257-1-Eugeniy.Paltsev@synopsys.com>
Add support for 148.5MHz clock for HDMI PLL
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
---
drivers/clk/clk-hsdk-pll.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/clk/clk-hsdk-pll.c b/drivers/clk/clk-hsdk-pll.c
index 0ea7af57a5b1..b4f8852201cb 100644
--- a/drivers/clk/clk-hsdk-pll.c
+++ b/drivers/clk/clk-hsdk-pll.c
@@ -81,6 +81,7 @@ static const struct hsdk_pll_cfg asdt_pll_cfg[] = {
static const struct hsdk_pll_cfg hdmi_pll_cfg[] = {
{ 27000000, 0, 0, 0, 0, 1 },
+ { 148500000, 0, 21, 3, 0, 0 },
{ 297000000, 0, 21, 2, 0, 0 },
{ 540000000, 0, 19, 1, 0, 0 },
{ 594000000, 0, 21, 1, 0, 0 },
--
2.21.1
next prev parent reply other threads:[~2020-03-11 13:41 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-03-11 13:41 [PATCH 0/3] CLK: HSDK: CGU: updates for HSDK clock management Eugeniy Paltsev
2020-03-11 13:41 ` [PATCH 1/3] CLK: HSDK: CGU: check if PLL is bypassed first Eugeniy Paltsev
2020-05-29 4:07 ` Stephen Boyd
2020-03-11 13:41 ` [PATCH 2/3] CLK: HSDK: CGU: support PLL bypassing Eugeniy Paltsev
2020-05-29 4:07 ` Stephen Boyd
2020-03-11 13:41 ` Eugeniy Paltsev [this message]
2020-05-29 4:07 ` [PATCH 3/3] CLK: HSDK: CGU: add support for 148.5MHz clock Stephen Boyd
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