From: Sowjanya Komatineni <skomatineni@nvidia.com>
To: Stephen Boyd <sboyd@kernel.org>, <jason@lakedaemon.net>,
<jonathanh@nvidia.com>, <linus.walleij@linaro.org>,
<marc.zyngier@arm.com>, <mark.rutland@arm.com>, <stefan@agner.ch>,
<tglx@linutronix.de>, <thierry.reding@gmail.com>
Cc: <pdeschrijver@nvidia.com>, <pgaikwad@nvidia.com>,
<linux-clk@vger.kernel.org>, <linux-gpio@vger.kernel.org>,
<jckuo@nvidia.com>, <josephl@nvidia.com>, <talho@nvidia.com>,
<linux-tegra@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
<mperttunen@nvidia.com>, <spatra@nvidia.com>,
<robh+dt@kernel.org>, <digetx@gmail.com>,
<devicetree@vger.kernel.org>
Subject: Re: [PATCH V3 06/17] clk: tegra: pll: save and restore pll context
Date: Tue, 25 Jun 2019 14:22:43 -0700 [thread overview]
Message-ID: <1d34f117-9882-7e11-9641-90f3b7ebc273@nvidia.com> (raw)
In-Reply-To: <20190625204640.D640E205ED@mail.kernel.org>
On 6/25/19 1:46 PM, Stephen Boyd wrote:
> Quoting Sowjanya Komatineni (2019-06-18 00:46:20)
>> diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c
>> index 1583f5fc992f..4b0ed8fc6268 100644
>> --- a/drivers/clk/tegra/clk-pll.c
>> +++ b/drivers/clk/tegra/clk-pll.c
>> @@ -1008,6 +1008,54 @@ static unsigned long clk_plle_recalc_rate(struct clk_hw *hw,
>> return rate;
>> }
>>
>> +void tegra_clk_sync_state_pll(struct clk_hw *hw)
>> +{
>> + if (!__clk_get_enable_count(hw->clk))
>> + clk_pll_disable(hw);
>> + else
>> + clk_pll_enable(hw);
>> +}
>> +
>> +static int tegra_clk_pll_save_context(struct clk_hw *hw)
>> +{
>> + struct tegra_clk_pll *pll = to_clk_pll(hw);
>> +
>> + pll->rate = clk_hw_get_rate(hw);
>> +
>> + if (!strcmp(__clk_get_name(hw->clk), "pll_mb"))
>> + pll->pllbase_ctx = pll_readl_base(pll);
>> + else if (!strcmp(__clk_get_name(hw->clk), "pll_re_vco"))
>> + pll->pllbase_ctx = pll_readl_base(pll) & (0xf << 16);
>> +
>> + return 0;
>> +}
>> +
>> +static void tegra_clk_pll_restore_context(struct clk_hw *hw)
>> +{
>> + struct tegra_clk_pll *pll = to_clk_pll(hw);
>> + u32 val;
>> +
>> + if (clk_pll_is_enabled(hw))
>> + return;
>> +
>> + if (!strcmp(__clk_get_name(hw->clk), "pll_mb")) {
> Is there any way to avoid doing a string comparison here, and instead do
> something like a pointer comparison? Or maybe look at some flag in the
> tegra_clk_pll to figure out what to do differently? Using a string
> comparison is not too nice. Or even have different clk ops for the
> different clks and then do different things in this restore clk_op?
OK, Will update...
>> + pll_writel_base(pll->pllbase_ctx, pll);
>> + } else if (!strcmp(__clk_get_name(hw->clk), "pll_re_vco")) {
>> + val = pll_readl_base(pll);
>> + val &= ~(0xf << 16);
>> + pll_writel_base(pll->pllbase_ctx | val, pll);
>> + }
>> +
>> + if (pll->params->set_defaults)
>> + pll->params->set_defaults(pll);
>> +
>> + clk_set_rate(hw->clk, pll->rate);
> Do you need to call clk_set_rate() here to change the frequency of the
> clk or just the parents of the clk, or both? I'd think that when we're
> restoring the clk the cached rate of the clk would match whatever we're
> restoring to, so this is a NOP. So does this do anything?
>
> I'd prefer that the restore ops just restore the clk hardware state of
> the clk_hw passed in, and not try to fix up the entire tree around a
> certain clk, if that's even possible.
On restore, need to program tegra plls rate back to the same rate as
they were before suspend, so I am calling clk_set_rate to program pll
m,n,p values in hw registers.
>> +
>> + /* do not sync pllx state here. pllx is sync'd after dfll resume */
>> + if (strcmp(__clk_get_name(hw->clk), "pll_x"))
>> + tegra_clk_sync_state_pll(hw);
>> +}
>> +
>> const struct clk_ops tegra_clk_pll_ops = {
>> .is_enabled = clk_pll_is_enabled,
>> .enable = clk_pll_enable,
>> @@ -1015,6 +1063,8 @@ const struct clk_ops tegra_clk_pll_ops = {
>> .recalc_rate = clk_pll_recalc_rate,
>> .round_rate = clk_pll_round_rate,
>> .set_rate = clk_pll_set_rate,
>> + .save_context = tegra_clk_pll_save_context,
>> + .restore_context = tegra_clk_pll_restore_context,
next prev parent reply other threads:[~2019-06-25 21:22 UTC|newest]
Thread overview: 47+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-06-18 7:46 [PATCH V3 00/17] SC7 entry and exit support for Tegra210 Sowjanya Komatineni
2019-06-18 7:46 ` [PATCH V3 01/17] irqchip: tegra: do not disable COP IRQ during suspend Sowjanya Komatineni
2019-06-18 9:19 ` Marc Zyngier
2019-06-18 10:58 ` Thierry Reding
2019-06-18 7:46 ` [PATCH V3 02/17] pinctrl: tegra: add suspend and resume support Sowjanya Komatineni
2019-06-18 9:22 ` Dmitry Osipenko
2019-06-18 9:30 ` Dmitry Osipenko
2019-06-18 15:41 ` Stephen Warren
2019-06-18 16:50 ` Sowjanya Komatineni
2019-06-18 17:34 ` Sowjanya Komatineni
2019-06-18 20:00 ` Dmitry Osipenko
2019-06-18 20:04 ` Sowjanya Komatineni
2019-06-19 8:31 ` Thierry Reding
2019-06-19 8:40 ` Dmitry Osipenko
2019-06-19 8:33 ` Thierry Reding
2019-06-19 8:57 ` Thierry Reding
2019-06-18 11:31 ` Thierry Reding
2019-06-18 7:46 ` [PATCH V3 03/17] gpio: tegra: use resume_noirq for tegra gpio resume Sowjanya Komatineni
2019-06-18 11:39 ` Thierry Reding
2019-06-18 7:46 ` [PATCH V3 04/17] clk: tegra: save and restore divider rate Sowjanya Komatineni
2019-06-18 11:40 ` Thierry Reding
2019-06-18 7:46 ` [PATCH V3 05/17] clk: tegra: pllout: save and restore pllout context Sowjanya Komatineni
2019-06-18 11:41 ` Thierry Reding
2019-06-18 7:46 ` [PATCH V3 06/17] clk: tegra: pll: save and restore pll context Sowjanya Komatineni
2019-06-18 11:45 ` Thierry Reding
2019-06-25 20:46 ` Stephen Boyd
2019-06-25 21:22 ` Sowjanya Komatineni [this message]
2019-06-18 7:46 ` [PATCH V3 07/17] clk: tegra: save and restore CPU and System clocks context Sowjanya Komatineni
2019-06-18 11:48 ` Thierry Reding
2019-06-18 7:46 ` [PATCH V3 08/17] clk: tegra: add support for peripheral clock suspend and resume Sowjanya Komatineni
2019-06-18 11:50 ` Thierry Reding
2019-06-18 7:46 ` [PATCH V3 09/17] clk: tegra: support for saving and restoring OSC clock context Sowjanya Komatineni
2019-06-18 11:51 ` Thierry Reding
2019-06-18 7:46 ` [PATCH V3 10/17] clk: tegra: add suspend resume support for DFLL Sowjanya Komatineni
2019-06-18 11:59 ` Thierry Reding
2019-06-18 7:46 ` [PATCH V3 11/17] clk: tegra210: support for Tegra210 clocks suspend and resume Sowjanya Komatineni
2019-06-18 12:16 ` Thierry Reding
2019-06-18 17:58 ` Sowjanya Komatineni
2019-06-19 8:15 ` Thierry Reding
2019-06-21 20:44 ` Sowjanya Komatineni
2019-06-18 7:46 ` [PATCH V3 12/17] soc/tegra: pmc: allow support for more tegra wake Sowjanya Komatineni
2019-06-18 9:26 ` Marc Zyngier
2019-06-18 7:46 ` [PATCH V3 13/17] soc/tegra: pmc: add pmc wake support for tegra210 Sowjanya Komatineni
2019-06-18 7:46 ` [PATCH V3 14/17] arm64: tegra: enable wake from deep sleep on RTC alarm Sowjanya Komatineni
2019-06-18 7:46 ` [PATCH V3 15/17] soc/tegra: pmc: configure core power request polarity Sowjanya Komatineni
2019-06-18 7:46 ` [PATCH V3 16/17] soc/tegra: pmc: configure deep sleep control settings Sowjanya Komatineni
2019-06-18 7:46 ` [PATCH V3 17/17] arm64: dts: tegra210-p2180: Jetson TX1 SC7 timings Sowjanya Komatineni
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